KR20130000997A - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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Publication number
KR20130000997A
KR20130000997A KR1020110061840A KR20110061840A KR20130000997A KR 20130000997 A KR20130000997 A KR 20130000997A KR 1020110061840 A KR1020110061840 A KR 1020110061840A KR 20110061840 A KR20110061840 A KR 20110061840A KR 20130000997 A KR20130000997 A KR 20130000997A
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South Korea
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data
data line
line
tft
pixel
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KR1020110061840A
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Korean (ko)
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KR101800893B1 (en
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김기상
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엘지디스플레이 주식회사
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • G09G3/3688Details of drivers for data electrodes suitable for active matrices only
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02Details of power systems and of start or stop of display operation

Abstract

The present invention relates to a liquid crystal display device, comprising: a liquid crystal display panel including data lines, gate lines crossing the data lines, TFTs, and a plurality of pixels; A data driving circuit for supplying data voltages of a first color having a first polarity to the first data line and supplying data voltages of a second color having a second polarity to the second data lines during one frame period; And a gate driving circuit which sequentially supplies gate pulses synchronized with the data voltages to the gate lines. Each of the pixels includes a plurality of subpixels. Sub pixels connected in a zigzag form to a first data line are sequentially supplied with data voltages of a first color having the first polarity through the first data line during the one frame period. Sub-pixels connected in a zigzag form to the second data line are sequentially supplied with data voltages of a second color having the second polarity through the second data line during the one frame period.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

Liquid crystal displays can be miniaturized compared to cathode ray tubes (CRTs), which are applied to displays in portable information devices, office equipment, computers, etc., as well as televisions, and are rapidly replacing cathode ray tubes.

The liquid crystal display includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a source drive integrated circuit (IC) for supplying data voltages to data lines of the liquid crystal display panel, and a gate line of the liquid crystal display panel. And a gate drive IC for supplying a gate pulse (or scan pulse) to the light sources (or scan lines), a control circuit for controlling the ICs, a light source driving circuit for driving a light source of the backlight unit, and the like.

The applicant of the present application is Korean Patent Application No. 10-2002-0021792 (2002. 04. 20), 10-2002-0021795 (2002. 04. 20), 10-2002-0070305 (2002. 11. 13) The TFTs (Thin Film Transistors) arranged along the column direction are arranged in a zigzag form so that the liquid crystal cells arranged in the zigzag form along the column direction (or the vertical line direction) in the pixel array share the same data line. A liquid crystal display device (hereinafter referred to as "Z inversion liquid crystal display device") has been proposed.

The Z inversion liquid crystal display device may supply data voltages output from the column inversion type source drive IC to data lines of the liquid crystal display panel and drive the liquid crystal cells of the liquid crystal display panel in dot inversion. The column inversion type source drive ICs supply data voltages of opposite polarity to neighboring data lines, but maintain the polarity of the data voltage for one frame period. In the dot inversion, polarities of the data voltages charged in the left and right neighboring liquid crystal cells are opposite to each other, and polarities of the data voltages charged in the up and down neighboring liquid crystal cells are opposite to each other.

Since the Z inversion liquid crystal display device maintains the same polarity of the data voltage output from the source drive IC for one frame period, the amount of heat generated and power consumption of the source drive IC can be reduced, and the data charged in the liquid crystal cells of the liquid crystal display panel can be reduced. By inverting the polarity of the voltage in the form of dot inversion, there are many advantages such as minimizing flicker.

However, in the Z inversion liquid crystal display, when the voltage difference between the sub pixel data voltages continuously supplied through the same data line increases, the power consumption reduction effect is reduced. Here, the subpixel data voltages continuously supplied through the same data line mean data voltages of different colors. The existing Z inversion liquid crystal display includes data lines alternately supplied with a red data voltage and a green data voltage, and data lines alternately supplied with a blue data voltage and a green data voltage. Therefore, when input image data having a large amount of red data, green data, and even blue data in neighboring pixels is input to the Z inversion liquid crystal display device, the swing width of the data voltage output from the source drive IC is increased to consume current. Increases in power consumption and heat generation.

The present invention provides a liquid crystal display that can reduce power consumption and heat generation of a source drive IC even when displaying image data having a large gray level difference between data of different colors in neighboring pixels.

A liquid crystal display device according to the present invention comprises: a liquid crystal display panel including data lines, gate lines crossing the data lines, TFTs, and a plurality of pixels; A data driving circuit for supplying data voltages of a first color having a first polarity to the first data line and supplying data voltages of a second color having a second polarity to the second data lines during one frame period; And a gate driving circuit which sequentially supplies gate pulses synchronized with the data voltages to the gate lines. Each of the pixels includes a plurality of subpixels. Sub-pixels connected in a zigzag form to a first data line are sequentially supplied with data voltages of a first color having the first polarity through the first data line during the one frame period. Sub-pixels connected in a zigzag form to the second data line are sequentially supplied with data voltages of a second color having the second polarity through the second data line during the one frame period.

According to an embodiment of the present invention, subpixels connected to one data line are disposed in subpixels of the same color, and data voltages of the same color having the same polarity are supplied to the dataline for one frame period. When displaying image data having a large gray level difference between the data, power consumption and heat generation of the data driving circuit can be minimized.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating a first embodiment of the pixel array shown in FIG. 1.
3 is a diagram illustrating an example in which a data line disposed at the leftmost end and a data line disposed at the rightmost end are commonly connected to one output channel formed in the same source drive IC.
FIG. 4 is a diagram illustrating a second embodiment of the pixel array shown in FIG. 1.
FIG. 5 is a waveform diagram illustrating data voltages supplied to data lines of the pixel array illustrated in FIGS. 2 and 4.
FIG. 6 is a diagram illustrating a third embodiment of the pixel array shown in FIG. 1.
FIG. 7 is a diagram illustrating a fourth exemplary embodiment of the pixel array illustrated in FIG. 1.
FIG. 8 is a waveform diagram illustrating data voltages supplied to data lines of the pixel array illustrated in FIGS. 6 and 7.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel, a source drive IC 12, a gate driving circuit 13, a timing controller 11, and the like. A backlight unit for uniformly irradiating light onto the liquid crystal display panel may be disposed below the liquid crystal display panel.

The liquid crystal display panel includes an upper glass substrate and a lower glass substrate facing each other with a liquid crystal layer interposed therebetween. The liquid crystal display panel includes a pixel array 10 for displaying video data. The pixel array 10 displays video data including liquid crystal cells arranged in a matrix by a cross structure of data lines and gate lines. The pixel array 10 includes TFTs formed at intersections of data lines and gate lines, and pixel electrodes connected to the TFTs. The TFTs of the pixel array 10 are arranged in a zigzag form in the column direction (or data line direction). Each of the liquid crystal cells of the pixel array 10 is driven by the voltage difference of the pixel electrode charging the data voltage through the TFT and the voltage of the common electrode to which the common voltage is applied, thereby adjusting the transmission amount of light to adjust the gray level of the video data. Express Subpixels of the same color arranged in neighboring columns in the pixel array 10 are connected to the same data line. The pixel array 10 may be implemented in various forms as shown in FIGS. 2, 5, 6, and 8.

A black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the liquid crystal display panel. The common electrode is formed on the upper glass substrate in the case of the vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode. In the case of the same horizontal electric field driving method, the pixel electrode is formed on the lower glass substrate together with the pixel electrode.

A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed.

The liquid crystal mode of the liquid crystal display panel applicable to the present invention can be implemented not only in the TN mode, the VA mode, the IPS mode, and the FFS mode, but also in any liquid crystal mode. In addition, the liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The source drive ICs 12 are mounted on a tape carrier package (TCP) 15 and bonded to a lower glass substrate of a liquid crystal display panel by a tape automated bonding (TAB) process, and a source printed circuit board (PCB) 14. Is connected to. The source drive ICs 12 may be adhered to the lower glass substrate of the liquid crystal display panel by a chip on glass (COG) process. The data output channels of each of the source drive ICs 12 are connected 1: 1 to the data lines of the pixel array 10.

Each of the source drive ICs 12 receives digital video data from the timing controller 11. The source drive ICs 12 convert the digital video data into a positive / negative analog data voltage in response to a source timing control signal from the timing controller 11 to transmit a data line of the pixel array 10 through the data output channels. Feed the fields. The source drive ICs 12 supply data voltages having opposite polarities to neighboring data lines under the control of the timing controller 11, and make the polarities of the data voltages supplied to the respective data lines equal to each other for one frame period. Keep it. Each of the source drive ICs 12 continuously supplies subpixel data voltages of the same color to the same data line maintaining the same polarity for one frame period. The source drive ICs 12 half the polarities of the data voltages by one frame period. Thus, the source drive ICs 12 can be implemented with a source drive IC of column inversion type.

The gate driving circuit 13 sequentially supplies gate pulses (or scan pulses) to the gate lines of the pixel array in response to the gate timing control signal from the timing controller 11. The gate driving circuit 13 is mounted on a tape carrier package (TCP) and bonded to a lower glass substrate of a liquid crystal display panel by a TAB process, or simultaneously on a lower glass substrate simultaneously with a pixel array by a GIP (Gate In Panel) process. Can be formed directly. The gate driving circuit 13 may be disposed at both sides of the pixel array 10 or at one side of the pixel array 10.

The timing controller 11 supplies digital video data input from an external host system to the source drive ICs 12. The timing controller 11 generates a source timing control signal for controlling the operation timing of the source drive ICs 12 and a gate timing control signal for controlling the operation timing of the gate driving circuit 13. The timing controller 11 is mounted on the control PCB 16. The control PCB 16 and the source PCB 14 are connected through a flexible circuit board 17 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

2 is an equivalent circuit diagram showing a first embodiment of the pixel array 10.

Referring to FIG. 2, the pixel array 10 includes m (m is a positive integer) data lines S1 to Sm, n (n is a positive integer) gate lines G1 to Gn, and many Pixels of PIX. Each of the pixels PIX includes a red subpixel R + / R−, a green subpixel G + / G−, and a blue subpixel B + / B−. The pixels PIX include red subpixels R + / R-, green subpixels G + / G-, and blue subpixels B + / B- arranged in one display line as in the upper right of FIG. 2. 2, red subpixels R + / R-, green subpixels G + / G-, and blue subs disposed on two adjacent display lines, such as two display lines positioned at the right center of FIG. 2. Pixels B + / B- may be included. The liquid crystal cell of the subpixel includes a pixel electrode and a TFT. In FIG. 2, "R" is a liquid crystal cell of a red subpixel charged with a red data voltage, and "G" is a liquid crystal cell of a green subpixel filled with a green data voltage. "B" is a liquid crystal cell of a blue subpixel charged with a blue data voltage. "+" Means the liquid crystal cell of the sub-pixel to which the positive data voltage is supplied, and "-" means the liquid crystal cell of the sub-pixel to which the negative data voltage is supplied.

In FIG. 2, each of the odd display lines LINE # 1 and LINE # n-1 includes first and second subpixels. The first subpixel includes a first TFT T11 and a first pixel electrode P11. The second subpixel includes a second TFT T12 and a second pixel electrode P12. Each of the even display lines LINE # 2 and LINE # n includes third and fourth subpixels. The third sub pixel includes a third TFT T21 and a third pixel electrode P21. The fourth subpixel includes a fourth TFT T22 and a fourth pixel electrode P22. Each of the TFTs supplies a data voltage from the data line to the pixel electrode in response to a gate pulse from the gate line. In Fig. 2, the arrow indicates the charging order of the data voltage.

The first TFT T11 subtracts the data voltage supplied through the i (i is a positive integer less than or equal to m) data line in response to a gate pulse from the jth (j is a positive integer less than or equal to n) gate line. It is supplied to one pixel electrode P11. The first pixel electrode P11 is disposed on the left side of the i-th data line. The gate electrode of the first TFT T11 is connected to the jth gate line. The drain electrode of the first TFT T11 is connected to the i-th data line, and its source electrode is connected to the first pixel electrode P11.

The second TFT T12 supplies a data voltage supplied through the i + 1th data line to the second pixel electrode P12 in response to a gate pulse from the jth gate line. The second pixel electrode P12 is disposed on the left side of the i + 1th data line. The gate electrode of the second TFT T12 is connected to the jth gate line. The drain electrode of the second TFT T12 is connected to the i + 1th data line, and its source electrode is connected to the second pixel electrode P12.

The third TFT T21 supplies a data voltage supplied through the i-th data line to the third pixel electrode P21 in response to a gate pulse from the j + 1th gate line. The third pixel electrode P21 is disposed on the right side of the i-th data line. The gate electrode of the third TFT T21 is connected to the j + 1 gate line. The drain electrode of the third TFT T21 is connected to the i-th data line, and its source electrode is connected to the third pixel electrode P21.

The fourth TFT T22 supplies the data voltage supplied through the i + 1th data line to the fourth pixel electrode P22 in response to the gate pulse from the j + 1th gate line. The fourth pixel electrode P22 is disposed on the right side of the i + 1th data line. The gate electrode of the fourth TFT T22 is connected to the j + 1th gate line. The drain electrode of the fourth TFT T22 is connected to the i + 1th data line, and the source electrode thereof is connected to the fourth pixel electrode P22.

The first subpixel of the first display line LINE # 1, the third subpixel of the second display line LINE # 2 disposed in the diagonal direction at the lower right of the first subpixel, and the third subpixel. The first subpixel of the third display line arranged in the lower left diagonal direction, and the third subpixel of the fourth display line arranged in the lower right diagonal direction of the first subpixel are within one frame period as shown by an arrow. The sub pixel data voltages of the first color having the same polarity are successively charged. The first color is any one of red (R), green (G), and blue (B). Of the second sub-pixel of the first display line LINE # 1, the fourth sub-pixel of the second display line LINE # 2 disposed in the diagonal direction at the lower right of the second sub-pixel, and the fourth sub-pixel. The second sub-pixel of the third display line disposed in the lower left diagonal direction, and the fourth sub-pixel of the fourth display line disposed in the lower right diagonal direction of the second sub pixel are within one frame period as shown by the arrow. The sub pixel data voltages of the second color having the same polarity are successively charged. The second color is one other than the first color among red (R), green (G), and blue (B). Therefore, liquid crystal cells arranged in a zigzag form and sharing the same data line in two columns sequentially charge data voltages of the same color having the same polarity within one frame period.

In general, red data in neighboring pixels that are not boundary parts in one frame image has almost no gray level difference. Similarly, there is little gray level difference between the green data in neighboring pixels that are not the boundary portion in one frame image, and also little gray level difference between the blue data. In the pixel array 10 of the liquid crystal display panel as shown in FIG. 2, one data line is connected to subpixels of the same color. The source drive ICs 12 repeatedly output data voltages of the same color having the same polarity on one data line. Accordingly, the liquid crystal display of the present invention arranges subpixels connected to one data line by subpixels having the same color, and supplies neighboring pixels by supplying data voltages of the same color having the same polarity to the data line for one frame period. Even when displaying image data having a large gray level difference between data of different colors, power consumption and heat generation of the source drive ICs 12 may be minimized.

In FIG. 2, the first data line S1 disposed at the leftmost side and the mth data line Sm disposed at the rightmost side are connected to one output channel in the same source drive IC using the method shown in FIG. 3. It can be connected in common. The present invention can prevent the increase in the number of output channels of the source drive IC by connecting the first and m-th data lines S1 and Sm to the same output channel in the same source drive IC, and at both ends of the pixel array. By varying the load conditions of the arranged data lines S1 and Sn and other data lines, it is possible to prevent a phenomenon that luminance is changed at both ends of the pixel array.

3 shows an example in which the first data line S1 disposed at the leftmost end and the mth data line Sm disposed at the rightmost end are commonly connected to one output channel formed in the same source drive IC 12. The figure shows.

Referring to FIG. 3, the liquid crystal display of the present invention includes a connection line 111 connecting the first data line S1 and the m-th data line Sm. In the liquid crystal display, other components except for the connection line 111 are substantially the same as the above-described embodiment, and the same reference numerals as those of the above-described embodiment will be omitted.

The connection line 111 is a data pad formed at the end of the first data line S1 and a metal wiring connected to the first output channel of the first source drive IC 12 for supplying a data voltage through the data pad. . The connection line 111 is connected to the first data line S1 via TCP 15 bonded to the upper left side of the LCD panel, the source PCB 14, and TCP 15 bonded to the upper right side of the LCD panel. ) And the m th data line Sm, and the data lines S1 and Sm are commonly connected to the first output channel of the first source drive IC 12. Therefore, the first source drive IC 12 may supply a data voltage to the first and m th data lines S1 and Sm through the first output channel.

4 is an equivalent circuit diagram showing a second embodiment of the pixel array 10.

Referring to FIG. 4, the pixel array 10 includes m data lines S1 to Sm, n gate lines G1 to Gn, and a plurality of pixels PIX. Each of the pixels PIX includes a red subpixel R + / R−, a green subpixel G + / G−, and a blue subpixel B + / B−. The pixels PIX include a red subpixel R + / R-, a green subpixel G + / G-, and a blue subpixel B + / B- arranged in one display line, or two neighboring pixels. The red subpixels R + / R-, the green subpixels G + / G-, and the blue subpixels B + / B- may be disposed on the display lines. The liquid crystal cell of the subpixel includes a pixel electrode and a TFT. In FIG. 4, "R" is a liquid crystal cell of a red subpixel charged with a red data voltage, and "G" is a liquid crystal cell of a green subpixel filled with a green data voltage. "B" is a liquid crystal cell of a blue subpixel charged with a blue data voltage. "+" Means the liquid crystal cell of the sub-pixel to which the positive data voltage is supplied, and "-" means the liquid crystal cell of the sub-pixel to which the negative data voltage is supplied.

In FIG. 4, each of the odd display lines LINE # 1 and LINE # n-1 includes first and second subpixels. The first sub pixel includes a first TFT T31 and a first pixel electrode P31. The second subpixel includes a second TFT T32 and a second pixel electrode P32. Each of the even display lines LINE # 2 and LINE # n includes third and fourth subpixels. The third sub pixel includes a third TFT T41 and a third pixel electrode P41. The fourth subpixel includes a fourth TFT T42 and a fourth pixel electrode P42. Each of the TFTs supplies a data voltage from the data line to the pixel electrode in response to a gate pulse from the gate line. In Fig. 4, the arrow indicates the charging order of the data voltage.

The first TFT T31 supplies the data voltage supplied through the i-th data line to the first pixel electrode P31 in response to a gate pulse from the j-th gate line. The first pixel electrode P31 is disposed on the right side of the i-th data line. The gate electrode of the first TFT T31 is connected to the jth gate line. The drain electrode of the first TFT T31 is connected to the i-th data line, and the source electrode thereof is connected to the first pixel electrode P31.

The second TFT T32 supplies a data voltage supplied through the i + 1th data line to the second pixel electrode P32 in response to a gate pulse from the jth gate line. The second pixel electrode P32 is disposed on the right side of the i + 1th data line. The gate electrode of the second TFT T32 is connected to the jth gate line. The drain electrode of the second TFT T32 is connected to the i-th data line, and the source electrode thereof is connected to the second pixel electrode P32.

The third TFT T41 supplies the data voltage supplied through the i-th data line to the third pixel electrode P41 in response to the gate pulse from the j + 1th gate line. The third pixel electrode P41 is disposed on the left side of the i-th data line. The gate electrode of the third TFT T41 is connected to the j + 1 gate line. The drain electrode of the third TFT T41 is connected to the i-th data line, and the source electrode thereof is connected to the third pixel electrode P41.

The fourth TFT T42 supplies the data voltage supplied through the i + 1th data line to the fourth pixel electrode P42 in response to the gate pulse from the j + 1th gate line. The fourth pixel electrode P42 is disposed on the left side of the i + 1th data line. The gate electrode of the fourth TFT T42 is connected to the j + 1th gate line. The drain electrode of the fourth TFT T42 is connected to the i + 1th data line, and the source electrode thereof is connected to the fourth pixel electrode P42.

Of the first sub-pixel of the first display line LINE # 1, the third sub-pixel of the second display line LINE # 2 disposed in the diagonal direction at the lower left of the first sub-pixel, and the third sub-pixel The first subpixel of the third display line disposed in the lower right diagonal direction, and the third subpixel of the fourth display line disposed in the lower left diagonal direction of the first subpixel are within one frame period as shown by an arrow. The sub pixel data voltages of the first color having the same polarity are successively charged. The first color is any one of red (R), green (G), and blue (B). Of the second sub-pixel of the first display line LINE # 1, the fourth sub-pixel of the second display line LINE # 2 disposed in the diagonal direction at the lower left of the second sub-pixel, and the fourth sub-pixel The second subpixel of the third display line disposed in the diagonal direction at the lower right and the fourth subpixel of the fourth display line disposed in the diagonal direction at the lower left of the second subpixel are within one frame period as shown by an arrow. The sub pixel data voltages of the second color having the same polarity are successively charged. The second color is one other than the first color among red (R), green (G), and blue (B). Therefore, liquid crystal cells arranged in a zigzag form and sharing the same data line in two neighboring columns sequentially charge data voltages of the same color having the same polarity within one frame period.

In general, red data in neighboring pixels that are not boundary parts in one frame image has almost no gray level difference. Similarly, there is little gray level difference between the green data in neighboring pixels that are not the boundary portion in one frame image, and also little gray level difference between the blue data. In the pixel array 10 of the liquid crystal display panel as shown in FIG. 4, one data line is connected to subpixels of the same color. The source drive ICs 12 repeatedly output data voltages of the same color having the same polarity on one data line. Accordingly, the liquid crystal display of the present invention arranges subpixels connected to one data line by subpixels having the same color, and supplies neighboring pixels by supplying data voltages of the same color having the same polarity to the data line for one frame period. Even when displaying image data having a large gray level difference between data of different colors, power consumption and heat generation of the source drive ICs 12 may be minimized.

FIG. 5 is a waveform diagram illustrating data voltages supplied to data lines S1 to Sm of the pixel array 10 illustrated in FIGS. 2 and 4.

Referring to FIG. 5, the source drive IC 12 controls the first and m-th data of the negative blue data voltage B− during the Nth (N is a positive integer) frame period under the control of the timing controller 11. Supply to lines S1 and Sm. The source drive IC 12 supplies the positive red data voltage R + to the second data lines S2 during the Nth frame period under the control of the timing controller 11, and the negative green data voltage G−. ) Is supplied to the third data lines S3. The source drive IC 12 supplies the positive green data voltage G + to the m−1th data lines Sm−1 during the Nth frame period under the control of the timing controller 11. The source drive IC 12 then inverts the polarities of the data voltages R + / R-, G + / G-, and B + / B- in the N + 1th frame period under the control of the timing controller 11. The polarity is maintained for one frame period.

The gate driving circuit 13 sequentially transmits a gate pulse (or scan pulse) to the gate lines G1 to Gn in synchronization with the data voltages supplied to the data lines S1 to Sm under the control of the timing controller 11. Supply.

Meanwhile, the liquid crystal display of the present invention may or may not perform charge sharing between data voltages continuously supplied to the data lines S1 to Sm. Charge sharing short circuits the neighboring data lines during the horizontal blank period between the data voltages and applies the average voltages of the positive data voltage and the negative data voltage to the data lines as shown by the dotted lines. . According to the present invention, when the data voltages having the same polarity and the same gray level are continuously supplied to the data lines, the number of transitions can be minimized like a solid line when the charge sharing is not performed. Therefore, the liquid crystal display of the present invention can further reduce power consumption when charge sharing is not performed.

6 is an equivalent circuit diagram showing a third embodiment of the pixel array 10.

Referring to FIG. 6, the pixel array 10 includes m data lines S1 to Sm, n gate lines G1 to Gn, and a plurality of pixels PIX. Each of the pixels PIX includes a red subpixel R + / R−, a green subpixel G + / G−, and a blue subpixel B + / B−. The pixels PIX include a red subpixel R + / R-, a green subpixel G + / G-, and a blue subpixel B + / B- arranged in one display line, or two neighboring pixels. The red subpixels R + / R-, the green subpixels G + / G-, and the blue subpixels B + / B- may be disposed on the display lines. The liquid crystal cell of the subpixel includes a pixel electrode and a TFT. In Fig. 6, "R" is a liquid crystal cell of a red subpixel charged with a red data voltage, and "G" is a liquid crystal cell of a green subpixel filled with a green data voltage. "B" is a liquid crystal cell of a blue subpixel charged with a blue data voltage. "+" Means the liquid crystal cell of the sub-pixel to which the positive data voltage is supplied, and "-" means the liquid crystal cell of the sub-pixel to which the negative data voltage is supplied.

In FIG. 6, each of the odd display lines LINE # 1 and LINE # n-1 includes first and second subpixels. The first subpixel includes a first TFT T51 and a first pixel electrode P51. The second sub pixel includes a second TFT T52 and a second pixel electrode P52. Each of the even display lines LINE # 2 and LINE # n includes third and fourth subpixels. The third subpixel includes a third TFT T61 and a third pixel electrode P61. The fourth subpixel includes a fourth TFT T62 and a fourth pixel electrode P62. Each of the TFTs supplies a data voltage from the data line to the pixel electrode in response to a gate pulse from the gate line. In Fig. 6, the arrow indicates the charging order of the data voltage.

The first TFT T51 supplies the data voltage supplied through the i-th data line to the first pixel electrode P51 in response to the gate pulse from the j-th gate line. The first pixel electrode P51 is disposed on the right side of the i-th data line. The gate electrode of the first TFT T51 is connected to the jth gate line. The drain electrode of the first TFT T51 is connected to the i-th data line, and its source electrode is connected to the first pixel electrode P51.

The second TFT T52 supplies a data voltage supplied through the i + 1th data line to the second pixel electrode P52 in response to a gate pulse from the jth gate line. The second pixel electrode P52 is disposed on the right side of the i + 1th data line. The gate electrode of the second TFT T52 is connected to the jth gate line. The drain electrode of the second TFT T52 is connected to the i + 1th data line, and its source electrode is connected to the second pixel electrode P52.

The third TFT T61 supplies a data voltage supplied through the i th data line to the third pixel electrode P61 in response to a gate pulse from the j + 1 th gate line. The third pixel electrode P61 is disposed on the left side of the i-th data line. The gate electrode of the third TFT T61 is connected to the j + 1 gate line. The drain electrode of the third TFT T61 is connected to the i-th data line, and its source electrode is connected to the third pixel electrode P61.

The fourth TFT T62 supplies the data voltage supplied through the i + 1th data line to the fourth pixel electrode P62 in response to the gate pulse from the j + 1th gate line. The fourth pixel electrode P62 is disposed on the left side of the i + 1th data line. The gate electrode of the fourth TFT T62 is connected to the j + 1 gate line. The drain electrode of the fourth TFT T62 is connected to the i + 1th data line, and its source electrode is connected to the fourth pixel electrode P62.

In the pixel array 10 illustrated in FIG. 6, the connection relationship between the data lines S1 to Sm, the gate lines G1 to Gn, the TFTs T51 to T62, and the pixel electrodes P51 to P62 is shown in FIG. 6. It is substantially the same as those of the pixel array shown in Fig. 4, and the colors of the sub pixels are different. Therefore, the driving method of the pixel array illustrated in FIG. 6 is substantially different from the driving method of the pixel array illustrated in FIG. 4 except that the colors of the subpixel data supplied to the data lines S1 to Sm and the polarities of the data voltages are different. same.

7 is an equivalent circuit diagram showing a fourth embodiment of the pixel array 10.

Referring to FIG. 7, the pixel array 10 includes m data lines S1 to Sm, n gate lines G1 to Gn, and a plurality of pixels PIX. Each of the pixels PIX includes a red subpixel R + / R−, a green subpixel G + / G−, and a blue subpixel B + / B−. The pixels PIX include a red subpixel R + / R-, a green subpixel G + / G-, and a blue subpixel B + / B- arranged in one display line, or two neighboring pixels. The red subpixels R + / R-, the green subpixels G + / G-, and the blue subpixels B + / B- may be disposed on the display lines. The liquid crystal cell of the subpixel includes a pixel electrode and a TFT. In FIG. 7, "R" is a liquid crystal cell of a red subpixel charged with a red data voltage, and "G" is a liquid crystal cell of a green subpixel filled with a green data voltage. "B" is a liquid crystal cell of a blue subpixel charged with a blue data voltage. "+" Means the liquid crystal cell of the sub-pixel to which the positive data voltage is supplied, and "-" means the liquid crystal cell of the sub-pixel to which the negative data voltage is supplied.

In FIG. 7, each of the odd display lines LINE # 1 and LINE # n-1 includes first and second subpixels. The first subpixel includes a first TFT T71 and a first pixel electrode P71. The second subpixel includes a second TFT T72 and a second pixel electrode P72. Each of the even display lines LINE # 2 and LINE # n includes third and fourth subpixels. The third subpixel includes a third TFT T81 and a third pixel electrode P81. The fourth sub-pixel includes a fourth TFT T82 and a fourth pixel electrode P82. Each of the TFTs supplies a data voltage from the data line to the pixel electrode in response to a gate pulse from the gate line. In Fig. 7, the arrow indicates the charging order of the data voltage.

The first TFT T71 supplies the data voltage supplied through the i-th data line to the first pixel electrode P71 in response to a gate pulse from the j-th gate line. The first pixel electrode P71 is disposed on the left side of the i-th data line. The gate electrode of the first TFT T71 is connected to the jth gate line. The drain electrode of the first TFT (T71) is connected to the i-th data line, and its source electrode is connected to the first pixel electrode (P71).

The second TFT T72 supplies a data voltage supplied through the i + 1th data line to the second pixel electrode P72 in response to a gate pulse from the jth gate line. The second pixel electrode P72 is disposed on the left side of the i + 1th data line. The gate electrode of the second TFT T72 is connected to the jth gate line. The drain electrode of the second TFT T72 is connected to the i + 1th data line, and its source electrode is connected to the second pixel electrode P72.

The third TFT T81 supplies the data voltage supplied through the i-th data line to the third pixel electrode P81 in response to the gate pulse from the j + 1th gate line. The third pixel electrode P81 is disposed on the right side of the i-th data line. The gate electrode of the third TFT T81 is connected to the j + 1th gate line. The drain electrode of the third TFT (T81) is connected to the i-th data line, and its source electrode is connected to the third pixel electrode (P81).

The fourth TFT T82 supplies the data voltage supplied through the i + 1th data line to the fourth pixel electrode P82 in response to the gate pulse from the j + 1th gate line. The fourth pixel electrode P82 is disposed on the right side of the i + 1th data line. The gate electrode of the fourth TFT T82 is connected to the j + 1th gate line. The drain electrode of the fourth TFT (T82) is connected to the i + 1th data line, and its source electrode is connected to the fourth pixel electrode (P82).

In the pixel array 10 illustrated in FIG. 7, the connection relationship between the data lines S1 to Sm, the gate lines G1 to Gn, the TFTs T71 to T82, and the pixel electrodes P71 to P82 is It is substantially the same as those of the pixel array shown in Fig. 2, and the colors of the sub pixels are different. Therefore, the driving method of the pixel array shown in FIG. 7 is substantially different from the driving method of the pixel array shown in FIG. 2 except that the colors of the subpixel data and the polarities of the data voltages supplied to the data lines S1 to Sm are different. same.

FIG. 8 is a waveform diagram illustrating data voltages supplied to data lines S1 to Sm of the pixel array 10 illustrated in FIGS. 6 and 7.

Referring to FIG. 8, the source drive IC 12 may apply the positive red data voltage R + to the first and m th data lines S1 and Sm during the Nth frame period under the control of the timing controller 11. Supply. The source drive IC 12 supplies the negative green data voltage G− to the second data lines S2 during the Nth frame period under the control of the timing controller 11, and the positive blue data voltage B +. ) Is supplied to the third data lines S3. The source drive IC 12 supplies the negative blue data voltage B− to the m−1th data lines Sm−1 during the Nth frame period under the control of the timing controller 11. The source drive IC 12 then inverts the polarities of the data voltages R + / R-, G + / G-, and B + / B- in the N + 1th frame period under the control of the timing controller 11. The polarity is maintained for one frame period.

The gate driving circuit 13 sequentially transmits a gate pulse (or scan pulse) to the gate lines G1 to Gn in synchronization with the data voltages supplied to the data lines S1 to Sm under the control of the timing controller 11. Supply.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: pixel array 11: timing controller
12: source drive IC 13: gate driving circuit

Claims (5)

  1. A liquid crystal display panel including data lines, gate lines crossing the data lines, TFTs, and a plurality of pixels;
    A data driving circuit for supplying data voltages of a first color having a first polarity to the first data line and supplying data voltages of a second color having a second polarity to the second data lines during one frame period; And
    A gate driving circuit sequentially supplying gate pulses synchronized with the data voltages to the gate lines,
    Each of the pixels comprises a plurality of subpixels,
    Sub-pixels connected in a zigzag form to a first data line are sequentially supplied with data voltages of a first color having the first polarity through the first data line during the one frame period.
    The sub-pixels connected in a zigzag form to the second data line are sequentially supplied with data voltages of a second color having the second polarity through the second data line during the one frame period. Device.
  2. The method of claim 1,
    The subpixels,
    First and second sub pixels on the first display line of the liquid crystal display panel; And
    Third and fourth subpixels on the second display line of the liquid crystal display panel;
    The TFTs,
    A first TFT connecting the pixel electrode of the first sub-pixel to the first data line in response to a first gate pulse from a first gate line;
    A second TFT connecting the pixel electrode of the second sub pixel to the second data line in response to the first gate pulse;
    A third TFT connecting the pixel electrode of the third sub pixel to the first data line in response to a second gate pulse from a second gate line; And
    And a fourth TFT for connecting the pixel electrode of the fourth sub-pixel to the second data line in response to the second gate pulse.
  3. The method of claim 2,
    The pixel electrode of the first TFT and the first sub pixel is disposed on the left side of the first data line,
    The pixel electrode of the second TFT and the second sub pixel is disposed on the left side of the second data line,
    The pixel electrode of the third TFT and the third sub pixel is disposed on the right side of the first data line,
    And the pixel electrode of the fourth TFT and the fourth sub pixel is disposed on the right side of the second data line.
  4. The method of claim 2,
    The pixel electrode of the first TFT and the first sub pixel is disposed on the right side of the first data line,
    The pixel electrode of the second TFT and the second sub pixel is disposed on the right side of the second data line,
    The pixel electrode of the third TFT and the third sub pixel is disposed on the left side of the first data line,
    And a pixel electrode of the fourth TFT and the fourth sub pixel is disposed on the left side of the second data line.
  5. The method of claim 1,
    And a data line disposed at the leftmost end of the data lines and a data line disposed at the rightmost end of the data lines are commonly connected to one output channel of the output channels of the data driving circuit.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2508642A (en) * 2012-12-06 2014-06-11 Univ Swansea Nanostructure antireflective coatings for silicon substrates
KR20140093474A (en) * 2013-01-18 2014-07-28 엘지디스플레이 주식회사 Liquid crystal display
US9536906B2 (en) 2014-06-30 2017-01-03 Shanghai Tianma Micro-electronics Co., Ltd. Pixel structure, liquid crystal display array substrate and liquid crystal display panel
CN107180606A (en) * 2016-10-21 2017-09-19 友达光电股份有限公司 Display device
US9778528B2 (en) 2014-08-26 2017-10-03 Samsung Display Co., Ltd. Display apparatus
US9835908B2 (en) 2015-02-25 2017-12-05 Samsung Display Co., Ltd. Display apparatus
US10146091B2 (en) 2014-10-22 2018-12-04 Samsung Display Co., Ltd. Display apparatus
CN109427278A (en) * 2017-08-31 2019-03-05 昆山国显光电有限公司 Display panel and display device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2508642A (en) * 2012-12-06 2014-06-11 Univ Swansea Nanostructure antireflective coatings for silicon substrates
KR20140093474A (en) * 2013-01-18 2014-07-28 엘지디스플레이 주식회사 Liquid crystal display
US9536906B2 (en) 2014-06-30 2017-01-03 Shanghai Tianma Micro-electronics Co., Ltd. Pixel structure, liquid crystal display array substrate and liquid crystal display panel
US9778528B2 (en) 2014-08-26 2017-10-03 Samsung Display Co., Ltd. Display apparatus
US10146091B2 (en) 2014-10-22 2018-12-04 Samsung Display Co., Ltd. Display apparatus
US9835908B2 (en) 2015-02-25 2017-12-05 Samsung Display Co., Ltd. Display apparatus
CN107180606A (en) * 2016-10-21 2017-09-19 友达光电股份有限公司 Display device
CN107180606B (en) * 2016-10-21 2020-03-24 友达光电股份有限公司 Display device
CN109427278A (en) * 2017-08-31 2019-03-05 昆山国显光电有限公司 Display panel and display device

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