KR101977252B1 - Liquid crystal display and method of driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof, in which a horizontal charging period is increased in a portion where a gray level difference between adjacent horizontal lines is relatively larger than a relatively small gray level portion, Increases the duration of one horizontal charge in a larger portion than in a relatively small portion.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD)

The present invention relates to a liquid crystal display device capable of increasing luminance uniformity and a driving method thereof.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as " TFT ") as a switching element. Liquid crystal cells of a liquid crystal display display an image by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode.

There are various factors that influence the data voltage charging characteristics of the liquid crystal cells in the liquid crystal display device.

The greater the difference in gradation of the input image data, the larger the data voltage charge deviation of the liquid crystal cells. When the data voltage is continuously supplied to the liquid crystal cells k (k is a positive integer of 2 or more) through the data lines for the k horizontal periods, if the difference in gradation of the data voltage is small, the voltage of the liquid crystal cell is charged to the target gradation voltage . On the other hand, if the difference in gradation of the data voltage is large, the voltage of the liquid crystal cell may not be charged up to the target gradation voltage.

The data voltage charge deviation of the liquid crystal cells is greatly influenced by the RC delay of the data voltage. As the screen size of the liquid crystal display device increases and the resolution increases, the resistance and capacitance of the liquid crystal display panel increase, and the RC delay of the data voltage supplied through the data line increases. The data voltage charging rate of the liquid crystal cells located in a portion where the RC delay is large in the large-screen liquid crystal display device is relatively small. 1, the data voltage output from the source drive IC (Integrated Circuit) is supplied to the liquid crystal cell through the data line at the target voltage V2, but due to the RC delay, the voltage Vp of the liquid crystal cell becomes equal to one horizontal charge period Lt; RTI ID = 0.0 > (1HC) < / RTI > but does not reach V2. 1, the SIC output data voltage is a data voltage output from the source drive IC (SIC).

One horizontal charge period 1HC is a time allocated to the charging of the liquid crystal cells arranged in one horizontal line, and is determined according to the vertical resolution of the liquid crystal display panel and one frame period. When the liquid crystal display panel having the FHD resolution (1920 * 1080) is driven at a frame frequency of 120 Hz, one horizontal charge period (1HC) is approximately 7.7 s (8.33 ms / 1080). However, since the conventional liquid crystal display device sets one horizontal charge period (1HC) at every position of the liquid crystal display panel as shown in Fig. 2, the charge rate variation of the data voltage due to the RC delay can not be eliminated.

The present invention provides a liquid crystal display device and a driving method thereof that can improve data voltage charging characteristics of liquid crystal cells in a high resolution large-screen liquid crystal display device.

A liquid crystal display device of the present invention includes: a liquid crystal display panel in which data lines and gate lines are crossed and liquid crystal cells are arranged in a matrix type; A data driver for supplying a data voltage to the data lines; A gate driver sequentially supplying a gate pulse synchronized with the data voltages to the gate lines; And Nth line data to be written in liquid crystal cells arranged in an Nth (N is a positive integer) horizontal line of the liquid crystal display panel and Nth line data to be written in liquid crystal cells in an (N + 1) th horizontal line of the liquid crystal display panel And adjusts one horizontal charge period corresponding to each horizontal line of the liquid crystal display panel by adjusting timing control signals for controlling the operation timings of the data driver and the gate driver based on a difference in gradation between the (N + 1) th line data And a timing controller.

The timing control signals include a gate output enable signal for controlling an output timing of the gate driver and a source output enable signal for controlling an output timing of the data driver.

Wherein the timing controller sets one horizontal charge period of a horizontal line having the smallest RC delay in the liquid crystal display panel as a reference period, The horizontal period of the gate output enable signal and the source output enable signal of each of the gate output enable signal and the source output enable signal are set to the initial value of the initial period of the (N + 1) th horizontal line in proportion to the gradation difference, Th horizontal line is less than the set value and the gradation difference between the (N + 1) th line data and the (N + 1) The width of the low period of each of the gate output enable signal and the source output enable signal is increased from the initial set value All.

The timing controller determines that one horizontal charge period of the (N + 1) th horizontal line is greater than a second horizontal charge period of the (N + 1) th horizontal line when the gradation difference between the Period of the gate output enable signal and the source output enable signal is maintained at the initial set value.

The timing controller further adjusts the adjusted gate output enable signal and the source output enable signal on the basis of a predetermined weight for each position to further adjust the one horizontal charge period in units of horizontal lines.

Wherein the weight for each position is set to a first value in a first block having the smallest RC delay and a third value greater than the first value in a third block having the largest RC delay, And is set to a second value between the first value and the third value in a second block disposed between the third blocks.

When the gradation differences of the Nth line data and the N + 1th line data in the first to third blocks are equal to each other, the variation width between one horizontal charger that changes from the reference period is smaller than that of the block with a smaller weight per location The weight for each position is larger in a block having a larger weight.

The timing controller controls the total sum of the reduced width and the increased width between one horizontal charger in all the horizontal lines of the liquid crystal display panel to be " 0 "

The timing controller selects the maximum gray level value among data to be written in the liquid crystal cells arranged in the Nth horizontal line as the Nth line data and writes the maximum gray level value into the liquid crystal cells arranged in the (N + 1) And selects the minimum gray level value among the data to be processed as the (N + 1) -th line data.

Wherein the timing controller selects the minimum gray level value of data to be written in the liquid crystal cells arranged in the Nth horizontal line as the Nth line data and writes the minimum gray level value in the liquid crystal cells arranged in the (N + 1) And selects the maximum gradation value among the data to be processed as the (N + 1) -th line data.

A data driver for supplying a data voltage to the data lines; a gate driver for applying a gate pulse synchronized with the data voltages to the gate electrode, The method of driving a liquid crystal display device having a gate driver for sequentially supplying data to lines includes: Nth line data to be written in liquid crystal cells arranged in an Nth (N is a positive integer) horizontal line of the liquid crystal display panel; Calculating a gradation difference between the (N + 1) -th line data to be written in the liquid crystal cells of the (N + 1) -th horizontal line of the liquid crystal display panel; And adjusting one horizontal charge period corresponding to each horizontal line of the liquid crystal display panel by adjusting timing control signals for controlling operation timings of the data driver and the gate driver based on the calculated gray level difference do.

The present invention adjusts the gate output enable signal and the source output enable signal based on the sum of line data applied to neighboring horizontal lines and adjusts one horizontal charge period corresponding to each horizontal line through this adjustment Thus, in one portion where the gradation difference of the data between neighboring horizontal lines is relatively small, one horizontal charging period is reduced as compared with the reference period, while in the portion where the gradation difference of the data between neighboring horizontal lines is relatively large, To the reference period. Further, the present invention further adjusts the adjusted gate output enable signal and the source output enable signal based on a predetermined weight for each position, and further adjusts the one horizontal charging period in units of horizontal lines. Accordingly, the present invention can improve the display quality by reducing the difference in the charging rate of the liquid crystal cells due to the difference in the gradation between the RC delay and the data, thereby greatly increasing the luminance uniformity even at a high resolution and a large screen.

1 is a waveform diagram showing a drop in the data voltage charging rate of a liquid crystal cell due to an RC delay.
2 is a waveform chart showing that one horizontal charge period is set to be the same in all positions of the conventional liquid crystal display panel.
3 shows a double-bank driving circuit of a liquid crystal display device.
4 shows a single bank driving circuit of a liquid crystal display device.
5 is an equivalent circuit diagram showing a part of the TFT array of the display panel shown in Figs. 3 and 4. Fig.
FIG. 6 is a waveform diagram showing a data voltage and a gate pulse applied to the TFT array shown in FIG. 5. FIG.
7 shows a block diagram for adjusting the timing control signal in the timing controller of the present invention.
Fig. 8 shows a driving procedure of the timing controller for adjusting the timing control signal.
9 is a waveform diagram showing an example of first-order adjustment of one horizontal charge period in units of horizontal lines.
10A and 10B show examples in which weights are set differently on a block-by-block basis.
FIG. 11 is a waveform chart showing that the variation width between one horizontal charger is larger in a block having a larger weight than a block having a lower weight.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

3 shows a double bank driving circuit of a liquid crystal display device. 4 shows a single bank driving circuit of a liquid crystal display device.

3 and 4, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 20, data drivers 12, 12A and 12B, and gate drivers 14 and 14A , 14B.

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel includes liquid crystal cells arranged in a matrix form by an intersection structure of the data lines S1 to Sm and the gate lines G1 to Gn. The liquid crystal cells are divided into red (R) sub-liquid crystal cells, green (G) sub-liquid crystal cells and blue (B) sub-liquid crystal cells B as shown in FIG. Each sub-liquid crystal cell includes liquid crystal cells Clc, a TFT, and a storage capacitor Cst.

The liquid crystal cell array in which the input image is displayed in the liquid crystal display panel 10 is divided into a TFT array and a color filter array. A TFT array as shown in Fig. 5 is formed on the lower glass substrate of the liquid crystal display panel 10. Fig. The TFT array includes TFTs connected to the pixel electrodes 1 of the liquid crystal cells Clc, gate lines G1 to Gn crossing the data lines S1 to Sm, data lines S1 to Sm, And a storage capacitor Cst. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel 10, a color filter array including a black matrix, a color filter, and the like is formed. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system.

The liquid crystal display panel 10 applicable to the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 20 supplies the digital video data of the input image input from the host system 30 to the data drivers 12A and 12B. The timing controller 20 receives a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock CLK from the host system 30. The timing controller 20 generates timing control signals for controlling the operation timings of the data drivers 12A and 12B and the gate drivers 14A and 14B based on the timing signals input from the host system 30. [ The timing control signals include a gate timing control signal for controlling the operation time of the gate driver 14, 14A, 14B and a data timing for controlling the operation timing of the data driver 12, 12A, 12B and the vertical polarity of the data voltage And a control signal.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP controls the operation start timing of the gate drive IC (Integrated Circuit) constituting the gate drivers 14, 14A and 14B. The gate shift clock GSC controls the shift timing of the gate pulse by a clock signal commonly input to the gate drive ICs. The gate output enable signal GOE controls the output timing of the gate drive ICs.

The data timing control signal includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, a source output enable signal SOE, and the like. The source start pulse SSP controls the data sampling start timing of the source drive ICs constituting the data drivers 12, 12A and 12B. The source sampling clock SSC is a clock signal for controlling the sampling timing of data in each of the source drive ICs. The source output enable signal SOE controls the output timing of the data drivers 12, 12A, and 12B. The source start pulse SSP and the source sampling clock SSC may be omitted if the interface for signal transmission between the timing controller 20 and the data drivers 12, 12A and 12B is mini LVDS (Low Voltage Differential Signaling) .

The timing controller 20 compares data of neighboring horizontal lines in the liquid crystal display panel 10 as shown in FIG. 8, calculates a difference in gradation of the data, and outputs a gate output corresponding to each horizontal line The operation timing of the data driving circuits 12, 12A, and 12B and the gate driving circuits 14, 14A, and 14B is controlled by first adjusting the enable signal GOE and the source output enable signal SOE. The timing controller 20 secondarily adjusts the first-order adjusted gate output enable signal GOE and the source output enable signal SOE in accordance with the predetermined weight by position in accordance with each horizontal line, 12, 12A, 12B and the gate drive circuits 14, 14A, 14B can be further controlled. The timing controller 20 adjusts one horizontal charge period corresponding to each horizontal line through adjustment of the gate output enable signal GOE and the source output enable signal SOE. Accordingly, the timing controller 20 can reduce the difference in the charging rate of the liquid crystal cells due to the difference between the RC delay and the data gradation. One horizontal charge period 1HC is the time allocated for charging the liquid crystal cells arranged on one horizontal line.

The data driver 12, 12A, 12B includes one or more source drive ICs. Each of the source drive ICs includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The source drive IC latches the digital video data (RGB DATA) under the control of the timing controller 20. The source drive ICs convert the digital video data to an analog positive / negative gamma compensation voltage to generate a data voltage and invert the polarity of the data voltage in response to the polarity control signal POL. The source drive ICs output the data voltage to the data lines S1 to Sm in response to the source output enable signal SOE. These source driver ICs apply a first polarity (+) data voltage to the odd-numbered data lines S1, S3, ..., Sm-1 during the Nth frame period (N is a positive integer) Supplies data voltages of the second polarity (-) to the even-numbered data lines S2, S2, ..., Sm, and inverts the polarity of the data voltage in the (N + 1) -th frame period. Therefore, the source drive ICs of the present invention maintain the same polarity of the data voltage supplied to the same data line during one frame period and invert the polarity of the data voltage in the next frame period, Since the current consumption is smaller than that of drive ICs, power consumption and heat generation can be reduced.

The gate drive ICs of the gate driver 14, 14A, 14B include a shift register and a level shifter. The gate drivers 14A and 14B sequentially supply gate pulses to the gate lines G1 to Gn in synchronization with the data voltage in response to the gate timing control signal.

The host system 30 may be implemented in any one of a television system, a home theater system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), and a phone system. The host system 30 scales the digital video data of the input image according to the resolution of the liquid crystal display panel 10. The host system 30 transmits the timing signals Vsync, Hsync, DE, and MCLK to the timing controller 20 together with the digital video data RGB of the input image.

The double bank driving circuit shown in FIG. 3 includes a first data driver 12A disposed at the upper end of the liquid crystal display panel 10, a second data driver 12B disposed at the lower end of the liquid crystal display panel 10, A first gate driving part 14A disposed on the left side of the panel 10 and a second gate driving part 14B disposed on the left side of the liquid crystal display panel 10. [ The first data driver 12A supplies data voltages to the data lines S1 to Sm through data pads connected to the upper ends of the data lines S1 to Sm. The second data driver 12B supplies data voltages to the data lines S1 to Sm through data pads connected to the lower ends of the data lines S1 to Sm. The first and second data drivers 12A and 12B operate simultaneously under the control of the timing controller 20 to simultaneously supply data voltages to both the data lines S1 to Sm, Compensate for RC delay. The first gate driver 14A supplies a gate pulse synchronized with the data voltage to the gate lines G1 through Gn through gate pads connected to the left ends of the gate lines G1 through Gn. The second gate driver 14B supplies a gate pulse synchronized with the data voltage to the gate lines G1 to Gn through gate pads connected to the right ends of the gate lines G1 to Gn. The first and second gate drivers 14A and 14B operate simultaneously under the control of the timing controller 20 to supply gate pulses at both the gate lines G1 to Gn at the same time, Compensate for RC delay. This double bank driving circuit can compensate the RC delay to reduce the charging rate deviation of the liquid crystal cells Clc. However, since the number of ICs required to implement the double bank driving circuit is larger than that of the single bank implementing circuit of FIG. 4 Resulting in an increase in the cost of the liquid crystal display device.

4 includes a data driver 12 disposed at the upper or lower end of the liquid crystal display panel 10 and a gate driver 14 disposed at the left or right of the liquid crystal display panel 10. The single- Since the single-bank driving circuit supplies the data voltage through one end of the data lines and supplies the gate pulse through one end of the gate lines, an RC delay increases as the data lines move to the other end and to the other end of the gate lines The data voltage charging rate of the liquid crystal cells is lowered. On the other hand, since the number of necessary ICs in the single bank driver circuit is smaller than that of the double bank driver circuit, the unit cost of the liquid crystal display device can be reduced. Such a single-bank driving circuit is mainly applied to a liquid crystal display device of a medium and small size in the prior art.

The driving circuit of the liquid crystal display of the present invention may be implemented by a combination of the single bank data driver 12 and the double bank gate drivers 14A and 14B. The present invention, which is intended for a large-screen and high-resolution liquid crystal display device, controls the charging rate of liquid crystal cells at a similar level throughout the screen by applying the driving method described below.

5 is an equivalent circuit diagram showing a part of the TFT array of the display panel shown in Figs. 3 and 4. Fig. FIG. 6 is a waveform diagram showing a data voltage and a gate pulse applied to the TFT array shown in FIG. 5. FIG.

5 and 6, the odd-numbered horizontal lines L (N) and L (N + 2) of the liquid crystal display panel 10 are connected to the pixel electrodes As shown in FIG. The even horizontal lines L (N + 1) of the liquid crystal display panel 10 include TFTs connected to the pixel electrodes disposed on the left side of the data lines S1 to S6. Therefore, the TFTs connected to one data line along the vertical direction (the y-axis direction of FIG. 3 and FIG. 4) are alternately connected to the left and right sides of the data line and arranged in a zigzag form.

The source drive ICs of the data drivers 12, 12A and 12B supply the data voltages of the first polarity to the odd-numbered data lines S1, S3, ..., and Sm-1 during one frame period, And supplies the data voltages of the second polarity to the lines S2, S2, ..., Sm. Therefore, the polarity of the data voltage continuously supplied to one data line during one frame period maintains the same polarity. If data voltages of the same polarity are supplied to one data line in one frame period, the neighboring liquid crystal cells in the horizontal direction (x-axis direction in FIG. 3 and FIG. 4) To charge the data voltage having the opposite polarity. Here, one dot means one sub-liquid crystal cell or one liquid crystal cell. Further, adjacent liquid crystal cells in the vertical direction (y-axis direction in FIGS. 3 and 4) are charged with data voltages whose polarities are opposite to each other in one dot unit due to the zigzag arrangement of the TFTs. Therefore, the source drive ICs of the data drivers 12, 12A, and 12B reverse the polarities of the data voltages in a column-inversion manner, and the liquid crystal cells of the liquid crystal display panel 10 emit data voltages that are inverted by one- Charge.

FIG. 7 shows a block diagram for adjusting the timing control signals GOE and SOE in the timing controller of the present invention. 8 shows a driving procedure of the timing controller for adjusting the timing control signals GOE and SOE. 9 is a waveform diagram showing an example of first-order adjustment of one horizontal charge period in units of horizontal lines. 10A and 10B show examples in which weights are set differently on a block-by-block basis. FIG. 11 is a waveform chart showing that the variation width between one horizontal charger is larger in a block having a larger weight than a block having a lower weight.

7 and 8, the timing controller 20 includes a memory 21, a data comparing unit 22, a control signal adjusting unit 23, and the like, for adjusting the timing control signals GOE and SOE .

The data comparing unit 22 compares the Nth line data stored in the memory 21 with the (N + 1) th line data and calculates the difference in gradation between the Nth line data and the (N + 1) th line data. N line data is data to be written in the liquid crystal cells arranged in the Nth horizontal line L (N), and the (N + 1) th line data is data to be written in the (N + 1) th horizontal line L Data to be written in the liquid crystal cells.

There are various methods for data comparison. The data comparison method can compare the representative values of the line data. Here, the representative values of the line data include the N-th line representative value and the representative value of the (N + 1) -th line data.

The representative value can be selected as the maximum gradation value and the minimum gradation value. For example, the N-th line representative value may be selected as the maximum gradation value of the data constituting the N-th line data, and the (N + 1) -th line representative value may be selected as the minimum gradation value . ≪ / RTI > On the contrary, the N-th line representative value can be selected as the minimum gradation value of the data constituting the N-th line data, and the (N + 1) -th line representative value can be selected as the maximum gradation value . ≪ / RTI >

On the other hand, the representative value may be selected as an average value or a mode value. For example, the N-th line representative value may be selected as an average value or a mode value of data constituting the N-th line data. The (N + 1) -th line representative value may be selected as an average value or a mode value of data constituting the (N + 1) -th line data.

The data comparator 22 calculates the gray level difference between the Nth line data and the (N + 1) th line data with respect to all the horizontal lines of the liquid crystal display panel 10 during one frame (S22)

The control signal adjusting unit 23 first adjusts the gate output enable signal GOE and the source output enable signal SOE corresponding to each horizontal line based on the gradation difference calculated by the data comparing unit 22 9, one horizontal charging period is adjusted in units of horizontal lines (S23). In FIG. 9, X1 to X6 indicate one horizontal charging period of the first horizontal line to the sixth horizontal line, respectively. X1 to X6 correspond to on-times of the first to sixth gate pulses supplied to the first to sixth gate lines G1 to G6, respectively. In Fig. 9, "a1, b1, c1, d1, e1" indicates the variation width between one horizontal charger.

The control signal adjusting section 23 sets one horizontal charge period of the horizontal line (the first and nth horizontal lines in Fig. 3 and the first horizontal line in Fig. 4) as the reference period Tref having the smallest RC delay. 9). Here, the reference period Tref corresponds to a value obtained by dividing one frame period by the vertical resolution.

When the gradation difference between the (N + 1) th line data and the (N + 1) th line data falls within the first range, the control signal adjusting unit 23 adjusts the horizontal charging period of the (L) width of the gate output enable signal GOE and the source output enable signal SOE to be smaller than the initial value Tref. Referring to X2 and X3 in FIG. 9, it can be seen that X2 is reduced by "a1" compared to the reference period Tref, and X3 is reduced by "b1" compared to the reference period Tref.

On the other hand, when the gradation difference between the Nth line data and the (N + 1) th line data falls within the second range which is the largest, the control signal adjusting unit 23 adjusts the horizontal charge period of the The width of the low period (L) of the gate output enable signal GOE and the source output enable signal SOE is increased beyond the initial set value so as to be longer than the reference period. Referring to X4 to X6 in Fig. 9, X4 is equal to "c1" compared to the reference period Tref, X5 is equal to "d1" relative to the reference period Tref, and X6 is equal to "e1 "As shown in FIG.

On the other hand, when the gradation difference between the (N + 1) th line data and the (N + 1) th line data falls within the first range and the second range, (L) width of the gate output enable signal GOE and the source output enable signal SOE to be maintained at the initial setting.

The control signal adjusting unit 23 secondarily adjusts the first-adjusted gate output enable signal GOE and the source output enable signal SOE with reference to the previously set weights as shown in FIGS. 10A and 10B One horizontal charge period is further adjusted in units of horizontal lines (S24).

The weight for each position can be set as shown in FIG. 10A corresponding to the double bank driving circuit shown in FIG. 3, and can be set as shown in FIG. 10B corresponding to the sink bank driving circuit shown in FIG. In FIG. 10A, the position-weighted value is a value obtained by multiplying the first value w1 in the first block BL1 with the smallest RC delay by the third value BL1 in the third block BL3 having the largest RC delay, (W1) and the third value (w3) in a second block (BL2) arranged between the first block (BL1) and the third block (BL3) (W2) < / RTI > of < / RTI > In FIG. 10B, the weight for each position is the first value w1 in the first and sixth blocks BL1 and BL6 having the smallest RC delays, and the third and fourth blocks BL3 and BL4 having the largest RC delay The second block BL2 arranged between the first and third blocks BL1 and BL3 and the fourth and sixth blocks BL4 and BL2 are arranged at a third value w3 larger than the first value w1, And a second value w2 between the first value w1 and the third value w3 in a fifth block BL5 arranged between the first value w1 and the second value w2.

When the gradation differences of the Nth line data and the (N + 1) th line data are equal to each other in the weighting blocks of FIG. 10A or 10B, the change width between one horizontal charger, which is changed from the reference period Tref, Is larger in large blocks. For example, when the gradation difference between the Nth line data and the (N + 1) th line data is the same in the first and third blocks BL1 and BL3 as shown in FIG. 11, (y2) is larger than the variation width (y1) between one horizontal charger in the first block (BL1). "A1, b1, c1, d1, e1" in Fig. 9 depend on the weighting block.

The frame rate and the frame period are fixed. Therefore, when one horizontal charge period is increased when the difference in gradation between neighboring line data is large, one frame period may be insufficient to charge all the horizontal lines. In consideration of this, according to the present invention, by making the total sum of the reduced variation and the increased variation between one horizontal charger to the reference period (Tref) in all horizontal lines be " 0 " Can be charged.

delete

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 12, 12A, 12B:
14, 14A, 14B: Gate driver 20: Timing controller

Claims (20)

A liquid crystal display panel in which data lines and gate lines are crossed and liquid crystal cells are arranged in a matrix type;
A data driver for supplying a data voltage to the data lines;
A gate driver sequentially supplying a gate pulse synchronized with the data voltages to the gate lines; And
A plurality of Nth line data to be written in liquid crystal cells arranged in an Nth (N is a positive integer) horizontal line of the liquid crystal display panel and a plurality of Nth line data to be written in liquid crystal cells in an And the timing control signals for controlling the operation timings of the data driver and the gate driver are adjusted based on the gradation difference between a plurality of (N + 1) -th line data to be supplied to one horizontal charging period corresponding to each horizontal line of the liquid crystal display panel And a timing controller which adjusts the timing of the timing signal,
The timing controller includes:
And comparing the first representative value selected from the plurality of the Nth line data with a second representative value selected from the plurality of (N + 1) -th line data, and comparing the gradation difference between the Nth line data and the (N + 1) Respectively,
Wherein a horizontal charging period of the horizontal line having the smallest RC delay is set as a reference period in the liquid crystal display panel and a total sum of the reduced variation between one horizontal charger and the extended variation in all the horizontal lines of the liquid crystal display panel And the horizontal charge period corresponding to each horizontal line is adjusted to be " 0 ". The method according to claim 1,
Wherein the timing control signals include a gate output enable signal for controlling an output timing of the gate driving unit and a source output enable signal for controlling an output timing of the data driving unit. 3. The method of claim 2,
The timing controller includes:
When the gradation difference between the (N + 1) th line data and the (N + 1) th line data falls within the first range, the horizontal charging period of the (N + 1) th horizontal line is reduced in comparison with the reference period in proportion to the gradation difference The width of the low period of each of the gate output enable signal and the source output enable signal is set to be smaller than the initial set value,
When the gradation difference between the (N + 1) -th line data and the (N + 1) -th line data belongs to the second range which is the largest, the one horizontal charge period of the (N + 1) And the width of the low period of each of the gate output enable signal and the source output enable signal is set to be larger than the initial set value. The method of claim 3,
The timing controller includes:
And a horizontal charging period of the (N + 1) th horizontal line is maintained in the reference period when a gradation difference between the Nth line data and the (N + 1) th line data falls between the first range and the second range. And maintains a low period width of each of the gate output enable signal and the source output enable signal at the initial set value. The method of claim 3,
The timing controller includes:
And further adjusts the adjusted gate output enable signal and the source output enable signal based on a preset weight for each position to further adjust the one horizontal charge period in units of horizontal lines. 6. The method of claim 5,
The position-
The RC delay is set to the first value in the smallest first block, the RC delay is set to the third value larger than the first value in the third block having the largest RC delay, and the third block is arranged between the first block and the third block And the second value is set to a second value between the first value and the third value in the second block. The method according to claim 6,
When the gradation differences of the Nth line data and the N + 1th line data in the first to third blocks are equal to each other, the variation width between one horizontal charger that changes from the reference period is smaller than that of the block with a smaller weight per location Wherein the weight of each position is larger in a block having a larger weight. delete The method according to claim 1,
The timing controller includes:
A first gray level value of data to be written in the liquid crystal cells arranged in the Nth horizontal line is selected as the first representative value of the Nth line data, And selects the minimum gray-scale value among the data to be written as the second representative value of the (N + 1) -th line data. The method according to claim 1,
The timing controller includes:
Selecting the minimum gray scale value among data to be written in the liquid crystal cells arranged on the Nth horizontal line as the first representative value of the Nth line data, And selects the maximum gradation value among the data to be written as the second representative value of the (N + 1) -th line data. A liquid crystal display panel in which data lines and gate lines are crossed and liquid crystal cells are arranged in a matrix type, a data driver for supplying a data voltage to the data lines, a gate driver for synchronizing a gate pulse, And a gate driver for sequentially supplying the driving signal to the gate driver,
A plurality of Nth line data to be written in liquid crystal cells arranged in an Nth (N is a positive integer) horizontal line of the liquid crystal display panel and a plurality of Nth line data to be written in liquid crystal cells of an (N + 1) th horizontal line of the liquid crystal display panel Calculating gradation differences between a plurality of (N + 1) -th line data; And
Adjusting timing control signals for controlling the operation timings of the data driver and the gate driver based on the calculated gradation difference to adjust one horizontal charge period corresponding to each horizontal line of the liquid crystal display panel ,
Wherein the step of calculating the gradation difference between the plurality of Nth line data and the plurality of (N + 1) -th line data comprises: calculating a gradation difference between the first representative value selected from the plurality of Nth line data and the Further comprising comparing the selected second representative value,
Wherein the step of adjusting one horizontal charge period corresponding to each horizontal line of the liquid crystal display panel includes the steps of setting one horizontal charge period of a horizontal line having the smallest RC delay in the liquid crystal display panel as a reference period, Further comprising the step of adjusting one horizontal charging period corresponding to each horizontal line so that the total sum of the decreased variation and the increased variation between one horizontal charger in the entire horizontal lines of the reference period is " 0 " A method of driving a liquid crystal display device.


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