KR102316566B1 - Orgainc light emitting diode display device and timing tuning method thereof - Google Patents

Abstract

The present invention provides an organic light emitting diode display capable of compensating for a data charge amount deviation by sensing a data charge amount and appropriately setting an output period of a data signal according to a position of a sub-pixel, and a timing setting method thereof.
The OLED display device according to an embodiment senses a data charge amount of a subpixel for each of a plurality of regions through data ICs, and outputs each source that individually controls a data output period of the data ICs while checking the sensed data charge amount and a timing controller for setting an enable period of the enable signal.

Description

Organic light emitting diode display device and method for setting timing thereof

The present invention relates to an organic light emitting diode display capable of appropriately setting an output period of a data signal according to a position of a sub-pixel by sensing a data charge amount, and a timing setting method thereof.

Recently, as a display device that displays an image using digital data, a liquid crystal display (LCD) using liquid crystal, an OLED display using an organic light emitting diode (OLED), and electrophoretic particles are used. An electrophoretic display (EPD), etc. used is a representative example.

Among them, the OLED display device is a self-luminous device that emits light from an organic light emitting layer by recombination of electrons and holes, and is expected as a next-generation display device because of its high luminance, low driving voltage, and ultra-thin film formation.

In the OLED display device, each sub-pixel includes an OLED element and a pixel circuit independently driving the OLED element. Each sub-pixel receives the data signal supplied to the corresponding data line from the data driver through a switching thin film transistor (TFT) during the scan period when the scan pulse is supplied to the corresponding gate line from the gate driver, and stores data in the storage capacitor. The driving voltage Vgs corresponding to the signal is charged. Each sub-pixel adjusts the brightness of the OLED device by controlling the current Ids at which the driving TFT drives the OLED device according to the charged driving voltage Vgs.

As OLED display devices become higher-resolution and larger, the RC delay of the gate signal due to the line resistance (R) and the capacitor (C) is increasing. Accordingly, since the data filling rate is different due to the delay deviation of the gate signal according to the position of the sub-pixel, a luminance deviation problem occurs.

In order to solve this problem, there is a need for a method of compensating for a data charge rate deviation due to the delay of the gate signal by adjusting the timing of a source enable signal (SOE) that determines the output period of the data signal according to the position of the sub-pixel. .

At this time, since the timing and delay of the gate/data signal are different according to panel characteristics such as the size or model of the display device, it is necessary to set the timing of the SOE signal appropriately according to the position of the subpixel in accordance with the panel characteristics.

In addition, since the delay of the gate/data signal may fluctuate due to the temperature fluctuation of the display device, it is necessary to appropriately adjust the timing of the SOE signal according to the position of the subpixel in accordance with the temperature characteristic.

The present invention provides an organic light emitting diode display capable of compensating for a data charge amount deviation by sensing a data charge amount and appropriately setting an output period of a data signal according to a position of a sub-pixel, and a timing setting method thereof.

An OLED display device according to an embodiment includes data ICs for dividing and driving a display panel, a gate driver, and a pixel array into a plurality of regions, and sensing a data charge amount of a subpixel in each of the plurality of regions through the data ICs; and a timing controller that sets an enable period of each source output enable signal that individually controls a data output period of the data ICs while checking a sensed data charge amount.

Each data IC senses the current supplied from the driving TFT according to the sensing data voltage charged in the storage capacitor of each sub-pixel during the scan period, and converts the sensing result into a sensed value of the data charge of each sub-pixel and provides it to the timing controller. .

The timing controller drives a first region close to the gate driver, and uses the first data IC controlled by the first source output enable signal to respond to the first values of the sensed data charge amount sensed from the subpixels of the first region. Calculate the average value. The timing controller drives the second region and senses from the subpixels of the second region while adjusting the enable period of the second source output enable signal through the second data IC controlled by the second source output enable signal. A second average value of the sensed data charge amount is calculated. The timing controller sets an enable period in which the second average value falls within the same range as the first average value as an enable period of the second source output enable signal. The timing controller sets the enable period of the source output enable signal for each of the data ICs other than the first and second data ICs among the data ICs through the same process as that of the second data IC.

When the timing controller determines that it is necessary to adjust the timing of the data output period because the temperature sensed by the temperature sensor fluctuates, the timing controller checks the data charge amount sensed value of the corresponding area through each of the data ICs and outputs the source for each of the data ICs. Adjust the enable period of the enable signal.

According to an exemplary embodiment, the data charging characteristics of sub-pixels are sensed and checked through the data IC when timing is set according to characteristics such as the size of the display panel, and the output period of the data signal (the enable period of the SOE signal) for each data IC is facilitated. can be set. Accordingly, the luminance uniformity may be improved by compensating for the data charge amount deviation due to the delay of the gate/data signal.

According to an embodiment, even when the timing of the gate/data signal is changed according to the temperature fluctuation due to the surrounding environment or the driving of the display device, the data charging characteristic is sensed and checked through the data IC while the output period (SOE) of the data signal for each data IC is checked. By appropriately adjusting the enable period of the signal), the luminance uniformity can be improved by compensating for the data charge amount deviation.

1 is a block diagram schematically showing the configuration of an OLED display device according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram illustrating the configuration of the sub-pixel shown in FIG. 1 .
3 is a diagram schematically illustrating the configuration of an OLED display device for SOE timing tuning according to an embodiment of the present invention.
4 is a diagram schematically illustrating a relationship between a gate delay and an enable magnitude of a source output enable (SOE) signal in an OLED display according to an exemplary embodiment.
5 is a flowchart illustrating a method for setting SOE timing in an OLED display according to an embodiment of the present invention in stages.
6 is a diagram schematically illustrating a characteristic in which an enable period of an SOE signal according to a position of a sub-pixel is adjusted according to a temperature in an OLED display device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram schematically showing the configuration of an OLED display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram illustrating the configuration of one sub-pixel shown in FIG. 1 .

Referring to FIG. 1 , an OLED display according to an exemplary embodiment includes a display panel 100 , a gate driver 200 , a data driver 300 , a timing controller 400 , a memory 500 , a power supply unit 600 , and a temperature. sensor 700 and the like.

The display panel 100 displays an image through a pixel array in which sub-pixels SP are arranged in a matrix form. The basic pixel may be composed of at least three sub-pixels capable of expressing white by color mixing among white (W), red (R), green (G), and blue (B) sub-pixels. For example, a basic pixel is subpixels in R/G/B combination, subpixels in W/R/G combination, subpixels in B/W/R combination, subpixels in combination G/B/W or may be composed of sub-pixels of a W/R/G/B combination.

Referring to FIG. 2 , each subpixel SP is disposed between a high potential driving voltage (first driving voltage; hereinafter EVDD) line PW1 and a low potential driving voltage (second driving voltage; hereinafter EVSS) line PW2. A pixel circuit including at least the connected OLED element 10 and first and second switching TFTs ST1 and ST2 and a driving TFT DT and a storage capacitor Cst for independently driving the OLED element 10 . to provide Meanwhile, various configurations different from the configuration of FIG. 2 may be applied to the pixel circuit.

The switching TFTs ST1 and ST2 and the driving TFT DT may be an amorphous silicon (a-Si) TFT, a poly-Si TFT, an oxide TFT, or an organic TFT. have.

The OLED element 10 includes an anode connected to the source node N2 of the driving TFT DT, a cathode connected to the EVSS line PW2, and an organic light emitting layer between the anode and the cathode. The anode is independent for each subpixel, but the cathode may be a common electrode shared by all subpixels. In the OLED device 10, when a driving current is supplied from the driving TFT (DT), electrons from the cathode are injected into the organic emission layer, and holes from the anode are injected into the organic emission layer. By emitting the phosphor material, light having a brightness proportional to the current value of the driving current is generated.

The first switching TFT ST1 is driven by the first gate signal SCAN supplied from the gate driver 200 to the first gate line GLn1 and supplied from the data driver 300 to the data line DL. The data voltage Vdata is supplied to the gate node N1 of the driving TFT DT.

The second switching TFT ST2 is driven by the second gate signal SENSE supplied from the gate driver 200 to the second gate line GLn2 and supplied from the data driver 300 to the reference line REF. The reference voltage Vref is supplied to the source node N2 of the driving TFT DT. Also, when each subpixel SP is driven in the sensing mode, the second switching TFT ST2 outputs the current supplied from the driving TFT DT to the reference line REF in a floating state.

The storage capacitor Cst connected between the gate node N1 and the source node N2 of the driving TFT DT is connected to the gate node (ST1, ST2) through the first and second switching TFTs ST1 and ST2 turned on during the scan period. The difference voltage between the data voltage Vdata and the reference voltage Vref supplied to N1) and the source node N2, respectively, is charged to the driving voltage Vgs of the driving TFT DT, and the first and second switching TFTs ( The charged driving voltage Vgs is held during the light emission period when ST1 and ST2 are turned off.

The driving TFT DT controls the current supplied from the EVDD line PW1 in accordance with the driving voltage Vgs supplied from the storage capacitor Cst to transmit the driving current determined by the driving voltage Vgs to the OLED device 10 . By supplying, the OLED element 10 is made to emit light.

In the mode of sensing the characteristics of the driving TFT DT, the driving TFT DT applies the sensing data voltage Vdata supplied from the data driver 300 through the data line DL to the first switching TFT ST1. supplied and driven through The current of the driving TFT DT in which the driving characteristic (Vth, mobility) of the driving TFT DT is reflected is charged to a voltage in the line capacitor of the reference line REF through the second switching TFT ST2, and the data driver 300 ) is sensed by

In addition, in the mode of sensing the data charge amount of each subpixel SP, sensing supplied from the data driver 300 through the data line DL during the scan period of the first and second gate signals SCAN and SENSE The data voltage Vdata for the storage capacitor Cst is charged, and the current of the driving TFT DT determined according to the charged voltage (data charge amount) is transferred to the data through the second switching TFT ST2 and the reference line REF. By sensing the voltage by the driver 300 , the data charge amount determining the current of each sub-pixel SP may be sensed.

The gate driver 200 receives a gate control signal from the timing controller 400 to drive a plurality of gate lines of the display panel 100 . The gate driver 200 supplies a gate-on voltage pulse to the corresponding gate line in the driving period of each gate line, and supplies the gate-off voltage in the non-driving period. The gate driver 200 is disposed on both sides of the display panel 100 , and the gate signal delay can be reduced by simultaneously supplying the gate signal from both sides of each gate line.

The gate driver 200 includes a plurality of gate ICs (Integrated Circuits) for dividingly driving the gate lines, and each gate IC is individually mounted on a circuit film such as a COF (Chip On Film) to form a part of the display panel 100 . It can be attached to the side or both sides. Alternatively, the gate driver 200 may be formed in a GIP (Gate In Panel) type that is directly formed in the non-display area of the substrate together with the TFT array of the pixel array of the panel 100 and is embedded in the panel 100 .

The data driver 300 converts the data supplied from the timing controller 400 into an analog data voltage by using the data control signal supplied from the timing controller 400 , and supplies the data voltage to the display panel 100 . The data driver 300 converts digital data into analog data voltages using the gamma voltage for each gray level supplied from the gamma voltage generator.

When the data driver 300 is in the sensing mode under the control of the timing controller 400 , the data voltage for sensing is supplied to the data line to drive each sub-pixel, and the driving characteristics or data charge amount of the driven sub-pixel SP The pixel current representing the characteristic is sensed as a voltage through the reference line REF, and converted into digital sensing information (sensed data) and provided to the timing controller 400 .

The data driver 300 includes a plurality of data ICs that divide and drive data lines, and each data IC may be mounted on each circuit film and attached to the display panel 100 .

Compensation information for each sub-pixel to be used by the timing controller 400 may be stored in the memory 500 and updated through a sensing mode. For example, the compensation information of each sub-pixel includes a mobility compensation value of each sub-pixel for compensating for a mobility deviation of the driving TFT between sub-pixels, a Vth compensation value of each sub-pixel for compensating the Vth of the driving TFT, etc. may include.

The timing controller 400 receives image data and basic timing control signals from an external system. The system may be any one of a computer, a TV system, a set-top box, a system of a portable terminal such as a tablet or a mobile phone. The basic timing control signals may include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

The timing controller 400 controls the driving timings of the data driver 300 and the gate driver 200 using basic timing control signals supplied from the outside and timing setting information (start timing, pulse width, etc.) stored in an internal register, respectively. Data control signals and gate control signals for controlling are generated and supplied.

For example, the gate control signals include a gate start pulse (GSP) and a gate shift clock (GSC) that control a scan operation of the gate driver 200 and a gate signal that determines an output period of the gate signal. gate output enable (GOE); and the like. The data control signals are a source start pulse (SSP) and a source shift clock (SSC) that control the shift register operation in the data driver 300 , and a source output that determines the data output period of the output buffer unit. and an enable (Source Output Enable; SOE) signal and the like.

The timing controller 400 compensates image data to be supplied to each sub-pixel SP using a compensation value stored in the memory 500 , and supplies the compensated image data to the data driver 300 . The timing controller 400 may further perform various image processing for compensating for deterioration of the OLED device, reducing power consumption, and the like.

In the sensing mode, the timing controller 400 controls the OLED display device to operate in the sensing mode, senses driving characteristics of each subpixel of the display panel 100 through the data driver 300 and uses the sensing result. Accordingly, the compensation value for each sub-pixel stored in the memory 500 may be updated.

For example, the timing controller 400 may sense a linear section in which the source voltage is increased by driving the driving TFT in each subpixel to update the mobility compensation value of each subpixel stored in the memory 500 . The fast sensing mode for updating the mobility compensation value may be mainly allocated to the power-on period and the vertical blank period of each frame during the display period. The timing controller 400 may sense a voltage at which the source voltage is saturated by driving the driving TFT in each subpixel to update the Vth compensation value of each subpixel stored in the memory 500 . A slow sensing mode for updating the Vth compensation value may be mainly allocated to a power-off period.

In particular, the timing controller 400 senses and confirms the data charge amount of each sub-pixel through the data driver 300 when setting the initial timing suitable for characteristics such as the size of the display device before shipment of the product, and checks the data charge amount of each sub-pixel according to the position of the sub-pixel. The timing (start timing, pulse width) of the SOE signal can be set and stored in the internal register. Accordingly, the enable period of the SOE signal (the output period of the data signal) may be set according to the data charging characteristic according to the position of the subpixel.

In addition, when it is determined that timing adjustment is necessary according to the temperature characteristic of the display device sensed by the temperature sensor 700 after product shipment, the timing controller 400 operates the OLED display device in a sensing mode for sensing the amount of data charge. By controlling the timing of the SOE signal while sensing and checking the data charge amount of each sub-pixel through the data driver 300 , the enable period of the SOE signal (the output period of the data signal) may be adjusted according to the temperature characteristic.

The temperature sensor 700 senses the ambient temperature and the temperature of the display device according to the lapse of driving time of the OLED display device, and supplies temperature information to the timing controller 400 .

When the timing controller 400 determines that timing adjustment is necessary because the sensing temperature of the display device rises or falls through the temperature sensor 700 , the timing controller 400 senses the data charge amount through the data driver 300 to control the SOE signal stored in the register. You can modify the timing.

For example, when the sensing temperature of the display device falls within a high temperature range (over 40 degrees Celsius) higher than room temperature, the delay of a gate signal or data signal increases, and the sensing temperature of the display device falls within a low temperature range (below zero) lower than room temperature. In this case, the delay of the gate signal or the data signal is reduced.

In consideration of the delay according to the temperature characteristic, the timing controller 400 increases the output period of the data signal by increasing the enable period of the SOE signal from that in the room temperature range so that the data charge amount is not insufficient when the sensing temperature is in the high temperature range. can do it The timing controller 400 may reduce the enable period of the SOE signal when the sensing temperature is in the low temperature range compared to when the sensing temperature is in the room temperature range.

The power supply unit 600 generates and outputs various driving voltages (EVDD, EVSS, etc.) required for the timing controller 400 , the gate driver 200 , the data driver 300 , the display panel 100 , and the like by using the input voltage. . For example, the power supply unit 600 may include the driving voltages EVDD and EVSS and the reference voltage Vref supplied to the display panel 100 through the data driver 300 , the data driver 300 , the timing controller 400 , and the like. A driving voltage of a digital circuit supplied, a driving voltage of an analog circuit supplied to the data driver 300 , a gate-on voltage (gate high voltage) and a gate-off voltage (gate low voltage) used in the gate driver 200 are generated. can be supplied.

3 is a diagram schematically showing the configuration of an OLED display device for timing setting of an SOE signal according to an embodiment of the present invention, and FIG. 4 is a diagram illustrating gate delay and source output enable ( SOE) is a diagram schematically illustrating a relationship between enable magnitudes of signals.

Referring to FIG. 3 , the gate driver 200 includes a plurality of gate ICs G#1 to G#n for dividing and driving the gate lines of the display panel 100 . The plurality of gate ICs G#1 to G#n are individually mounted on the COF 210 and attached to both sides of the display panel 100, and simultaneously supply gate signals from both ends of each gate line.

The data driver 300 includes a plurality of data ICs D#1 to D#2m for dividing and driving data lines of the display panel 100 . A plurality of data ICs (D#1 to D#2m) are individually mounted on the COF 310 and attached to one side of the display panel 100 as well as on one side of the source printed circuit board (PCB) 320 . is attached

The timing controller 400 is mounted on the control PCB 410 . The data ICs (D#1 to D#2m) are timing via a flexible flat cable (FFC) connected between the source PCB 320 and the control PCB 410 and the source PCB 320 and the control PCB 410 . It is connected to the controller 400 .

The timing controller 400 generates and individually supplies SOE1 to SOE2m signals for each of the plurality of data ICs D#1 to D#2m by using source timing information stored in a register for each data IC. Each of the plurality of data ICs D#1 to D#2m outputs a data signal to a corresponding region during an enable period determined by each of the SOE1 to SOE2m signals individually supplied from the timing controller 400 .

The pixel array of the display panel 100 includes a plurality of areas A1 to A2m driven and sensed by each of the plurality of data ICs D#1 to D#2m. In the display panel 100 , as shown in FIG. 4 , the RC of the gate line goes from the side regions A1 and A2m close to the gate ICs G#1 to G#n toward the center region Am and Am+1. As the delay D is gradually increased, the rising and falling timings of the gate signal are gradually increased.

In order to compensate for the deviation of the data charge amount due to the gate delay, the data driving IC D#1 that drives both side regions A1 and A2m close to the gate ICs G#1 to G#n in the display panel 100 . , D#2m) from the SOE1 and SOE2m signals, respectively, to the SOEm and SOEm+1 signals of the data driving ICs (D#m, D#m+1) driving the center area (Am, Am+1). The enable period is set to gradually increase as shown in FIG. 4 . An enable period of SOE1 to SOEm for each of the first to m-th data driving ICs D#1 to D#m for driving the first to m-th regions A1 to Am, respectively, and the 2m-th to m+ The enable periods of SOE2m to SOEm+1 for each of the 2m to m+1th data driving ICs D#2m to D#m+1 respectively driving the first regions A2m to Am+1 are symmetrical with each other. can have size. Accordingly, as the output period of the data signal gradually increases from the both sides A1 and A2m to the center area Am and Am+1, the data charge amount deviation due to the gate delay may be compensated.

When setting the timing, when the temperature changes, the timing controller 400 senses and checks the data charge amount through the data ICs D#1 to D#2m, and outputs a source suitable for each of the data ICs D#1 to D#2m By setting the timing of the enable signals SOE1 to SOE2m, the enable period of the SOE signal can be set for each IC.

The timing controller 400 may set the data output period of the SOE signal to gradually increase as it moves away from the gate IC based on the data output period of the SOE signal of the data IC close to the gate ICs G#1 to G#n. . Accordingly, as shown in FIG. 4 , as the RC delay of the gate signal increases according to the position of the subpixel, the enable period (data output period) of the SOE signal is increased to compensate for the data charge amount deviation.

5 is a flowchart illustrating a step-by-step method for tuning the timing of an SOE signal in an OLED display device according to an embodiment of the present invention.

When setting the initial timing before shipment of the product, the timing controller 400 according to an exemplary embodiment uses a method of tuning the timing of the SOE signal while sensing the data charge amount as shown in FIG. 5 to the data ICs D#1 to D #2m) Set the optimal timing of SOE1 to SOE2m signals for each.

First, the timing controller 400 stores and fixes a set value for timing information (start timing, pulse width, etc.) of a gate control signal (GOE, etc.) in a register.

Next, the timing controller 400 sets all registers SOE1 to SOE2m as mood timing information using the timing information (start timing, pulse width) of SOE1 corresponding to the first data IC D#1 as reference timing information. do (S402). An SOE1 signal having a minimum enable period may be generated using the SOE1 timing information.

The timing controller 400 supplies the same sensing data to the data ICs D#1 to D#2m and the same SOE1 signal as the SOE1 to SOE2m signals of the data ICs D#1 to D#2m. The timing controller 400 senses the data charge amount of each subpixel by driving each of the subpixels with the same data voltage through the data ICs D#1 to D#2m and sensing the current of each subpixel as a voltage (S404) ).

The timing controller 400 calculates a sensing average value of the first data IC D#1 (S406).

The timing controller 400 changes the timing of the SOE2 register corresponding to the second data IC D#2 (S408). At this time, any one of the start timing and the pulse width, which are the SOE2 timing information, can be changed, but it is preferable to change the enable period by fixing the start timing and changing the timing of the pulse width.

The timing of SOE2 may be changed by calculating and applying a difference between the sensing average values of the first data IC D#1 and the second data IC D#2 to which the same SOE1 signal is applied. The SOE2 register is changed so that the enable period of the SOE2 signal is longer than the enable period of the SOE1 signal.

The timing controller 400 calculates an average value of the data charge amount sensed values of the second area A2 sensed through the second data IC #2 by applying the SOE2 signal ( S420 ).

The timing controller 400 compares the sensing average value of the first data IC (D#1) calculated in S406 with the sensing average value of the second data IC (D#2) calculated in S410 to determine whether they belong to the same range do (S412).

When the sensing average value of the first data IC (D#1) and the sensing average value of the second data IC (D#2) do not fall within the same range, the SOE2 timing change of S408 to S412 described above, the data charge amount sensing, and the sensing average value calculation , repeat the sensing average value comparison process.

When the sensing average value of the first data IC D#1 and the sensing average value of the second data IC D#2 are within the same range, the SOE2 register setting is completed with the SOE2 timing information changed in S408 (S414).

Next, in response to each of the third to mth data ICs (D#3 to D#m), the above-described S408 to S414 are applied in the same manner, and the timing of the SOE2 to SOEm registers is sensed and set while checking the data charge amount. do (S416).

Further, the timing information of the SOE2m to SOEm+1 registers is set symmetrically to the set SOE1 to SOEm registers (S418), and the timing setting of the SOE is finished.

On the other hand, when the timing controller 400 determines that the SOE timing setting is necessary because the temperature sensed by the temperature sensor 700 is changed, the SOE tuning method described in FIG. 5 is applied in the same manner to correspond to each data IC. The SOE timing of each data IC is set sequentially while changing the timing of the SOE signal and sensing and checking the amount of data charge.

6 is a diagram schematically illustrating a characteristic in which an enable period of an SOE signal according to a position of a sub-pixel is adjusted according to a temperature in an OLED display device according to an embodiment of the present invention.

Referring to FIG. 6 , it can be seen that the delay characteristic of the gate signal SCAN varies at low temperature, room temperature, and high temperature in the OLED display according to the exemplary embodiment. For example, it can be seen that compared with the delay of the gate signal at room temperature, the delay of the gate signal decreases as the temperature decreases, and the delay of the gate signal increases as the temperature increases.

Accordingly, when the driving temperature or ambient temperature of the OLED display changes, the delay of the gate signal fluctuates and does not coincide with the timing of the SOE signal, so the embodiment adjusts the data output period of the SOE signal while sensing the data charge amount.

Referring to FIG. 6 , when the gate delay increases as the temperature of the display device changes from room temperature to high temperature, the SOE timing setting method described in FIG. 5 is applied to SOE1 corresponding to each of the data ICs D#1 to D#2m. The enable period of the to SOE2m signal may be set to increase compared to the case of room temperature.

Meanwhile, when the gate delay is reduced as shown in FIG. 6 as the temperature of the display device changes from room temperature to low temperature, the SOE timing setting method described in FIG. 5 is applied to SOE1 corresponding to each of the data ICs D#1 to D#2m. to SOE2m may be set to be shorter than in the case of room temperature.

The timing setting according to the temperature change may be performed regardless of image display in at least one of a power-on time, a power-off time, and a vertical blank period.

According to an exemplary embodiment, the data charging characteristics of sub-pixels are sensed and checked through the data IC when timing is set according to characteristics such as the size of the display panel, and the output period of the data signal (the enable period of the SOE signal) for each data IC is facilitated. can be set. Accordingly, the luminance uniformity may be improved by compensating for the data charge amount deviation due to the delay of the gate/data signal.

According to an embodiment, even when the timing of the gate/data signal is changed according to the temperature fluctuation due to the surrounding environment or the driving of the display device, the data charging characteristic is sensed and checked through the data IC while the output period (SOE) of the data signal for each data IC is checked. By appropriately adjusting the enable period of the signal), the luminance uniformity can be improved by compensating for the data charge amount deviation.

In the above, it has been shown and described as a specific embodiment to illustrate the technical idea of the present invention, but the present invention is not limited to the same configuration and operation as the specific embodiment as described above, and various modifications do not depart from the technical spirit of the present invention. It can be implemented within the scope. Accordingly, such modifications should be considered to fall within the scope of the present invention, and the scope of the present invention should be determined by the following claims.

100: display panel 200: gate driver
300: data driver 400: timing controller
500: memory 600: power unit
700: temperature sensor

Claims (10)

a display panel including a pixel array;
a gate driver driving gate lines of the pixel array;
data ICs for dividing and driving the data lines of the pixel array into a plurality of regions and sensing a data charge amount of a subpixel in each of the plurality of regions;
a timing controller for controlling the gate driver and individually controlling the enable period of each source output enable signal to individually control the data output period of the data ICs based on the sensed data charge amount;
Each of the data ICs is
OLED display that senses the current supplied from the driving TFT according to the sensing data voltage charged in the storage capacitor of each sub-pixel during the scan period, converts the sensing result into a data charge amount sensed value of each sub-pixel, and provides it to the timing controller Device. delete The method according to claim 1,
the timing controller
A first average value of the sensed values of the data charge amount sensed from the subpixels of the first region through a first data IC that drives a first region close to the gate driver and is controlled by a first source output enable signal calculate,
Through the second data IC driving the second region and controlled by the second source output enable signal, the sensed from the subpixels of the second region while adjusting the enable period of the second source output enable signal By calculating a second average value for the data charge amount sensed values,
an enable period in which the second average value falls within the same range as the first average value is set as an enable period of the second source output enable signal;
An enable period of a source output enable signal for each of the data ICs other than the first and second data ICs among the data ICs is set by performing the same process as that of the second data IC. 4. The method according to claim 3,
An enable period of a source output enable signal of the data ICs gradually increases from a region close to the gate driver to a region farther from the region. The method according to claim 1,
the timing controller
When it is determined that the timing adjustment of the data output period is necessary because the temperature sensed by the temperature sensor fluctuates, the source output for each of the data ICs while checking the data charge amount sensed value of the corresponding area through each of the data ICs An OLED display that adjusts the enable period of the enable signal. 6. The method of claim 5,
the timing controller
increasing an enable period of a source output enable signal for each of the data ICs when the sensed temperature is in a high temperature range higher than the room temperature range;
An OLED display device for reducing an enable period of a source output enable signal for each of the data ICs in a low temperature range lower than the room temperature range. In the method for setting the timing of the OLED display device according to claim 1,
In the pixel array, a data charge amount is sensed from subpixels of the first region through a first data IC that drives a first region close to the gate driver and is controlled by a first source output enable signal, and the first calculating a first average value for the sensed values of the region;
A second data IC that drives a second region in the pixel array and is controlled by a second source output enable signal, adjusts an enable period of the second source output enable signal and subpixels of the second region Sensing the data charge amount from the data and calculating a second average value of the sensed values of the second area;
and setting an enable period in which the second average value falls within the same range as the first average value as an enable period of the second source output enable signal. 8. The method of claim 7,
A method for setting a timing of an OLED display for setting an enable period of a source output enable signal for each of the data ICs other than the first and second data ICs by performing the same process as that of the second data IC. 9. The method of claim 8,
When it is determined that timing adjustment of the source output enable signal is necessary because the sensing temperature of the OLED display sensed through the temperature sensor fluctuates, the data charge amount sensed value of the corresponding area is checked through each of the data ICs. A timing setting method of an OLED display for adjusting an enable period of a source output enable signal for each of the data ICs. The method according to claim 1,
Each of the data ICs is
An OLED display device for sensing a data charge amount of each subpixel through a reference line connected to each subpixel.

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