KR102646055B1 - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an organic light emitting diode display device that can improve brightness uniformity by sensing the charging voltage ratio according to the position of each subpixel and accurately compensating for the difference in charging amount due to the voltage drop at each position. An OLED according to an embodiment During the voltage drop sensing operation, the timing controller of the display device charges the capacitor of each subpixel under the same conditions through the panel driver, then senses the charging voltage of each capacitor through the data line, and compares the sensed voltage with the representative value. The voltage drop compensation value is calculated and stored in the memory, and during display operation, the voltage drop compensation value stored in the memory is applied to compensate the image data.

Description

Organic light emitting diode display device {ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE}

The present invention relates to an organic light emitting diode display device that can improve luminance uniformity by accurately sensing and compensating for the charging deviation according to the position of each subpixel.

Display devices include a liquid crystal display using liquid crystal, an organic light emitting diode (OLED) display using an organic light emitting diode, and an electrophoretic display using electrophoretic particles.

Among these, OLED displays are self-luminous devices that emit light through an organic light-emitting layer by recombination of electrons and holes. They have the advantages of high brightness, low driving voltage, ultra-thin film, and freedom of shape.

Each subpixel that makes up the OLED display has an OLED element and a pixel circuit that independently drives the OLED element. The pixel circuit controls the brightness of the OLED device by adjusting the current (Ids) through which the driving thin film transistor (TFT) drives the OLED device according to the driving voltage (Vgs) corresponding to the data signal.

However, in OLED display devices, a voltage drop (IR drop) occurs due to resistance (load) and current of wiring including the power (EVDD) line, data line, etc., so the farther the subpixel is from the output of the data driver, the farther the subpixel is. IR drop increases and data charging amount decreases. Because of this, the amount of data charged varies depending on the location of each subpixel, causing a problem of uneven luminance compared to the same data.

To reduce the problem of luminance unevenness depending on the position of the subpixel, increase the power wiring width, predict the amount of voltage drop depending on the position of the subpixel, adjust the width of the source enable signal that controls the data output period of the data driver, or adjust the data output period. Various technologies have been proposed, such as compensating, but the problem of luminance unevenness still occurs because the difference in charge amount due to the voltage drop depending on the position of each subpixel cannot be accurately measured and compensated.

The present invention provides an organic light emitting diode display device that can improve luminance uniformity by accurately sensing and compensating for charging deviation according to the position of each subpixel.

The timing controller of the OLED display device according to one embodiment charges the capacitor of each subpixel under the same conditions through the panel driver during the voltage drop sensing operation, then senses the charging voltage of each capacitor through the data line, and Compare the voltage with the representative value to calculate the voltage drop compensation value and store it in memory. During a display operation, the timing controller compensates the image data by applying the voltage drop compensation value stored in the memory and outputs the compensated image data to the panel through the panel driver.

When sensing a voltage drop, the timing controller according to one embodiment performs a sensing mode for a plurality of subpixels on a line-by-line basis, and charges the capacitor of each subpixel of a line selected in a programming period among the line-by-line sensing modes, During the sensing period of each line-unit sensing mode, the charging voltage of the capacitor of each subpixel of the selected line is sensed through the data line.

The timing controller according to one embodiment calculates the average value of the voltages sensed for each line, uses the average value of the line closest to the data driver as a representative value, and calculates the charging voltage ratio of the average value of other lines to the representative value. A compensation value to compensate for the calculated charging voltage ratio is calculated line by line and stored in memory.

The timing controller according to one embodiment uses the voltage sensed from the subpixel closest to the data driver and gate driver as a representative value, calculates the charging voltage ratio of other subpixels compared to the representative value, and compensates for the calculated charging voltage ratio. The compensation value for this is calculated in subpixel units and stored in memory.

A timing controller according to one embodiment calculates the average value of the sensed voltages for each line, uses the average value of the line closest to the data driver as a representative value, and calculates the difference between the representative value and the average value of other lines. The charging deviation offset value is calculated, and a compensation value to compensate for the calculated charging deviation offset value is calculated in line units and stored in the memory.

The timing controller according to one embodiment uses the voltage sensed from the subpixel closest to the data driver and gate driver as a representative value, and calculates the difference between the representative value and the sensed voltage of other subpixels as a charging deviation offset value. A compensation value for compensating for one charging deviation offset value is calculated in subpixel units and stored in memory.

The timing controller according to one embodiment compensates the image data by applying a voltage drop compensation value to the image data and then further applying a compensation value for the characteristic deviation of each subpixel stored in the memory.

The timing controller according to one embodiment performs a voltage drop sensing operation at any one of power-on time, vertical blank time, and power-off time.

A data driver according to an embodiment includes a digital-to-analog converter that analogizes data supplied from a timing controller and outputs it; A sampling unit that samples and holds the voltage sensed through the data line; An analog-to-digital converter that digitizes the output voltage of the sampling unit and outputs it to a timing controller; a first switch connecting a digital-to-analog converter and a data line in a programming period; a second switch connecting the data line and the sampling unit in the sensing period; a third switch connecting the reference line and the sampling unit in another sensing mode that senses characteristics of each subpixel; and a fourth switch that connects the reference voltage supply unit and the reference line during the programming period and the sensing period, and the sampling unit senses the charging voltage of the capacitor by sampling and holding the charging voltage of the capacitor through the data line at the sampling point during the sensing period.

Each subpixel includes a light emitting element, a driving TFT that drives the light emitting element, a first switching TFT connecting a data line and a gate node of the driving TFT, and a second switching TFT connecting a source node of the driving TFT; and a capacitor connected between the gate node and the source node of the driving TFT, wherein the gate driver supplies a scan gate pulse to the scan gate line connected to the first switching TFT in each of the programming period and the sensing period, and the programming period And in the sensing period, a sensing gate pulse is supplied to the sensing gate line connected to the second switching TFT to select a line for a voltage drop sensing operation.

The OLED display device according to one embodiment operates in a voltage drop sensing mode, charges the capacitor of each subpixel under the same conditions, then senses the charging voltage of the capacitor through a data line, and determines the charging voltage ratio compared to the representative value based on the sensing result. Alternatively, the voltage drop compensation value according to the charging deviation can be accurately calculated.

Therefore, the OLED display device according to one embodiment can compensate for the charging deviation due to the voltage drop according to the position of each subpixel by compensating the image data using the calculated voltage drop compensation value to minimize the luminance deviation, and as a result, The brightness uniformity of the panel can be improved.

1 is a block diagram schematically showing the configuration of an OLED display device according to an embodiment of the present invention.
Figure 2 is an equivalent circuit diagram illustrating some configurations of a pixel circuit and a data driver according to an embodiment of the present invention.
3 and 4 are equivalent circuit diagrams and driving waveform diagrams for explaining the sensing mode operation of an OLED display device according to an embodiment of the present invention.
5 to 8 are diagrams showing a method of compensating image data by generating voltage drop compensation data according to an embodiment of the present invention.
9 to 11 are flowcharts showing a method of driving an OLED display device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing the configuration of an OLED display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram illustrating a partial configuration of a pixel circuit and a data driver according to an embodiment of the present invention. .

Referring to FIG. 1, an OLED display device according to an embodiment includes a panel 100, a gate driver 200, a data driver 300, a timing controller 400, a memory 500, and a gamma voltage generator 600. , power supply unit 700, etc.

The power supply unit 700 uses the input voltage to generate and output various driving voltages necessary for driving the OLED display. For example, the power supply unit 700 drives the driving voltage of the digital circuit supplied to the data driver 300 and the timing controller 400, and the analog circuit supplied to the data driver 300 and the gamma voltage generator 600. Voltage, gate-on voltage (VGH) and gate-off voltage (VGL) used in the gate driver 200 are generated and supplied. The power supply unit 700 further generates a plurality of driving voltages (EVDD, EVSS) and a reference voltage (Vref) required to drive the panel 100 and supplies them to the panel 100 through the data driver 300.

The panel 100 displays an image through a pixel array in which subpixels P are arranged in a matrix form. A basic pixel may be composed of two-, three-, or four-color subpixels among white (W), red (R), green (G), and blue (B) subpixels.

Subpixels (P) arranged in the X-axis and Y-axis directions form a plurality of horizontal lines and a plurality of column lines. The subpixels P of each horizontal line arranged in the X-axis direction are commonly connected to the scan gate line GLsc and the sense gate line GLse. The subpixels (P) of each column arranged in the Y-axis direction are commonly connected to each data line (DL). The subpixels (P) of each column or multiple columns may be commonly connected to the reference line (RL) and the power line (PL). For example, as shown in Figure 1, four columns of subpixels P may be commonly connected to the reference line RL, and two columns of subpixels P may be commonly connected to the power line PL. there is.

Each subpixel (P) includes an OLED element (light-emitting element) and a pixel circuit that independently drives the OLED element. For example, referring to FIG. 2, each subpixel (P) includes first and second switching TFTs (ST1, ST2), a driving TFT (DT), and a storage capacitor (FIG. and a pixel circuit including at least Cst). Meanwhile, since the pixel circuit is diverse in addition to the configuration shown in FIG. 2, various configurations may be applied.

The switching TFT (ST1, ST2) and driving TFT (DT) can be an amorphous silicon (a-Si) TFT, poly-silicon (poly-Si) TFT, oxide TFT, or organic TFT. there is.

The OLED device 10 includes an anode connected to the source node (N2) of the driving TFT (DT), a cathode to which a low-potential power signal (EVSS) is supplied, and an organic light-emitting layer between the anode and the cathode. The anode is independent for each subpixel, but the cathode is a common electrode shared by all subpixels. When current is supplied from the driving TFT (DT) to the OLED device 10, electrons from the cathode are injected into the organic light-emitting layer, and holes from the anode are injected into the organic light-emitting layer, resulting in fluorescence or phosphorescence due to recombination of electrons and holes in the organic light-emitting layer. By making the material emit light, light of brightness proportional to the size of the current is generated.

The first switching TFT (ST1) is driven by the scanning gate pulse (SCAN) supplied from the gate driver 200 to the scanning gate line (GLsc) and supplied to the data line (DL) from the data driver 300. The data signal (Vdata) is supplied to the gate node (N1) of the driving TFT (DT).

The second switching TFT (ST2) is driven by the sensing gate pulse (SENSE) supplied from the gate driver 200 to the sensing gate line (GLse), and the sensing gate pulse (SENSE) supplied from the data driver 300 to the reference line (RL). The reference voltage (Vref) is supplied to the source node (N2) of the driving TFT (DT). The second switching TFT (ST2) is further used as a current path that causes the current passing through the source node (N2) of the driving TFT (DT) to flow to the reference line (RL) in the sensing mode.

The first and second switching TFTs (ST1, ST2) may be controlled by different gate lines (GLsc, GLse) as shown in FIG. 2 or may be controlled by the same gate line.

A storage capacitor (Cst) connected between the gate node (N1) and the source node (N2) of the driving TFT (DT) is connected to the gate node (N1) and the source node (N2) through the first and second switching TFTs (ST1, ST2). The difference voltage between the data signal (Vdata) and the reference voltage (Vref) supplied to N2) is charged and supplied as the driving voltage (Vgs) of the driving TFT (DT).

The driving TFT (DT) controls the current supplied from the power line (PL) that supplies the high-potential power signal (EVDD) according to the driving voltage (Vgs) and supplies the controlled current to the OLED element 10 to drive the OLED element ( 10) emits light.

The gate driver 200 and data driver 300 connected to the panel 100 can be defined as a panel driver.

The gate driver 200 receives a plurality of gate control signals from the timing controller 400 and operates a shift register to individually drive the gate lines of the panel 100. The gate driver 200 supplies a gate pulse of the gate-on voltage (VGH) to the corresponding gate line during the driving period of each gate line, and supplies a gate-off voltage (VGL) to the corresponding gate line during the non-driving period of each gate line. do.

The gate driver 200 includes a scan shift register 210 that drives a plurality of scan gate lines (GLsc1 to GLsc(n)) of the panel 100 and a plurality of sense gate lines (GLse1 to GLse(n)). It may include a sense shift register 220 that drives .

The gamma voltage generator 600 generates a plurality of reference gamma voltages with different voltage levels and supplies them to the data driver 300. The gamma voltage generator 600 may generate a plurality of reference gamma voltages corresponding to the gamma characteristics of the display device under the control of the timing controller 400 and supply them to the data driver 300. The gamma voltage generator 600 may receive gamma data from the timing controller 400, adjust the reference gamma voltage level according to the gamma data, and output it to the data driver 300. The gamma voltage generator 600 may adjust the high potential voltage according to the peak luminance control of the timing controller 400 and output it to the data driver 300.

The data driver 300 converts the data supplied from the timing controller 400 into an analog data signal according to the data control signal supplied from the timing controller 400 and connects the data lines DL1 to DLm of the panel 100. supplied to each. At this time, the data driver 300 subdivides the plurality of reference gamma voltages supplied from the gamma voltage generator 600 into a plurality of gamma voltages, and converts the digital data into an analog data signal using the subdivided gamma voltages.

The data driver 300 may convert image data, sensing data, recovery data, etc. supplied from the timing controller 400 into corresponding data voltage signals and supply them to each of the plurality of data lines DL1 to DLm.

The data driver 300 supplies the reference voltage (Vref) supplied from the power supply unit 700 to a plurality of reference lines (RL1 to RLk) of the panel 100 under the control of the timing controller 400. The data driver 300 can supply the reference voltage (Vref) separately for display and sensing according to the control of the timing controller 400.

The timing controller 400 receives image data and timing control signals from the host system. The host system may be any one of a computer, a TV system, a set-top box, and a mobile terminal system such as a tablet or mobile phone. Timing control signals may include a dot clock, data enable signal, vertical synchronization signal, horizontal synchronization signal, etc. The timing controller 400 uses timing control signals supplied from the host system and timing setting information stored internally to generate a plurality of data control signals that control the driving timing of the data driver 300. and generates a plurality of gate control signals that control the driving timing of the gate driver 200 and supplies them to the gate driver 200.

The timing controller 400 can perform various image processing on image data to compensate for deterioration of OLED elements and correct image quality, and can reduce power consumption by analyzing image data and controlling image brightness.

The timing controller 400 applies a compensation value for the characteristic deviation of the driving TFT of each subpixel stored in the memory 500 to compensate for image data, sensing data, recovery data (RT sensing mode), and the compensated data. is supplied to the data driver 300. The memory 500 stores compensation information for each subpixel, including the Vth characteristic of the driving TFT (DT) for each subpixel, a Vth compensation value for compensating for mobility deviation, and a mobility compensation value.

The timing controller 400 may control the OLED display to operate in a sensing mode in order to update the compensation value stored in the memory 500. In the sensing mode, the timing controller 400 controls the gate driver 200 and the data driver 300 to drive the panel 100 in the sensing mode, and each subpixel ( The characteristics of P) can be sensed and the compensation value of each subpixel stored in the memory 500 can be updated using the sensing result.

For example, the timing controller 400 operates in a driving environment ( The mobility of the driving TFT (DT), which is affected by (illuminance, temperature), can be sensed and the mobility compensation value stored in the memory 500 can be updated using the sensing result. The timing controller 400 may sense the Vth change amount of the driving TFT that shifts according to stress accumulation in the RS sensing mode operating during the power-off time and update the Vth compensation value stored in the memory 500 using the sensing result. In addition, the sensing mode of the OLED display may be performed according to the needs of the timing controller 400 or the host system, or may be performed by user request through the host system.

In addition, the timing controller 400 operates in a voltage drop (IR Drop) sensing mode, charges the storage capacitor (Cst) of each subpixel under the same conditions through the panel drivers 200 and 300, and then charges each data line (DL1). The charging voltage of each capacitor (Cst) can be sensed through ~DLm). During a voltage drop (IR Drop) sensing operation, the timing controller 400 may output sensing data to the data driver 300 without compensating the Vth compensation value and the mobility compensation value.

The timing controller 400 uses the sensing voltage to calculate the charging voltage ratio or charging deviation of each capacitor (Cst) with respect to the representative value on a per-pixel line or per-pixel basis, and to compensate for the calculated charging voltage ratio or charging deviation. The voltage drop compensation value can be calculated for each line or subpixel and stored in the memory 500. The timing controller 400 may use the voltage sensed from the nth pixel line closest to the panel driver, that is, the data driver 300, as a representative value. When calculating the charging voltage ratio or charging deviation on a line-by-line basis, the timing controller 400 may use the average value of the sensed voltages of the nth pixel line as a representative value. When calculating the charging voltage ratio or charging deviation on a line-by-line basis, the timing controller 400 uses the first subpixel of the nth pixel line closest to the gate driver 200 and the data line 300, for example, the red subpixel. The sensed voltage can be used as a representative value.

The timing controller 400 may compensate the image data by applying the voltage drop compensation value stored in the memory 500 to the image data. Meanwhile, the timing controller 400 may first apply the voltage drop compensation value before applying the Vth compensation value and mobility compensation value for each subpixel to the image data, resulting in a characteristic deviation of the driving TFT. This can be done so that it does not affect the compensation.

The timing controller 400 operates the above-mentioned voltage drop sensing mode at any one of the power-on time, vertical blank period, and power-off time to optimize each subpixel for each panel with different unique characteristics such as shape and design conditions. The voltage drop can be sensed and compensated for.

Referring to FIG. 2, the data driver 300 is a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a sampling unit (SAM), a path between the digital-to-analog converter (DAC) and the data line (DL). A first switch (SW1) for switching, a second switch (SW2) for switching the path between the data line (DL) and the sampling unit (SAM), and a second switch (SW2) for switching the path between the reference line (RL) and the sampling unit (SAM). Some components include a third switch (SW3) that switches the path between the supply part of the reference voltage (Vref) and the reference line (RL), and these components control the timing controller 400. It can operate according to.

1 and 2, during the programming period of the voltage drop sensing mode, the data driver 300 converts the sensing data (Vdata) supplied from the timing controller 400 to analog through a digital-to-analog converter (DAC). And, it is supplied to each data line (DL) through the turned-on first switch (SW), and the sensing reference voltage (Vref) is supplied to each reference line (RL) through the turned-on fourth switch (SW4). do. In the subpixel (P) selected by the scan gate pulse (SCAN) and the sense gate pulse (SENSE) from the gate driver 200, the storage capacitor (Cst) has a data voltage for sensing supplied through the first switching TFT (ST1). The driving voltage (Vgs), which is the difference between (Vdata) and the sensing reference voltage (Vref) supplied through the second switching TFT (ST2), is charged. Since the scan gate pulse (SCAN) and sense gate pulse (SENSE) are the same as those supplied in display mode, which is normal driving, the storage capacitor (Cst) maintains the driving voltage (Vgs) for the same time (1H) as in display mode. It can be recharged.

In the sensing period of the voltage drop sensing mode, the first switch SW1 is turned off and the turned-on second switch SW2 connects the data line DL to the sampling unit SAM. The data driver 300 senses by sampling and holding the voltage (Vgs) charged in the storage capacitor (Cst) through the sampling unit (SAM) and data line (DL), and detects the voltage (Vgs) through an analog-to-digital converter (ADC). The sensing voltage of each subpixel (SP) is digitized and output to the timing controller 400.

3 and 4 are equivalent circuit diagrams and driving waveform diagrams for explaining the sensing mode operation of an OLED display device according to an embodiment of the present invention.

In the voltage drop sensing mode, the timing controller 400 performs a sensing operation of sensing n pixel lines by charging the sensing voltage for each line through the gate driver 200 and the data driver 300, and sequentially charges the sensing voltage. Proceed. The sensing operation period of each pixel line includes a programming period for charging the sensing voltage and a sensing period for sensing the charging voltage.

During the programming period during the sensing operation period of the first pixel line, the gate driver 200 sends a scanning gate pulse (SCAN1) and a sensing gate pulse (SENSE1) to the first scan gate line (GLse1) and the second sense gate line (GLse1). ), and the data driver 300 supplies the data voltage (VDATA) for sensing to the data line (DL) through the first switch (SW1), and the reference voltage (Vref) for sensing through the fourth switch (SW). ) is supplied to the reference line (DL). Accordingly, the storage capacitor (Cst) of each subpixel in the first pixel line is connected to the sensing data voltage (VDATA) supplied through the first switching TFT (ST1) and the sensing data voltage (VDATA) supplied through the second switching TFT (ST2). Charge the difference voltage with the reference voltage (Vref).

During the sensing period during the sensing operation period of the first pixel line, the gate driver 200 sends a scanning gate pulse (SCAN1) and a sensing gate pulse (SENSE1) to the first scan gate line (GLse1) and the second sense gate line (GLse1). ) is supplied, and in the data driver 300, the first switch (SW1) is turned off and the second switch (SW2) is turned on. Accordingly, the data driver 300 charges the storage capacitor Cst of the first pixel line through the second switch SW2 and the data line DL at the sampling time of the sampling unit SAM during the sensing period. The voltage (Vgs) is sensed by sampling and holding, and the sensed voltage is digitized and output to the timing controller 400.

The timing controller 300 applies the above-described sensing operation for the first pixel line to the remaining second to nth pixel lines in line sequential order through the gate driver 200 and the data driver 300, thereby The voltage (Vgs) charged in the storage capacitor (Cst) of each subpixel can be sensed on a line basis.

During the above-mentioned voltage drop sensing mode, the third switch (SW3) between the reference line (RL) and the sampling unit (SAM) in the data driver 300 is maintained in the turn-off state, and the fourth switch (SW4) is turned on. -Can remain in the on state. Meanwhile, the third switch SW3 may be turned on when sensing the Vth, mobility, etc. of each subpixel through the reference line RL.

5 to 8 are diagrams showing a method of compensating image data by generating voltage drop compensation data according to an embodiment of the present invention.

5 to 8, the timing controller 400 according to one embodiment can sense the charging voltage for the storage capacitor of each subpixel of the entire panel 100 through the panel drivers 200 and 300. .

Referring to FIG. 5, the timing controller 400 calculates a line-by-line average value for the voltage sensed for each pixel line and calculates a charging voltage ratio (gain) on a line-by-line basis. The timing controller 400 calculates the ratio of the average value of each of the remaining lines based on the average value (representative value) of the Nth line closest to the data driver 300 by the line-specific charging voltage ratio (gain=(n ^th line avg)/( It can be calculated as N ^th line avg)). The timing controller 400 calculates a compensation gain (1/gain) (voltage drop compensation value) for each line by reflecting the charging voltage ratio calculated for each line and stores it in the memory 500. The timing controller 400 may compensate the image data by multiplying and applying a compensation gain (voltage drop compensation value) for each line to the image data of each subpixel.

Referring to FIG. 6, the timing controller 400 according to one embodiment charges each subpixel based on the charging voltage (representative value) of the first subpixel of the Nth line closest to the panel driver 200, 300. The voltage ratio (gain) can be calculated, and the compensation gain (voltage drop compensation value) of each subpixel can be calculated by reflecting the charging voltage ratio (gain) for each subpixel and stored in the memory 500. The timing controller 400 may compensate the image data by multiplying and applying a compensation gain (voltage drop compensation value) for each subpixel to the image data of each subpixel.

In this way, the timing controller 400 compensates the image data by calculating a compensation gain so that the charging voltage ratio for each line or each subpixel is 1:1 based on the representative value, thereby reducing the voltage drop due to different voltage drops depending on the pixel position. Charging deviation can be compensated.

Referring to FIG. 7, the timing controller 400 according to one embodiment may calculate an average value for each line of the voltage sensed for each pixel line and calculate an offset value, which is a charging deviation, on a line-by-line basis. The timing controller 400 may calculate the difference between the average value of the Nth line and the average value of each other line as an offset value for each line. The timing controller 400 reflects the offset value calculated for each line to calculate an offset compensation value (voltage drop compensation value) for each line and stores it in the memory 500. The timing controller 400 may compensate the image data by adding and applying the compensation offset value (voltage drop compensation value) for each line to the image data of each subpixel.

Referring to FIG. 8, the timing controller 400 according to an embodiment may calculate an offset value, which is the charging deviation, for each subpixel based on the charging voltage (representative value) of the first subpixel of the N-th line, By reflecting the offset value for each subpixel, the compensation offset value (voltage drop compensation value) of each subpixel can be calculated and stored in the memory 500. The timing controller 400 may compensate image data by adding and applying a compensation offset value (voltage drop compensation value) for each subpixel to the image data of each subpixel.

9 to 11 are flowcharts showing a method of driving an OLED display device according to an embodiment of the present invention.

Referring to FIG. 9, the OLED display device according to one embodiment is turned on and performs the above-described voltage drop sensing mode before entering normal driving (display operation) (S902). In the voltage drop sensing mode, the OLED display device charges the storage capacitor of each subpixel with a driving voltage under the same conditions for each line for all subpixels of the panel and senses the charging voltage through the data line. Compare the sensing voltage of each subpixel with the representative value, or calculate the average value of each line unit and compare it with the representative value, calculate the charging voltage ratio or charging deviation offset for each line or each subpixel, and use the calculation results to calculate the charging voltage ratio or charging deviation offset. The voltage drop compensation value of the line or each subpixel is calculated and stored in memory.

Normal driving (display operation) starts (S904), and the OLED display device compensates the image data by reflecting the voltage drop compensation value stored in the memory to the image data (S906), and supplies the compensated image data to each subpixel. Display the video (S908). The OLED display device may compensate the image data by applying a voltage drop compensation value to the image data in the image data compensation step (S906) and then further applying the Vth compensation value and mobility compensation value of each subpixel stored in the memory. The OLED display device performs the image data compensation step (S906) and the image display step (S908) until the power is turned off (S910; N), and ends when the power is turned off (S910; Y).

Referring to FIG. 10, the OLED display device according to one embodiment starts normal operation, compensates image data using compensation values stored in memory (S102), and stores image data in each subpixel in the active period of each frame. The image is displayed by writing (S104). The OLED display device performs the above-described voltage drop sensing mode in real time during the vertical blank period (S106; Y) to sense the voltage drop of each line or each subpixel, generates a voltage drop compensation value based on the sensing result, and stores it in memory. Do it (S108). The OLED display device compensates the image data by reflecting the voltage drop compensation value stored in the memory to the image data (S102), and supplies the compensated image data to each subpixel to display the image (S104). The OLED display device may compensate the image data by applying a voltage drop compensation value to the image data in the image data compensation step (S102) and then further applying the Vth compensation value and mobility compensation value of each subpixel stored in the memory.

Referring to FIG. 11, the OLED display device according to one embodiment is turned on and checks for the presence or absence of a voltage drop compensation value stored in the NAND memory (S112). If there is no voltage drop compensation value (S112; N), normal display operation is performed. Display the video through (S114). When a power-off signal occurs (S118, Y), the OLED display device performs the voltage drop sensing mode operation described above to sense the voltage drop of each line or each subpixel and generates a voltage drop compensation value based on the sensing result to Save to memory (S120, S122).

The OLED display device turns on and checks the presence or absence of the voltage drop compensation value stored in the NAND memory. If there is a compensation value (S112, Y), it loads the voltage drop compensation value stored in the NAND memory and displays the loaded voltage drop compensation value as an image. The image data is compensated by reflecting the data (S114), and the compensated image data is supplied to each subpixel to display the image (S116). The OLED display device may compensate the image data by applying a voltage drop compensation value to the image data in the image data compensation step (S114) and then further applying the Vth compensation value and mobility compensation value of each subpixel stored in the memory.

In this way, the OLED display device according to one embodiment operates in a voltage drop sensing mode, charges the capacitor of each subpixel under the same conditions, then senses the charging voltage of the capacitor through the data line, and compares the representative value based on the sensing result. The voltage drop compensation value according to the charging voltage ratio or charging deviation can be accurately calculated.

Therefore, the OLED display device according to one embodiment can compensate for the charging deviation due to the voltage drop according to the position of each subpixel by compensating the image data using the calculated voltage drop compensation value to minimize the luminance deviation, and as a result, The brightness uniformity of the panel can be improved.

The above description is merely an exemplary description of the present invention, and various modifications may be made by those skilled in the art without departing from the technical spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention do not limit the present invention. The scope of the present invention should be interpreted in accordance with the scope of the patent claims below, and all technologies within the equivalent scope thereof should be interpreted as being included in the scope of the present invention.

100: panel 200: gate driver
300: data driver 400: timing controller
500: memory 600: gamma voltage generator
700: Power supply unit

Claims (10)

A panel including a plurality of subpixels;
a panel driver including a gate driver and a data driver that drives the panel; and
It includes a timing controller that controls the panel driver,
The timing controller is
During the voltage drop sensing operation, the capacitor of each subpixel is charged under the same conditions through the panel driver, then the charging voltage of each capacitor is sensed through the data line, and the sensed voltage is compared with a representative value to determine the voltage drop. The compensation value is calculated and stored in memory,
During the characteristic deviation sensing operation, the characteristic deviation of the driving transistor of each subpixel is sensed, a compensation value for the characteristic deviation is calculated, and stored in the memory,
An OLED display device that compensates image data by applying a voltage drop compensation value stored in the memory and a compensation value for the characteristic deviation during a display operation and outputs the compensated image data to the panel through the panel driver. In claim 1,
The timing controller is,
During the voltage drop sensing operation, a sensing mode is performed on the plurality of subpixels on a line-by-line basis, and the line unit includes a plurality of subpixels arranged in an extension direction of the gate line,
Charging the capacitor of each subpixel of the line selected in the programming period among the sensing modes for each line,
An OLED display device that senses the charging voltage of a capacitor of each subpixel of the selected line through the data line during a sensing period among the sensing modes for each line. In claim 2,
The timing controller is
Calculate the average value of the voltages sensed for each line,
Using the average value of the line closest to the data driver as the representative value, a charging voltage ratio of the average value of other lines compared to the representative value is calculated, and a compensation value to compensate for the calculated charging voltage ratio is calculated on a line-by-line basis. An OLED display device that stores the information in the memory. In claim 1,
The timing controller is
Using the voltage sensed from the subpixel closest to the data driver and the gate driver as the representative value, a ratio of the charging voltage of other subpixels to the representative value is calculated, and a compensation value to compensate for the calculated charging voltage ratio is calculated. An OLED display device that calculates data in subpixel units and stores it in the memory. In claim 2,
The timing controller is
Calculate the average value of the voltages sensed for each line,
Using the average value of the line closest to the data driver as the representative value, the difference between the representative value and the average value of other lines is calculated as a charging deviation offset value, and a compensation value to compensate for the calculated charging deviation offset value is set to the line An OLED display device that calculates in units and stores them in the memory. In claim 1,
The timing controller is
Using the voltage sensed from the subpixel closest to the data driver and the gate driver as the representative value, the difference between the representative value and the sensed voltage of other subpixels is calculated as a charging deviation offset value, and the calculated charging deviation offset An OLED display device that calculates a compensation value in subpixel units and stores it in the memory. In claim 1,
The timing controller applies the voltage drop compensation value to the image data, and then additionally applies a compensation value for characteristic deviation of each subpixel stored in the memory to compensate for the image data. In claim 1,
The timing controller is
An OLED display device that performs the voltage drop sensing operation at any one of power-on time, vertical blank time, and power-off time. In claim 2,
The data driver is
a digital-to-analog converter that analogizes the data supplied from the timing controller and outputs it;
a sampling unit that samples and holds the voltage sensed through the data line;
an analog-to-digital converter that digitizes the output voltage of the sampling unit and outputs it to the timing controller;
a first switch connecting the digital-to-analog converter and the data line in the programming period;
a second switch connecting the data line and the sampling unit in the sensing period;
a third switch connecting a reference line and the sampling unit in a different sensing mode for sensing characteristics of each subpixel;
A fourth switch connects a reference voltage supply and the reference line during the programming period and the sensing period,
An OLED display device in which the sampling unit senses the charging voltage of the capacitor by sampling and holding the charging voltage of the capacitor through the data line at a sampling point during the sensing period. In claim 9,
Each subpixel includes a light emitting element, a driving TFT driving the light emitting element, a first switching TFT connecting the data line and a gate node of the driving TFT, and a second switching TFT connecting a source node of the driving TFT; and the capacitor connected between the gate node and the source node of the driving TFT,
The gate driver is
Supplying a scan gate pulse to the scan gate line connected to the first switching TFT in each of the programming period and the sensing period, and providing sensing to the sensing gate line connected to the second switching TFT in the programming period and the sensing period. An OLED display device that selects a line for the voltage drop sensing operation by supplying a gate pulse.