CN115831031A - Level conversion circuit, display panel and display device - Google Patents
Level conversion circuit, display panel and display device Download PDFInfo
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- CN115831031A CN115831031A CN202310070273.2A CN202310070273A CN115831031A CN 115831031 A CN115831031 A CN 115831031A CN 202310070273 A CN202310070273 A CN 202310070273A CN 115831031 A CN115831031 A CN 115831031A
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Abstract
The application provides a level conversion circuit, display panel and display device, wherein, level conversion circuit integration sets up on display panel and is connected with the GOA drive circuit who sets up on display panel, level conversion circuit includes first switch circuit, second switch circuit and level switching circuit, when display panel normally works, level switching circuit triggers control second switch circuit to switch on, output bars closes signal to GOA drive circuit, GOA drive circuit normally outputs row scanning signal drive each row of pixel unit and opens and close row by row, when display panel shuts down, level switching circuit triggers control first switch circuit to switch on, and open signal to display panel through GOA drive circuit output bars, thereby drive each row of pixel unit and open and carry out the charge discharge, solve display panel shutdown ghost problem, and simultaneously, display panel's structure has been simplified.
Description
Technical Field
The application belongs to the technical field of display panels, and particularly relates to a level conversion circuit, a display panel and a display device.
Background
The display panel is widely applied to electronic equipment such as mobile phones, computers, liquid crystal televisions and the like, and the GOA (Gate Driver on Array) technology, namely the Array substrate line driving technology, is a driving mode that a Gate scanning driving circuit is manufactured on a thin film transistor Array substrate by utilizing an Array manufacturing process to realize line-by-line scanning, has the advantages of reducing the production cost and realizing the design of a narrow frame of the panel, and is used for various displays.
In the display process of the display panel, the pixel capacitor and the storage capacitor store charges in the display process, and when the display panel is turned off, the pixel capacitor and the storage capacitor still store charges, so that the display panel has residual shadows.
In order to solve the problem of the shutdown afterimage of the display panel, when the display panel is shutdown, the thin film transistor of the display panel is usually controlled to be simultaneously turned on for a certain time to discharge the charges in the pixel capacitor and the storage capacitor, and this function is usually called XON (all turn on).
Currently the XON process is generally as follows: after the display panel is shut down, the front end module provides an XON signal to the special level conversion chip, and the GOA driving circuit pulls the grid closing signal end from the VGL negative voltage to the VGH positive voltage under the control of the output signal of the level conversion chip, so that the displayed pixel voltage is opened, and the residual charges of the pixel capacitor and the storage capacitor are discharged. However, a special level conversion chip is required for realizing charge leakage, and the level conversion chip cannot be integrated on an array substrate of a display panel with a GOA architecture due to the structural characteristics of the level conversion chip, and needs to be arranged outside the display panel, so that the structure of the display panel is more complex.
Disclosure of Invention
An object of the present application is to provide a level shifter circuit, which aims to solve the problem that the structure of a display panel is complex because a conventional level shifter chip cannot be integrated on an array substrate.
A first aspect of the embodiments of the present application provides a level shift circuit, where the level shift circuit is integrally disposed on a display panel, the display panel further includes a GOA driving circuit and pixel units arranged in an array, the GOA driving circuit is respectively connected to the pixel units in each row through a plurality of rows of scanning lines, a signal output end of the level shift circuit is connected to a gate-off signal end of the GOA driving circuit, and the level shift circuit includes:
the input end of the first switch circuit is used for inputting a gate start signal, and the first switch circuit is triggered and conducted by a first level signal and outputs the gate start signal to the GOA driving circuit and the pixel unit through the GOA driving circuit so as to control the pixel unit to be started;
the input end of the second switch circuit is used for inputting a grid closing signal, the output end of the second switch circuit is connected with the output end of the first switch circuit to form a signal output end of the level conversion circuit, the second switch circuit is triggered to be switched on by a second level signal, and the second level signal and the first level signal are level signals with opposite polarities;
the input end of the level switching circuit is used for receiving a shutdown signal, the output end of the level switching circuit is respectively connected with the first switch circuit and the second switch circuit, and the level switching circuit switches and outputs the second level signal when not receiving the shutdown signal and switches and outputs the first level signal when receiving the shutdown signal.
Optionally, the power management integrated circuit is connected to the level shifter circuit through a driving circuit and outputs the gate on signal, the gate off signal and the shutdown signal, and the driving circuit is further connected to a signal end of the timing control circuit.
Optionally, the first switching circuit comprises a first electronic switching tube and a first resistor;
the first end of the first electronic switching tube and the first end of the first resistor are connected together to form the input end of the first switching circuit, the control end of the first electronic switching tube and the second end of the first resistor are connected together to form the control end of the first switching circuit, and the second end of the first electronic switching tube forms the output end of the first switching circuit.
Optionally, the second switching circuit comprises a second electronic switching tube and a second resistor;
the first end of the second electronic switching tube and the first end of the second resistor are connected together to form the input end of the second switching circuit, the control end of the second electronic switching tube and the second end of the second resistor are connected together to form the control end of the second switching circuit, and the second end of the second electronic switching tube forms the output end of the second switching circuit.
Optionally, the output end of the level switching circuit includes a first output end and a second output end, the first output end of the level switching circuit is connected to the control end of the first switch circuit, and the second output end of the level switching circuit is connected to the control end of the second switch circuit;
the level switching circuit comprises a third resistor, a fourth resistor, a third electronic switching tube, a fourth electronic switching tube and a fifth electronic switching tube;
the first end of the third resistor and the control end of the third electronic switching tube are connected in common to form an input end of the level switching circuit, the second end of the third resistor, the first end of the third electronic switching tube and the first end of the fourth electronic switching tube are connected in common to ground, the second end of the third electronic switching tube, the control end of the fourth electronic switching tube, the first end of the fourth resistor and the control end of the fifth electronic switching tube are connected, the first end of the fourth resistor and the first end of the fifth electronic switching tube are connected in common to be connected with a positive power source end, the second end of the fourth electronic switching tube forms a first output end of the level switching circuit, and the second end of the fifth electronic switching tube forms a second output end of the level switching circuit.
Optionally, the level shift circuit further includes:
the input end of the first voltage reduction circuit is used for inputting the shutdown signal, and the output end of the first voltage reduction circuit is connected with the input end of the level switching circuit;
the input end of the second voltage reduction circuit is connected with the first output end of the level switching circuit, and the output end of the second voltage reduction circuit is connected with the control end of the first switch circuit;
and the input end of the third voltage reduction circuit is connected with the second output end of the level switching circuit, and the output end of the second voltage reduction circuit is connected with the control end of the second switch circuit.
Optionally, the first voltage-reducing circuit includes a fifth resistor, and a first end and a second end of the fifth resistor respectively constitute an input end and an output end of the first voltage-reducing circuit;
the second voltage reduction circuit comprises a sixth resistor, and a first end and a second end of the sixth resistor respectively form an input end and an output end of the second voltage reduction circuit;
the third voltage reduction circuit comprises a seventh resistor, and a first end and a second end of the seventh resistor respectively form an input end and an output end of the third voltage reduction circuit.
A second aspect of the embodiments of the present application provides a display panel, which includes a GOA driving circuit, pixel units arranged in an array, and the level shift circuit as described above;
the level conversion circuit is integrated on the display panel, the GOA driving circuit is respectively connected with the pixel units through a plurality of rows of scanning lines, and the signal output end of the level conversion circuit is connected with the gate closing signal end of the GOA driving circuit.
Optionally, the GOA driving circuit includes a plurality of cascaded GOA units, and signal output terminals of the level shifter circuit are respectively connected to signal input terminals of the plurality of GOA units in common.
A third aspect of the embodiments of the present application provides a display device, which includes a power management integrated circuit, a timing control circuit, a driving circuit, and the display panel as described above, where the power management integrated circuit is connected to the display panel through the driving circuit, the driving circuit is disposed on the display panel and connected to multiple columns of pixel units through multiple columns of data lines, and the driving circuit is further connected to the timing control circuit.
Compared with the prior art, the embodiment of the application has the advantages that: the level switching circuit is arranged on the display panel in an integrated mode and connected with the GOA driving circuit arranged on the display panel, the level switching circuit comprises a first switch circuit, a second switch circuit and a level switching circuit, when the display panel works normally, the level switching circuit triggers and controls the second switch circuit to be conducted, a grid closing signal is output to the GOA driving circuit, the GOA driving circuit normally outputs row scanning signals to drive pixel units of all rows to be opened and closed line by line, when the display panel is shut down, the level switching circuit triggers and controls the first switch circuit to be conducted, and the grid opening signal is output to the display panel through the GOA driving circuit, so that the pixel units of all rows are driven to be opened and charge is discharged, the problem of shutdown ghost of the display panel is solved, and meanwhile, the structure of the display panel is simplified.
Drawings
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a pixel array in the display device shown in FIG. 1;
FIG. 3 is a schematic structural diagram of a pixel unit in the pixel array shown in FIG. 2;
FIG. 4 is a schematic diagram of a GOA driving circuit of the display device shown in FIG. 1;
FIG. 5 is a schematic circuit diagram of a GO unit in the GOA driving circuit shown in FIG. 4;
FIG. 6 is a first circuit diagram of a middle level shift circuit of the display device shown in FIG. 1;
FIG. 7 is a signal waveform diagram of the level shifter circuit shown in FIG. 6;
fig. 8 is a second circuit diagram of the middle level shift circuit of the display device shown in fig. 1.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In a first aspect of the embodiment of the present application, a level shift circuit 10 is provided, where the level shift circuit 10 receives a shutdown signal XON and outputs a gate start signal VGH to a GOA driving circuit 20, so that when a display panel 100 is shutdown, each row of pixel units 31 is started by the GOA driving circuit 20, charges of a pixel capacitor Cls and a storage capacitor Cst in the pixel units 31 are discharged, and a shutdown ghost problem is solved.
As shown in fig. 1, the level shifter 10 is integrally disposed on the display panel 100, the display panel 100 further includes a GOA driver 20 and pixel units 31 arranged in an array, the pixel units 31 form a pixel array 30 and are located in a display area, as shown in fig. 2, the display panel 100 further includes a plurality of rows of data lines disposed in parallel and at intervals and a plurality of rows of scan lines disposed in parallel and at intervals, for example, a red pixel unit 31 in a first row and a first column is connected to a first data line S1 and a first scan line G1, the pixel unit 31 is respectively connected to an adjacent data line and scan line, the GOA driver 20 is respectively connected to each row of pixel units 31 through the plurality of rows of scan lines, the driving circuit 300 is connected to each row of data lines through a plurality of data lines, wherein the display panel 100 is composed of a color film substrate, an array substrate, and a liquid crystal layer disposed between the color film substrate and the array substrate, the GOA driving circuit 20, the level conversion circuit 10, the data lines S1 to Sn, the scan lines G1 to Gn, first common electrode lines and pixel units 31 are disposed on the array substrate, and second common electrode lines are disposed on the color film substrate, wherein as shown in fig. 3, the pixel units 31 include thin film transistors T and pixel electrodes, the pixel electrodes and the first common electrode lines form storage capacitors Cst, and the pixel electrodes and the second common electrode lines form pixel capacitors Cls.
The driving circuit 300 is further connected to the GOA driving circuit 20 through a control signal line for transmitting the GOA control signal to the GOA driving circuit 20, the GOA driving circuit 20 outputs the gate-on signal VGH row by row according to the received GOA control signal, and outputs the gate-off signals VGL in the remaining rows, thereby driving the pixel units 31 in each row to be turned on and off, and when the pixel units 31 in each row are turned on, the pixel units 31 receive the data signals transmitted by the data lines and display the corresponding image information under the driving of the data signals.
The GOA control signal includes a clock signal and a gate off signal VGL, a gate off signal terminal Vss of the GOA driving circuit 20 is connected to a signal terminal of the driving circuit 300, and receives the gate off signal VGL, as shown in fig. 4, the GOA driving circuit 20 includes a plurality of cascaded GOA units 21, a signal output terminal of the level shifter circuit 10 is respectively connected to signal input terminals of the plurality of GOA units 21, that is, is connected to the gate off signal terminal Vss of each GOA unit 21, the GOA units 21output the gate on signal VGH and the gate off signal VGL to each row of scanning lines one by one, and in normal display operation, each row of pixel units 31 is turned on and off row by row.
For example, as shown in fig. 5, the GOA unit 21 has a 4T1C structure, and the working timing of the GOA unit 21 of 4T1C is analyzed as follows.
The first step is as follows: before the Output signal of the GOA unit 21 in the previous stage arrives, although the CLK signal line has a high voltage input to the source of M3, PU is at a low voltage, M3 is in an off state, and Output does not Output a high voltage.
The second step is that: output N-1 of the previous-stage GOA unit 21 provides an input signal to the GOA unit 21, M1 is turned on, PU node is raised to V1, and M3 is also in an on state, but since the CLK signal connected to the source of M3 is still low, output N of the GOA unit 21 still does not Output high.
The third step: the CLK signal outputs a high potential at this time, and under the capacitive coupling effect of the gate and source parasitic capacitors cgd of M3, the potential at the PU point is also pulled high synchronously, that is, the potential at the PU point is raised from V1 to V2, at this time, the conduction capability of M3 is also increased greatly, and a current is Output, so that Output outputs a high potential, and the thin film transistor T of the connected row of pixel units 31 is turned on.
The fourth step: since Output of the current GOA cell 21 is an input signal of the next stage GOA cell 21, the next stage is also being precharged during Output. As the CLK signal changes from high to low, the high-potential signal Output N +1 of the next stage is input to the current stage as a reset signal, and the PD point is high, then M2 and M4 are turned on, so that the two ends of the capacitor Cgd are connected to the gate-off signal end for discharging, output N is also connected to the low-potential gate-off signal end Vss, and the thin film transistor T of the connected row of pixel units 31 is turned off.
Since the pixel capacitors Cls and the storage capacitors Cst store charges during the display process, and the pixel capacitors Cls and the storage capacitors Cst still store charges during the shutdown process, so that the display panel 100 has shutdown ghosting, on the premise of simplifying the display panel 100, the level shift circuit 10 is provided, a signal output end of the level shift circuit 10 is connected to the gate off signal end Vss of the GOA driving circuit 20, and outputs the gate on signal VGH to the gate off signal ends Vss of the GOA units 21 of the GOA driving circuit 20 during the shutdown process, and outputs the gate on signal VGH to the pixel units 31 in each row through the GOA units 21, so as to discharge the residual charges of the pixel capacitors Cls and the storage capacitors Cst in the pixel units 31, and solve the shutdown ghosting problem.
Specifically, as shown in fig. 1, the level shift circuit 10 includes:
the first switch circuit 11, an input end of the first switch circuit 11 is used for inputting a gate start signal VGH, the first switch circuit 11 is triggered and conducted by a first level signal, and outputs the gate start signal VGH to the GOA driving circuit 20 and to the pixel unit 31 through the GOA driving circuit 20, so as to control the pixel unit 31 to be turned on;
the input end of the second switch circuit 12 is used for inputting a gate-off signal VGL, the output end of the second switch circuit 12 is connected with the output end of the first switch circuit 11 to form a signal output end of the level shift circuit 10, the second switch circuit 12 is triggered and conducted by a second level signal, and the second level signal and the first level signal are level signals with opposite polarities;
the input end of the level switching circuit 13 is used for receiving the shutdown signal XON, the output end of the level switching circuit 13 is respectively connected with the first switch circuit 11 and the second switch circuit 12, and the level switching circuit 13 switches to output the second level signal when the shutdown signal XON is not received and switches to output the first level signal when the shutdown signal XON is received.
When the display panel 100 normally works, the driving circuit 300 outputs a data signal to a data line, the GOA driving circuit 20 outputs a row scanning signal to a scanning line, the display panel 100 receives a corresponding data signal and a row scanning signal to display image information, meanwhile, the level switching circuit 13 does not receive the shutdown signal XON, the level switching circuit 13 triggers to output a second level signal, the second level signal triggers the second switch circuit 12 to be turned on, the gate shutdown signal VGL is output to the gate shutdown signal terminal Vss of each GOA unit 21 of the GOA driving circuit 20, the gate start signal VGH is a high level signal, the gate shutdown signal VGL is a low level signal, and the GOA driving circuit 20 normally drives the display panel 100 to work after receiving the gate shutdown signal VGL with a low level.
Meanwhile, when the display panel 100 is turned off, the level switching circuit 13 receives the shutdown signal XON output by the front end module and triggers to output the first level signal to the first switch circuit 11, the first switch circuit 11 triggers to turn on and outputs the gate on signal VGH with a high potential to each GOA unit 21 of the GOA driving circuit 20, the GOA units 21 synchronously output the gate on signal VGH to each row of pixel units 31, the pixel units 31 are turned on and perform charge discharge on the pixel capacitors Cls and the storage capacitors Cst inside the pixel units, so as to discharge residual charges in the display panel 100 and eliminate shutdown ghost.
The level shift circuit 10 is integrally disposed on the display panel 100 and connected to the GOA driving circuit 20 disposed on the display panel 100, so that the structure of the display panel 100 is simplified, the level shift circuit 10 can be disposed on the array substrate in a corresponding process manner, optionally, the level shift circuit 10 is printed on the array substrate in a printing manner, thereby reducing the design process of the display panel 100 and reducing the production cost.
Meanwhile, the gate-on signal VGH, the gate-off signal VGL, and the shutdown signal XON may be generated by the driving circuit 300, or generated by the timing control circuit 200 at the front end, and may also be generated by the power management integrated circuit 400, where the power management integrated circuit 400 is configured to provide the operating power and/or the control signal required by the timing control circuit 200, the driving circuit 300, and the GOA driving circuit 20, and the timing control circuit 200 is configured to provide the timing control signal required by the GOA driving circuit 20 and the driving circuit 300.
In order to improve the discharging timeliness and the aperture ratio, optionally, the power management integrated circuit 400 is connected to the level shift circuit 10 through the driving circuit 300 and outputs the gate-on signal VGH, the gate-off signal VGL and the shutdown signal XON, and the driving circuit 300 is further connected to a signal terminal of the timing control circuit 200.
When the display panel 100 is turned on or off, the power management integrated circuit 400 is the first-response module, and therefore, the timeliness of the discharge of the shutdown signal XON output correspondingly through the power management integrated circuit 400 is high, meanwhile, when a GOA driving architecture is adopted, the driving circuit 300 is composed of a plurality of chip-on-films, the chip-on-films are bound on the display panel 100 and connected with the pixel unit 31 and the GOA driving circuit 20 through signal lines, a driving chip and a plurality of transmission channels are arranged inside the chip-on-films, the driving chip is connected with the timing control circuit 200 and the power management integrated circuit 400, the driving chip transmits corresponding signals to the pixel unit 31 and the GOA driving circuit 20 through the plurality of transmission channels, and in order to improve the aperture ratio and reduce additional wiring on the display panel 100, the power management integrated circuit 400 indirectly outputs the gate opening signal VGH, the gate closing signal VGL and the shutdown signal XON to the level conversion circuit 10 through the driving circuit 300, and improve the aperture ratio of the display panel 100.
The first switch circuit 11, the second switch circuit 12 and the level switch circuit 13 may adopt corresponding switch tubes, signal conversion circuits and other structures, and optionally, as shown in fig. 6, the first switch circuit 11 includes a first electronic switch tube Q1 and a first resistor R1;
the first end of the first electronic switch tube Q1 and the first end of the first resistor R1 are connected together to form an input end of the first switch circuit 11, the control end of the first electronic switch tube Q1 and the second end of the first resistor R1 are connected together to form a control end of the first switch circuit 11, and the second end of the first electronic switch tube Q1 forms an output end of the first switch circuit 11.
The second switch circuit 12 comprises a second electronic switch tube Q2 and a second resistor R2;
a first end of the second electronic switching tube Q2 and a first end of the second resistor R2 are commonly connected to form an input end of the second switching circuit 12, a control end of the second electronic switching tube Q2 and a second end of the second resistor R2 are commonly connected to form a control end of the second switching circuit 12, and a second end of the second electronic switching tube Q2 forms an output end of the second switching circuit 12.
The output end of the level switching circuit 13 comprises a first output end and a second output end, the first output end of the level switching circuit 13 is connected with the control end of the first switch circuit 11, and the second output end of the level switching circuit 13 is connected with the control end of the second switch circuit 12;
the level switching circuit 13 comprises a third resistor R3, a fourth resistor R4, a third electronic switching tube Q3, a fourth electronic switching tube Q4 and a fifth electronic switching tube Q5;
the first end of the third resistor R3 and the control end of the third electronic switch tube Q3 are connected in common to form an input end of the level switching circuit 13, the second end of the third resistor R3, the first end of the third electronic switch tube Q3 and the first end of the fourth electronic switch tube Q4 are connected in common to ground, the second end of the third electronic switch tube Q3, the control end of the fourth electronic switch tube Q4, the first end of the fourth resistor R4 and the control end of the fifth electronic switch tube Q5 are connected in common to each other, the first end of the fourth resistor R4 and the first end of the fifth electronic switch tube Q5 are connected in common to a positive power supply end, the second end of the fourth electronic switch tube Q4 forms a first output end of the level switching circuit 13, and the second end of the fifth electronic switch tube Q5 forms a second output end of the level switching circuit 13.
In this embodiment, the positive voltage VDD inputted by the positive power terminal may be provided by the power management integrated circuit 400 or provided by other modules, as shown in fig. 7, when the display panel 100 normally works, the shutdown signal XON is high potential, the third electronic switching tube Q3 is turned on, the point a, that is, the control terminals of the fourth electronic switching tube Q4 and the fifth electronic switching tube Q5, is low potential, the fifth electronic switching tube Q5 is controlled to be turned on, the second switching circuit 12 receives high level, the second electronic switching tube Q2 is controlled to be turned on, and outputs the gate-off signal VGL to the gate-off signal terminal Vss of the GOA driving circuit 20, the fourth electronic switching tube Q4 is turned off, the first electronic switching tube Q1 is synchronously turned off, and the GOA driving circuit 20 normally drives the display panel 100 to be turned on and turned off line by line.
When the display panel 100 is turned off, the turn-off signal XON is at a low potential, the third electronic switch Q3 is turned off, the point a is at a high potential, the fourth electronic switch Q4 is triggered to be turned on, the fifth electronic switch Q5 is triggered to be turned off, the first electronic switch Q1 is triggered to be turned on, and outputs the gate-on signal VGH to the gate-off signal terminal Vss of the GOA driving circuit 20 and to the pixel units 31 through the GOA driving circuit 20, so as to drive the thin film transistors T of each row of the pixel units 31 to be turned on and perform charge discharge on the pixel capacitors Cls and the storage capacitors Cst, thereby eliminating the turn-off ghost of the display panel 100 and simplifying the structure of the display panel 100.
The third electronic switch Q3 may adopt a corresponding switch structure corresponding to the on/off manner of the shutdown signal XON, such as an NPN triode and an NMOS transistor, and optionally, the third electronic switch Q3 is an NMOS transistor, correspondingly, the fourth electronic switch Q4 is an NMOS transistor, the fifth electronic switch Q5 is a PMOS transistor, the first electronic switch Q1 is a PMOS transistor, the second electronic switch Q2 is an NMOS transistor, the first level signal is a low level, and the second level signal is a high level.
In the embodiment, the array substrate can be directly formed on the array substrate by printing through a simple structure of a plurality of electronic switching tubes and a plurality of resistors, so that the design process is simplified.
In order to ensure that each electronic switch tube inputs an operating voltage within a normal operating voltage range, and avoid the electronic switch tube from being damaged due to overvoltage, as shown in fig. 8, the level shift circuit 10 optionally further includes:
the input end of the first voltage-reducing circuit 14 is used for inputting a shutdown signal XON, and the output end of the first voltage-reducing circuit 14 is connected with the input end of the level switching circuit 13;
the input end of the second voltage-reducing circuit 15 is connected with the first output end of the level switching circuit 13, and the output end of the second voltage-reducing circuit 15 is connected with the control end of the first switch circuit 11;
and an input end of the third voltage-reducing circuit 16 is connected with a second output end of the level switching circuit 13, and an output end of the second voltage-reducing circuit 15 is connected with a control end of the second switch circuit 12.
Wherein, first step-down circuit 14 is used for stepping down the high low potential of the shutdown signal XON of input, avoid third electronic switch pipe Q3 overvoltage to damage, second step-down circuit 15 is used for stepping down the voltage between level switching circuit 13 and first switch circuit 11 and handles, avoid first electronic switch pipe Q1 overvoltage to damage, simultaneously, third step-down circuit 16 is used for stepping down the voltage between level switching circuit 13 and second switch circuit 12, avoid second electronic switch pipe Q2 overvoltage to damage.
Each voltage reduction circuit may adopt a BUCK circuit, a voltage stabilizing circuit, a voltage dividing resistor, and other structures, as shown in fig. 8, optionally, the first voltage reduction circuit 14 includes a fifth resistor R5, and a first end and a second end of the fifth resistor R5 respectively form an input end and an output end of the first voltage reduction circuit 14;
the second voltage-reducing circuit 15 includes a sixth resistor R6, and a first end and a second end of the sixth resistor R6 respectively constitute an input end and an output end of the second voltage-reducing circuit 15;
the third voltage-reducing circuit 16 includes a seventh resistor R7, and a first end and a second end of the seventh resistor R7 respectively constitute an input end and an output end of the third voltage-reducing circuit 16.
In this embodiment, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are used to perform voltage reduction and current limitation, so as to perform overvoltage and overcurrent protection on the electronic switching tubes respectively connected correspondingly, thereby improving the reliability of the level shift circuit 10, and moreover, the simple resistor structure is adopted, so that the design cost is reduced, and meanwhile, the printing process of the level shift circuit 10 is facilitated.
Compared with the prior art, the embodiment of the application has the advantages that: the level shift circuit 10 is integrally disposed on the display panel 100 and connected to the GOA driving circuit 20 disposed on the display panel 100, the level shift circuit 10 includes a first switch circuit 11, a second switch circuit 12 and a level shift circuit 13, when the display panel 100 normally works, the level shift circuit 13 triggers and controls the second switch circuit 12 to be turned on, and outputs a gate off signal VGL to the GOA driving circuit 20, the GOA driving circuit 20 normally outputs a row scanning signal to drive the pixel units 31 of each row to be turned on and off row by row, when the display panel 100 is turned off, the level shift circuit 13 triggers and controls the first switch circuit 11 to be turned on, and outputs a gate on signal VGH to the display panel 100 through the GOA driving circuit 20, thereby driving the pixel units 31 of each row to be turned on and discharging charges, and solving the problem of shutdown ghost of the display panel 100, and simultaneously simplifying the structure of the display panel 100.
The present application further provides a display panel 100, where the display panel 100 includes a GOA driving circuit 20, pixel units 31 arranged in an array, and a level shift circuit 10, and the specific structure of the level shift circuit 10 refers to the above embodiments, and since the display panel 100 adopts all technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is provided herein. The level shift circuit 10 is integrally disposed on the display panel 100, the GOA driving circuit 20 is respectively connected to the pixel units 31 in each row through a plurality of rows of scan lines, and a signal output end of the level shift circuit 10 is connected to a gate-off signal terminal Vss of the GOA driving circuit 20.
In this embodiment, as shown in fig. 1, the level shift circuit 10 is integrally disposed on the display panel 100, the display panel 100 further includes a GOA driving circuit 20 and pixel units 31 arranged in an array, the pixel units 31 form a pixel array 30 and are located in a display area, as shown in fig. 2, the display panel 100 further includes a plurality of rows of data lines arranged in parallel and at intervals and a plurality of rows of scanning lines arranged in parallel and at intervals, the pixel units 31 are respectively connected with adjacent data lines and scanning lines, the GOA driving circuit 20 is respectively connected with each row of pixel units 31 through the plurality of rows of scanning lines, the driving circuit 300 is connected with each row of data lines through the plurality of data lines, wherein the display panel 100 is composed of a color film substrate, an array substrate and a liquid crystal layer disposed between the color film substrate and the array substrate, the GOA driving circuit 20, the level shift circuit 10, data lines S1 to Sn, scanning lines G1 to Gn, first common electrode lines and the pixel units 31 are disposed on the color film array substrate, and second common electrode lines are disposed on the color film substrate, wherein, as shown in fig. 3, the pixel units include a thin film transistor and a pixel T, and a pixel storage electrode, and a second common storage electrode line, and a second common storage capacitor.
The driving circuit 300 is further connected to the GOA driving circuit 20 through a control signal line for transmitting the GOA control signal to the GOA driving circuit 20, the GOA driving circuit 20 outputs the gate-on signal VGH row by row according to the received GOA control signal, and outputs the gate-off signals VGL in the remaining rows, thereby driving the pixel units 31 in each row to be turned on and off, and when the pixel units 31 in each row are turned on, the pixel units 31 receive the data signals transmitted by the data lines and display the corresponding image information under the driving of the data signals.
The GOA control signal includes a clock signal and a gate-off signal VGL, a gate-off signal terminal Vss of the GOA driving circuit 20 is connected to a signal terminal of the driving circuit 300 and receives the gate-off signal VGL, as shown in fig. 4, optionally, the GOA driving circuit 20 includes a plurality of cascaded GOA units 21, a signal output terminal of the level shifter circuit 10 is respectively connected to signal input terminals of the plurality of GOA units 21, i.e., connected to the gate-off signal terminal Vss of each GOA unit 21, the GOA units 21output gate-on signals VGH and gate-off signals VGL to each row of scan lines one by one, and the pixel units 31 in each row are turned on and off row by row during normal display operation.
For example, as shown in fig. 5, the GOA unit 21 has a 4T1C structure, and the working timing of the GOA unit 21 of 4T1C is analyzed as follows.
The first step is as follows: before the Output signal of the GOA unit 21 in the previous stage arrives, although the CLK signal line has a high voltage input to the source of M3, PU is at a low voltage, M3 is in an off state, and Output does not Output a high voltage.
The second step is that: output N-1 of the previous-stage GOA unit 21 provides an input signal to the GOA unit 21, M1 is turned on, PU node is raised to V1, and M3 is also in an on state, but since the CLK signal connected to the source of M3 is still low, output N of the GOA unit 21 still does not Output high.
The third step: the CLK signal outputs a high potential at this time, and under the capacitive coupling effect of the gate and source parasitic capacitors cgd of M3, the potential at the PU point is also pulled high synchronously, that is, the potential at the PU point is raised from V1 to V2, at this time, the conduction capability of M3 is also increased greatly, and a current is Output, so that Output outputs a high potential, and the thin film transistor T of the connected row of pixel units 31 is turned on.
The fourth step: since Output of the current GOA cell 21 is an input signal of the next stage GOA cell 21, the next stage is also being precharged during Output. As the CLK signal changes from high to low, the high signal Output N +1 of the next stage is input to the current stage as a reset signal, so that the PD point is high, M2 and M4 are turned on, the two ends of the capacitor Cgd are connected to the gate-off signal end for discharging, the Output N is also connected to the low gate-off signal end Vss, and the thin film transistor T of the connected row of pixel units 31 is turned off.
Since the pixel capacitors Cls and the storage capacitors Cst store charges during the display process, and the pixel capacitors Cls and the storage capacitors Cst still store charges during the shutdown process, so that the display panel 100 has shutdown ghosting, on the premise of simplifying the display panel 100, the level shift circuit 10 is provided, a signal output end of the level shift circuit 10 is connected to the gate off signal end Vss of the GOA driving circuit 20, and outputs the gate on signal VGH to the gate off signal ends Vss of the GOA units 21 of the GOA driving circuit 20 during the shutdown process, and outputs the gate on signal VGH to the pixel units 31 in each row through the GOA units 21, so as to discharge the residual charges of the pixel capacitors Cls and the storage capacitors Cst in the pixel units 31, and solve the shutdown ghosting problem.
As shown in fig. 1, the display device includes a power management integrated circuit 400, a timing control circuit 200, a driving circuit 300, and a display panel 100, and the specific structure of the display panel 100 refers to the above embodiments, and since the display device adopts all the technical solutions of all the above embodiments, the display device at least has all the beneficial effects brought by the technical solutions of the above embodiments, and details are not repeated herein. The power management integrated circuit 400 is connected to the display panel 100 through the driving circuit 300, the driving circuit 300 is disposed on the display panel 100 and connected to a plurality of rows of the pixel units 31 through a plurality of rows of data lines, and the driving circuit 300 is further connected to the timing control circuit 200.
In this embodiment, when the display panel 100 normally works, the driving circuit 300 outputs a data signal to a data line, the GOA driving circuit 20 outputs a row scanning signal to a scanning line, the display panel 100 receives a corresponding data signal and a row scanning signal to display image information, meanwhile, the level switching circuit 13 does not receive the shutdown signal XON, the level switching circuit 13 triggers to output a second level signal, the second level signal triggers the second switch circuit 12 to be turned on, the gate shutdown signal VGL is output to the gate shutdown signal terminal Vss of each GOA unit 21 of the GOA driving circuit 20, the gate startup signal VGH is a high level signal, the gate shutdown signal VGL is a low level signal, and the GOA driving circuit 20 normally drives the display panel 100 to work after receiving the low level gate shutdown signal VGL.
Meanwhile, when the display panel 100 is turned off, the level switching circuit 13 receives a shutdown signal XON output by the front end module, and triggers to output a first level signal to the first switch circuit 11, the first switch circuit 11 triggers to turn on, and outputs a gate on signal VGH with a high potential to each GOA unit 21 of the GOA driving circuit 20, the GOA units 21 synchronously output the gate on signals VGH to each row of pixel units 31, the pixel units 31 are turned on, and perform charge discharge on the pixel capacitors Cls and the storage capacitors Cst inside the pixel units 31, so as to discharge residual charges in the display panel 100 and eliminate shutdown ghost.
The level shift circuit 10 is integrally disposed on the display panel 100 and connected to the GOA driving circuit 20 disposed on the display panel 100, so that the structure of the display panel 100 is simplified, the level shift circuit 10 can be disposed on the array substrate in a corresponding process manner, optionally, the level shift circuit 10 is printed on the array substrate in a printing manner, thereby reducing the design process of the display panel 100 and reducing the production cost.
Meanwhile, the gate turn-on signal VGH, the gate turn-off signal VGL, and the turn-off signal XON may be generated by the driving circuit 300, or generated by the timing control circuit 200 at the front end, or generated by the power management integrated circuit 400, where the power management integrated circuit 400 is configured to provide the operating power and/or the control signal required by the timing control circuit 200, the driving circuit 300, and the GOA driving circuit 20, and the timing control circuit 200 is configured to provide the timing control signal required by the GOA driving circuit 20 and the driving circuit 300.
In order to improve the discharging timeliness and the aperture ratio, optionally, the power management integrated circuit 400 is connected to the level shift circuit 10 through the driving circuit 300 and outputs the gate-on signal VGH, the gate-off signal VGL and the shutdown signal XON, and the driving circuit 300 is further connected to a signal terminal of the timing control circuit 200.
When the display panel 100 is turned on or off, the power management integrated circuit 400 is the first-response module, and therefore, the timeliness of the discharge of the shutdown signal XON output correspondingly through the power management integrated circuit 400 is high, meanwhile, when a GOA driving architecture is adopted, the driving circuit 300 is composed of a plurality of chip-on-films, the chip-on-films are bound on the display panel 100 and connected with the pixel unit 31 and the GOA driving circuit 20 through signal lines, a driving chip and a plurality of transmission channels are arranged inside the chip-on-films, the driving chip is connected with the timing control circuit 200 and the power management integrated circuit 400, the driving chip transmits corresponding signals to the pixel unit 31 and the GOA driving circuit 20 through the plurality of transmission channels, and in order to improve the aperture ratio and reduce additional wiring on the display panel 100, the power management integrated circuit 400 indirectly outputs the gate opening signal VGH, the gate closing signal VGL and the shutdown signal XON to the level conversion circuit 10 through the driving circuit 300, and improve the aperture ratio of the display panel 100.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A level shift circuit is integrally arranged on a display panel, the display panel further comprises a GOA driving circuit and pixel units arranged in an array, the GOA driving circuit is respectively connected with the pixel units in each row through a plurality of rows of scanning lines, a signal output end of the level shift circuit is connected with a gate closing signal end of the GOA driving circuit, and the level shift circuit comprises:
the input end of the first switch circuit is used for inputting a gate start signal, and the first switch circuit is triggered and conducted by a first level signal and outputs the gate start signal to the GOA driving circuit and the pixel unit through the GOA driving circuit so as to control the pixel unit to be started;
the input end of the second switch circuit is used for inputting a grid closing signal, the output end of the second switch circuit is connected with the output end of the first switch circuit to form a signal output end of the level conversion circuit, the second switch circuit is triggered to be switched on by a second level signal, and the second level signal and the first level signal are level signals with opposite polarities;
the input end of the level switching circuit is used for receiving a shutdown signal, the output end of the level switching circuit is respectively connected with the first switch circuit and the second switch circuit, and the level switching circuit switches and outputs the second level signal when not receiving the shutdown signal and switches and outputs the first level signal when receiving the shutdown signal.
2. The level shift circuit as claimed in claim 1, wherein the power management integrated circuit is connected to the level shift circuit through a driving circuit and outputs the gate-on signal, the gate-off signal and the shutdown signal, and the driving circuit is further connected to a signal terminal of the timing control circuit.
3. The level shift circuit of claim 1, wherein the first switching circuit comprises a first electronic switching tube and a first resistor;
the first end of the first electronic switch tube and the first end of the first resistor are connected together to form the input end of the first switch circuit, the control end of the first electronic switch tube and the second end of the first resistor are connected together to form the control end of the first switch circuit, and the second end of the first electronic switch tube forms the output end of the first switch circuit.
4. The circuit of claim 1, wherein the second switching circuit comprises a second electronic switch tube and a second resistor;
the first end of the second electronic switching tube and the first end of the second resistor are connected together to form the input end of the second switching circuit, the control end of the second electronic switching tube and the second end of the second resistor are connected together to form the control end of the second switching circuit, and the second end of the second electronic switching tube forms the output end of the second switching circuit.
5. The level shift circuit of claim 1, wherein the output terminals of the level shift circuit comprise a first output terminal and a second output terminal, the first output terminal of the level shift circuit being connected to the control terminal of the first switch circuit, the second output terminal of the level shift circuit being connected to the control terminal of the second switch circuit;
the level switching circuit comprises a third resistor, a fourth resistor, a third electronic switching tube, a fourth electronic switching tube and a fifth electronic switching tube;
the first end of the third resistor and the control end of the third electronic switching tube are connected in common to form an input end of the level switching circuit, the second end of the third resistor, the first end of the third electronic switching tube and the first end of the fourth electronic switching tube are connected in common to ground, the second end of the third electronic switching tube, the control end of the fourth electronic switching tube, the first end of the fourth resistor and the control end of the fifth electronic switching tube are connected, the first end of the fourth resistor and the first end of the fifth electronic switching tube are connected in common to be connected with a positive power source end, the second end of the fourth electronic switching tube forms a first output end of the level switching circuit, and the second end of the fifth electronic switching tube forms a second output end of the level switching circuit.
6. The level shift circuit of claim 5, wherein the level shift circuit further comprises:
the input end of the first voltage reduction circuit is used for inputting the shutdown signal, and the output end of the first voltage reduction circuit is connected with the input end of the level switching circuit;
the input end of the second voltage reduction circuit is connected with the first output end of the level switching circuit, and the output end of the second voltage reduction circuit is connected with the control end of the first switch circuit;
and the input end of the third voltage reduction circuit is connected with the second output end of the level switching circuit, and the output end of the second voltage reduction circuit is connected with the control end of the second switch circuit.
7. The circuit of claim 6, wherein the first voltage-reducing circuit comprises a fifth resistor, a first terminal and a second terminal of the fifth resistor respectively constituting an input terminal and an output terminal of the first voltage-reducing circuit;
the second voltage reduction circuit comprises a sixth resistor, and a first end and a second end of the sixth resistor respectively form an input end and an output end of the second voltage reduction circuit;
the third voltage reduction circuit comprises a seventh resistor, and a first end and a second end of the seventh resistor respectively form an input end and an output end of the third voltage reduction circuit.
8. A display panel comprising a GOA driver circuit, an array of pixel cells, and a level shifter circuit according to any one of claims 1~7;
the level conversion circuit is integrated on the display panel, the GOA driving circuit is respectively connected with the pixel units through a plurality of rows of scanning lines, and the signal output end of the level conversion circuit is connected with the gate closing signal end of the GOA driving circuit.
9. The display panel according to claim 8, wherein the GOA driving circuit comprises a plurality of cascaded GOA units, and signal output terminals of the level shifter circuit are respectively connected in common with signal input terminals of the plurality of GOA units.
10. A display device, comprising a power management integrated circuit, a timing control circuit, a driving circuit and the display panel of claim 8 or 9, wherein the power management integrated circuit is connected to the display panel through the driving circuit, the driving circuit is disposed on the display panel and connected to a plurality of rows of the pixel units through a plurality of rows of data lines, and the driving circuit is further connected to the timing control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202310070273.2A CN115831031A (en) | 2023-02-07 | 2023-02-07 | Level conversion circuit, display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310070273.2A CN115831031A (en) | 2023-02-07 | 2023-02-07 | Level conversion circuit, display panel and display device |
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| CN115831031A true CN115831031A (en) | 2023-03-21 |
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| CN202310070273.2A Pending CN115831031A (en) | 2023-02-07 | 2023-02-07 | Level conversion circuit, display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117275431A (en) * | 2023-11-14 | 2023-12-22 | 惠科股份有限公司 | Driving circuit and display device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320171A (en) * | 2007-06-08 | 2008-12-10 | 群康科技(深圳)有限公司 | LCD and method for improving power-off ghost |
| US20120206430A1 (en) * | 2011-02-16 | 2012-08-16 | Sct Technology, Ltd. | Circuits for eliminating ghosting phenomena in display panel having light emitters |
| CN104575433A (en) * | 2015-02-04 | 2015-04-29 | 京东方科技集团股份有限公司 | GOA reset circuit and driving method, array substrate, display panel and device |
| CN107146590A (en) * | 2017-07-06 | 2017-09-08 | 深圳市华星光电技术有限公司 | The driving method of GOA circuits |
| CN207425330U (en) * | 2017-11-17 | 2018-05-29 | 四川长虹电器股份有限公司 | The quick circuit for eliminating LCD TV power-off ghost shadow |
| CN109785788A (en) * | 2019-03-29 | 2019-05-21 | 京东方科技集团股份有限公司 | Level processing circuit, gate driving circuit and display device |
| CN214203169U (en) * | 2021-01-14 | 2021-09-14 | 昆山龙腾光电股份有限公司 | Display module |
| CN114974150A (en) * | 2021-02-24 | 2022-08-30 | 京东方科技集团股份有限公司 | Discharge circuit, discharge method and display device |
-
2023
- 2023-02-07 CN CN202310070273.2A patent/CN115831031A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101320171A (en) * | 2007-06-08 | 2008-12-10 | 群康科技(深圳)有限公司 | LCD and method for improving power-off ghost |
| US20120206430A1 (en) * | 2011-02-16 | 2012-08-16 | Sct Technology, Ltd. | Circuits for eliminating ghosting phenomena in display panel having light emitters |
| CN104575433A (en) * | 2015-02-04 | 2015-04-29 | 京东方科技集团股份有限公司 | GOA reset circuit and driving method, array substrate, display panel and device |
| CN107146590A (en) * | 2017-07-06 | 2017-09-08 | 深圳市华星光电技术有限公司 | The driving method of GOA circuits |
| CN207425330U (en) * | 2017-11-17 | 2018-05-29 | 四川长虹电器股份有限公司 | The quick circuit for eliminating LCD TV power-off ghost shadow |
| CN109785788A (en) * | 2019-03-29 | 2019-05-21 | 京东方科技集团股份有限公司 | Level processing circuit, gate driving circuit and display device |
| CN214203169U (en) * | 2021-01-14 | 2021-09-14 | 昆山龙腾光电股份有限公司 | Display module |
| CN114974150A (en) * | 2021-02-24 | 2022-08-30 | 京东方科技集团股份有限公司 | Discharge circuit, discharge method and display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117275431A (en) * | 2023-11-14 | 2023-12-22 | 惠科股份有限公司 | Driving circuit and display device |
| CN117275431B (en) * | 2023-11-14 | 2024-02-23 | 惠科股份有限公司 | Driving circuit and display device |
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