JP2009245564A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2009245564A5 JP2009245564A5 JP2008094104A JP2008094104A JP2009245564A5 JP 2009245564 A5 JP2009245564 A5 JP 2009245564A5 JP 2008094104 A JP2008094104 A JP 2008094104A JP 2008094104 A JP2008094104 A JP 2008094104A JP 2009245564 A5 JP2009245564 A5 JP 2009245564A5
- Authority
- JP
- Japan
- Prior art keywords
- signal
- voltage
- output
- current path
- reference potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Claims (12)
前記各レジスタ回路は、
前段の出力信号が入力信号として印加され、次段の出力信号がリセット信号として入力され、前記入力信号に基づく第１の信号を出力する保持回路と、
前記第１の信号に基づく電圧が印加され、該第１の信号に基づく信号を前記出力信号として出力する出力回路と、
を備え、
前記保持回路は、
前記入力信号が印加される入力端子と、
前記リセット信号が印加されるリセット端子と、を有し、
２つの電圧レベルを交互に有する第１のクロック信号と所定の基準電位の電圧とが印加され、
前記入力信号が前記入力端子に印加されたとき、前記第１のクロック信号の信号レベルに応じた電圧を前記第１の信号として出力し、前記リセット信号が前記リセット端子に印加されたとき、前記基準電位に応じた電圧を前記第１の信号として出力する手段を有し、
前記出力回路が前記出力信号を出力する出力期間における前記第１のクロック信号の電位と前記出力期間における前記入力信号の電位とが等電位に設定されていることを特徴とするシフトレジスタ。 A multi-stage shift register comprising a plurality of register circuits connected in cascade,
Each of the register circuits is
A holding circuit that applies the output signal of the previous stage as an input signal, the output signal of the next stage as a reset signal, and outputs a first signal based on the input signal;
An output circuit to which a voltage based on the first signal is applied and which outputs a signal based on the first signal as the output signal;
With
The holding circuit is
An input terminal to which the input signal is applied;
A reset terminal to which the reset signal is applied,
A first clock signal having two voltage levels alternately and a voltage of a predetermined reference potential are applied;
When the input signal is applied to the input terminal, a voltage corresponding to the signal level of the first clock signal is output as the first signal, and when the reset signal is applied to the reset terminal, a voltage corresponding to the reference potential have a means for outputting as said first signal,
Shift register, wherein the output circuit is characterized that you have been set to the potential and equipotential of the input signal at the potential and the output period of the first clock signal in an output period for outputting the output signal.
第２の電流路と第２の制御端子を有し、前記第２の電流路の一端が前記第１の薄膜トランジスタの前記第１の電流路の他端に接続され、前記第２の電流路の他端が前記基準電位に接続され、前記第２の制御端子が前記リセット端子に接続された第２の薄膜トランジスタと、
を有することを特徴とする請求項１に記載のシフトレジスタ。 The holding circuit has a first current path and a first control terminal, the first clock signal is applied to one end of the first current path, and the first control terminal is connected to the input terminal. A connected first thin film transistor;
A second current path and the second control terminal, the second current path end connected to the other end of the first current path of the first thin film transistor, said second current path A second thin film transistor having the other end connected to the reference potential and the second control terminal connected to the reset terminal;
The shift register according to claim 1, further comprising:
前記保持回路は、前記入力信号が印加されたとき、前記第１の信号の電圧を前記第１の電圧に応じた電圧とし、次に前記リセット信号が印加されるまでの前記第１の信号の電圧を、前記第１の電圧に応じた電圧又はそれ以上の電位の電圧に保持することを特徴とする請求項１又は２に記載のシフトレジスタ。 The first clock signal has, as voltage levels, a first voltage having a potential higher than the reference potential and a second voltage having a potential lower than the first voltage, and The input signal is applied when the first clock signal is at the first voltage;
When the input signal is applied, the holding circuit sets the voltage of the first signal to a voltage corresponding to the first voltage, and then applies the first signal until the reset signal is applied. 3. The shift register according to claim 1, wherein the voltage is held at a voltage corresponding to the first voltage or a voltage higher than the first voltage. 4.
前記第２のクロック信号は電圧レベルとして、前記基準電位より高い電位を有する第３の電圧と、前記基準電位以上で前記第３の電圧より低い電位の第４の電圧と、を有し、前記第１のクロック信号が前記第１の電圧である期間と前記第２のクロック信号が前記第３の電圧である期間とは重ならないタイミングに設定され、
前記第１の信号の信号レベルが前記第１の電圧に応じた電圧又はそれ以上の電位の電圧であるとき、前記出力信号の信号レベルを前記第２のクロック信号の信号レベルに近づけるように変化させ、前記第１の信号の信号レベルが前記基準電圧に応じた電圧であるとき、前記出力信号の信号レベルを前記基準電位に応じた電圧にする手段を有することを特徴とする請求項３に記載のシフトレジスタ。 The output circuit has a second clock signal having two voltage levels alternately and the reference potential, and has an output terminal for outputting the output signal.
The second clock signal has, as voltage levels, a third voltage having a potential higher than the reference potential, and a fourth voltage having a potential higher than the reference potential and lower than the third voltage, The period when the first clock signal is the first voltage and the period when the second clock signal is the third voltage are set at a timing that does not overlap.
When the signal level of the first signal is a voltage corresponding to the first voltage or higher, the signal level of the output signal changes so as to approach the signal level of the second clock signal. And a means for setting the signal level of the output signal to a voltage corresponding to the reference potential when the signal level of the first signal is a voltage corresponding to the reference voltage. The shift register described.
一端が前記第３の薄膜トランジスタの前記第３の制御端子に接続され、他端が前記第３の薄膜トランジスタの前記第３の電流路の他端に接続された容量成分と、
を有することを特徴とする請求項３に記載のシフトレジスタ。 The output circuit has a third current path and a third control terminal, the second clock signal is applied to one end of the third current path, and the other end of the third current path is It is connected to the output terminal, and a third thin film transistor to which the first signal is applied to the third control terminal,
A capacitive component having one end connected to the third control terminal of the third thin film transistor and the other end connected to the other end of the third current path of the third thin film transistor;
The shift register according to claim 3, further comprising:
前記各レジスタ回路は、
前段の出力信号が入力信号として印加され、次段の出力信号がリセット信号として入力され、前記入力信号に基づく第１の信号を出力する保持回路と、
前記第１の信号と前記第１の信号の反転信号に対応する第２の信号とが印加され、該第１の信号に基づく信号を前記出力信号として出力する出力回路と、
前記第１の信号が印加され、前記第２の信号を出力するインバータ回路と、
を備え、
前記保持回路は、少なくとも、前記基準電位より高い電位を有する第１の電圧と、前記基準電位以上で前記第１の電圧より低い電位の第２の電圧とを有する信号を前記第１の信号として出力し、
前記インバータ回路は、
２つの電圧レベルを交互に有する第１のクロック信号と、所定の基準電位の電圧と、が印加され、
前記第１の信号の信号レベルが前記第１の電圧又はそれより高い電位の電圧であるとき、前記第２の信号の信号レベルを前記基準電位に応じた電圧に変化させ、前記第１の信号の信号レベルが前記第２の電圧であるとき、前記第２の信号の信号レベルを、前記第１のクロック信号の電圧のレベルに応じた電圧に変化させる手段を有し、
前記第１のクロック信号は、前記入力信号が印加される入力期間において、前記第２の信号より高い電圧に設定され、前記入力期間と前記リセット信号が入力されるリセット期間及び前記出力信号を出力する出力期間を除く期間において、前記第２の信号より低い電位に設定される期間を有することを特徴とするシフトレジスタ。 A multi-stage shift register comprising a plurality of register circuits connected in cascade,
Each of the register circuits is
A holding circuit that applies the output signal of the previous stage as an input signal, the output signal of the next stage as a reset signal, and outputs a first signal based on the input signal;
An output circuit to which the first signal and a second signal corresponding to an inverted signal of the first signal are applied, and a signal based on the first signal is output as the output signal;
An inverter circuit that receives the first signal and outputs the second signal;
With
The holding circuit uses, as the first signal, a signal having at least a first voltage having a potential higher than the reference potential and a second voltage having a potential equal to or higher than the reference potential and lower than the first voltage. Output,
The inverter circuit is
A first clock signal having two voltage levels alternately and a voltage of a predetermined reference potential are applied;
When the signal level of the first signal is the voltage of the first voltage or higher, the signal level of the second signal is changed to a voltage corresponding to the reference potential, and the first signal when the signal level of a second voltage, the signal level of the second signal, have a means for varying the voltage corresponding to the level of the voltage of the first clock signal,
The first clock signal is set to a voltage higher than the second signal in an input period in which the input signal is applied, and outputs the input period, the reset period in which the reset signal is input, and the output signal in a period except for the output period of the shift register, characterized in that have a duration that is set to a lower potential than the second signal.
第５の電流路と第５の制御端子を有し、前記第５の電流路の一端が前記第４の薄膜トランジスタの前記第４の電流路の他端に接続されて前記第２の信号を出力し、前記第５の電流路の他端が前記基準電位に接続され、前記第５の制御端子に前記第１の信号が印加される第５の薄膜トランジスタと、
を有することを特徴とする請求項６に記載のシフトレジスタ。 The inverter circuit has a fourth current path and a fourth control terminal, the first clock signal is applied to one end of the fourth current path, and the fourth control terminal is the fourth control terminal. A fourth thin film transistor connected to one end of the current path;
A fifth current path and a fifth control terminal, wherein one end of the fifth current path is connected to the other end of the fourth current path of the fourth thin film transistor to output the second signal; and, the other end of the fifth current path is connected to the reference potential, and a fifth thin film transistor, wherein the fifth said first signal to the control terminal of the is applied,
The shift register according to claim 6, further comprising:
２つの電圧レベルを交互に有する第２のクロック信号と、前記基準電位と、が印加され、
前記第１のクロック信号は電圧レベルとして、前記基準電位より高い電位を有する第１の電圧と、前記第１の電圧より低い電位の第２の電圧と、を有して、前記保持回路に対して前記入力信号は前記第１のクロック信号が前記第１の電圧であるときに印加され、
前記第２のクロック信号は電圧レベルとして、前記基準電位より高い電位を有する第３の電圧と、前記基準電位以上で前記第３の電圧より低い電位の第４の電圧と、を有し、前記第１のクロック信号が前記第１の電圧である期間と前記第２のクロック信号が前記第３の電圧である期間とは重ならないタイミングに設定され、
前記第１の信号の信号レベルが前記第１の電圧又はそれより高い電位の電圧であり、前記第２の信号の信号レベルが前記基準電位に応じた電圧であるとき、前記出力信号の信号レベルを前記第２のクロック信号の信号レベルに近づけ、
前記第１の信号の信号レベルが前記基準電圧に応じた電圧であり、前記第２の信号の信号レベルが前記第１の電圧に応じた電圧であるとき、前記出力信号の信号レベルを前記基準電位に応じた電圧にする手段を有することを特徴とする請求項６に記載のシフトレジスタ。 The output circuit has an output terminal for outputting the output signal,
A second clock signal having two voltage levels alternately and the reference potential are applied;
The first clock signal has, as voltage levels, a first voltage having a potential higher than the reference potential and a second voltage having a potential lower than the first voltage, and The input signal is applied when the first clock signal is at the first voltage;
The second clock signal has, as voltage levels, a third voltage having a potential higher than the reference potential, and a fourth voltage having a potential higher than the reference potential and lower than the third voltage, The period when the first clock signal is the first voltage and the period when the second clock signal is the third voltage are set at a timing that does not overlap.
When the signal level of the first signal is the voltage of the first voltage or higher and the signal level of the second signal is a voltage corresponding to the reference potential, the signal level of the output signal Close to the signal level of the second clock signal,
When the signal level of the first signal is a voltage corresponding to the reference voltage and the signal level of the second signal is a voltage corresponding to the first voltage, the signal level of the output signal is set to the reference voltage. 7. The shift register according to claim 6, further comprising means for setting a voltage corresponding to the potential.
第７の電流路と第７の制御端子を有し、前記第７の電流路の一端が前記第６の薄膜トランジスタの前記第６の電流路の他端に接続され、前記第７の電流路の他端が前記基準電位に接続され、前記第７の制御端子に前記第２の信号が印加される第７の薄膜トランジスタと、
一端が前記第６の薄膜トランジスタの前記第６の制御端子に接続され、他端が前記第６の薄膜トランジスタの前記第６の電流路の他端に接続された容量成分と、
を有することを特徴とする請求項８に記載のシフトレジスタ。 The output circuit has a sixth current path and a sixth control terminal, the second clock signal is applied to one end of the sixth current path, and the other end of the sixth current path is is connected to the output terminal, a sixth thin film transistor, wherein the sixth said first signal to the control terminal of the is applied,
A control terminal of the seventh current path and the seventh, the end of the seventh current path is connected to the sixth and the other end of the current path of said sixth thin film transistor, said seventh current path the other end is connected to the reference potential, the seventh thin film transistor, wherein the second signal to said seventh control terminal of is applied,
A capacitive component having one end connected to the sixth control terminal of the sixth thin film transistor and the other end connected to the other end of the sixth current path of the sixth thin film transistor;
9. The shift register according to claim 8, further comprising:
前記入力信号が印加されたとき、前記第１のクロック信号の信号レベルに応じた電圧を前記第１の信号として出力し、前記リセット信号が印加されたとき、前記基準電位に応じた電圧を前記第１の信号として出力する手段と、
前記入力信号及び前記リセット信号が前記入力端子及び前記リセット端子に印加されていないとき、前記第１の信号の信号レベルをそれ以前の信号レベルに基づく電圧にする手段と、
を有することを特徴とする請求項６に記載のシフトレジスタ。 The holding circuit is applied with a first clock signal having two voltage levels alternately and a predetermined reference potential,
When the input signal is applied, a voltage according to the signal level of the first clock signal is output as the first signal, and when the reset signal is applied, a voltage according to the reference potential is output. Means for outputting as a first signal;
Means for setting the signal level of the first signal to a voltage based on the previous signal level when the input signal and the reset signal are not applied to the input terminal and the reset terminal;
The shift register according to claim 6, further comprising:
前記入力信号が印加されたとき、前記電源電圧の電圧レベルに応じた電圧を前記第１の信号として出力し、前記リセット信号が印加されたとき、前記基準電位に応じた電圧を前記第１の信号として出力する手段と、
前記入力信号及び前記リセット信号が前記入力端子及び前記リセット端子に印加されていないとき、前記第１の信号の信号レベルをそれ以前の信号レベルに基づく電圧にする手段と、
を有することを特徴とする請求項６に記載のシフトレジスタ。 The holding circuit is applied with a power supply voltage having a predetermined voltage level and a predetermined reference potential,
When the input signal is applied, a voltage corresponding to the voltage level of the power supply voltage is output as the first signal, and when the reset signal is applied, a voltage corresponding to the reference potential is output to the first signal. Means for outputting as a signal;
Means for setting the signal level of the first signal to a voltage based on the previous signal level when the input signal and the reset signal are not applied to the input terminal and the reset terminal;
The shift register according to claim 6, further comprising:
所定の方向に並んだ前記表示素子を接続する複数の走査ラインと、
請求項１から請求項１１までのいずれか１項に記載のシフトレジスタを含み、当該シフトレジスタに含まれる個々のレジスタ回路の出力端子が個々の前記走査ラインに接続された走査ドライバと、
を備えることを特徴とする表示装置。 A plurality of display elements arranged in a matrix;
A plurality of scanning lines connecting the display elements arranged in a predetermined direction;
A scan driver comprising the shift register according to any one of claims 1 to 11, wherein an output terminal of each register circuit included in the shift register is connected to each scan line;
A display device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008094104A JP5433966B2 (en) | 2008-03-31 | 2008-03-31 | Shift register and display device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008094104A JP5433966B2 (en) | 2008-03-31 | 2008-03-31 | Shift register and display device using the same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009245564A JP2009245564A (en) | 2009-10-22 |
| JP2009245564A5 true JP2009245564A5 (en) | 2011-05-12 |
| JP5433966B2 JP5433966B2 (en) | 2014-03-05 |
Family
ID=41307266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008094104A Expired - Fee Related JP5433966B2 (en) | 2008-03-31 | 2008-03-31 | Shift register and display device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5433966B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012591B (en) * | 2009-09-04 | 2012-05-30 | 北京京东方光电科技有限公司 | Shift register unit and liquid crystal display gate drive device |
| KR102586642B1 (en) | 2010-02-18 | 2023-10-11 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| TWI805306B (en) * | 2011-08-29 | 2023-06-11 | 日商半導體能源研究所股份有限公司 | Semiconductor device |
| JP6009153B2 (en) * | 2011-10-06 | 2016-10-19 | 株式会社ジャパンディスプレイ | Display device |
| KR101354365B1 (en) * | 2011-12-30 | 2014-01-23 | 하이디스 테크놀로지 주식회사 | Shift Register and Gate Driving Circuit Using the Same |
| US9036766B2 (en) | 2012-02-29 | 2015-05-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| CN104246897B (en) * | 2012-04-25 | 2017-03-01 | 株式会社日本有机雷特显示器 | Shift register and display device |
| CN105632444B (en) | 2016-03-16 | 2017-12-26 | 京东方科技集团股份有限公司 | A kind of shift register, gate driving circuit and display panel |
| CN107146589A (en) | 2017-07-04 | 2017-09-08 | 深圳市华星光电技术有限公司 | GOA circuits and liquid crystal display device |
| CN107784977B (en) * | 2017-12-11 | 2023-12-08 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, grid driving circuit and display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3873165B2 (en) * | 2000-06-06 | 2007-01-24 | カシオ計算機株式会社 | Shift register and electronic device |
| TWI220051B (en) * | 2003-05-22 | 2004-08-01 | Au Optronics Corp | Shift register circuit |
| JP2005251348A (en) * | 2004-03-08 | 2005-09-15 | Casio Comput Co Ltd | Shift register circuit and its driving control method |
| JP4968671B2 (en) * | 2006-11-27 | 2012-07-04 | Ｎｌｔテクノロジー株式会社 | Semiconductor circuit, scanning circuit, and display device using the same |
| CN102651186B (en) * | 2011-04-07 | 2015-04-01 | 北京京东方光电科技有限公司 | Shift register and grid line driving device |
-
2008
- 2008-03-31 JP JP2008094104A patent/JP5433966B2/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2009245564A5 (en) | ||
| CN105448261B (en) | Liquid crystal display | |
| KR102054408B1 (en) | Goa circuit for liquid crystal display device | |
| KR101143531B1 (en) | A gate drive device for a liquid crystal display | |
| CN103971628B (en) | Shift register cell, gate driver circuit and display device | |
| JP2006277860A5 (en) | ||
| JP2007004176A5 (en) | ||
| JP2007094415A5 (en) | ||
| JP6077681B2 (en) | Shift register, gate drive circuit, array substrate, and display device | |
| US20170221578A1 (en) | Shift register unit, gate drive circuit, and display device | |
| TWI476742B (en) | Multiplex driving circuit | |
| JP2007199723A5 (en) | ||
| JP2015519679A5 (en) | ||
| JP2006351171A5 (en) | ||
| JP2008077051A5 (en) | ||
| JP2011139309A5 (en) | ||
| TW201013625A (en) | Apparatus, shift register unit, liquid crystal displaying device and method for eliminating afterimage | |
| JP2017503208A (en) | Scan driving circuit and organic light emitting display device | |
| WO2016161725A1 (en) | Shift register unit, gate electrode driver device, and display device | |
| KR20130130721A (en) | Shift register, driving circuit, and display apparatus | |
| JP2016110684A5 (en) | ||
| JP2007317344A5 (en) | ||
| JP2009054273A5 (en) | ||
| JP2010238323A5 (en) | ||
| JP2010086640A (en) | Shift register circuit |