JP2009245564A - Shift register and display using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve service life and reliability of a shift register and a display using the same by reducing a change in the threshold voltage of a thin-film transistor to be used for the shift register. <P>SOLUTION: A clock signal is supplied to one end of a current path of an n-channel TFT 51a. For the clock signal, a high level voltage and a low level voltage are alternately repeated. When a high level input signal is input to an input terminal IN, during the clock signal to be applied to a clock terminal CKm keeps high level voltage, one end and the end of the current path of the n-channel TFT 51a are conducted, and high level voltage is applied to a node n1. Similarly, the clock signal is supplied to a gate electrode and one end of the current path of an n-channel TFT 61a. During the clock signal keeps high level voltage, one end and the other end of the current path of the n-channel TFT 61a are conducted and the high level voltage is applied to a node n3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a shift register using a thin film transistor and a display device using the shift register.

A liquid crystal display device or an organic EL (Electro-Luminescence) display device includes a display panel, a scan driver, and a signal driver.
Display elements are arranged in a matrix on the display panel. The scanning line connects display elements arranged in the row direction. The data line connects the display elements arranged in the column direction.
The scan driver sequentially applies a scan pulse to each scan line, and sequentially selects display elements connected to each scan line. The signal driver applies a signal voltage corresponding to the image data to each data line, and writes the image data to the selected display element.

Each display element is formed to have a thin film transistor structure using amorphous silicon (hereinafter referred to as a-Si) or polysilicon (hereinafter referred to as p-Si).
In order to reduce the size and reduce the cost, a scanning driver and / or a signal driver is formed of a thin film transistor (TFT, Thin Film Transistor) using a-Si or p-Si, for example, integrally with a display element. It is preferable. Furthermore, since a-Si can be formed at a relatively low cost than p-Si, it is preferable to use an a-Si TFT for cost reduction.
However, a-Si has extremely small hole mobility. For this reason, when an a-Si TFT is used, it is difficult to manufacture a p-channel TFT, and a circuit must be formed using only an n-channel TFT.

  The scan driver includes a shift register for sequentially applying scan pulses to the scan lines. Therefore, a shift register that can be configured only by n-channel TFTs has been proposed (for example, see Patent Document 1 and Patent Document 2).

JP 2001-52494 A JP 2006-164477 A

  However, it is known that in an a-Si n-channel TFT, when a voltage is applied to the gate electrode, the change over time in which the threshold voltage Vth gradually changes is relatively large.

  When a negative voltage is applied between the gate and source electrodes or between the gate and drain electrodes, the threshold voltage Vth gradually decreases. That is, if the voltage applied to the gate electrode is relatively lower than the voltage applied to the source electrode, or the voltage applied to the gate electrode is relatively lower than the voltage applied to the drain electrode, The threshold voltage Vth gradually decreases. Reduction of the threshold voltage Vth is not preferable because it increases leakage current.

  Further, when a current flows between the drain electrode and the source electrode, the threshold voltage Vth gradually increases. In particular, when a current having a large current density frequently flows between the drain electrode and the source electrode of an a-Si n-channel TFT, the threshold voltage Vth of the a-Si n-channel TFT increases rapidly. If the threshold voltage Vth is increased, it becomes difficult for a current to flow between the drain electrode and the source electrode, and malfunction is caused depending on the circuit structure.

  As described above, when the TFT characteristics deteriorate and the threshold voltage Vth changes, the operation of a shift register including the TFT may become unstable or malfunction may occur. In addition, the power consumption of such a shift register and a driver circuit using the shift register may increase.

  An object of the present invention is to provide a shift register that includes only a thin film transistor of a predetermined conductivity type and in which the thin film transistor is less likely to deteriorate, and a display device using the shift register.

  The invention according to claim 1 is a shift register of a plurality of stages comprising a plurality of register circuits connected in cascade, wherein each register circuit is applied with the output signal of the previous stage as an input signal, and the output signal of the next stage Is input as a reset signal, a holding circuit that outputs a first signal based on the input signal, a voltage based on the first signal is applied, and a signal based on the first signal is output as the output signal A first clock having an input terminal to which the input signal is applied and a reset terminal to which the reset signal is applied, and having two voltage levels alternately. When a signal and a voltage of a predetermined reference potential are applied and the input signal is applied to the input terminal, a voltage corresponding to the signal level of the first clock signal is output as the first signal. And, when the reset signal is applied to the reset terminal, and having means for outputting a voltage corresponding to the reference potential as said first signal.

  According to a second aspect of the present invention, in the shift register according to the first aspect, the holding circuit has a first clock signal applied to one end of a current path, and a control terminal connected to the input terminal. A first thin film transistor, a second end of the current path connected to the other end of the first thin film transistor, a second end of the current path connected to the reference potential, and a control terminal connected to the reset terminal. And a thin film transistor.

  According to a third aspect of the present invention, in the shift register according to the first or second aspect, the first clock signal has a first voltage having a potential higher than the reference potential as a voltage level, and the first clock signal A second voltage having a potential lower than a voltage, and the input signal is applied to the holding circuit when the first clock signal is the first voltage, and the holding circuit When the input signal is applied, the voltage of the first signal is set to a voltage corresponding to the first voltage, and the voltage of the first signal until the reset signal is applied next is It is characterized by being held at a voltage corresponding to the voltage of 1 or a voltage having a potential higher than that.

  According to a fourth aspect of the present invention, in the shift register according to the third aspect, the output circuit is supplied with a second clock signal having two voltage levels alternately and the reference potential, and the output circuit An output terminal for outputting a signal, wherein the second clock signal has a voltage level of a third voltage having a potential higher than the reference potential, and a second voltage having a potential higher than the reference potential and lower than the third voltage. 4 is set to a timing that does not overlap a period in which the first clock signal is the first voltage and a period in which the second clock signal is the third voltage, When the signal level of the first signal is a voltage corresponding to the first voltage or higher, the signal level of the output signal is changed to approach the signal level of the second clock signal. ,in front When the signal level of the first signal is a voltage corresponding to the reference voltage, and having a means for the signal level of the output signal to a voltage corresponding to the reference potential.

  According to a fifth aspect of the present invention, in the shift register according to the third aspect, in the output circuit, the second clock signal is applied to one end of a current path, and the other end of the current path is connected to the output terminal. A third thin film transistor in which the first signal is applied to the control terminal, one end connected to the control terminal of the third thin film transistor, and the other end connected to the other end of the current path of the third thin film transistor And a capacitive component.

  The invention according to claim 6 is a shift register of a plurality of stages comprising a plurality of register circuits connected in cascade, wherein each register circuit is applied with the output signal of the previous stage as an input signal, and the output signal of the next stage Is input as a reset signal, a holding circuit that outputs a first signal based on the input signal, a first signal and a second signal corresponding to an inverted signal of the first signal are applied, An output circuit that outputs a signal based on a first signal as the output signal; and an inverter circuit that receives the first signal and outputs the second signal. The holding circuit includes at least the A signal having a first voltage having a potential higher than a reference potential and a second voltage having a potential equal to or higher than the reference potential and lower than the first voltage is output as the first signal, and the inverter circuit includes: 2 When a first clock signal alternately having a voltage level of and a predetermined reference potential are applied and the signal level of the first signal is the first voltage or a voltage higher than the first voltage, When the signal level of the second signal is changed to a voltage corresponding to the reference potential, and the signal level of the first signal is the second voltage, the signal level of the second signal is changed to the first signal level. And a means for changing the voltage to a voltage corresponding to the voltage level of the clock signal.

  According to a seventh aspect of the present invention, in the shift register according to the sixth aspect, in the inverter circuit, the first clock signal is applied to one end of a current path, and a control terminal is connected to one end of the current path. A fourth thin film transistor and one end of a current path connected to the other end of the current path of the fourth thin film transistor to output the second signal, the other end of the current path connected to the reference potential, and a control terminal And a fifth thin film transistor to which the first signal is applied.

  According to an eighth aspect of the present invention, in the shift register according to the sixth aspect, the output circuit includes an output terminal for outputting the output signal, and a second clock signal having two voltage levels alternately. , The reference voltage is applied, and the first clock signal has a voltage level of a first voltage having a potential higher than the reference potential, and a second voltage having a potential lower than the first voltage, And the input signal is applied to the holding circuit when the first clock signal is the first voltage, and the second clock signal is higher than the reference potential as a voltage level. A third voltage having a potential, and a fourth voltage having a potential that is equal to or higher than the reference potential and lower than the third voltage, and the period in which the first clock signal is the first voltage; The second clock signal is 3 is set at a timing that does not overlap with the period of 3 voltage, the signal level of the first signal is the voltage of the first voltage or higher, and the signal level of the second signal is the reference voltage When the voltage is in accordance with the potential, the signal level of the output signal is brought close to the signal level of the second clock signal, the signal level of the first signal is a voltage in accordance with the reference voltage, and the second And a means for setting the signal level of the output signal to a voltage corresponding to the reference potential when the signal level of the signal is a voltage corresponding to the first voltage.

  According to a ninth aspect of the present invention, in the shift register according to the eighth aspect, the output circuit has the second clock signal applied to one end of a current path, and the other end of the current path is connected to the output terminal. And the sixth thin film transistor to which the first signal is applied to the control terminal, one end of the current path is connected to the other end of the current path of the sixth thin film transistor, and the other end of the current path is set to the reference potential. A seventh thin film transistor connected to the control terminal and having one end connected to the control terminal of the sixth thin film transistor and the other end connected to the other end of the current path of the sixth thin film transistor; And a connected capacitive component.

  According to a tenth aspect of the present invention, in the shift register according to the sixth aspect, the holding circuit is applied with a first clock signal having two voltage levels alternately and a predetermined reference potential, and the input signal Is applied, the voltage corresponding to the signal level of the first clock signal is output as the first signal, and when the reset signal is applied, the voltage corresponding to the reference potential is output to the first signal. Means for outputting as a signal, and means for setting the signal level of the first signal to a voltage based on the previous signal level when the input signal and the reset signal are not applied to the input terminal and the reset terminal; It is characterized by having.

  According to an eleventh aspect of the present invention, in the shift register according to the sixth aspect, when the holding circuit is applied with a power supply voltage having a predetermined voltage level and a predetermined reference potential, and the input signal is applied. Outputting a voltage corresponding to a voltage level of the power supply voltage as the first signal, and outputting a voltage corresponding to the reference potential as the first signal when the reset signal is applied; Means for setting the signal level of the first signal to a voltage based on the previous signal level when the input signal and the reset signal are not applied to the input terminal and the reset terminal. .

  A display device according to a twelfth aspect of the present invention includes a plurality of display elements arranged in a matrix and a plurality of scanning lines connecting the display elements arranged in a predetermined direction. A shift driver according to any one of Items 11 to 11, further comprising: a scan driver in which an output terminal of each register included in the shift register is connected to each scan line.

  According to the present invention, it is possible to provide a shift register that includes only a thin film transistor of a predetermined conductivity type and in which the thin film transistor is unlikely to deteriorate, and a display device using the shift register.

Hereinafter, an active matrix driving type liquid crystal display device according to an embodiment of the present invention will be described.
FIG. 1 is a diagram illustrating an example of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating scan pulses sequentially applied to scan lines. As shown in FIG. 1, the active matrix liquid crystal display device 100 includes a display panel 1, a scan driver 2, and a signal driver 3.

  The display panel 1 includes display elements 10 arranged in a matrix, a plurality of scanning lines LS1 to LSn arranged in the row direction, and a plurality of data lines LD1 to LDm arranged in the column direction.

  The display element 10 is disposed in the vicinity of the intersection of the data lines LD1 to LDm and the scanning lines LS1 to LSn.

  In order to write the image data for one screen into the display element 10, the scan driver 2 first applies a scan pulse that is at a high level (for example, +15 V) for a period of ts to the scan line LS1, as shown in FIG. Apply. The display element 10 connected to the scanning line LS1 is selected by this scanning pulse. Next, as shown in FIG. 2B, the scan driver 2 applies a scan pulse that is at a high level for the next ts to the scan line LS2. The display element 10 connected to the scanning line LS2 is selected by this scanning pulse. Then, as shown in FIG. 2C, the scan driver 2 applies a scan pulse that is at a high level for the next ts to the scan line LS3. The display element 10 connected to the scanning line LS3 is selected by this scanning pulse.

  The scan driver 2 sequentially applies a scan pulse that is at a high level for a period ts from the scan line LS4 to the scan line LS (n-1) shown in FIG. 2D, and applies to the scan lines LS4 to LS (n-1). The connected display elements 10 are sequentially selected. Finally, as shown in FIG. 2E, the scan driver 2 applies a scan pulse that is at a high level for a period ts to the scan line LSn. The display element 10 connected to the scanning line LSn is selected by this scanning pulse.

  The signal driver 3 applies a signal voltage corresponding to the image data to the data lines LD1 to LDm. When a signal voltage is applied to the display element 10 selected by the scanning pulse, image data is written to the display element 10. The image data written in the display element 10 is stored until the image data of the next screen is written, and is displayed on the display panel 1 as an image.

  The liquid crystal display device 100 is an example of the display device of the present invention, the display element 10 is an example of the display element of the present invention, the scan lines LS1 to LSn are examples of the scan line of the present invention, and the scan driver 2 Is an example of a scan driver of the present invention.

FIG. 3 is a diagram illustrating an example of the shift register according to the embodiment of the present invention. Scan driver 2 includes a shift register 200 according to the embodiment of the present invention. The shift register 200 generates a scan pulse. As shown in FIG. 3, the shift register 200 includes n register circuits 40 corresponding to the scanning lines LS1 to LSn, respectively.
The register circuit 40 includes an input terminal IN, an output terminal OUT, a reset terminal RST, a clock terminal CKm, a clock terminal CKp, and a low level power supply voltage terminal Vss.

The n register circuits 40 are arranged in a cascade and constitute an n-stage shift register 200. A high-level start signal equal to a high-level (for example, +15 V) power supply voltage Vdd (hereinafter referred to as a high-level power supply voltage) is supplied to an input terminal IN of the first-stage register circuit 40 from a control circuit (not shown). The
Alternatively, when the scanning driver 2 is continuously driven, a high-level start signal is supplied to the input terminal IN of the first-stage register 40 as an initial pulse when starting the display of the first image. When displaying the second and subsequent images, an output signal output from the output terminal OUT of the final stage (n-th stage) register circuit 40 to the input terminal IN of the first-stage register circuit 40 as a start signal. OUT (n) may be supplied.

The output terminal OUT of the previous-stage (k−1) -stage register circuit 40 is connected to the input terminal IN of the k-stage register circuit 40 other than the first stage (k is an integer from 1 to n). The output terminal OUT of the k-th register circuit 40 is connected to the corresponding scan line Lsk, and the output signal OUT (k) of the k-th register circuit 40 is output to the scan line Lsk.
The clock signal CK1 and the clock signal CK2 are two-phase clock signals, the square wave voltage output circuit 41 is a circuit that outputs a clock signal CK1 of a pulse signal, and the square wave voltage output circuit 42 outputs a clock signal CK2 of a pulse signal. Circuit. The clock signal CK1 and the clock signal CK2 are alternately applied to the clock terminal CKp and the clock terminal CKm of each register circuit 40.

  FIG. 4 is a diagram illustrating an example of a two-phase clock signal. As shown in FIG. 4, the clock signal CK1 and the clock signal CK2 output from the square wave voltage output circuit 41 and the square wave voltage output circuit 42 have a high level voltage equal to the high level power supply voltage Vdd and a low level (for example, This is a two-phase clock signal that alternately repeats a low level voltage equal to a power supply voltage Vss (hereinafter referred to as a low level power supply voltage) of −15V). The duty ratio (t1 / t0) is smaller than 50%, and the period in which the clock signal CK1 is at a high level does not overlap with the period in which the clock signal CK2 is at a high level.

  The clock signal CK1 and the clock signal CK2 are supplied to the clock terminal CKm and the clock terminal CKp of the odd-numbered register circuit 40, respectively. The clock signal CK2 and the clock signal CK1 are supplied to the clock terminal CKm and the clock terminal CKp of the even-numbered register circuit 40, respectively.

  The output terminal OUT of the register circuit 40 in the subsequent stage (k + 1 stage) is connected to the reset terminal RST of the register circuit 40 in the k stage other than the nth stage (final stage). A reset signal is supplied from a control circuit (not shown) to the reset terminal RST of the n-th (last stage) register circuit 40. Alternatively, the (n + 1) -th stage register circuit 40 is added, the output terminal OUT is connected to the reset terminal RST of the n-th stage register circuit 40, and the output signal OUT ( n + 1) may be input.

  The low level power supply voltage Vss is applied to the low level power supply voltage terminal Vss.

  The shift register 200 is an example of the shift register of the present invention.

  FIG. 5 is a diagram showing a circuit configuration example of the register circuit according to the embodiment of the present invention. As shown in FIG. 5, the register circuit 40a according to the embodiment of the present invention includes a holding circuit 50a and an output circuit 70a. The register circuit 40a is an example of the register circuit 40 illustrated in FIG.

  The holding circuit 50a includes an n-channel TFT 51a and an n-channel TFT 52 whose current paths are connected in series. In the n-channel TFT 51a, one end of the gate electrode and the current path is connected to the input terminal IN and the clock terminal CKm, respectively. In the n-channel TFT 52, the gate electrode is connected to the reset terminal RST, one end of the current path is connected to the low-level power supply voltage terminal Vss, and the other end of the current path is connected to the other end of the current path of the n-channel TFT 51a. . The other end of the current path of the n-channel TFT 51a and the other end of the current path of the n-channel TFT 52 are connected to the node n1.

FIG. 6 is a diagram illustrating an example of voltages at various parts of the holding circuit. When a high-level input signal is input to the input terminal IN, the n-channel TFT 51a is turned on, and one end and the other end of the current path are conducted, and a voltage applied to the clock terminal CKm is applied to the node n1. In the holding circuit 50a, as shown in FIGS. 6A and 6B, a high level input signal is input when a high level voltage is applied to the clock terminal CKm. Therefore, a high level voltage is applied to the node n1.
When a high-level reset signal is input to the reset terminal RST, the n-channel TFT 52 is turned on, and one end and the other end of the current path are conducted, and a low-level voltage is applied to the node n1.

  Therefore, when a high level input signal is input to the input terminal IN as shown in FIG. 6B, the holding circuit 50a has a low level held at the node n1 as shown in FIG. 6D. The voltage is changed to a high level voltage. 6C, when a high level reset signal is input to the reset terminal RST, as shown in FIG. 6C, the high level voltage held at the node n1 as shown in FIG. 6D. Is changed to a low level voltage. When a high level input signal is not input to the input terminal IN and a high level reset signal is not input to the reset terminal RST, the holding circuit 50a holds the voltage level of the node n1. The holding circuit 50a outputs the voltage held at the node n1 and supplies it to the output circuit 70a.

  Note that in FIG. 6D, the broken line indicates that the node n1 is in a floating state, and the solid line indicates that a high-level or low-level voltage is applied to the node n1. Similarly, in the following drawings, a broken line indicates a floating state, and a solid line indicates that a high-level or low-level voltage is applied.

  The output circuit 70a includes an n-channel TFT 71, a capacitor Cc, and a capacitor Co. In the n-channel TFT 71, the gate electrode is connected to the node n1, one end of the current path is connected to the clock terminal CKp, and the other end of the current path is connected to the node n2 (output terminal OUT). The capacitor Cc has one end connected to the node n1 and the other end connected to the node n2 (output terminal OUT). One end of the capacitor Co is connected to the node n2 (output terminal OUT), and the other end is grounded.

  FIG. 7 is a diagram illustrating an example of voltages at various parts of the output circuit. As shown in FIGS. 7A, 7B, and 7C, the n-channel TFT 71 is turned on when the voltage held at the node n1 is at a high level, and one end and the other end of the current path are connected to each other. Conduction is performed, and the voltage level of the node n2 (output terminal OUT) is changed to be the same as the voltage level applied to the clock terminal CKp.

  The capacitors Cc and Co are provided in order to eliminate the influence of noise and prevent malfunction. The register circuit 40a operates even without the capacitors Cc and Co. However, if the capacitors Cc and Co are absent, the register circuit 40a is likely to malfunction due to the influence of noise.

  FIG. 8 is a diagram illustrating an example of voltages at respective parts of one register circuit 40a when a plurality of register circuits 40a are arranged in cascade and the shift register 200 is configured as shown in FIG.

As shown in FIGS. 8A and 8B, a clock signal CKm and a clock terminal CKp are supplied with a two-phase signal that does not overlap in a high level period.
A period ta shown in FIG. 8 is an input period. In the input period, as shown in FIGS. 8B and 8C, when a high level voltage is applied to the clock terminal CKm, a high level input signal is input to the input terminal IN. As a result, one end and the other end of the current path of the n-channel TFT 51a become conductive, and as shown in FIG. 8E, a voltage that is lower than the high-level power supply voltage Vdd by the threshold voltage Vth of the n-channel TFT 51a Applied to n1.
During the input period, the n-channel TFT 71 is electrically connected to one end and the other end of the current path. However, since a low level voltage is applied to the clock terminal CKp, as illustrated in FIG. The voltage at the output terminal OUT) is at a low level.

A period tb shown in FIG. 8 is an output period. In the output period, since a high-level voltage is applied to the clock terminal CKp, as illustrated in FIG. 8F, the voltage of the node n2 (output terminal OUT) becomes high level.
During the output period, as shown in FIGS. 8C and 8D, both the input signal and the reset signal are at a low level. For this reason, the node n1 is floating. At this time, as shown in FIG. 8E, the voltage of the node n1 rises above the high level power supply voltage Vdd by the same principle as the charge pump. That is, the voltage at the node n1 is the sum of the voltage generated by the stray capacitance between the gate and drain electrodes of the n-channel TFT 71 and the charge accumulated in the capacitor Cc during the input period and the voltage supplied from the clock terminal CKp.
Thus, during the output period, the voltage applied to the gate electrode of the n-channel TFT 71 becomes higher than the high level power supply voltage Vdd. For this reason, the voltage at the node n2 (output terminal OUT) is not affected by the drop of the threshold voltage Vth of the n-channel TFT 71, and fully swings to the high level power supply voltage Vdd.

A period tc shown in FIG. 8 is a reset period. A clock signal CK1 and a clock signal CK2 are supplied to the clock terminal CKm and the clock terminal CKp. As shown in FIG. 4, the clock signal CK1 and the clock signal CK2 are high-level voltages during a period of low-level voltage. Is longer than the period.
FIG. 9 is an enlarged view of the output period tb and the reset period tc. As shown in FIG. 9A, in the output period tb, the voltage applied to the clock terminal CKp is at a low level. However, as illustrated in FIG. 9E, the voltage of the node n1 remains at a high level until a reset signal is input in the reset period tc. At this time, one end and the other end of the current path of the n-channel TFT 71 are conductive. For this reason, as indicated by an arrow, the voltage of the node n2 (output terminal OUT) is at a low level. After that, when a reset signal RST is input as shown in FIG. 9D, one end and the other end of the current path of the n-channel TFT 52 become conductive, and the voltage at the node n1 is low as shown in FIG. Become a level. As a result, the n-channel TFT 71 is turned off, one end and the other end of the current path become non-conductive, and the node n2 becomes floating. While the node n2 (output terminal OUT) is floating, the node n2 (output terminal OUT) holds a low level voltage.

  In the following, as shown in FIG. 8, a period including the input period ta, the output period tb, and the reset period tc is called an operation period, and the other period is called a non-operation period.

In an n-channel TFT, generally, the lower side of the current path is called the source electrode, and the higher side is called the drain electrode.
Here, as shown in FIGS. 8B and 8E, when the output period tb is excluded, the voltage of the clock terminal CKm is higher than the voltage of the node n1, or the voltages of the clock terminal CKm and the node n1 are equal. In this case, in the n-channel TFT 51a, the other end of the current path connected to the node n1 is a source electrode, and one end of the current path connected to the clock terminal CKm is a drain electrode.
On the other hand, in the output period tb, the voltage of the clock terminal CKm is lower than the voltage of the node n1. In this case, in the n-channel TFT 51a, the other end of the current path connected to the node n1 is a drain electrode, and one end of the current path connected to the clock terminal CKm is a source electrode.
Thus, the n-channel TFT 51a changes which one of the one end and the other end of the current path is the source electrode and which is the drain electrode.

FIG. 10 is a diagram illustrating a holding circuit as a comparative example with respect to the holding circuit included in the register circuit of FIG.
The holding circuit 50b shown in FIG. 10 is different from the n-channel TFT 51a of the holding circuit 50a in FIG. 5 in that the high-level power supply voltage Vdd is supplied to one end of the current path of the n-channel TFT 51b. The n-channel TFT 52 is the same in the holding circuit 50a and the holding circuit 50b.
The register circuit 40 in which the holding circuit 50a in FIG. 5 is replaced with the holding circuit 50b also operates in the same manner as the register circuit 40a. However, the n-channel TFT 51a and the n-channel TFT 51b differ in the degree to which the threshold voltage Vth deteriorates.

  Table 1 shows an example of the gate-source voltage Vgs and the gate-drain voltage Vgd of the n-channel TFT 51a and the n-channel TFT 51b.

  When a high level (for example, + 15V) voltage is applied to the clock terminal CKm, the gate-source voltage Vgs of the n-channel TFT 51a included in the holding circuit 50a and the n-channel TFT 51b included in the holding circuit 50b and the gate-drain voltage. The voltage Vgd is the same.

  In the input period ta, as shown in FIG. 8C, a high-level (for example, +15 V) input signal is input to the gate electrodes (input terminals IN) of the n-channel TFT 51a and the n-channel TFT 51b. As shown in FIG. 8B, a high level (for example, +15 V) voltage is applied to the drain electrode (clock terminal CKm). The source electrode and the drain electrode are brought into conduction, and as shown in FIG. 8E, a voltage (for example, +15 V−Vth) reduced from the high level by the threshold voltage Vth is supplied to the source electrode. At this time, the other end of the current path connected to the node n1 is the source electrode, and one end of the current path connected to the clock terminal CKm or the high-level power supply voltage Vdd is the drain electrode. Therefore, the gate-source voltage Vgs = Vth and the gate-drain voltage Vgd = 0V.

In the output period tb, as shown in FIG. 8C, the voltage of the gate electrode (input terminal IN) of the n-channel TFT 51a and the n-channel TFT 51b is at a low level (for example, −15V). At this time, as shown in FIG. 8E, the node n1 becomes floating, so that the voltage of the node n1 exceeds the high level power supply voltage Vdd (for example, +15 V) as shown in FIG. 8E. For example, it rises to about + 39V. Therefore, the voltage at the other end of the current path connected to the node n1 is higher than one end of the current path connected to the clock terminal CKm or the high-level power supply voltage Vdd. That is, the other end of the current path connected to the node n1 is the drain electrode, and one end of the current path connected to the clock terminal CKm or the high level power supply voltage Vdd is the source electrode. Both the gate-drain voltage Vgd of the n-channel TFT 51a and the n-channel TFT 51b is about -54V.
On the other hand, -15V is applied to the source electrode of the n-channel TFT 51a connected to the clock terminal CKm, as shown in FIG. However, + 15V (high level power supply voltage Vdd) is applied to the source electrode of the n-channel TFT 51b. For this reason, the gate-source voltages Vgs of the n-channel TFT 51a and the n-channel TFT 51b are 0 V and −30 V, respectively, and are different.

  In the reset period tc, as shown in FIG. 8C, the voltages of the gate electrodes (input terminals IN) of the n-channel TFT 51a and the n-channel TFT 51b are at a low level (for example, −15V). On the other hand, as shown in FIG. 8D, a high level (for example, +15 V) reset signal is input to the gate electrode of the n-channel TFT 52. At this time, since the n-channel TFT 52 becomes conductive, the voltage of the node n1 becomes low level (for example, −15 V) as shown in FIG. In the n-channel TFT 51a and the n-channel TFT 51b, the other end of the current path connected to the node n1 is the source electrode, and one end of the current path connected to the clock terminal CKm or the high level power supply voltage Vdd is the drain electrode. . A high level (for example, + 15V) voltage is supplied to the drain electrodes of the n-channel TFT 51a and the n-channel TFT 51b. Therefore, the gate-source voltage Vgs = 0V and the gate-drain voltage Vgd = -30V.

In the non-operation period, the n-channel TFT 51b has a gate-source voltage Vgs = 0V and a gate-drain voltage Vgd = -30V, as in the reset period.
When the voltage applied to the clock terminal CKm is also at a high level (for example, + 15V), the n-channel TFT 51a has the gate-source voltage Vgs = 0V and the gate-drain voltage Vgd = -30V as in the reset period.
On the other hand, when the voltage applied to the clock terminal CKm is at a low level (for example, −15V), the gate-source voltage Vgs = 0V and the gate-drain voltage Vgd = 0V of the n-channel TFT 51a.

While the gate-source voltage Vgs or the gate-drain voltage Vgd is negative, the a-Si TFT deteriorates as the threshold voltage Vth decreases.
As described above, the n-channel TFT 51a has a gate-drain voltage when the gate-source voltage Vgs in the output period tb is 0 V and the voltage at the CKm terminal is at a low level (-15 V) in the non-operation period. Vgd is also 0V. On the other hand, the n-channel TFT 51b has a gate-source voltage Vgs of -30V in the output period tb, and the gate-drain voltage Vgd is always -30V in the non-operating period.

For this reason, the n-channel TFT 51a of the holding circuit 50a is less likely to deteriorate than the n-channel TFT 51b of the holding circuit 50b. When the n-channel TFT 51a or the n-channel TFT 51b deteriorates, a leakage current increases, and thus charges are easily accumulated in the node n1 during the non-operation period. When the charge is accumulated, the potential of the node n1 rises, so that the operation of the register circuit 40 becomes unstable.
Moreover, the n-channel TFT 51a of the holding circuit 50a has a drain-source voltage Vds of 0V when the voltage at the CKm terminal is at a low level (for example, -15V) during the non-operation period. At this time, no leak current flows through the n-channel TFT 51a. Therefore, the leakage current in the non-operating period of the n-channel TFT 51a is reduced to approximately half of the leakage current of the n-channel TFT 51b.
Therefore, the register circuit 40a using the holding circuit 50a operates more stably for a longer period than the register circuit 40 using the holding circuit 50b, and power consumption is reduced.

  The register circuit 40a is an example of the register circuit of the present invention, the holding circuit 50a is an example of the holding circuit of the present invention, and the output circuit 70a is an example of the output circuit of the present invention.

FIG. 11 is a diagram illustrating a circuit configuration example of a register circuit according to another embodiment of the present invention. FIG. 12 illustrates a register when the register circuits illustrated in FIG. 11 are arranged in cascade to form a shift register. FIG. 13 is a diagram illustrating an example of a voltage of each part of the circuit, and FIG. 13 is a diagram illustrating an example of a voltage of each part of the inverter circuit.
The register circuit 40b includes a holding circuit 50a, an inverter circuit 60a, and an output circuit 70b. The register circuit 40 b is different from the register circuit 40 a of FIG. 5 in that an inverter circuit 60 a is added and an output circuit 70 b includes an n-channel TFT 72. The same components in FIGS. 5 and 11 are denoted by the same reference numerals.

The output circuit 70b is obtained by adding an n-channel TFT 72 to the output circuit 70a. In the n-channel TFT 72, the gate electrode is connected to the node n3 of the inverter circuit 60a, one end of the current path is connected to the low-level power supply voltage terminal Vss, and the other end of the current path is connected to the node n2 (output terminal OUT). Yes.
As shown in FIG. 12G, the n-channel TFT 72 conducts at one end and the other end of the current path during the non-operation period, and fixes the voltage at the node n2 (output terminal OUT) to the low level power supply voltage Vss. The voltage of the node n1 in the non-operation period is floating as shown in FIG. 12E, but the potential of the node n1 is also stabilized through the capacitor Cc because the potential of the node n2 is stable. To do.

  As shown in FIGS. 12C, 12D, and 12G, the register circuit 40b is different from the register circuit 40a in that the input signal, the reset signal, and the output signal are fixed to the low level power supply voltage Vss during the non-operation period. ing. For this reason, the register circuit 40b is more resistant to noise than the register circuit 40a during the non-operating period, and is less likely to malfunction due to noise.

  Inverter circuit 60a includes an n-channel TFT 61a and an n-channel TFT 62 having current paths connected in series. In the n-channel TFT 61a, one end of the gate electrode and the current path is connected to the clock terminal CKm. In the n-channel TFT 62, the gate electrode is connected to the node n1, one end of the current path is connected to the low-level power supply voltage terminal Vss, and the other end of the current path is connected to the other end of the n-channel TFT 61a. The other end of the current path of the n-channel TFT 61a and the other end of the current path of the n-channel TFT 62 are connected to the node n3.

Inverter circuit 60a inverts the voltage at node n1 and outputs the result from node n3.
When a high level voltage is applied to the clock terminal CKm, the n-channel TFT 61a conducts at one end and the other end of the current path, and applies a high level voltage to the node n3. On the other hand, in the n-channel TFT 61a, when a low level voltage is applied to the clock terminal CKm, one end and the other end of the current path become non-conductive.

  As shown in FIG. 13B, the n-channel TFT 62 becomes non-conductive when the voltage at the node n1 is at a low level. At this time, since one end and the other end of the current path of the n-channel TFT 61a are conducted while the voltage of the clock terminal CKm is at a high level, the node n3 is charged. As shown in FIG. 13C, while the voltage at the clock terminal CKm is at a high level, the voltage at the node n3 is at a high level. On the other hand, while the voltage at the clock terminal CKm is at a low level, the node n3 is in a floating state, and a high level voltage is maintained.

On the other hand, when the voltage at the node n1 is at a high level, one end and the other end of the current path of the n-channel TFT 62 are conducted, and the low-level power supply voltage Vss is applied to the node n3.
At this time, since the one end and the other end of the current path of the n-channel TFT 61a are non-conductive while the voltage of the clock terminal CKm is low level, the voltage of the node n3 is low level as shown in FIG. Full swing to power supply voltage Vss.
On the other hand, while the voltage at the clock terminal CKm is at a high level, the n-channel TFT 61a is turned on, and a through current flows through the n-channel TFT 61a and the n-channel TFT 62. For this reason, as shown in FIG. 13C, the voltage of the node n3 rises from the low level power supply voltage Vss.

When the register circuit 40b configures the shift register 200 as shown in FIG. 3, the voltage at the node n2 (output terminal OUT) becomes high level only during the output period tb as shown in FIG. 12 (G). is there. During a period other than the output period tb, the voltage at the node n2 (output terminal OUT) is at a low level. In other words, it is only the output period tb that one end and the other end of the current path of the n-channel TFT 72 need to be turned off to cut off the low-level power supply voltage Vss.
Here, in the output period tb, as shown in FIG. 12B, the voltage of the clock terminal CKm is at a low level. For this reason, one end and the other end of the current path of the n-channel TFT 61a are non-conductive. Accordingly, as shown in FIG. 12F, the voltage of the node n3 fully swings to the low level power supply voltage Vss in the output period tb.
As described above, when the register circuit 40b configures the shift register 200 as shown in FIG. 3, in the output period tb in which one end and the other end of the current path of the n-channel TFT 72 must be non-conductive, The voltage fully swings to the low level power supply voltage Vss.

  In the a-Si n-channel TFT, when a current having a large current density flows between the drain electrode and the source electrode, the threshold voltage Vth rapidly increases and deteriorates. The voltage at the node n3 when the n-channel TFT 62 becomes non-conductive is (high level power supply voltage Vdd−threshold voltage Vth of the n-channel TFT 61a). For this reason, when the threshold voltage Vth of the n-channel TFT 61a increases, the voltage of the node n1 becomes low level, and the node in the non-operation period is a period in which one end and the other end of the current path of the n-channel TFT 62 are nonconductive. The voltage of n3 falls from the high level. When the voltage at the node n3 decreases from the high level, it becomes difficult to turn on the n-channel TFT 72 included in the output circuit 70b and to sufficiently conduct one end and the other end of the current path. For this reason, it is difficult to keep the voltage of the node n2 (output terminal OUT) at a low level during the non-operation period, and the shift register 200 may malfunction.

  In the inverter circuit 60a shown in FIG. 11, during the output period tb, the voltage at the clock terminal CKm is at a low level, so that the n-channel TFT 61a becomes non-conductive. Therefore, the voltage at the node n3 fully swings to the low level power supply voltage Vss regardless of the on-resistance of the n-channel TFT 61a. Therefore, the n-channel TFT 61a can have a wide channel width and a low on-resistance.

As shown in FIGS. 12B and 12E, in the input period ta, the voltage at the clock terminal CKm and the voltage at the node n1 are both high. At this time, both the n-channel TFT 61a and the n-channel TFT 62 become conductive, and a through current flows. However, when the channel width of the n-channel TFT 61a is wide, the current density of the current flowing between one end and the other end of the current path is small. For this reason, the increase in the threshold voltage Vth is small, and the n-channel TFT 61a is hardly deteriorated.
When the on-resistance of the n-channel TFT 61a decreases, as shown in FIG. 12F, the voltage of the node n3 does not decrease to a sufficiently small level in the input period ta. However, as shown in FIGS. 12A and 12G, in the input period ta, the voltage applied to the clock terminal CKp of the output circuit 70b and the output signal OUT are both at a low level. Since the voltage at both ends of the current path of the n-channel TFT 71 and the voltage at both ends of the current path of the n-channel TFT 72 are all at a low level, there is no problem even if the voltage at the node n3 is high.

Furthermore, since one end and the other end of the current path of the n-channel TFT 62 become non-conductive during the non-operation period, the voltage at the node n3 becomes (high level voltage−threshold voltage Vth of the n-channel TFT 61a). In the inverter circuit 60a, the voltage at the clock terminal CKm repeats a high level voltage and a low level voltage alternately. Since the voltage of the clock terminal CKm is supplied to the gate electrode of the n-channel TFT 61a, when a low-level voltage is applied to the clock terminal CKm, the gate electrode (clock terminal CKm) and drain electrode (node n3) of the n-channel TFT 61a. ) Is a negative voltage (for example, −27 V). When a negative voltage is applied between the gate and drain electrodes, the threshold voltage Vth gradually decreases.
On the other hand, as described above, in the input period ta, both the n-channel TFT 61a and the n-channel TFT 62 are conducted, and a through current flows. At this time, the threshold voltage Vth of the n-channel TFT 61a increases.

Thus, the inverter circuit 60a has a period during which the threshold voltage Vth of the n-channel TFT 61a is increased and a period during which the threshold voltage Vth is decreased.
Further, as described above, the n-channel TFT 61a can increase the channel width and reduce the current density of the current flowing between one end and the other end of the current path.
Due to these effects, the n-channel TFT 61a is not easily deteriorated, and the register circuit 40a using the inverter circuit 60a operates stably for a long period of time.

  Further, no through current flows through the n-channel TFT 61a and the n-channel TFT 62 during the output period tb. Inverter circuit 60a consumes less power by the amount that no through current flows during output period tb.

FIG. 14 is a diagram showing a first modification of the register circuit according to another embodiment of the present invention.
A register circuit 40c illustrated in FIG. 14 includes a holding circuit 50b, an inverter circuit 60a, and an output circuit 70b. The register circuit 40c is obtained by replacing the holding circuit 50a of the register circuit 40b shown in FIG. 11 with the holding circuit 50b shown in FIG. The register circuit 40c operates in the same manner as the register circuit 40b.

FIG. 15 is a diagram showing a second modification of the register circuit according to another embodiment of the present invention.
The register circuit 40d illustrated in FIG. 15 includes a holding circuit 50c, an inverter circuit 60a, and an output circuit 70b. The register circuit 40d is obtained by replacing the holding circuit 50a of the register circuit 40b shown in FIG. 11 with a holding circuit 50c.

The holding circuit 50c is different from the n-channel TFT 51a of the holding circuit 50a of FIG. 11 in that the gate of the n-channel TFT 51c and one end of the current path are connected. The n-channel TFT 52 is the same in the holding circuit 50a and the holding circuit 50c.
The register circuit 40d also operates in the same manner as the register circuit 40b.

  The inverter circuit 60a is an example of the inverter circuit of the present invention, the output circuit 70b is an example of the output circuit of the present invention, and the register circuit 40b, the register circuit 40c, and the register circuit 40d are examples of the register circuit of the present invention. is there.

FIG. 16 is a diagram showing a circuit configuration example of a register circuit according to still another embodiment of the present invention.
The register circuit 40e includes a holding circuit 50d, an inverter circuit 60b, and an output circuit 70b.
The register circuit 40e differs from the register circuit 40b of FIG. 11 in that the holding circuit 50d includes an n-channel TFT 53 and the inverter circuit 60b includes an n-channel TFT 63 and an n-channel TFT 64. The same components in FIGS. 11 and 16 are denoted by the same reference numerals.

The holding circuit 50d is obtained by adding an n-channel TFT 53 to the holding circuit 50a. In the n-channel TFT 53, the gate electrode is connected to the node n3 of the inverter circuit 60b, one end of the current path is connected to the low level power supply voltage terminal Vss, and the other end of the current path is connected to the node n1.
The n-channel TFT 53 fixes the voltage of the node n1 during the non-operation period to the low level power supply voltage Vss. Since the voltage at the node n1 during the non-operation period is stabilized, the voltage becomes strong against noise, and the capacitance Cc included in the output circuit 70b can be reduced.
Note that the holding circuit 50d may have a configuration in which an n-channel TFT 53 is added to the holding circuit 50b or the holding circuit 50c.

The inverter circuit 60b is obtained by adding an n-channel TFT 63 and an n-channel TFT 64 to the inverter circuit 60a.
In the n-channel TFT 63, the gate electrode is connected to the reset terminal RST, one end of the current path is connected to the clock terminal CKm, and the other end of the current path is connected to the node n3. In the n-channel TFT 64, the gate electrode is connected to the input terminal IN, one end of the current path is connected to the low level power supply voltage terminal Vss, and the other end of the current path is connected to the node n3.

  When a high level reset signal is input, one end and the other end of the current path of the n-channel TFT 63 are conducted. The high level reset signal is input when the voltage applied to the clock terminal CKm is at a high level, as shown in FIGS. 12 (b) and 12 (c). Therefore, when a reset signal is input, a high level voltage is applied to the node n3. When the voltage at the node n3 becomes high level, one end and the other end of the current path of the n-channel TFT 72 of the output circuit 70b become conductive, and the voltage at the node n2 (output terminal OUT) is changed from high level to low level. Further, when the voltage at the node n3 becomes high level, one end and the other end of the current path of the n-channel TFT 53 become conductive, and the voltage at the node n1 is changed from high level to low level.

As described above, the n-channel TFT 63 is provided to advance the fall of the output signal OUT and change the node n1 to the non-operating voltage at an early stage.
For the same reason as the n-channel TFT 51a included in the holding circuit 50a, the n-channel TFT 63 is suppressed from decreasing the threshold voltage Vth and hardly deteriorates.

  When a high-level input signal is input, one end and the other end of the current path of the n-channel TFT 64 become conductive, and the voltage at the node n3 is quickly changed from a high level to a low level. When the voltage at the node n3 becomes low level, the n-channel TFT 53 included in the holding circuit 50d and the n-channel TFT 72 included in the output circuit 70b are turned off. The n-channel TFT 64 is provided to quickly change the voltage of the node n3 to the low level in the input period ta.

  The holding circuit 50d is an example of the holding circuit of the present invention, the inverter circuit 60b is an example of the inverter circuit of the present invention, and the register circuit 40e is an example of the register circuit of the present invention.

  In the above embodiment, the circuit constituted by n-channel TFTs has been described. However, the present invention can be similarly applied to a circuit constituted by p-channel TFTs. Further, the present invention can be similarly applied to a circuit constituted by a field effect transistor having a structure other than the TFT.

  In the above embodiment, the active matrix driving type liquid crystal display device 100 has been described. However, the present invention can also be applied to a passive matrix driving type liquid crystal display device. Further, the present invention can be similarly applied to an organic EL display device. Furthermore, the present invention is not limited to a display device, and any device having a shift register using a TFT formed of amorphous silicon or polysilicon may be used. For example, it has a structure equivalent to a TFT made of amorphous silicon or polysilicon. The present invention can be similarly applied to an image sensor in which a plurality of light receiving elements configured as described above are arranged.

  As described above, according to the present invention, a TFT formed of amorphous silicon or polysilicon can be made difficult to deteriorate. Therefore, the operation of the shift register using TFTs formed of amorphous silicon or polysilicon can be stabilized for a long period of time, and the reliability and life of the liquid crystal display device and organic EL display device using the shift register are improved. Can be made.

  In addition, power consumption of a shift register using a TFT formed of amorphous silicon or polysilicon can be reduced. Furthermore, even if the present invention is applied to a shift register configured using field effect transistors other than TFTs formed of amorphous silicon or polysilicon, the power consumption of the shift register can be reduced. it can.

  Further, according to the present invention, the wiring for the high-level power supply voltage Vdd is not necessary, so that the area of the shift register can be reduced.

  Although the embodiments of the present invention have been described above, various modifications and combinations necessary for design reasons and other factors are described in the inventions described in the claims and the specific embodiments described in the embodiments of the invention. It should be understood that it falls within the scope of the invention corresponding to the examples.

It is a figure which shows an example of the liquid crystal display device which concerns on embodiment of this invention. It is a figure which shows the scanning pulse applied sequentially to a scanning line. It is a figure which shows an example of the shift register which concerns on embodiment of this invention. It is a figure which shows an example of a two-phase clock signal. It is a figure showing an example of circuit composition of a register circuit concerning an embodiment of the invention. It is a figure which shows an example of the voltage of each part of a holding circuit. It is a figure which shows an example of the voltage of each part of an output circuit. FIG. 6 is a diagram showing an example of voltages at various parts of the register circuit when the register circuits shown in FIG. 5 are arranged in cascade to form a shift register. It is the figure which expanded the output period and reset period of FIG. FIG. 6 is a diagram showing a holding circuit as a comparative example with respect to the holding circuit included in the register circuit of FIG. 5. It is a figure which shows the circuit structural example of the register circuit based on another embodiment of this invention. It is a figure which shows an example of the voltage of each part of a register circuit when the register circuit shown in FIG. 11 is arrange | positioned in cascade and a shift register is comprised. It is a figure which shows an example of the voltage of each part of an inverter circuit. It is a figure which shows the 1st modification of the register circuit which concerns on another embodiment of this invention. It is a figure which shows the 2nd modification of the register circuit which concerns on another embodiment of this invention. It is a figure which shows the circuit structural example of the register circuit which concerns on another embodiment of this invention.

Explanation of symbols

2 ... Scanning driver 10 ... Display elements 51a, 52, 61a, 62, 63, 71, 72 ... n-channel TFTs
40a, 40b, 40c, 40d, 40e ... register circuits 50a, 50b, 50c, 50d ... holding circuits 60a, 60b ... inverter circuits 70a, 70b ... output circuit 100 ... liquid crystal display device 200 ... shift registers LS1 to LSn ... scanning lines

Claims (12)

A multi-stage shift register comprising a plurality of register circuits connected in cascade,
Each of the register circuits is
A holding circuit that applies the output signal of the previous stage as an input signal, the output signal of the next stage as a reset signal, and outputs a first signal based on the input signal;
An output circuit to which a voltage based on the first signal is applied and which outputs a signal based on the first signal as the output signal;
With
The holding circuit is
An input terminal to which the input signal is applied;
A reset terminal to which the reset signal is applied,
A first clock signal having two voltage levels alternately and a voltage of a predetermined reference potential are applied;
When the input signal is applied to the input terminal, a voltage corresponding to the signal level of the first clock signal is output as the first signal, and when the reset signal is applied to the reset terminal, A shift register comprising means for outputting a voltage corresponding to a reference potential as the first signal. The holding circuit includes a first thin film transistor in which the first clock signal is applied to one end of a current path, and a control terminal is connected to the input terminal;
A second thin film transistor having one end of a current path connected to the other end of the current path of the first thin film transistor, the other end of the current path connected to the reference potential, and a control terminal connected to the reset terminal;
The shift register according to claim 1, further comprising: The first clock signal has, as voltage levels, a first voltage having a potential higher than the reference potential and a second voltage having a potential lower than the first voltage, and The input signal is applied when the first clock signal is at the first voltage;
When the input signal is applied, the holding circuit sets the voltage of the first signal to a voltage corresponding to the first voltage, and then applies the first signal until the reset signal is applied. 3. The shift register according to claim 1, wherein the voltage is held at a voltage corresponding to the first voltage or a voltage higher than the first voltage. 4. The output circuit has a second clock signal having two voltage levels alternately and the reference potential, and has an output terminal for outputting the output signal.
The second clock signal has, as voltage levels, a third voltage having a potential higher than the reference potential, and a fourth voltage having a potential higher than the reference potential and lower than the third voltage, The period when the first clock signal is the first voltage and the period when the second clock signal is the third voltage are set at a timing that does not overlap.
When the signal level of the first signal is a voltage corresponding to the first voltage or higher, the signal level of the output signal changes so as to approach the signal level of the second clock signal. And a means for setting the signal level of the output signal to a voltage corresponding to the reference potential when the signal level of the first signal is a voltage corresponding to the reference voltage. The shift register described.   A third thin film transistor in which the second clock signal is applied to one end of a current path, the other end of the current path is connected to the output terminal, and the first signal is applied to a control terminal; And a capacitance component having one end connected to the control terminal of the third thin film transistor and the other end connected to the other end of the current path of the third thin film transistor. Shift register. A multi-stage shift register comprising a plurality of register circuits connected in cascade,
Each of the register circuits is
A holding circuit that applies the output signal of the previous stage as an input signal, the output signal of the next stage as a reset signal, and outputs a first signal based on the input signal;
An output circuit to which the first signal and a second signal corresponding to an inverted signal of the first signal are applied, and a signal based on the first signal is output as the output signal;
An inverter circuit that receives the first signal and outputs the second signal;
With
The holding circuit uses, as the first signal, a signal having at least a first voltage having a potential higher than the reference potential and a second voltage having a potential equal to or higher than the reference potential and lower than the first voltage. Output,
The inverter circuit is
A first clock signal having two voltage levels alternately and a voltage of a predetermined reference potential are applied;
When the signal level of the first signal is the voltage of the first voltage or higher, the signal level of the second signal is changed to a voltage corresponding to the reference potential, and the first signal And a means for changing the signal level of the second signal to a voltage corresponding to the voltage level of the first clock signal when the signal level of the first clock signal is the second voltage. . The inverter circuit is
A fourth thin film transistor in which the first clock signal is applied to one end of the current path, a control terminal is connected to one end of the current path, and one end of the current path is connected to the other end of the current path of the fourth thin film transistor And a fifth thin film transistor, wherein the second signal is output, the other end of the current path is connected to the reference potential, and the first signal is applied to a control terminal. Item 7. The shift register according to Item 6. The output circuit has an output terminal for outputting the output signal,
A second clock signal having two voltage levels alternately and the reference potential are applied;
The first clock signal has, as voltage levels, a first voltage having a potential higher than the reference potential and a second voltage having a potential lower than the first voltage, and The input signal is applied when the first clock signal is at the first voltage;
The second clock signal has, as voltage levels, a third voltage having a potential higher than the reference potential, and a fourth voltage having a potential higher than the reference potential and lower than the third voltage, The period when the first clock signal is the first voltage and the period when the second clock signal is the third voltage are set at a timing that does not overlap.
When the signal level of the first signal is the voltage of the first voltage or higher and the signal level of the second signal is a voltage corresponding to the reference potential, the signal level of the output signal Close to the signal level of the second clock signal,
When the signal level of the first signal is a voltage corresponding to the reference voltage and the signal level of the second signal is a voltage corresponding to the first voltage, the signal level of the output signal is set to the reference voltage. 7. The shift register according to claim 6, further comprising means for setting a voltage corresponding to the potential. The output circuit includes a sixth thin film transistor in which the second clock signal is applied to one end of a current path, the other end of the current path is connected to the output terminal, and the first signal is applied to a control terminal; ,
A seventh thin film transistor in which one end of a current path is connected to the other end of the current path of the sixth thin film transistor, the other end of the current path is connected to the reference potential, and the second signal is applied to a control terminal; ,
9. The shift according to claim 8, further comprising: a capacitance component having one end connected to a control terminal of the sixth thin film transistor and the other end connected to the other end of the current path of the sixth thin film transistor. register. The holding circuit is applied with a first clock signal having two voltage levels alternately and a predetermined reference potential,
When the input signal is applied, a voltage according to the signal level of the first clock signal is output as the first signal, and when the reset signal is applied, a voltage according to the reference potential is output. Means for outputting as a first signal;
Means for setting the signal level of the first signal to a voltage based on the previous signal level when the input signal and the reset signal are not applied to the input terminal and the reset terminal;
The shift register according to claim 6, further comprising: The holding circuit is applied with a power supply voltage having a predetermined voltage level and a predetermined reference potential,
When the input signal is applied, a voltage corresponding to the voltage level of the power supply voltage is output as the first signal, and when the reset signal is applied, a voltage corresponding to the reference potential is output to the first signal. Means for outputting as a signal;
Means for setting the signal level of the first signal to a voltage based on the previous signal level when the input signal and the reset signal are not applied to the input terminal and the reset terminal;
The shift register according to claim 6, further comprising: A plurality of display elements arranged in a matrix;
A plurality of scanning lines connecting the display elements arranged in a predetermined direction;
A scan driver comprising the shift register according to any one of claims 1 to 11, wherein an output terminal of each register circuit included in the shift register is connected to each scan line;
A display device comprising:

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