JP2009017432A - Level shift circuit, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain output having a sufficient level by preventing amplitude drop in both Hi and Lo levels when composing a level shifter in a negative direction by using a bootstrap inverter in a one-channel configuration. <P>SOLUTION: The level shift circuit 10 has bootstrap buffers 240a, 240b at the post stage of the bootstrap level shifter 300 in a negative direction using the same conductivity TFTs, and has a bootstrap buffer 240c further at the post stage. The level shifter 300 is of a two-input/two-output type, and the buffers 240a, 240b, 240c are of two-input/one-output types. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a level shift circuit using a bootstrap effect in a one-channel configuration and a display device using the level shift circuit.

For example, as described in Patent Document 1, it is known that a level shifter is configured by connecting two stages of inverters using a bootstrap effect in a one-channel configuration. Such a level shifter generates an output signal having a voltage higher than that of the input signal by using a plurality of inverters that use a voltage higher than that of the input signal as a power source. At this time, the amplitude drop on the Hi side of the output signal can be prevented by the bootstrap effect.
JP 2002-328643 A (refer to FIG. 6 etc.)

  Patent Document 1 does not mention a negative-direction level shifter that shifts the amplitude of an input signal in the negative direction. However, a negative-direction level shifter is configured using a bootstrap inverter configured by N-channel transistors. Then, for example, a circuit as shown in FIG. That is, the two-input level shifter 300 and the two-input buffers 240a and 240b can be combined.

  6B shows a circuit configuration of the 2-input level shifter 300, and FIG. 6C shows a circuit configuration of the 2-input buffer 240. Note that VDD is a positive power source, and VEE is a negative power source. The input signal “01” has an amplitude between GND and VDD, and the input “/ 01” is an inverted signal thereof.

  In this figure, when the input signal in (/ 01) becomes Hi level, since the transistor Tr101 is turned on, the gate of the transistor Tr102 becomes VDD and turned on. Since the gate-source voltage of the transistor Tr102 is held in the capacitor C107, the gate voltage of the transistor Tr102 is further increased and is sufficiently turned on. Due to the bootstrap effect of the capacitor C107, the output signal out (/ 02) becomes VDD and the transistor Tr106 is turned on, but the gate voltage of the transistor Tr105 at that time is at the GND level, and the gate-source voltage of the Tr105 becomes VEE. Turn on weakly. Since the level of the output signal / out (02) is a voltage determined by the ratio of the on-resistance of the transistor Tr105 and the transistor Tr106, the Lo level is slightly higher than VEE in the output signal / out (02).

  FIG. 7 is a waveform diagram during operation of the circuit shown in FIGS. “01” and “/ 01” are input signals of the negative direction level shifter 300, and “02” and “/ 02” are output signals of the negative direction level shifter 300. “OA” and “OB” are output signals of the buffers 240a and 240b. From this waveform diagram, it can be confirmed that the Lo level float of “02” and “/ 02” and the Hi level drop of the outputs “OA” and “OB” in the buffers 240a and 240b receiving the output are confirmed.

  When such a level shifter is applied to a driving circuit of a display device using, for example, a thin film transistor (hereinafter referred to as a thin film transistor, TFT), the control signal does not fully swing. Problems occur.

  The present invention has been made in view of such circumstances, and when a negative level shift circuit is configured using a single-channel bootstrap inverter, the amplitude drop is prevented for both the Hi level and the Lo level. The problem to be solved is to obtain a sufficient level of output.

  In order to solve the above-described problem, in the level shift circuit according to the present invention, the absolute value of the logic level on the second potential side with respect to the input signal having the amplitude levels of the first potential and the second potential is the second value. A level shifter for generating an output signal greater than the potential; and at least two buffers connected in series in the subsequent stage of the level shifter; all the transistors constituting the level shifter and the at least two buffers have the same conductivity The logic level on the second potential side in the output signal of the level shifter has a smaller absolute value of the potential than the second potential side power source supplied to the at least two buffers, and the at least two buffers Each includes an input terminal, an output terminal, a first power supply terminal to which the first potential side power is supplied, and a second power supply terminal to which the second potential side power is supplied. A first transistor whose drain is connected to the first power supply terminal and whose source is connected to the output terminal; a second transistor whose drain is connected to the output terminal and whose source is connected to the second power supply terminal; A capacitance element is provided between the output terminal and the gate of the first transistor, and gate voltages of the first transistor and the second transistor are controlled according to a logic level of a signal supplied to the input terminal. And a gate voltage control unit.

  According to the present invention, the Hi level drop in the first stage buffer output caused by the Lo level float generated at the output of the level shifter is eliminated by using the second stage buffer, whereby the Hi level and the Lo level are eliminated. In both cases, a drop in amplitude can be prevented and a sufficient level of output can be obtained. That is, it becomes possible to eliminate the difference between the source side power supply voltage and the same output voltage in the level shifter constituted by one channel. As a result, it is possible to suppress the occurrence of leakage in subsequent circuits, and a level shift circuit with high reliability and low power consumption can be configured. Here, the transistor may be configured with either an n-channel or a p-channel, but when the level shift circuit is configured with an n-channel transistor, the level shift circuit has an amplitude between the first low potential and the first high potential. A level shifter for generating an output signal whose logic level on the low potential side is lower than the first low potential with respect to an input signal having a level; and at least two buffers connected in series downstream of the level shifter, All the transistors constituting the level shifter and the at least two buffers are of the same conductivity type, and the logic level on the low potential side in the output signal of the level shifter is a low potential power source supplied to the at least two buffers Each of the at least two buffers is supplied by an input terminal, an output terminal, and a high-potential power source. A first power supply terminal, a second power supply terminal to which the low-potential power is supplied, a drain connected to the first power supply terminal, a source connected to the output terminal, and a drain connected to the output A signal supplied to the input terminal, the second transistor having a source connected to the second power supply terminal and a capacitor connected between the output terminal and the gate of the first transistor; It is preferable that a gate voltage control unit that controls gate voltages of the first transistor and the second transistor according to a logic level of the first transistor and the second transistor.

Here, the first potential side power source is a third potential having an absolute value larger than the first potential and having the same polarity, and the second potential side power source has an absolute potential greater than the second potential. The fourth potential is preferably a large value and the same polarity. In this case, the level of the input signal can be shifted in both positive and negative directions. In the case where the transistor is formed of an n-channel, the high potential power source is a second high potential that is higher than the first high potential, and the low potential power source is lower than the first low potential. A second low potential is preferred.

  In the level shift circuit described above, the level shifter includes a first input terminal to which the input signal is supplied, a second input terminal to which an inverted input signal obtained by inverting the input signal, and a signal in phase with the input signal And a second output terminal for outputting a signal in phase with the inverted input signal, each of the at least two buffers being configured in a form of two inputs and one output. , A second buffer, and a third buffer, each buffer having a positive input terminal and a negative input terminal, the positive input terminal of the first buffer being connected to the second output terminal of the level shifter, The negative input terminal of the level shifter is connected to the first output terminal of the level shifter, and the positive input terminal of the second buffer is connected to the first output terminal of the level shifter. The input terminal is connected to the second output terminal of the level shifter, the positive input terminal of the third buffer is connected to the output terminal of the first buffer, and the negative input terminal of the third buffer is connected to the output terminal of the second buffer. It is preferred that

  More specifically, each of the first buffer, the second buffer, and the third buffer is connected in series between the first power supply terminal and the second power supply terminal as the gate voltage control unit. A third transistor and a fourth transistor, wherein the gate of the third transistor is connected to the positive input terminal, the gate of the fourth transistor is connected to the negative input terminal, and the gate of the second transistor is It is preferable to be connected to the positive input terminal. The two-input type buffer does not require the third transistor to be diode-connected, so that a quasi-stationary current does not flow. Thus, power consumption can be reduced.

  The level shift circuit described above further includes a fourth buffer and a fifth buffer having one input and one output provided in a preceding stage of the level shifter, and instead of supplying the input signal to the first input terminal of the level shifter, Instead of supplying the input signal to the input terminal of the fourth buffer, supplying the output signal of the fourth buffer to the first input terminal of the level shifter, and supplying the inverted input signal to the second input terminal of the level shifter Preferably, the output signal of the fifth buffer is supplied, and the output signal of the fourth buffer is supplied to the input terminal of the fifth buffer. In this case, the level shift is executed in the second potential direction using the fourth buffer and the fifth buffer, and then the level shift is executed in the first potential direction (negative direction). Since a level shift in the first potential direction (negative direction) is generally difficult, by first performing a level shift in the second potential direction and then performing a level shift in the first potential direction (west direction), It is more advantageous in terms of circuit scale, reliability, and power consumption than performing a level shift in the first potential direction in advance and performing a level shift in the second potential direction after performing amplitude compensation in the subsequent buffer. .

  In the level shift circuit described above, it is preferable that all the transistors constituting the level shift circuit are thin film transistors. The thin film transistor is greatly deteriorated due to so-called hot carriers that occurs when the gate voltage is in the vicinity of the threshold voltage. However, according to the present invention, the output signal of the level shift circuit can be fully swung. The deterioration of the thin film transistor can be suppressed. As a result, inconveniences such as review of the process, improvement in design freedom, increase in layout area, and cost increase accompanying improvement in transistor reliability can be solved.

  Next, a display device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines. A scanning line driving circuit for supplying a scanning signal to each of the plurality of scanning lines; and a data line driving circuit for supplying a data signal to each of the plurality of data lines. The level shift circuit described above is used at the output stage of the drive circuit. According to the present invention, it is possible to easily supply a scanning signal having a large amplitude with respect to the parasitic capacitance associated with the scanning line.

  The pixel circuit includes a switching transistor for capturing the data signal supplied via the data line, and the switching transistor is turned on based on the scanning signal supplied via the scanning line. And the off state are preferably controlled. In this case, since the amplitude of the scanning signal can be fully swung to the power supply voltage supplied to the level shift circuit, the leakage current flowing out from the pixel circuit to the data line can be reduced.

<1. First Embodiment>
FIG. 1 is a block diagram showing a configuration of a level shift circuit 10 according to the first embodiment of the present invention. The level shift circuit 10 shifts the level of the input signals 01 and / 01 having an amplitude of VDD (first high potential) -GND (second potential) in the negative direction so that the amplitude is VDD (first potential)- An output signal OC that becomes VEE (fourth potential) is generated. The magnitude relationship between the voltages is VDD>GND> VEE. The same circuit parts as those in FIG. 6 are denoted by the same reference numerals. As shown in this figure, the level shift circuit 10 is connected to a two-input one-channel bootstrap system level shifter 300 with two-input one-channel bootstrap systems buffers 240a and 240b as a first-stage buffer, A two-input single-channel bootstrap buffer 240c is connected as an eye buffer. The circuit configuration of the level shifter 300 is the same as that in FIG. 6B, and the circuit configurations of the buffers 240a, 240b, and 240c are the same as those in FIG.

  That is, the level shifter 300 includes a first input terminal / in to which the input signal 01 is supplied, a second input terminal in to which an inverted input signal / 01 obtained by inverting the input signal 01, and a signal in phase with the input signal 01. Is output, and a second output terminal / out that outputs a signal in phase with the inverted input signal / 01. Further, the buffer 240a includes a positive input terminal in connected to the second output terminal / out and a negative input terminal / in connected to the first output terminal out. The buffer 240b includes a positive input terminal in connected to the first output terminal out and a negative input terminal / in connected to the second output terminal / out. Further, the positive input terminal in of the buffer 240c is connected to the output terminal out of the buffer 240a, and the negative input terminal / in is connected to the output terminal out of the buffer 240b.

  In this level shift circuit 10, the output signal 02 of the one-channel bootstrap system level shifter 300 is perfect because the gate-source voltage of the transistor Tr 105 becomes VEE as described above when the input signal / 01 is at the Hi level. Since the on-resistance of the transistor Tr105 is not high but the on-resistance of the transistor Tr105 and the transistor Tr106, the Lo level of the output signal 02, which is determined by the ratio of the on-resistance of the transistor Tr105 and the transistor Tr106, is slightly higher than VEE ′. The same applies to the output signal 02.

Thus, when floating occurs in the Lo level of the output signals 02 and 02, it causes a leak in the buffers 240a and 240b in the first stage. This is because, in the circuit shown in FIG. 6, VEE ′ slightly higher than VEE is supplied as the gate voltage of the transistor Tr204, the transistor Tr204 is not completely turned off, and a leak current flows through the transistor Tr204. As a result, the Hi level of the output signals OA and OB decreases. The Hi level of the output signals OA and OB is VDD ′, which is slightly lower than VDD. In particular, when a TFT having a high driving capability is used as the transistor Tr204, the threshold voltage is lowered, and thus a drop in amplitude at the Hi level cannot be ignored.
Therefore, in the present embodiment, the output signals OC and OB of the first-stage buffers 240a and 240b are received by the second-stage buffer 240c, whereby an output signal OC having sufficient levels for both the Hi level and the Lo level can be obtained. I can do it.

  Specific operations of the first-stage buffers 240a and 240b and the second-stage buffer 240c will be described with reference to FIGS. 1 and 6B and 6C. When the output signals 02 and / 02 of the level shifter 300 with the Lo level floating are input to the first-stage buffers 240a and 240b, the pull-down transistor Tr204 is weakly turned on. The Hi levels of the output signals OA and OB are determined by the ratio of the on resistances of the drive transistor Tr203 and the pull-down transistor Tr204. As a result, the Hi levels of the output signals OA and OB are lowered.

  In the second-stage buffer 240c, the gate voltage of the drive transistor Tr203 becomes about (VDD−Vth + VDD) due to the bootstrap effect, so that the Tr203 is sufficiently turned on and the Hi level of the output signal OC becomes VDD. Therefore, sufficient output can be obtained from the second stage buffer 240c for both the Hi level and the Lo level.

  FIG. 2 is a diagram showing waveforms during operation of the level shift circuit 10. “01” and “/ 01” are input signals of the negative direction level shifter 300, “02” and “/ 02” are output signals of the negative direction level shifter 300, and “OA” and “OB” are output signals of the first stage buffers 240a and 240b. , “OC” is an output signal of the second-stage buffer 240c. From this figure, the Lo level float of “02” and “/ 02” and the Hi level drop of “OA” and “OB” have occurred, but the output “OC” of the second-stage buffer 240c is fully swung. It can be confirmed.

  As described above, in this embodiment, by connecting the two-stage buffer to the one-channel bootstrap system level shifter 300, it is possible to obtain sufficient outputs for both the Hi level and the Lo level. Note that the number of buffers connected to the level shifter may be three or more. Further, the present invention is not limited to the bootstrap type level shifter, and the present invention can be effectively applied to any level shifter that generates a Lo level float.

<2. Second Embodiment>
FIG. 3 is a block diagram showing a configuration of the level shift circuit 20 according to the second embodiment. The same circuit parts as those in FIG. 1 are denoted by the same reference numerals. In the present embodiment, two one-input positive direction level shifters 110a and 110b are connected to the preceding stage of the negative level shifter 300 in which two stages of buffers are connected to the subsequent stage described in the first embodiment. The circuit configuration of the level shifter 300 and the circuit configurations of the buffers 240a, 240b, and 240c can be the same as those in FIGS. 6B and 6C. FIG. 4 is a diagram illustrating a circuit configuration of the positive direction level shifter 110. The forward direction level shifter 110 is generally used, and is equivalent to a diode 240-connected Tr 201 in the buffer 240 shown in FIG.

The forward direction level shifter 110 is configured to input the output of the forward direction level shifter 110b that inputs the input signal in to the forward direction level shifter 110b in order to generate a reverse phase signal from the input signal in. By using the bootstrap effect, the level shift in the positive direction can be performed relatively easily. On the other hand, level shifting in the negative direction is generally difficult. For this reason, first, by performing level shift in the positive direction (drain side reference voltage) using the positive direction level shifters 110a and 110b, a signal that can output almost Hi level and Lo level is generated and then the negative direction (source If the level shift to the side reference voltage) is performed in advance, the level shift in the negative direction is preceded, and the amplitude compensation is performed in the buffer, and then the level shift in the positive direction is performed. This is advantageous in terms of power consumption. With this circuit, it is possible to obtain an output signal OC that is fully swinged in both the positive and negative directions from the buffer 240c.
In the first embodiment and the second embodiment, the operation has been described by taking up the level shifter and the buffer composed of the Nch transistor, but the same effect can be obtained also in the Pch transistor. In this case, the level shift in the negative direction can be performed relatively easily by using the bootstrap effect, but the level shift in the positive direction is generally difficult.

<3. Third Embodiment>
Next, an electronic device using the above-described level shift circuits 10 and 20 will be described. In this example, the level shifter is applied to a display device using a liquid crystal or an organic light emitting diode element. The display device includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits arranged in a matrix corresponding to the intersections. The pixel circuit includes a switching transistor that captures a data signal supplied via the data line in accordance with a scanning signal supplied via the scanning line. In addition, the display device includes a scanning line driving circuit that drives a plurality of scanning lines and a data line driving circuit that drives a plurality of data lines. The buffer circuits 1 and 2 described above can be applied to a scanning line driving circuit and a data line driving circuit. Hereinafter, a case where the buffer circuits 1 and 2 are used in the scanning line driving circuit of the liquid crystal display device will be described. Note that the entire display device is composed of TFTs of the same conductivity type.

FIG. 5 shows part of the structure of the scan line driver circuit. The scanning line driving circuit 100 includes a shift register 110 that sequentially transfers the start pulse SP according to the Y clock signal YCK and outputs transfer signals y1, y2,... Ym, and m drivers U1 to Un.
The pixel circuit P includes a switching transistor 20 and a liquid crystal element 21. The liquid crystal element 21 includes a pixel electrode connected to the switching transistor 20 and a counter electrode, and is configured with a liquid crystal sandwiched between the pixel electrode and the counter electrode. The data signal Vdata supplied through the data line 30 is taken into the pixel circuit P and applied to the liquid crystal element when the scanning signal Y is at the Hi level. Even when the scanning signal Y transitions to the Lo level, the applied voltage is held by the liquid crystal capacitance. Note that a storage capacitor may be provided in parallel with the liquid crystal element 21.

  Here, the data signal Vdata changes between GND and VDD. In this case, in order to turn the switching transistor 20 sufficiently on and sufficiently turn off, it is preferable to set the amplitude of the scanning signal Y from VEE (<GND) to VDH (> VDD). In the shift register 20, a transfer signal y having an amplitude of VEE to VDH can be generated and used as the scanning signal Y. However, in such a case, the power consumption of the shift register 20 increases. Therefore, the shift register 20 is supplied with the first high-potential power supply VDD and the first low-potential power supply GND, and generates a transfer signal y having an amplitude of GND to VDD.

The drivers U1 to Um are configured by the level shift circuit 20 described above. Therefore, the amplitudes of the scanning signals Y1 to Ym are VEE-VDH. Since the scanning line is accompanied by parasitic capacitance, it is necessary to use a pull-down transistor Tr204 shown in FIG. 6 having a high driving capability and a low threshold voltage. In this case, it is necessary to set the gate voltage of the pull-down transistor Tr204 to VEE so that the Hi level of the scanning signals Y1 to Ym does not drop from VDH. Since the level shift circuit 10 or 20 receives the output signal of the negative level shifter using the two-stage buffer as described above, the scanning signals Y1 to Ym can be fully swung between the amplitudes VEE and VDH.
If the amplitudes of the scanning signals Y1 to Ym are reduced, the switching transistor 20 is not sufficiently turned on / off. For this reason, a leakage current flows from the switching transistor 20 to the data line 30. As a result, the voltage applied to the liquid crystal element 21 varies and the luminance varies. In the present embodiment, since the scanning signals Y1 to Ym can be fully swung, the luminance can be accurately displayed, and the display quality can be improved.

  The level shift circuit 10 or 20 described above can also be applied to a data line driving circuit. For example, there is a case where a demultiplexer is provided at the output stage of the data line driving circuit, and a data signal is supplied by selecting a plurality of data lines. In this case, the demultiplexer includes a plurality of transistors, but a large-amplitude control signal is required to reliably turn on and off these transistors. This control signal is subjected to a full swing with a large amplitude of VEE to VDH by level-shifting the output of the control signal generation circuit operating at a low amplitude via the level shift circuit 10 or 20 described above. As a result, crosstalk can be prevented between adjacent data lines, luminance unevenness can be improved, and a sufficient write margin can be secured. Further, the level shift circuit 10 or 20 described above may be incorporated in a shift register. These can be applied to display devices, in particular, liquid crystal display devices using amorphous TFTs and liquid crystal display devices using low-temperature polysilicon TFTs.

It is a block diagram which shows the structure of the level shifter which concerns on 1st Embodiment. It is a figure which shows the output waveform of the level shifter which concerns on 1st Embodiment. It is a block diagram which shows the structure of the level shifter which concerns on 2nd Embodiment. It is a circuit diagram which shows the circuit structure of a positive direction level shifter. It is a block diagram which shows the structure of a scanning line drive circuit. It is a figure which shows an example of a negative direction level shifter circuit. It is a figure which shows the output waveform of a negative direction level shifter circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Level shifter, 20 ... Level shifter, 110 ... Positive direction level shifter, 240 ... Single channel bootstrap system buffer, 300 ... Negative direction level shifter

Claims (8)

A level shifter that generates an output signal in which the absolute value of the logic level on the second potential side is greater than the second potential with respect to an input signal having amplitude levels of the first potential and the second potential;
And at least two buffers connected in series downstream of the level shifter,
All the transistors constituting the level shifter and the at least two buffers are of the same conductivity type,
The logic level on the second potential side in the output signal of the level shifter has a smaller absolute value of the potential than the second potential side power source supplied to the at least two buffers,
Each of the at least two buffers is
An input terminal;
An output terminal;
A first power supply terminal to which a first potential side power supply is supplied; a second power supply terminal to which the second potential side power supply is supplied;
A first transistor having a drain connected to the first power supply terminal and a source connected to the output terminal;
A second transistor having a drain connected to the output terminal and a source connected to the second power supply terminal;
A capacitive element provided between the output terminal and the gate of the first transistor;
A gate voltage control unit that controls gate voltages of the first transistor and the second transistor according to a logic level of a signal supplied to the input terminal;
A level shift circuit characterized by that. The first potential side power source is a third potential having an absolute value larger than the first potential and having the same polarity,
The second potential side power source is a fourth potential having an absolute value larger than the second potential and having the same polarity.
A level shift circuit characterized by that. The level shifter is
A first input terminal to which the input signal is supplied;
A second input terminal to which an inverted input signal obtained by inverting the input signal is supplied;
A first output terminal that outputs a signal in phase with the input signal;
A second output terminal that outputs a signal in phase with the inverted input signal;
Each of the at least two buffers includes a first buffer, a second buffer, and a third buffer configured in a form of two inputs and one output, each buffer having a positive input terminal and a negative input terminal;
A positive input terminal of the first buffer is connected to a second output terminal of the level shifter;
A negative input terminal of the first buffer is connected to a first output terminal of the level shifter;
A positive input terminal of the second buffer is connected to a first output terminal of the level shifter;
A negative input terminal of the second buffer is connected to a second output terminal of the level shifter;
A positive input terminal of the third buffer is connected to an output terminal of the first buffer;
A negative input terminal of the third buffer is connected to an output terminal of the second buffer;
A level shift circuit characterized by that. Each of the first buffer, the second buffer, and the third buffer serves as the gate voltage control unit,
A third transistor and a fourth transistor connected in series between the first power supply terminal and the second power supply terminal;
A gate of the third transistor is connected to the positive input terminal;
A gate of the fourth transistor is connected to the negative input terminal;
A gate of the second transistor is connected to the positive input terminal;
The level shift circuit according to claim 3. A fourth buffer and a fifth buffer having one input and one output provided in a stage preceding the level shifter;
Instead of supplying the input signal to the first input terminal of the level shifter, the input signal is supplied to the input terminal of the fourth buffer and the output signal of the fourth buffer is supplied to the first input terminal of the level shifter. And
Instead of supplying the inverted input signal to the second input terminal of the level shifter, supplying the output signal of the fifth buffer,
An output signal of the fourth buffer is supplied to an input terminal of the fifth buffer;
A level shift circuit characterized by that.   6. The level shift circuit according to claim 1, wherein all transistors constituting the level shift circuit are thin film transistors. A display device comprising a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines,
A scanning line driving circuit for supplying a scanning signal to each of the plurality of scanning lines;
A data line driving circuit for supplying a data signal to each of the plurality of data lines,
The level shift circuit according to any one of claims 1 to 6 is used as an output stage of the scanning line driving circuit.
A display device characterized by that. The pixel circuit includes a switching transistor for capturing the data signal supplied via the data line,
The switching transistor is controlled to be turned on and off based on the scanning signal supplied through the scanning line.
The display device according to claim 7.

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