JP2001350438A - Shift register and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a shift register capable of operating constantly for a long period by preventing transistors characteristics from being fluctuated. SOLUTION: This shift register is composed of plural stages, RS1 to RSn and each of stages, RS1 to RSn is composed of TFT 1 to TFT 6. In the Kth stage RSk, the output signal OUTk-1 of a front stage (in a first stage, the start signal Dst from the outside) is supplied to the gate of the TFT 1. When this signal turns to a high level, the TFT 1 is turned ON and it outputs a power source voltage Vdd from the drain to the source so as to store electric charge on a node Ak and to turn the TFT 2, 5 ON and the TFT 3 OFF. Moreover, the output signal OUTk+1 of a next stage RS ((k+1)th SRk+1) (in the Nth stage, the completion signal Dend from the outside) is supplied to the TFT 6 and when this signal turns to a high level, the TFT 6 is turned ON so as to release electric charge stored on the node Ak.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a shift register,
And an electronic device such as a display device or an imaging device using the shift register as a driver.

[0002]

2. Description of the Related Art In an active matrix type liquid crystal display device such as a TFT liquid crystal display device, display pixels arranged in a matrix are selected line by line, and display data is written into a pixel capacitance of the selected pixel to thereby obtain a desired display pixel. Getting the display. As a driver for selecting this line, a shift register that sequentially shifts an output signal in accordance with an external control signal is generally used.

Japanese Patent Laying-Open No. 2000-35772 discloses such a shift register. FIG. 27 is a diagram showing a circuit configuration of a shift register disclosed in the above publication. As shown, the shift register includes n stages RS (1) to RS (n).
Each of RS (n) is constituted by five TFTs 101 to 105. Each of the TFTs 101 to 105 is an n-channel type field effect transistor.

Next, the operation of this shift register will be described with reference to FIG.
This will be described with reference to the timing chart of FIG. First, the start signal Dst is at a high level from the timing T0 to T1, and the control signal φ1 is at a high level.
During this time, the TFT 101 of the first stage RS (1) is turned on, and charges are accumulated at the node A1. This allows
When the TFTs 102 and 105 are turned on and the TFT 105 is turned on, the gate voltage of the TFT 103 is changed to a low level, and the TFT 103 is turned off.

Next, when the clock signal CK1 changes to the high level at the timing T1, the output signal OU of the first stage RS (1) remains almost unchanged.
Output as T1. Between the timings T1 and T2, the high-level output signal OUT1 changes to the second stage RS (2).
Is supplied to the TFT 101, and the control signal φ2 goes to a high level. This causes charges to be accumulated in the node A2 of the second stage RS (2), turning on the TFTs 102 and 105 and turning off the TFT 103.

Next, when the clock signal CK2 changes to the high level at the timing T2, the output signal OU of the second stage RS (2) remains almost unchanged.
Output as T2. Between the timings T2 and T3, the high-level output signal OUT2 changes to the third stage RS (3).
Is supplied to the TFT 101, and the control signal φ1 goes to a high level. This causes charges to be accumulated at the node A3 of the third stage RS (3), turning on the TFTs 102 and 105 and turning off the TFT 103.

During this period, the charge stored in the node A1 of the first stage RS (1) is released by the control signal φ1 which has become high level, and the TFTs 102 and 105 are turned off and the TFT 103 is turned on. After this, the first stage RS
No charge is accumulated in the node A1 of (1) until the next start signal Dst is supplied, and the output signal OUT1 is output even if the clock signal CK1 changes to high level.
Does not go to high level.

After timing T3, the third and subsequent stages RS
(1) to RS (n) perform the same operation,
Each time the clock signals CK1 and CK2 go high during each period of T, the output signals OUT1 to OUTn sequentially go high and the output signals shift.

By way of example, in the lower stage of the timing chart of FIG. 28, the third stage RS (3) will be described as an example. The output signal is shifted from the first stage RS (1) to the nth stage RS (n). In this case, the control signal φ1 or φ2 applied to the gate of the TFT 101 becomes high level n / 2 times. That is, the high-level voltage is actually applied to the gate of the TFT 101 only twice for storing and discharging the electric charge, but the high-level voltage is actually applied n / 2 times. The Rukoto. In most cases, the voltage level of the drain and source of the TFT 101 is low.

As described above, since there are many periods in which the gate voltage of the TFT 101 is relatively positive with respect to the drain and source voltages, the gate threshold voltage characteristic of the TFT 101 changes to be more positive. As a result, when used for a long period of time, the TFT 1 that should be turned on
01 may not be turned on, and the charge may not be stored in the nodes A1 to An, or the stored charge may not be released. That is, the conventional shift register shown in FIG. 27 has a first problem that it causes a malfunction and lowers durability.

Further, in the shift register shown in FIG. 27, the start signal Dst or the output signal OUT1 of the preceding stage is output.
OUTn−1 are connected to the nodes A1 through A1 via the TFT 101.
Since the signal is transferred to An, the nodes A1 to An hold a voltage lower than the signal level Vdd by the threshold voltage of the TFT 101.

However, as shown in FIG. 28, while the clock signal CK1 or CK2 is at a high level, the node A is driven by a so-called bootstrap effect.
The signal levels 1 to An rise to a level higher than Vdd. Therefore, the T connected to the nodes A1 to An
The FTs 101, 102, and 105 receive a very large voltage stress, and the device characteristics are degraded. If the TFT 101, 102, 1
There is a second problem that the durability of the battery 05 is lowered because the battery 05 may fail.

The above publication discloses that each stage RS (1) to RS (n) of the shift register shown in FIG.
And by adding the number of control signals, the output signal O
UT1, OUT2,..., OUTn in the order of high level, and output signals OUTn, OUT
There is also disclosed a shift register that can perform both a backward shift to sequentially set a high level in the order of n−1,..., OUT1.

However, each stage RS (1) -RS
By adding a TFT to (n), the shift register can perform only one-way shift shown in FIG.
There is a third problem that the area is increased by the added TFT. The third problem further causes a problem that when the shift register is formed as a driver on the same substrate as the substrate of the liquid crystal display element, the relative area of the image display area is reduced. .

[0015]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and provides a shift register capable of operating stably for a long period of time by preventing fluctuations in transistor characteristics. The first purpose is to do so.

A second object of the present invention is to provide a shift register which can operate stably for a long period of time by preventing a large voltage stress from being applied to the shift register constituting each stage.

A third object of the present invention is to provide a shift register capable of performing a shift operation in both a forward direction and a reverse direction with substantially the same area as a shift register capable of performing only one-way shift.

A fourth object of the present invention is to provide an electronic device such as a display device or an image pickup device using such a shift register as a driver for selecting a display pixel or an image pickup pixel.

[0019]

To achieve the above object, a shift register according to a first aspect of the present invention is a shift register having a plurality of stages, wherein each stage of the shift register has a control terminal. , An output signal of an adjacent stage (for example, a previous stage) is supplied to one side, and a first end of the current path is
A first transistor to which the voltage signal is supplied, an output signal of an adjacent stage (for example, a subsequent stage) is supplied to the other side to the control terminal, and a second voltage signal is supplied to one end of the current path. And a control terminal is connected to the other end of each of the current paths of the first and second transistors, and the first or second power supply is supplied to the wiring therebetween through the first or second transistor. And the first or second clock signal supplied to one end of the current path is output from the other end of the current path to the output of the stage when the charge is accumulated by the voltage signal of (2) and turned on by the accumulated charge. A third transistor for outputting a signal, and at least one of the first and second transistors emits charges accumulated in the wiring in response to an output signal of an adjacent stage supplied to a control terminal. Characterized in that it is configured to allow.

Here, one of the first and second transistors at one end of the plurality of stages is turned on when a first control signal is externally supplied to a control terminal, and charges are applied to the wiring. The other of the first and second transistors at the other end of the plurality of stages is turned on when a second control signal is supplied from the outside to a control terminal, and charges accumulated in the wiring are turned on. It can be released.

In the shift register, since the signal supplied to the control terminal of the first or second transistor is an output signal of an adjacent stage, while the shift operation is sequentially performed from one end to another, The potential does not turn on unnecessarily. For this reason, the characteristics of the first or second transistor do not change much, and thus the transistor can operate stably for a long time.

The shift register switches the levels of the first and second voltage signals, thereby providing the first and second voltage signals.
Charges can be stored in the wiring through one of the second transistors, and charges stored in the wiring can be released through the other of the first and second transistors. it can.

In this case, the levels of the first and second voltage signals may be switched so that one of them is maintained at a low level.

By such switching of the voltage signal, the electric charge can be accumulated in the wiring by the output signal of the previous stage, or the electric charge can be accumulated in the wiring by the output signal of the subsequent stage. In other words, if charge is accumulated by the output signal of the previous stage, the output signal shifts toward the next stage, and if charge is accumulated by the output signal of the next stage, it shifts toward the previous stage. Therefore, a shift register capable of bidirectional shift can be provided.

In the above shift register, the first,
The high level of the second voltage signal is preferably lower than the high level of the first and second clock signals.

In the above shift register, the first,
It is preferable that each period in which the second voltage signal is at a high level is shorter than each period in which one of the first and second clock signals is at a high level.

As described above, the high level of the first and second voltage signals is set lower than the high level of the first and second clock signals, or the period during which the high level is high is limited. , And / or the voltage stress applied to the first and / or second transistors can be reduced.
Thus, the first and second transistors are less likely to fail, and can operate stably for a long time.

In the above shift register, the first clock signal and the second clock signal may be 180 ° out of phase with each other.

In the shift register, each transistor constituting each of the plurality of stages may be a same-channel type field effect transistor.

In the shift register, a control terminal is connected to the other end of each current path of the first and second transistors, and a control line is supplied to a wiring therebetween through the first or second transistor. While accumulating electric charge by the first or second voltage signal, and when turned on by the accumulated electric charge, a signal supplied from a voltage source via a load is applied to one end of the current path from the other end of the current path. A fourth transistor to be released, a control terminal connected to the voltage source via the load, and turning on by a signal connected from the voltage source when the fourth transistor is off; And a fifth transistor having one end connected to the other end of the current path of the third transistor.

To achieve the above object, an electronic device according to a second aspect of the present invention comprises a plurality of stages, a driver for sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, A driving element constituted by a plurality of pixels and driven by an output signal output from each stage of the driver, wherein each stage of the driver is supplied with an output signal of an adjacent stage on one side to a control terminal. And a first voltage signal is supplied to one end of the current path.
And a control terminal, an output signal of an adjacent stage is supplied to the other side, and a second voltage signal is supplied to one end of a current path. A control terminal is connected to the other end of each of the current paths, and charges are stored in the wiring therebetween by the first or second voltage signal supplied through the first or second transistor, and the stored charge is stored. A third transistor for outputting the first or second clock signal supplied to one end of the current path from the other end of the current path as an output signal of the stage when the first transistor is turned on by the accumulated electric charge; , A control terminal is connected to the other end of each current path of the second transistor, and the first or second
The first or the second supplied through the transistor of
A fourth signal for discharging a signal supplied from a voltage source via a load to one end of the current path from the other end of the current path when the charge is accumulated by the voltage signal of A transistor and a control terminal are connected to the voltage source via the load, and when the fourth transistor is off, the transistor is turned on by a signal connected from the voltage source, and one end of a current path is connected to the fourth transistor. And a fifth transistor connected to the other end of the current path of the third transistor, wherein at least one of the first and second transistors is connected to the control terminal via an output signal of an adjacent stage supplied to a control terminal. Characterized in that it is configured to be able to release the electric charge stored therein.

In the above electronic device, the driving element may be:
For example, a display element provided for each pixel may include a sixth transistor to which an output signal of any one of the stages of the driver is supplied to a control terminal and image data is externally supplied to one end of a current path. it can.

Further, the electronic device includes an image pickup unit including an image pickup device for picking up an optical image formed by an image pickup lens;
The image display device further includes a display unit that is provided rotatably with respect to the imaging unit about a direction substantially perpendicular to the imaging direction and includes a display element as the driving element and the driver that drives the display element. There may be. In this case, the display unit may display an image corresponding to an image captured by the imaging device on the display element.

In the case of such an electronic device,
Setting means for setting which of the first and second transistors accumulates electric charge in the wiring and discharges the accumulated electric charge, and angle detection for detecting an angle of the imaging unit with respect to the display unit Means for setting one of the first and second transistors by performing setting in accordance with the detection result of the angle detecting means and switching the level of the first and second voltage signals. It is preferable that charges can be stored in the wiring through the first transistor and the charges stored in the wiring can be released through the other of the first and second transistors.

In this case, it becomes possible for the driver to switch between the forward direction and the reverse direction and to perform a bidirectional shift operation. When the driver performs the shift operation in the reverse direction, the image displayed on the display unit can be easily inverted upside down. Thereby, the mirror image of the image captured by the imaging device can be displayed on the display unit without performing complicated control for reading out the image to be displayed.

In the above electronic device, the driving element is
A semiconductor layer that generates carriers by excitation light, a drain electrode and a source electrode respectively connected to both ends of the semiconductor layer, and a first gate electrode provided on one side of the semiconductor layer via a first gate insulating film And a second gate electrode provided on the other side of the semiconductor layer with a second gate insulating film interposed therebetween.

In this case, the driver comprises: a first driver for outputting an output signal to a first gate electrode;
And a second driver that outputs an output signal to the second gate electrode.

The electronic device as described above has a driver for driving the drive element having the same configuration as the shift register according to the first aspect.
For this reason, the durability of the driver is high, so that the electronic device as a whole can have excellent durability.

[0039]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a diagram showing an external configuration of a digital still camera according to this embodiment. As shown in the figure, the digital still camera includes a camera body 01 and a lens unit 02.

The camera body 01 has a display 1 on its front.
0 and a mode setting key 12a. The mode setting key 12a is a key for switching between a photographing mode for photographing an image and recording the image in an image memory described later and a reproduction mode for reproducing the recorded image. Display unit 10
Comprises a liquid crystal display device, which functions as a viewfinder for displaying an image captured by the lens 02a before shooting in a shooting mode (monitoring mode), and a display for displaying a recorded image in a playback mode. Function as The configuration of the display unit 10 will be described in detail.

The camera body 01 has a power key 11, a shutter key 12b, and a "+" key 1 on its upper surface.
2c, a "-" key 12d, and a serial input / output terminal 13
And The power key 11 is a key for turning on / off the power of the digital still camera by performing a slide operation. Shutter key 12b, "+"
The key 12c and the “−” key 12d constitute the key input unit 12 together with the mode setting key 12a described above.

The shutter key 12b is a key for instructing recording of an image in the photographing mode and for deciding the selected contents in the reproducing mode. "+" Key 12c
The "-" key 12d is used to select image data to be displayed on the display unit 10 from image data recorded in the image memory in the shooting mode, and to set conditions for recording / reproduction. The serial input / output terminal 13 is a terminal for inserting a cable for transmitting and receiving data to and from an external device (a personal computer, a printer, or the like).

The lens unit 02 has a lens 02a for forming an image to be photographed on the rear side in the figure.
The lens unit 02 is attached to be rotatable up and down 360 ° about an axis connected to the camera body 01.

FIG. 2 is a block diagram showing a circuit configuration of the digital still camera according to this embodiment. As shown in the figure, this digital still camera uses a CCD (Ch
argeCoupled Device) imaging device 20, A / D (Analogue)
/ Digital) converter 21, CPU (Central Processing U)
nit) 22, ROM (Read Only Memory) 23, RAM
(Random Access Memory) 24, compression / expansion circuit 25,
An image memory 26 is provided, as well as the display unit 10, the key input unit 12, and the serial input / output terminal 13 described above. These are connected to each other via a bus 30. CCD
The imaging device 20 and the A / D converter 21 are also connected by a dedicated line. The angle sensor 40 indicated by a broken line is not included as a component in this embodiment (see a second embodiment described later).

The CCD image pickup device 20 has a plurality of image pickup pixels formed in a matrix, photoelectrically converts light formed by the image pickup lens 02a, and outputs an electric signal corresponding to the light intensity of each pixel. Output. The A / D converter 21 has a CC
An analog electric signal output from the D imaging device 20 is converted into a digital signal and output.

The CPU 22 controls a circuit of each section of the digital still camera by executing a program stored in the ROM 23 in accordance with an input from the key input section 12. The ROM 23 stores programs executed by the CPU 22 and also stores fixed data. The RAM 24 is used as a work area when the CPU 22 executes a program. In the RAM 24,
Further, a VRAM area for expanding image data to be displayed on the display unit 10 is provided.

The compression / expansion circuit 25 includes a shutter key 1
When the 2b is operated, image data photographed by the CCD imaging device 20 and converted into a digital signal by the A / D converter 21 is compressed and recorded in the image memory 26. The compression / expansion circuit 25 also receives an instruction from the key input unit 12 to display a captured image.
The image data compressed and recorded in the image memory 26 is expanded.

The image memory 26 is constituted by a non-volatile storage medium such as a flash memory from which data can be erased, and records the photographed and compressed image data as described above. The image memory 26 may be configured to be detachable from the digital still camera.

FIG. 3 is a block diagram showing the structure of the liquid crystal display device constituting the display section 10. As shown in FIG. As shown, the liquid crystal display device includes a liquid crystal controller 50, a liquid crystal display element 51, a gate driver 52, and a drain driver 53. The control signal group Gcnt is supplied to the gate driver 52, and the control signal group Dcnt and the display data data are supplied to the drain driver 53 from the liquid crystal controller 50.

The liquid crystal controller 50 generates control signal groups Gcnt and Dcnt according to control signals from the CPU 22 and supplies them to the gate driver 52 and the drain driver 53, respectively. The liquid crystal controller 50 also has C
VRAM of RAM 24 according to control signal from PU 22
The image data expanded in the area is read out, and the display data d
The data is supplied to the drain driver 53 as “ata”.

The liquid crystal display element 51 has a structure in which liquid crystal is sealed in a pair of substrates.
TFTs 61 for active driving using Si as a semiconductor layer are formed in a matrix. The gate of each TFT 61 is connected to the gate line GL, and the drain is connected to the drain line DL.
The source is connected to pixel electrodes similarly formed in a matrix. A predetermined voltage Vco is applied to the other substrate.
A common electrode to which m is applied is formed, and a pixel capacitor 62 is formed by the common electrode, each pixel electrode, and liquid crystal therebetween. The liquid crystal display element 51 displays an image by controlling the amount of transmitted light by changing the alignment state of the liquid crystal by the electric charge stored in the pixel capacitor 62.

The gate driver 52 is constituted by a shift register that operates according to a control signal group Gcnt from the liquid crystal controller 50. The gate driver 52 includes:
According to the control signal group Gcnt from the liquid crystal controller 50, the gate lines GL are sequentially selected and a predetermined voltage is output. The shift register forming the gate driver 52 will be described later in detail.

The drain driver 53 sequentially takes in the display data data from the liquid crystal controller 50 according to the control signal group Dcnt from the liquid crystal controller 50. 1
When the display data data for the line is accumulated, the drain driver 53 outputs this to the drain line DL in accordance with the control signal group Dcnt from the liquid crystal controller 50, and the TFT 61 connected to the gate line GL selected by the gate driver 52. (ON state), and is accumulated in the pixel capacitor 62.

FIG. 4 is a diagram showing a circuit configuration of a shift register applied as the gate driver 52 of FIG.
As shown in the figure, this shift register has n stages RS (1) equal to the number of gate lines GL of the liquid crystal display element 51.
To RS (n) (n: even number).

When the shift register is applied as the gate driver 52, the clock signal CK 1, the clock signal CK 1,
CK2, power supply voltage Vdd, reference voltage Vss (<Vd
d), a start signal Dst and an end signal Dend are supplied. Among them, the power supply voltage Vdd and the reference voltage Vss
Indicates that the clock signal C is supplied to all the stages RS (1) to RS (n).
K1 is an odd-numbered stage RS (1), RS (3),.
(N-1), the clock signal CK2 is applied to the even-numbered stages RS
(2), RS (4),..., RS (n), the start signal Dst is applied only to the first stage RS (1), and the end signal Den
d is supplied only to the n-th stage RS (n).

Since the configuration of each stage is almost the same, the first stage RS (1) will be described as an example.
(1) has six TFTs 1 to 6 made of an a-Si semiconductor layer similarly to the TFT 61. TFT1-6
Are all the same channel type (here, n-channel type)
Field effect transistor.

The gate of the TFT 1 has a start signal Ds
t is supplied. The power supply voltage V is applied to the drain of TFT1.
dd is supplied. The source of TFT1 is TFT2
, The gate of the TFT 5, and the drain of the TFT 6. The source of this TFT1, TFT2
A wiring surrounded by and connected to the gate of the TFT 5, the gate of the TFT 5 and the drain of the TFT 6 is referred to as a node A1 (note that the second and subsequent stages are A2 to An, respectively). When the start signal Dst becomes high level and TF
When T1 is turned on, the power supply voltage Vdd is output from the source, so that electric charge is accumulated in the node A1.

The clock signal CK is connected to the drain of the TFT 2.
When the TFT 1 is supplied and the TFT 2 is turned on, the level of the clock signal CK1 is output as it is as the output signal OUT1 to the first gate line GL from the source. The source of TFT2 is connected to the drain of TFT3.

The power supply voltage Vdd is supplied to the gate and the drain of the TFT 4, and the TFT 4 is always on. T
The FT 4 functions as a load for supplying the power supply voltage Vdd, and applies the power supply voltage Vdd from the source thereof to T
Supply to the drain of FT5. The TFT 4 can be replaced with a resistance element or the like other than the TFT. TFT
5 is supplied with the reference voltage Vdd,
When the FT5 is turned on, the charge accumulated between the source of the TFT4 and the drain of the TFT5 is released.

The gate of the TFT 3 is connected to the source of the TFT 4 and the drain of the TFT 5, and is turned on by the power supply voltage Vdd supplied through the TFT 4 when the TFT 5 is off. While the TFT 5 is on, the electric charge accumulated in the wiring between the source of the TFT 4 and the TFT 5 is released, so that the gate voltage of the TFT 3 is at a low level and is turned off.

The output signal OUT2 of the next stage, the second stage RS (2), is supplied to the gate of the TFT6. T
The drain of FT6 is connected to the node A1, and the source is supplied with the reference voltage Vss. Output signal OU
When T2 becomes high level, TFT6 turns on, and node A
The electric charge stored in 1 is released.

The odd-numbered stages RS (3), R other than the first
, RS (n-1) are arranged in the gate of the TFT 1 at the previous stage RS (2), RS (4), ..., RS (n-
2), the output signals OUT2, OUT4,.
Is the same as that of the first stage RS (1) except that is supplied.

Odd-numbered stages other than the n-th stage RS (2), R
, RS (n−2) are arranged in the gate of the TFT 1 at the previous stage RS (1), RS (3),.
3) output signals OUT1, OUT3,..., OUTn-3
Except that the clock signal CK2 is supplied to the drain of the TFT2.
Same as (1). The configuration of the n-th stage RS (n) is
Except that the end signal Dend is supplied to the gate of the TFT 6, the other even-numbered stages RS (2), RS (4),.
Same as S (n-2).

The shift register constituting the gate driver 52 is composed of a combination of TFTs 1 to 6, and the TFTs 1 to 6 have substantially the same structure as the TFT 61 included in the liquid crystal display element 51. I have. Therefore, the gate driver 52 is provided with the TF of the liquid crystal display element 51.
It can be formed collectively by the same process on the substrate on the T61 side.

The operation of the digital still camera according to this embodiment will be described below. Before describing the overall operation, first, the operation of the shift register forming the gate driver 52 will be described with reference to the timing chart of FIG. When used as the gate driver 52, each control signal is supplied from the liquid crystal controller 50 as a control signal group Gcnt.

In this timing chart,
The high levels of the clock signals CK1 and CK2, the start signal Dst, and the end signal Dend are all equal to the power supply voltage Vdd. On the other hand, the low level of these signals is
Both are equal to the reference voltage Vss. The 1T period is one horizontal period in the display unit 10.

Before the shift operation is started according to this timing chart (before T0), output signal OU is output.
T1 to OUTn are all at a low level. Further, in any of the stages RS (1) to RS (n), no electric charge is stored in the nodes A1 to An, and the TFT2 and the TFT5 are on and the TFT3 is off.

When the start signal Dst goes high during the timing T0 to T1, the TFT1 of the first stage RS (1) is turned on, and the power supply voltage Vdd is output from the drain of the TFT1 to the source. Thereby, the first stage R
The electric charge is accumulated in the node A1 of S (1), the electric potential thereof becomes high level, and the TFT2 and the TFT5 are turned on.
When the TFT 5 is turned on, the source of the TFT 4 and T
The charge accumulated between the FT5 and the drain of the FT5 is released,
The TFT 3 turns off. This period is the first stage RS
The TFT2 of (1) turns on, but the level of the output signal OUT1 remains low because the clock signal CK1 is low.

Next, when the clock signal CK1 changes to the high level at the timing T1, this is output from the drain of the TFT2 of the first stage RS (1) to the source, and the level of the output signal OUT1 changes to the high level. I do. At this time, the potential of the node A1 rises to about twice the power supply voltage Vdd due to a so-called bootstrap effect, and reaches the saturation gate voltage of the TFT2. Therefore, the drain current of the TFT2 becomes a saturation current, and the level of the output signal OUT1 is increased. Quickly becomes almost equal to the high level of the clock signal CK1. That is, the output signal OUT1
Is almost equal to the power supply voltage Vdd. Thereafter, when the clock signal CK1 falls until the timing T2, the output signal OUT1 shifts to a low level.

In the period between timings T1 and T2,
High level output signal O of the first stage RS (1)
The UT1 turns on the TFT1 of the second stage RS (2). Thus, the power supply voltage Vdd is output from the source of the TFT1 of the second stage RS (2), so that the potential of the node A2 becomes high level, and the second stage RS (2)
TFT2 and TFT5 turn on, and TFT3 turns off.

Next, when the clock signal CK2 changes to the high level at the timing T2, this is output from the drain of the TFT2 of the second stage RS (2) to the source, and the level of the output signal OUT2 changes to the high level. I do. Thereby, the TFT of the first stage RS (1) is now
6 is turned on, and the accumulated charge is released from the node A1 via the TFT 6 to become the reference voltage Vss. Therefore, the output signal OUT1 is maintained at the low level, and the first stage RS ( 1) TFT2 and TFT5 are turned off, and TFT3 is turned on. Therefore, the output signal OUT
The potential of 1 surely becomes the reference voltage Vss, and this state continues at least until the timing Tn + 1. Thereafter, when the clock signal CK2 falls until the timing T3, the output signal OUT2 becomes low level.

In the period between timings T2 and T3,
The output signal O of the second stage RS (2) which has become high level
The UT2 turns on the TFT1 of the third stage RS (3). As a result, the power supply voltage Vdd is output from the source of the TFT1 of the third stage RS (3), so that the potential of the node A3 becomes high level, and the third stage RS (3)
TFT2 and TFT5 turn on, and TFT3 turns off.

Next, when the clock signal CK1 changes to the high level at the timing T3, this is output from the drain of the TFT2 of the third stage RS (3) to the source, and the level of the output signal OUT3 changes to the high level. I do. As a result, the TFT of the second stage RS (2)
6 is turned on, and the electric charge accumulated at the node A2 is equal to the TFT1 of the second stage RS (2) and the TFT1 of the first stage RS (1).
Since the signal is discharged via the TFT 6 without passing through the FT 3 and becomes the reference voltage Vss, the output signal OUT1 is maintained at the low level, and the second stage R
In S (2), TFT2 and TFT5 are turned off, and TFT3 is turned on. That is, in the second stage RS (2), TFT2
Becomes low level and the TFT3 is turned on, so that the potential of the output signal OUT2 is reliably set to the reference voltage Vss.
And this state continues at least until timing Tn + 1. Thereafter, when the clock signal CK1 falls until the timing T3, the output signal OUT3 goes low.

In the period between timings T3 and T4,
The output signal O of the third stage RS (3) which has become high level
The UT3 turns on the TFT1 of the fourth stage RS (4). As a result, the power supply voltage Vdd is output from the source of the TFT1 of the fourth stage RS (4), so that the potential of the node A4 becomes high level, and the fourth stage RS (4)
TFT2 and TFT5 turn on, and TFT3 turns off.

Hereinafter, the fourth and subsequent stages RS (4), RS
(5),... Perform the same operation as above for each 1T period, so that the output signals OUT4, OUT5,.
It changes to a high level at predetermined intervals within the period T.
In the period from timing Tn-1 to Tn, the TFT1 of the n-th stage RS (n) is output by the output signal OUTn-1 of the (n-1) -th stage RS (n-1) which has become high level.
Turns on. Thereby, the TF of the n-th stage RS (n)
By outputting the power supply voltage Vdd from the source of T1,
The potential of the node An becomes high level, and the n-th stage RS
(N) TFT2 and TFT5 are turned on, and TFT3 is turned off.

Next, when the clock signal CK2 changes to the high level at the timing Tn, this is output from the drain of the TFT2 of the n-th stage RS (n) to the source, and the level of the output signal OUTn changes to the high level. I do. Thereafter, when the clock signal CK2 falls before the timing Tn + 1, the output signal OUTn becomes low level.

Then, at the timing Tn + 1, the level of the end signal Dend changes to the high level. As a result, when the TFT1 of the n-th stage RS (n) is turned on, the electric charge accumulated in the node A2 is released, the TFT2 and the TFT5 of the second stage RS (2) are turned off, and the TFT3 is turned on. . Then, until the next high-level start signal Dst is supplied, the stage RS
In each of (1) to RS (n), nodes A1 to
An electric charge is not accumulated in An, and TFT2 and TFT5
Is kept on, and the TFT 3 is kept off.

As described above, the first stage RS (1)
While the output signal shifts from the first stage to the n-th stage RS (n), the third stage R determines how the potentials of the gate, drain and source of one TFT 1 change.
The TFT 1 of S (3) will be described as an example. The lower three rows in FIG. 5 show changes in the gate, drain, and source potential levels of the TFT 1 in the third row RS (3).

As shown in the figure, the gate voltage of the TFT 1 is set at the second level RS during the period between timings T2 and T3.
Only when the output signal OUT2 of (2) is at a high level, it goes to a high level (almost Vdd). Since the power supply voltage Vdd is always supplied to the drain of the TFT 1, the drain voltage is always the power supply voltage Vdd. TFT
When charge is accumulated in the node A3 at the timing T2, the source voltage of 1 becomes a voltage level lower than Vdd by the threshold voltage. When the clock signal CK1 is at the high level during the period between the timings T3 and T4, the clock signal CK1 has a level of about twice the power supply voltage Vdd due to the bootstrap effect described above. The fourth stage RS at timing T4
After the output voltage of (4) becomes high level, it becomes low level again.

As described above, the gate voltage of the TFT 1 of the k-th stage RS (k) in one scan of the shift register is always low except when at least the start signal Dst or the output signal OUTk-1 of the preceding stage is once at the high level. Since the gate voltage of each TFT 1 is relatively positive with respect to the lower one of the drain voltage and the source voltage, the clock signal CK1,
CK2, start signal Dst and end signal Dend are
When the high-level voltage is equal to the power supply voltage Vdd and the low-level voltage is equal to the reference voltage Vss, only the period during which the clock signal CK1 or CK2 is once at the high level.

The high-level voltages of the clock signals CK1 and CK2, the start signal Dst and the end signal Dend are attenuated by the parasitic capacitance between the gate and the drain of the TFT1, for example, the voltage of the node A3 during the period from timing T3 to T4. When the potential is lower than the potential, the gate voltage of the TFT 1 is always lower than the source voltage and the drain voltage. Therefore, the shift of the gate threshold voltage of the TFT 1 of the k-th stage RS (k) in the positive direction can be suppressed.

Next, the operation of the entire digital still camera according to this embodiment will be described. This digital still camera has two modes, one in which it operates in a shooting mode and the other in which it operates in a playback mode. These operation modes are determined according to the operation of the mode setting key 12a. Hereinafter, the operation of the digital still camera will be described separately for the shooting mode and the reproduction mode.

In the case of the photographing mode, electric charges are accumulated in each pixel of the CCD image pickup device 20 according to the light image formed by the image pickup lens 02a. CCD imaging device 20
According to an instruction from the CPU 22, the charge stored in each pixel is sequentially read and supplied to the A / D converter 21.
The A / D converter 21 converts this into digital data,
It is temporarily stored in a predetermined area of the RAM 24.

Next, the CPU 22 performs a predetermined process on the data of the photographed image temporarily stored in a predetermined area of the RAM 24, and generates image data corresponding to the image to be displayed on the display unit 10. Then, the generated image data is expanded in the VRAM area of the RAM 24. By sequentially repeating this operation, the imaging lens 0 is stored in the VRAM area.
The image data corresponding to the image captured in 2a is always expanded.

Here, when the user operates the shutter key 12b, an instruction from the CPU 22 causes the RAM 24 to operate.
The data of the photographed image stored in the VRAM area and the image data to be developed in the VRAM area are fixed. That is, the image captured by the imaging lens 02a at the timing of operating the shutter key 12b does not change the image stored in a predetermined area of the RAM 24, and the imaging lens 02a captures the image at the timing of operating the shutter key 12b. That is, the image data corresponding to the image which has been displayed is expanded in the VRAM area.

Next, the CPU 22 executes the compression / decompression circuit 25.
To compress the image data stored in a predetermined area of the RAM 24. Then, the compressed image data is transferred from the compression / expansion circuit 25 to the image memory 26 and stored therein. Then, for example, after a predetermined time has elapsed after operating the shutter key 12b, or when the user performs a predetermined operation on the key input unit 12, the CPU 22
Stores the image data read from the CCD imaging device 20 via the A / D converter 21 and returns the operation of the digital still camera so that the corresponding image data is expanded in the VRAM area.

In the case of the reproduction mode, the user
By operating the "+" key 12c or the "-" key 12d,
The image data to be displayed on the display unit 10 is selected from the image data stored in the image memory 26. The selected image data is transferred from the image memory 26 to the compression / decompression circuit 25 and decompressed. The CPU 22 performs a predetermined process on the decompressed image data, and
Generates the image data to be displayed on the
Expand to M area.

The display unit 10 reads out the image data expanded in the VRAM area of the RAM 24 and displays the corresponding image in both the photographing mode and the reproduction mode. Hereinafter, an operation for displaying an image on the display unit 10 will be described.

The liquid crystal controller 50 of the display unit 10
According to the control signal from the PU 22, the VRA
The image data developed in the M area is read out in a predetermined order.
The order of reading is controlled to be different between a case where an image substantially the same as the image captured by the CCD imaging device 20 is displayed and a case where a mirror image of the image captured by the CCD imaging device 20 is displayed.

The liquid crystal controller 50 controls the control signal group Dc.
In accordance with nt, the image data read from the VRAM area is taken into the drain driver 53 as display data data. When the drain driver 53 captures the display data data for one line, the liquid crystal controller 50
And outputs a voltage signal corresponding to the control signal group Dcnt to each drain line DL of the liquid crystal display element 51.

On the other hand, the liquid crystal controller 50 operates the gate driver 5 according to the control signal group Gcnt as described above.
2 is sequentially shifted, and the gate line GL of the liquid crystal display element 51 is sequentially selected. That is, the gate driver 52 selects the gate line GL corresponding to the display data data output from the drain driver 53.

The potential of the gate line GL selected by the gate driver 52 goes high according to the output signal, whereby the TFT 61 connected to the gate line GL is turned on. Then, each drain line DL is supplied from the drain driver 53 via the turned-on TFT 61.
Is written to the pixel capacitor 62.

Then, the alignment state of the liquid crystal is changed by the voltage signal written to the pixel capacitor 62, and the transmitted light amount in the pixel is changed. Such a selection operation is sequentially performed on the first to n-th gate lines GL, and each drain line DL of the voltage signal corresponding to the display data data.
By writing a voltage signal to each pixel capacitor 62 in response to the output, the image data developed in the VRAM area, that is, the image captured by the CCD imaging device 20 or the image selected from the image memory 26 is displayed on the display unit. 10 will be displayed.

As described above, in this embodiment, the shift register constituting the gate driver 52 has a period in which the gate voltage of the TFT 1 in each stage is relatively positive with respect to the drain and source voltages. short. TF
Due to its characteristics, when the gate voltage becomes relatively positive with respect to the drain and source voltages, the threshold characteristic tends to shift more than positive, but the gate voltage becomes relatively negative with respect to the drain and source voltages. Even so, the threshold characteristics are not likely to shift negatively.

In other words, in the shift register of this embodiment, even if the shift register is used for a long time, the characteristics of the TFT 1 are less likely to change than those of the conventional shift register.
It is unlikely that charges cannot be stored in the nodes A1 to An without turning on at the timing when the node 1 should be turned on. For this reason, it operates stably for a long time and has high durability.

Further, the failure of the display section 10 in which this shift register is applied as the gate driver 52 is naturally reduced, and the durability of the digital still camera including the shift register is also increased.

In this embodiment, the gate driver 52 applied to the liquid crystal display device constituting the display unit 10
Has a configuration shown in FIG. 4 and is configured by a shift register that operates according to a timing chart shown in FIG. 5 by a control signal output from the liquid crystal controller 50. However, the shift register applicable as the gate driver 52 is not limited to this.

FIG. 6 is a diagram showing a circuit configuration of another shift register applicable as the gate driver 52. Explaining the difference from the shift register shown in FIG.
Odd-numbered stages RS (1), R
S (3),..., RS (n-1)
K1 is an even-numbered stage RS (2), RS (4),.
In S (n), the clock signal CK2 is supplied. The clock signals CK1 and CK2, the start signal Dst and the end signal Dend all have a high-level voltage equal to the power supply voltage Vdd and a low-level voltage equal to the reference voltage Vss.

Next, the operation of the shift register of FIG. 6 will be described with reference to the timing chart of FIG. 7 while referring to differences from the shift register of FIG. Timing T0 to T1
When the start signal Dst becomes high level and the TFT1 of the first stage RS (1) is turned on during the period, the clock signal CK2 supplied to the drain of this TFT1 becomes high level, and the electric charge is stored in the node A1. Is accumulated.

In the period between timings T1 and T2, 1
When the output signal OUT1 of the second stage RS (1) goes high and the TFT1 of the second stage RS (2) turns on, the clock signal CK1 supplied to the drain of this TFT1 goes high, Electric charges are accumulated in the node A2. Similarly, in the period from timing Tn-1 to Tn, the output signal OUTn-1 of the (n-1) th stage RS (n-1) becomes high level, and the nth stage RS
When the TFT1 of (n) turns on, the clock signal CK2 supplied to the drain of the TFT1 becomes high level, and charges are accumulated at the node An.

In this shift register, as shown in the lower three stages of FIG.
The change in the potential levels of the gate, drain and source of T1 will be described. Only when the output signal OUT2 of the second stage RS (2) is at the high level during the period from the timing T2 to the timing T3, the high level (almost Vdd). ). The drain voltage goes high (substantially Vdd) only when the clock signal CK2 is high. When charge is accumulated at the node A3 at the timing T2, the source voltage becomes a voltage level lower than Vdd by the threshold voltage, and the clock signal CK is generated during the period from the timing T3 to T4.
While 1 is at the high level, the level is about twice the power supply voltage Vdd.

If the period during which the drain voltage of the TFT 1 is higher than the gate voltage is sufficiently long, the gate threshold voltage shifts to the negative side, and the leakage current at the time of OFF causes the node A to turn off.
In this shift register, the period during which the drain voltage of the TFT 1 is at a high level is shorter than that in the shift register shown in FIG. That is, the period in which the potential difference between the gate and the drain and between the source and the drain of the TFT 1 is short.
Therefore, the voltage stress applied to the TFT 1 is smaller than that of the shift register shown in FIG.
Since the element characteristics of the TFT 1 are hardly deteriorated, the TFT 1 is hardly broken down even after long-term use.

FIG. 8 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 52. In FIG. Explaining the difference from the shift register shown in FIG. 4, the voltage signal V1 is supplied. Although the high level of the voltage signal V1 is lower than the level of the power supply voltage Vdd,
The level is such that enough charges can be accumulated in the nodes A1 to An enough to turn on the TFT2 and the TFT5. On the other hand, the low level is the same as the reference voltage Vss. The clock signals CK1 and CK2, the start signal Dst and the end signal Dend all have a high-level voltage equal to the power supply voltage Vdd and a low-level voltage equal to the reference voltage Vss.

Next, the operation of the shift register shown in FIG. 8 will be described with reference to a timing chart shown in FIG. 9 while referring to differences from the shift register shown in FIG. In the operation according to the timing chart, the voltage signal V1 is always maintained at the high level.

During the period from timing T0 to T1, the start signal Dst goes high and the first stage RS
When the TFT1 of (1) is turned on, the voltage signal V1 is output from the drain of the TFT1 to the source, and the electric charge is accumulated at the node A1. At this time, the potential of the node A1 is lower than the voltage signal V1 lower than the power supply voltage Vdd by the threshold voltage of the TFT1, but is lower than the voltage signal V1.
Is higher than the threshold voltage. Thereby, the first stage R
In S (1), TFT2 and TFT5 are turned on, and TFT3 is turned off. Then, when the clock signal CK1 rises at the timing T1, the level of the output signal OUT1 becomes high.

Similarly, at timings Tn-1 to Tn-1
During the period of n, the output signal OUTn-1 of the (n-1) th stage RS (n-1) becomes high level, and the nth stage RS (n-1)
The TFT 1 of (n) turns on. Thereby, the node An
Is stored in the n-th stage RS so that the potential becomes lower than the voltage signal V1 by the threshold voltage of the TFT1.
(N) TFT2 and TFT5 are turned on, and TFT3 is turned off. Then, when the clock signal CK2 rises at the timing Tn, the level of the output signal OUTn becomes high.

In this shift register, one TF
How the potentials of the gate, drain, and source of T1 change will be described with reference to the lower three stages in FIG. 9 and the TFT1 in the third stage RS (3) as an example. As shown in the figure, the gate voltage of the TFT 1 is controlled at timings T2 to T2.
Only when the output signal OUT2 of the second stage RS (2) is at the high level during the period of 3, the power supply voltage Vdd is almost
Level.

The drain voltage of the TFT 1 is equal to the voltage signal V 1
, That is, a level slightly lower than the power supply voltage Vdd. When charge is accumulated in the node A3 at the timing T2, the source voltage of the TFT1 becomes a voltage level lower than the voltage signal V1 by the threshold voltage, and the clock signal CK1 is at the high level during the period from the timing T3 to T4. Sometimes, the power supply voltage V
The level becomes higher by dd.

That is, although the source voltage of the TFT 1 at this time is slightly higher than the power supply voltage Vdd, it is at a level sufficiently lower than twice the power supply voltage Vdd. Therefore, in the TFT 1, the potential difference between the gate and the drain when the gate is at the off level is smaller, and the potential difference between the gate and the source when the source voltage is the maximum is smaller. Similarly, the gate voltage of the TFT 2, the gate voltage of the TFT 5, and the drain voltage of the TFT 6 are not as large as those of the shift register of FIG. Therefore, TFT1,
No large voltage stress is applied to 2, 5, and 6,
Since the element characteristics of the TFTs 1, 2, 5, and 6 are less likely to be degraded than the shift register of FIG. 4, the TFTs are less likely to fail even after long-term use.

The shift register of FIG. 8 can also operate according to the timing chart of FIG. In the operation according to this timing chart, the voltage signal V1
Changes to a high level only while either the clock signal CK1 or CK2 is at a high level.
The difference between the operation according to the timing chart and the operation according to the timing chart of FIG. 9 will be described.

Only when the start signal Dst is at the high level during the period from the timing T0 to T1, the voltage signal V1 is at the high level and the electric charge is stored in the node A1. Only when the output signal OUT1 is at the high level during the period between the timings T1 and T2, the voltage signal V1 is at the high level, and charges are stored in the node A2. Similarly, during the period from timing Tn-1 to Tn, only when the output signal OUTn-1 is at the high level,
The voltage signal V1 becomes high level, and charges are stored in the node An.

In the case of this operation, the lower three rows in FIG.
As shown in the example of the first stage RS (1), the time during which a potential difference occurs between the gate and the drain and between the source and the drain of the TFT 1 is shorter than that according to the operation of FIG.
Voltage stress applied to FT1 is small. Therefore, FIG.
Since the element characteristics of the TFT 1 are less likely to deteriorate than the case of the operation described above, the TFT 1 is less likely to fail even after long-term use.

FIG. 11 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 52. In FIG. Explaining the difference from the shift register shown in FIG. 6, the drain of the TFT 1 has an odd-numbered stage RS
In (1), RS (3),..., RS (n−1), the clock signal CK1 ′ is changed to the even-numbered stages RS (2), RS (2)
(4),..., RS (n), the clock signal CK2 ′
Are supplied, respectively. Although the high level of the clock signals CK1 ′ and CK2 ′ is lower than the level of the power supply voltage Vdd, the TFTs 2 and TFTs are connected to the nodes A1 to An.
This is a level at which enough charges can be accumulated to turn on the transistor 5.

Next, the operation of the shift register of FIG. 11 will be described with reference to the timing chart of FIG. Timing T0
When the start signal Dst goes to a high level from T1 to T1, the clock signal CK2 'goes to a high level, and charges are stored in the node A1. Timing T1
When the output signal OUT1 goes high at T2, the clock signal CK1 'goes high, and charges are stored in the node A2. Similarly, when the output signal OUTn-1 goes to a high level at timings Tn-1 to Tn, the clock signal CK1 'goes to a high level, and charges are accumulated in the node An.

As shown by way of example of the TFT 1 in the third stage RS (3) in the lower three stages of FIG. 12, the source voltage of each TFT 1 is slightly higher than the power supply voltage Vdd even when it reaches the maximum level. However, it is at a level sufficiently lower than twice the power supply voltage Vdd. Similarly, TFT
The gate voltage of the TFT 2, the gate voltage of the TFT 5, and the drain voltage of the TFT 6 are not as large as those of the shift register of FIG. Therefore, a large voltage stress is not applied to the TFTs 1, 2, 5, and 6. Further, compared with the shift register of FIG. 8, the period in which the potential difference is generated between the gate and the drain and between the source and the drain of the TFT 1 is shorter. Compared with the shift register of FIGS.
Since the device characteristics of 2, 5, and 6 are hardly deteriorated, the device is hardly broken down even after long-term use.

[Second Embodiment] A digital still camera according to this embodiment is almost the same as that shown in the first embodiment, but has an angle sensor 40 shown by a dotted line in FIG. Is different. The shift register applied as the gate driver 52 of the display unit 10 is different from that of the first embodiment in that it can shift the output signal in both the forward and reverse directions. In accordance with this, the signals output from the liquid crystal controller 50 as the control signal group Gcnt are slightly different.

The angle sensor 40 includes a lens unit 02
Is detected with respect to the camera body 01. The detection signal of the angle sensor 40 is input to the CPU 22 and the CPU 2
In accordance with the detection signal, the control unit 2 sends to the display unit 10 a control signal indicating whether the display scanning direction (shift operation direction of the shift register applied as the gate driver 52) is forward or reverse.

FIG. 13 is a diagram showing a circuit configuration of a shift register applied as a gate driver 52 in this embodiment. This shift register also has n stages RS equal to the number of gate lines GL of the liquid crystal display element 51.
(1) -RS (n), and the stages RS (1) -RS
Each of (n) is composed of six TFTs 1 to 6, as in the shift register shown in FIG. Here, the TFTs 1 to 6 are all n-channel type field effect transistors.

The shift register shown in FIG. 13 will be described with respect to the differences from the shift register shown in FIG.
A voltage signal V1 is supplied to the drains of the TFTs (1) to RS (n) instead of the power supply voltage Vdd. Each stage R
Instead of the reference voltage Vss, a voltage signal V2 is supplied to the sources of the TFTs 6 of S (1) to RS (n).

A control signal D1 is supplied to the gate of the TFT1 of the first stage RS (1) instead of the start signal Dst. The control signal D2 is supplied to the gate of the TFT 6 of the n-th stage RS (n) instead of the end signal Dend. The voltage signals V1 and V2 have different levels between the forward operation and the reverse operation, and the control signals D1 and D2
Is different in the timing of the high level between the forward operation and the reverse operation.

The operation of the digital still camera according to this embodiment will be described below. First, the operation of the shift register forming the gate driver 52 will be described with reference to the timing charts of FIGS. 14 and 15, which are divided into a case of performing a forward shift and a case of performing a reverse shift.

In these timing charts, clock signals CK1 and CK2 and voltage signals V1 and V
2. Both the high levels of the control signals D1 and D2 are equal to the power supply voltage Vdd. On the other hand, the low level of each of these signals is equal to the reference voltage Vss. During the 1T period,
This is one horizontal period in the display unit 10.

Before the shift operation is started according to these timing charts (before T0), all of the output signals OUT1 to OUTn are at the low level. Further, in any of the stages RS (1) to RS (n), no electric charge is accumulated in the nodes A1 to An, and the TF
T2 and TFT5 are on, and TFT3 is off.

FIG. 14 is a timing chart showing the operation when shifting in the forward direction. In this case, the level of voltage signal V1 is maintained at a high level equal to power supply voltage Vdd, and the level of voltage signal V2 is maintained at a low level equal to reference voltage Vss. Also, the control signal D1
Is at a high level for a certain period between timings T0 and T1. The control signal D2 goes high for a certain period from the timing Tn to the timing Tn + 1.

That is, in the first embodiment, if the control signal D1 is replaced with the start signal Dst and the control signal D2 is replaced with the end signal Dend, the operation of the shift register described with reference to the timing chart of FIG. Become. Accordingly, the output signal O is output for a certain period within the period of 1T.
UT1 to OUTn sequentially shift to the high level.

FIG. 15 is a timing chart showing the operation in the case of shifting in the reverse direction. In this case, the level of the voltage signal V1 is maintained at a low level equal to the reference voltage Vss, and the level of the voltage signal V2 is maintained at the reference voltage Vss.
dd is maintained at a high level. Further, the control signal D2 is at a high level for a certain period between the timings T0 and T1. The control signal D1 is at a high level for a certain period from timing Tn to timing Tn + 1.

During the timing T0 to T1, the control signal D2
Becomes high level, the TFT of the n-th stage RS (n)
6 turns on, and a high-level voltage signal V2 is output from the source to the drain of the TFT6. As a result, charge is accumulated at the node An of the n-th stage RS (n), and the TFT 2
And TFT5 is turned on, and TFT3 is turned off. During this period, the TFT2 of the n-th stage RS (n) is turned on, but since the clock signal CK2 is at the low level, the output signal O
The level of UT2 remains at the low level.

Next, when the clock signal CK2 changes to the high level at the timing T1, this is output from the drain of the TFT2 of the n-th stage RS (n) to the source, and the level of the output signal OUTn changes to the high level. I do. Thereafter, the clock signal C is output until the timing T2.
When K2 falls, the output signal OUTn goes low.

In the period between timings T1 and T2,
The output signal O of the n-th stage RS (n) that has become high level
According to UTn, the TFT of the (n−1) th stage RS (n−1)
6 turns on. As a result, the (n−1) th stage RS (n−
1) The high-level voltage signal V from the drain of the TFT 6
2 is output, the potential of the node An-1 becomes high level, and the TFT2 of the (n-1) th stage RS (n-1)
And TFT5 is turned on, and TFT3 is turned off.

Next, when the clock signal CK1 changes to the high level at the timing T2, this is output from the drain of the TFT2 of the (n-1) th stage RS (n-1) to the source, and the output signal OUTn-1 is output. The level changes to high level. Thereby, the n-th stage RS
The (n) TFT 1 is turned on, the electric charge accumulated at the node An is released, and the TFTs 2 and T of the n-th stage RS (n) are turned off.
FT5 turns off and TFT3 turns on. Thereafter, when the clock signal CK1 falls before the timing T3, the output signal OUTn-1 becomes low level.

In the period between timings T1 and T2,
The output signal OUTn−1 of the (n−1) th stage RS (n−1) that has become high level causes the (n−2) th stage RS (n−
2) The TFT 6 is turned on. As a result, a high-level voltage signal V2 is output from the drain of the TFT 6 of the (n−2) th stage RS (n−2), and the potential of the node An−2 becomes a high level. Step RS (n-
2) TFT2 and TFT5 are turned on, and TFT3 is turned off.

Hereinafter, the stage RS (n-
2), RS (n-3),... Repeat the same operation as above for each 1T period in the direction of the previous stage, so that the output signals OUTn-2, OUTn-3,. The level changes to a high level at predetermined intervals within the period. During the period from timing Tn-1 to Tn, the output signal OU of the second stage RS (2) which has become high level
By T2, the TFT 6 of the first stage RS (1) is turned on. As a result, charges are accumulated in the node A1 of the first stage RS (1), and the TFT2 and the TFT5 are turned on, and the TF
T3 turns off.

Next, when the clock signal CK1 changes to high level at the timing Tn, this is output from the drain of the TFT2 of the first stage RS (1) to the source, and the level of the output signal OUT1 changes to high level. I do. Thereafter, when the clock signal CK1 falls before the timing Tn + 1, the output signal OUT1 goes low.

At the timing Tn + 1, the level of the control signal D1 changes to the high level. As a result, when the TFT1 of the first stage RS (1) is turned on, the electric charge accumulated in the node A1 is released, and the TFT2 and the TFT5 of the second stage RS (2) are turned off.
FT3 turns on. Until the control signal D2 changes to the high level, in any of the stages RS (1) to RS (n), no electric charge is stored in the nodes A1 to An, and the TFT2 and the TFT5 are turned on, and the TFT3 is turned on. Is kept off.

Next, the operation of the entire digital still camera according to this embodiment will be described. The operation is the same as that of the first embodiment except for the following points. The difference from the first embodiment will be described.
Detects the angle of the lens unit 02 with respect to the camera body 01, and inputs the detection signal to the CPU 22.
Then, the CPU 22 supplies a control signal corresponding to the input detection signal to the display unit 10.

In the display unit 10, the liquid crystal controller 50
However, when a control signal indicating that the imaging lens 02a of the lens unit unit 02 is on the opposite side to the display unit 10 is supplied from the CPU 22, the gate driver 52 transmits the control signal group Gcnt to the gate driver 52 so as to perform a forward shift. The supplied control signals D1, D2 and the voltage signals V1, V2 are switched. When a control signal indicating that the imaging lens 02a is on the display unit 10 side is supplied from the CPU 22, the control signals D1 and D2 and the control signals D1 and D2 supplied as the control signal group Gcnt to the gate driver 52 are shifted in the reverse direction. The voltage signals V1 and V2 are switched.

Hereinafter, the operation of capturing an image with the digital still camera according to this embodiment, particularly the relationship between the direction of the lens unit 02 and the image displayed on the display unit 10, will be described with a specific example. I do. Here, it is assumed that the mode setting key 12a has been set to the photographing mode, and the CPU 22
Is the scanning direction of the liquid crystal display element 51 (the gate driver 52
It is assumed that a control signal for changing the shift direction (shift direction of the shift register) is transmitted to the display unit 10.

First, as shown in FIG. 16A, the operation of the digital still camera for photographing an image of an object in front of the photographer will be described. in this case,
The photographer places the imaging lens 02a of the lens unit 02 on the same side as the display 10 of the camera body 01,
That is, the image is taken by rotating the lens unit 02 so that the lens unit 02 comes to a position substantially at 0 ° with respect to the camera body 01. At this time, the scanning direction of the liquid crystal display element 51 by the gate driver 52 is the forward direction.

In this state, as shown in FIG. 16A, the pixels P (1,1) to P (n,
The arrangement of m) matches the original upper, lower, left, and right directions of the liquid crystal display element 51. The vertical and horizontal directions of the lens unit 02 coincide with the original vertical and horizontal directions of the image. At this time, according to the image formed by the imaging lens 02a, horizontal scanning is performed from left to right in FIG. 16A, and vertical scanning is performed from top to bottom. A signal is output and the corresponding image data is stored in RAM
It is expanded to 24 VRAM areas.

On the other hand, in the display section 10, FIG.
In accordance with the direction of the horizontal arrow shown in (b), the developed image data is captured and output to the first to m-th drain lines DL of the liquid crystal display element 51 within one horizontal period. In addition, the gate driver 52 includes the liquid crystal display element 5.
The gate lines GL are sequentially selected in the order of 1st to 1st (from top to bottom in FIG. 16B).

As a result, the image data corresponding to the signal output from the pixel originally above the CCD image pickup device 20 is transferred to the pixel above the liquid crystal display element 51 (FIG. 1).
6 (b), image data corresponding to a signal output from a pixel originally on the left in the CCD image pickup device 20 is displayed on the original left pixel of the liquid crystal display element 51 (FIG. 16).
16 (b) is displayed on the left side of FIG.
As shown in FIG. 7, an image in the same direction as the captured image is displayed.

Next, as shown in FIG. 17A, the subject is displayed on the display unit 10 such as the photographer himself.
The operation of the digital still camera when shooting an image when the camera is on the side will be described. In this case, the photographer attaches the imaging lens 02a of the lens unit 02 to the camera body 0.
1 so as to be on the opposite side of the display unit 10, that is, the lens unit 02 is approximately 18
The image is taken by rotating it so that it comes to the position of 0 °. At this time, the scanning direction of the liquid crystal display element 51 by the gate driver 52 is reversed.

In this state, as shown in FIG. 17A, the pixels P (1,1) to P (n,
The arrangement of m) is opposite to the original upper, lower, left and right directions of the liquid crystal display element 51. In addition, the up, down, left, and right directions of the lens unit 02 coincide with the up, down, left, and right directions of the image. At this time, in accordance with the image formed by the imaging lens 02a, horizontal scanning is performed from right to left in FIG. 17A, and vertical scanning is performed from top to bottom, and an electric signal is output from each pixel of the CCD imaging device 20. The output and the corresponding image data are expanded in the VRAM area of the RAM 24.

On the other hand, in the display section 10, FIG.
In accordance with the direction of the horizontal arrow shown in (b), the developed image data is captured and output to the first to m-th drain lines DL of the liquid crystal display element 51 within one horizontal period. In addition, the gate driver 52 includes the liquid crystal display element 5.
The gate lines GL are sequentially selected in the order from the first to the n-th (in FIG. 17B, from bottom to top).

As a result, the image data corresponding to the signal output from the pixel originally above the CCD image pickup device 20 is transferred to the pixel below the liquid crystal display element 51 (see FIG. 1).
7 (b), the image data corresponding to the signal output from the pixel originally left in the CCD image pickup device 20 is converted to the original right pixel of the liquid crystal display element 51 (FIG. 17).
(B) to the right of FIG. 17 (b).
As shown in FIG. 7, a mirror image of the captured image is displayed.

As described above, in the shift register applied as the gate driver 52 of the digital still camera according to the present embodiment, the TFT 1 stores charges in the nodes A1 to An when operating in the forward direction. , And the TFT 6 functions as a transistor for releasing the accumulated charges. On the other hand, when operating in the reverse direction, the TFT 1 functions as a transistor for discharging the charges stored in the nodes A1 to An, and the TFT 6 functions as a transistor for storing the charges.

Since the TFTs 1 and 6 can be provided with such a function, the number of TFTs 1 to 6 constituting each stage RS (1) to RS (n) is determined by the gate driver 52 in the first embodiment. Can be the same as the shift register applied as For this reason, the area is not so large as compared with the first embodiment, and even if the gate driver 52 is formed on the same substrate as the liquid crystal display element 51, the relative area of the image display area is small. No.

Further, by applying a shift register capable of performing a bidirectional shift operation in the forward direction and the reverse direction to the gate driver 52, the liquid crystal controllers 50 to
By simply controlling the control signal group Gcnt supplied to the gate driver 52, a mirror image of the image captured by the CCD imaging device 20 can be displayed on the display unit 10. That is, the digital still camera according to this embodiment can display a mirror image on the display unit 10 without performing complicated control for reading image data developed in the VRAM area.

In this embodiment, the gate driver 52 has the configuration shown in FIG.
14 or FIG.
And a shift register that operates according to the timing chart shown in FIG. However, in this embodiment, the method of driving the shift register applicable as the gate driver 52 is not limited to this, and the configuration of the shift register is not limited to this.

FIGS. 18 and 19 are timing charts showing another operation of the shift register shown in FIG. When operating in the forward direction, as shown in FIG.
2 is maintained at a low level as in the case of FIG. 14, but the voltage signal V1 is the clock signal CK1 or C
It goes high only when K2 is high. For example, during the period from timing T0 to T1, when the control signal D1 goes high, the clock signal C
K1 is also at a high level, and T1 of the first stage RS (1)
FT1 turns on, and charge is stored in node A1.

On the other hand, when the operation in the reverse direction is performed, as shown in FIG. 19, the voltage signal V1 is maintained at the low level as in the case of FIG. 15, but the voltage signal V2 is changed to the clock signal CK1 or the clock signal CK1. It goes high only when CK2 is high. For example, timings T0 to T
During the period 1, when the control signal D2 goes high, the clock signal CK2 also goes high, turning on the TFT1 of the n-th stage RS (n) and accumulating charge at the node An.

In these cases, the time during which a potential difference occurs between the gate and the drain and between the source and the drain of each of the TFT 1 and the TFT 6 is shorter than when the operation is performed according to the timing charts of FIGS. As a result, the voltage stress applied to the TFT 1 and the TFT 6 can be reduced, and the characteristics are not easily deteriorated.

FIG. 20 is a diagram showing a circuit configuration of another shift register applicable as the gate driver 52 in this embodiment. The difference from the shift register shown in FIG.
(1), RS (3), ..., RS (n-1), T
The voltage signal V2 is supplied to the drain of the FT1, and the voltage signal V1 is supplied to the source of the TFT6. Even-numbered stage R
In S (2), RS (4),..., RS (n), TF
The voltage signal V1 is supplied to the drain of T1, and the voltage signal V2 is supplied to the source of the TFT6.

Next, the operation of the shift register of FIG. 20 will be described with reference to the timing charts of FIGS. When a forward operation is performed, timings T0 to T
In the period of 1, when the control signal D1 becomes high level, the TFT1 of the first stage RS (1) is turned on, and charge is accumulated in the node A1 by the high level voltage signal V2. When the clock signal CK1 goes high during the period between timings T1 and T2, the first stage RS
The output signal OUT1 of (1) becomes high level. As a result, the TFT1 of the second stage RS (2) is turned on, and charges are accumulated in the node A2 by the high-level voltage signal V1.

When the clock signal CK2 goes high during the next period T2 to T3, the output signal OUT2 of the second stage RS (2) goes high. As a result, the TFT1 of the third stage RS (3) is turned on, and the voltage of the node A is increased by the high-level voltage signal V2.
3 accumulates electric charges. In addition, the output signal OUT2 that has become high level causes the TFT6 of the first stage RS (1)
Turns on. At this time, since the voltage signal V1 is at the low level, the charge stored in the node A1 is released.

Similarly, the timings Tn to Tn +
When the clock signal CK2 goes high during the period of 1, the output signal OUTn of the n-th stage RS (n) goes high. Thereby, the (n-1) th stage RS (n
Since the TFT 6 of -1) is turned on and the voltage signal V1 is at the low level, the charge accumulated at the node An-1 is released. Then, at timing Tn + 1, the control signal D2 goes high, and the n-th stage R
The S (n) TFT 6 is turned on. At this time, the voltage signal V
Since 2 is at a low level, the charge stored in the node An is released.

On the other hand, in the case of performing the reverse operation, when the control signal D2 goes high during the period from timing T0 to T1, the TFT 6 of the n-th stage RS (n) turns on,
Charges are stored in the node An by the voltage signal V2 that has become high level. When the clock signal CK2 goes high during the period from the timing T1 to T2, the output signal OUTn of the n-th stage RS (n) goes high. Thereby, the TF of the (n−1) th stage RS (n−1)
T6 is turned on, and charge is accumulated at the node An-1 by the high-level voltage signal V2.

When the clock signal CK1 goes to the high level during the period between the next timings T2 and T3, n-1
The output signal OUTn-1 of the second stage RS (n-1) becomes high level. Thereby, T of the n-th stage RS (n)
Since the FT1 is turned on and the voltage signal V1 is at the low level, the charge accumulated at the node An is released.

Similarly, the timings Tn to Tn +
In a period of 1, when the clock signal CK1 goes high, the output signal OUT1 of the first stage RS (1) goes high. As a result, the TFT1 of the second stage RS (2) is turned on and the voltage signal V1 is at the low level, so that the charges accumulated at the node A2 are discharged. Then, at timing Tn + 1, the control signal D
1 becomes high level, the TF of the first stage RS (1)
T1 turns on. At this time, since the voltage signal V2 is at the low level, the charge stored in the node A1 is released.

FIG. 23 is a diagram showing a circuit configuration of another shift register applicable as the gate driver 52 in this embodiment. The difference from the shift register shown in FIG.
(1), RS (3), ..., RS (n-1), T
The voltage signal V2 is supplied to the drain of the FT1, and the voltage signal V4 is supplied to the source of the TFT6. Even-numbered stage R
In S (2), RS (4),..., RS (n), TF
The voltage signal V1 is supplied to the drain of T1, and the voltage signal V3 is supplied to the source of the TFT6.

Next, the operation of the shift register of FIG. 23 will be described with reference to the timing charts of FIGS. This shift register operates by replacing the voltage signal supplied to the source of the TFT 6 with V4 in the odd-numbered stages RS (1), RS (3),. 2), RS (4), ..., RS
If the voltage signal supplied to the source of the TFT 6 in (n) is replaced with V3, it is almost the same as that of the shift register in FIG.

However, in the case of performing the forward operation shown in FIG. 24, the source voltages (voltage signals V3 and V4) of the TFTs 6 of the respective stages RS (1) to RS (n) are maintained at a low level. In the case of performing the reverse operation shown in FIG. 25, the drain voltages (voltage signals V1 and V2) of the TFTs 1 of the respective stages RS (1) to RS (n) are maintained at a low level. That is, for the TFT 1 in the forward operation and for the TFT 6 in the reverse operation, the time during which a potential difference occurs between the gate and the drain and between the source and the drain is short. Therefore, the voltage stress applied to the TFT 1 and the TFT 6 can be made smaller than that of the shift register shown in FIG. .

In each shift register shown in this embodiment, the high level of the voltage signals V1 to V4 supplied to the drain of the TFT1 or the source of the TFT6 is
The charge stored in the nodes A1 to An causes the TFT 2
Alternatively, the voltage may be lower than the power supply voltage Vdd as long as the voltage level is sufficient to turn on the TFT 5. This allows
TFT1 and TFT6, and also TFT2 and TFT5
Can be reduced as compared with the case where the shift register is operated according to each of the timing charts described above.

[Other Embodiments] The present invention relates to the first,
The present invention is not limited to the second embodiment, and various modifications and applications can be made. Hereinafter, other embodiments to which the present invention is applied will be described.

In the second embodiment, whether the shift register applied as the gate driver 52 performs the forward shift operation or the reverse shift operation is determined by the lens unit 02 detected by the angle sensor 40. The setting is automatically made according to the angle with respect to the camera body 01. However, whether to perform the forward operation or the backward operation may be selected by the user operating a key of the key input unit 12.

In the first and second embodiments, the shift register shown in FIGS. 4, 6, 8, 11, 13, 20, and 23 is used as the gate driver 52 of the liquid crystal display device. The description has been given of an example in which the method is applied. However, display devices other than the liquid crystal display device, for example, a plasma display, a field emission display,
It can also be used as a driver for selecting a line such as an organic EL display device. Further, these shift registers can also be used as a driver for driving an image pickup device in which image pickup pixels are arranged in a predetermined arrangement (for example, a matrix arrangement) vertically and horizontally.

FIG. 26 is a block diagram showing a configuration of an image pickup apparatus having an image pickup element by applying a double gate transistor as a photo sensor. This imaging device is used, for example, as a fingerprint sensor.
It comprises a controller 70, an image sensor 71, a top gate driver 72, a bottom gate driver 73, and a drain driver 74.

The image sensor 71 is composed of a plurality of double gate transistors 81 arranged in a matrix.
Top gate electrode 91 of double gate transistor 81
Represents the top gate line TGL and the bottom gate electrode 92
Is connected to the bottom gate line BGL, the drain electrode 93 is connected to the drain line DL, and the source electrode 94 is connected to the ground line GrL. A backlight that emits light in a wavelength range that excites the semiconductor layer of the double-gate transistor 81 is mounted below the image sensor 71.

In the double gate transistor 81 constituting the image sensor 71, the voltage applied to the top gate electrode 91 is +25 (V) and the voltage applied to the bottom gate electrode 92 is 0 (V). The holes accumulated in the gate insulating film made of silicon nitride and the semiconductor layer disposed between the top gate electrode 91 and the semiconductor layer are discharged and reset. Double gate transistor 8
1 is 0 (V) between the source electrode 94 and the drain electrode 93.
And the voltage applied to the top gate electrode 91 is −1
At 5 (V), the voltage applied to the bottom gate electrode 92 becomes 0 (V), and the holes of the hole-electron pairs generated by the incidence of light on the semiconductor layer are changed to the semiconductor layer and the gate. The photo-sensing state is accumulated in the insulating film.
The amount of holes accumulated during this predetermined period depends on the amount of light.

In the photo-sensing state, the backlight irradiates light to the double gate transistor 81. However, the bottom gate electrode 92 located below the semiconductor layer of the double gate transistor 81 shields the light, so that the semiconductor layer has sufficient light. No carrier is generated. At this time, when a finger is placed on the insulating film above the double gate transistor 81, the semiconductor layer of the double gate transistor 81 immediately below the concave portion of the finger (corresponding to the groove for determining the fingerprint shape) is reflected by the insulating film or the like. Light does not enter much.

As described above, since the amount of incident light is small and a sufficient amount of holes are not accumulated in the semiconductor layer, the voltage applied to the top gate electrode 91 is -15 (V), and the bottom gate electrode When the voltage applied to 92 becomes +10 (V), the depletion layer spreads in the semiconductor layer, the n-channel is pinched off, and the semiconductor layer has high resistance. On the other hand, in the photo-sensing state, the light reflected by the insulating film or the like is incident on the semiconductor layer of the double gate transistor 81 immediately below the convex portion of the finger (the crest between the grooves of the finger), and a sufficient amount of light is reflected. When such a voltage is applied in a state where holes are accumulated in the semiconductor layer, the accumulated holes are attracted to and held by the top gate electrode 91 so that the bottom gate electrode of the semiconductor layer is An n-channel is formed on the 92 side,
The semiconductor layer has low resistance. The difference between the resistance values of the semiconductor layers in these read states appears as a change in the potential of the drain line DL.

The top gate driver 72 includes the image pickup device 7
One top gate line TGL, and selectively outputs a signal of +25 (V) or -15 (V) to each top gate line TGL according to a control signal group Tcnt from the controller 70. Top gate driver 72
Has substantially the same configuration as the shift register forming the gate driver 52 except for the difference in the level of the output signal, the difference in the level of the input signal corresponding thereto, and the difference in the phase of the output signal and the input signal. have.

The bottom gate driver 73 includes the image pickup device 7
It is connected to one bottom gate line BGL and outputs a signal of +10 (V) or 0 (V) to each bottom gate line BGL according to a control signal group Bcnt from the controller 70. The bottom gate driver 73 outputs the difference in the level of the output signal, the difference in the level of the input signal corresponding to the difference,
Except for the difference between the phase of the output signal and the phase of the input signal, the shift register has substantially the same configuration as the shift register forming the gate driver 52 described above.

The drain driver 74 is connected to the drain line DL of the image sensor 71, and according to a control signal group Dcnt from the controller 70, applies a constant voltage (+10) to all the drain lines DL in a predetermined period described later.
(V)) to precharge the electric charge. The drain driver 74 reads out the potential of each drain line DL that changes depending on whether or not a channel is formed in the semiconductor layer of the double gate transistor 81 in a predetermined period after the precharge according to whether or not light is incident on the semiconductor layer of the double gate transistor 81. Is supplied to the controller 70 as image data DATA.

The controller 70 controls the control signal group Tcn
Top gate driver 7 by t and Bcnt
2. Control the bottom gate driver 73 so that both drivers 72 and 73 output a signal of a predetermined level at a predetermined timing for each line. Thus, each line of the image sensor 71 is sequentially set to the reset state, the photo sense state, and the read state. Further, the controller 70 causes the drain driver 74 to read out the potential change of the drain line DL in accordance with the control signal group Dcnt, and sequentially takes in the image data DATA.

Also, FIGS. 4, 6, 8, 11, and 1
3. The shift register illustrated in FIGS. 20 and 23 can be applied to a purpose other than a use as a driver for driving an imaging element or a display element. For example, these shift registers can be applied to applications such as converting serial data to parallel data in a data processing device or the like.

In the first and second embodiments, the TFTs 1 to 6 constituting the shift register shown in FIGS. 4, 6, 8, 11, 13, 20, and 23 are all It was an n-channel type. On the other hand, a p-channel type can be used. For example, when all the p-channel type are used, the high and low levels of each signal may be inverted as compared with the n-channel type.

In the first and second embodiments, the case where the present invention is applied to a digital still camera for photographing a still image has been described as an example. However, a moving image is photographed, and the photographed image is displayed. The present invention can also be applied to a video camera using a liquid crystal display device or the like as a finder for viewing.
When the video camera is configured so that the orientation of the liquid crystal display device can be rotated with respect to the imaging lens, a mirror image is displayed by using the shift register described in the second embodiment as a gate driver of the liquid crystal display device. Can be.

[0180]

As described above, in the shift register of the present invention, the characteristics of the first or second transistor are less changed, and the shift register can operate stably for a long period of time.

Further, the first and second voltage signals are adjusted by adjusting the high level and the period of the first and second voltage signals.
Transistor is less likely to fail, and can operate stably for a long period of time.

In addition, by making it possible to switch between the first and second transistors for accumulating charges in the wiring and discharging the accumulated charges, bidirectional switching between the forward direction and the reverse direction is possible. To perform the shift operation.

Further, an electronic device in which the shift register of the present invention is applied as a driver also has excellent durability.

In addition, by applying a driver capable of performing a shift operation in both the forward direction and the reverse direction as a driver, it is possible to easily display an image whose upside down direction is inverted.

[Brief description of the drawings]

FIG. 1 is a diagram showing an external configuration of a digital still camera according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a circuit configuration of the digital still camera in FIG. 1;

FIG. 3 is a block diagram illustrating a circuit configuration of a display unit in FIG. 2;

4 is a diagram showing a circuit configuration of a shift register used as the gate driver in FIG.

FIG. 5 is a timing chart showing the operation of the shift register of FIG.

FIG. 6 is a diagram illustrating another circuit configuration of the shift register used as the gate driver in FIG. 3;

7 is a timing chart showing the operation of the shift register of FIG.

8 is a diagram illustrating another circuit configuration of the shift register used as the gate driver in FIG. 3;

FIG. 9 is a timing chart showing the operation of the shift register of FIG.

FIG. 10 is another timing chart showing the operation of the shift register of FIG.

11 is a diagram illustrating another circuit configuration of the shift register used as the gate driver in FIG. 3;

FIG. 12 is a timing chart showing the operation of the shift register of FIG.

FIG. 13 is a diagram showing a circuit configuration of a shift register used as the gate driver of FIG. 3 in the second embodiment of the present invention.

14 is a timing chart showing a forward operation of the shift register of FIG.

FIG. 15 is a timing chart showing the reverse operation of the shift register of FIG.

16A and 16B are diagrams showing a use state of the digital still camera shown in FIG. 1 in a forward direction according to the second embodiment of the present invention, wherein FIG. 16A shows an imaging state, and FIG. Indicates the display state.

17A and 17B are diagrams showing a use state of the digital still camera shown in FIG. 1 in a reverse direction in the second embodiment of the present invention, wherein FIG. 17A shows an image pickup state, and FIG. Indicates the display state.

18 is another timing chart showing a forward operation of the shift register of FIG.

FIG. 19 is another timing chart showing the reverse operation of the shift register of FIG. 13;

FIG. 20 is a diagram showing another circuit configuration of the shift register used as the gate driver in FIG. 3 in the second embodiment of the present invention.

21 is a timing chart showing a forward operation of the shift register of FIG.

FIG. 22 is a timing chart showing the reverse operation of the shift register of FIG. 20;

FIG. 23 is a diagram showing another circuit configuration of the shift register used as the gate driver in FIG. 3 in the second embodiment of the present invention.

24 is a timing chart showing a forward operation of the shift register of FIG.

FIG. 25 is a timing chart showing the reverse operation of the shift register of FIG. 20;

FIG. 26 is a block diagram illustrating a configuration of an imaging device according to another embodiment of the present invention.

FIG. 27 is a diagram showing a circuit configuration of a conventional shift register.

FIG. 28 is a timing chart showing the operation of a conventional shift register.

[Explanation of symbols]

1 to 6: TFT, 01: camera body, 02: lens unit, 02a: imaging lens, 10: display, 11 ...
Power key, 12 key input section, 12a mode setting key, 12b shutter key, 12c "+" key, 1
2d "-" key, 13 serial input / output terminal, 20 ...
CCD imaging device, 21 ... A / D converter, 22 ... CPU,
23 ROM, 24 RAM, 25 compression / expansion circuit,
26 image memory, 30 bus, 40 angle sensor, 5
0: liquid crystal controller, 51: liquid crystal display element, 52: gate driver, 53: drain driver, 61: TF
T, 62: pixel capacitance, 70: controller, 71: image sensor, 72: top gate driver, 73: bottom gate driver, 74: drain driver, 81: double gate transistor, 91: top gate electrode, 92: bottom gate electrode , 93: drain electrode, 94: source electrode, RS (1) to RS (n): step, GL: gate line, DL: drain line, TGL: top gate line, BGL: bottom gate line, GrL: ground line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 19/00 G11C 19/00 J G 19/28 19/28 Z

Claims (14)

[Claims] 1. A shift register comprising a plurality of stages, wherein each stage of the shift register is supplied with an output signal of an adjacent stage on one side to a control terminal, and a first voltage on one end of a current path. A first transistor to which a signal is supplied; an output signal of an adjacent stage to the control terminal to the other side; a second transistor to which a second voltage signal is supplied to one end of a current path; A control terminal is connected to the other end of each of the current paths of the first and second transistors, and an electric charge is supplied to a wiring therebetween by the first or second voltage signal supplied through the first or second transistor. And outputting the first or second clock signal supplied to one end of the current path as the output signal of the stage from the other end of the current path when the third path is turned on by the stored charge. Transistor Wherein at least one of the first and second transistors is configured to be capable of discharging charges accumulated in the wiring by an output signal of an adjacent stage supplied to a control terminal. A shift register characterized by the above-mentioned. 2. The first and second stages at one end of the plurality of stages.
One of the transistors is turned on when a first control signal is supplied to a control terminal from the outside, and charges are accumulated in the wiring, and the first and second transistors at the other end of the plurality of stages are 2. The shift register according to claim 1, wherein a second control signal is supplied to a control terminal from the outside, and the control signal turns on to discharge charges accumulated in the wiring. 3. The first and second voltage signals are switched so that electric charges can be accumulated in the wiring via one of the first and second transistors, and the first and second voltage signals are switched. 3. The shift register according to claim 1, wherein the electric charge accumulated in the wiring can be released through the other one of the transistors. 4. The shift register according to claim 3, wherein the levels of the first and second voltage signals are switched so that one of them is maintained at a low level. 5. The high-level of the first and second voltage signals is lower than the high-level of the first and second clock signals. The shift register according to the paragraph. 6. A period in which the first and second voltage signals are at a high level is shorter than a period in which one of the first and second clock signals is at a high level. The shift register according to claim 1, wherein: 7. The shift register according to claim 1, wherein the first clock signal and the second clock signal have phases different from each other by 180 °. 8. The shift register according to claim 1, wherein each transistor constituting each of the plurality of stages is a field effect transistor of the same channel type. 9. A control terminal is connected to the other end of each current path of the first and second transistors, and the first or second transistor is supplied to a wiring therebetween through the first or second transistor. A second voltage signal is used to accumulate electric charge, and to release a signal supplied from a voltage source via a load to one end of a current path from the other end of the current path when the charge is turned on by the accumulated electric charge. And a control terminal is connected to the voltage source via the load, and when the fourth transistor is off, it is turned on by a signal connected from the voltage source, and one end of a current path is The shift register according to claim 1, further comprising: a fifth transistor connected to the other end of the current path of the third transistor. 10. A driver comprising a plurality of stages and sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, and an output signal comprising a plurality of pixels and outputted from each stage of the driver. And a driving element driven by the first stage. Each stage of the driver has a control terminal to which an output signal of an adjacent stage is supplied on one side and a first voltage signal supplied to one end of a current path. A second transistor having a control terminal supplied with the other output signal of the adjacent stage on the other side, and a second voltage signal supplied to one end of a current path; When a control terminal is connected to the other end of each current path of the transistor, and a charge is accumulated by a first or second voltage signal supplied through the first or second transistor to a wiring therebetween, A third transistor for outputting the first or second clock signal supplied to one end of the current path from the other end of the current path as an output signal of the stage when both are turned on by the accumulated charge; A control terminal is connected to the other end of the current path of each of the first and second transistors, and the first or second voltage supplied to the wiring therebetween through the first or second transistor A fourth transistor for accumulating a charge by a signal and releasing a signal supplied from a voltage source via a load to one end of the current path from the other end of the current path when the transistor is turned on by the accumulated charge; A control terminal is connected to the voltage source via the load, and when the fourth transistor is off, it is turned on by a signal connected from the voltage source, and one end of the current path is A fifth transistor connected to the other end of the current path of the third transistor, wherein at least one of the first and second transistors is provided by an output signal of an adjacent stage supplied to a control terminal. An electronic device, wherein the electronic device is configured to be capable of discharging charges accumulated in the wiring. 11. The driving element includes a display transistor for each pixel, to which a control terminal is supplied with an output signal of any one of the stages of the driver and one end of a current path is supplied with image data from outside. The electronic device according to claim 10, wherein the electronic device is a display element. 12. An image pickup unit including an image pickup device for picking up an optical image formed by an image pickup lens, and provided rotatably with respect to the image pickup unit about an axis substantially perpendicular to the image pickup direction. The display device further includes a display element as the driving element, and a display unit including the driver for driving the display element, and the display unit displays an image corresponding to an image captured by the imaging device on the display element. The electronic device according to claim 10, wherein: 13. A setting means for setting which of the first and second transistors accumulates charge in the wiring and releases the accumulated charge, and an angle of the imaging unit with respect to the display unit. Further comprising an angle detecting means for detecting the first and second voltage signals, wherein the setting means performs setting in accordance with a detection result of the angle detecting means, and switches the levels of the first and second voltage signals. Wherein the charge stored in the wiring can be discharged through one of the transistors and the charge stored in the wiring can be discharged through the other of the first and second transistors. 13. The electronic device according to claim 12. 14. The driving element according to claim 1, wherein the driving element includes a semiconductor layer that generates carriers by excitation light, a drain electrode and a source electrode connected to both ends of the semiconductor layer, and a first gate insulating film. The first provided on one side
An image sensor comprising, for each pixel, a gate electrode and a second gate electrode provided on the other side of the semiconductor layer via a second gate insulating film, wherein the driver outputs an output signal to the first gate electrode. 11. The electronic device according to claim 10, further comprising: a first driver that outputs an output signal to the second gate electrode; and a second driver that outputs an output signal to the second gate electrode.