JP4086046B2 - SHIFT REGISTER, DISPLAY DEVICE, IMAGING ELEMENT DRIVE DEVICE, AND IMAGING DEVICE - Google Patents

Description

  The present invention relates to a shift register, a display device having a driver including the shift register, an imaging element driving device, and an imaging device.

  In recent years, digital still cameras for recording still images have become widespread. Such a digital still camera generally includes a liquid crystal display device that functions as a viewfinder for displaying an image captured by an image sensor and also functions as a display for displaying an image recorded in an image memory. Yes.

  As such a liquid crystal display device, an active matrix type device is generally used because of its wide viewing angle and good response characteristics. An active matrix type liquid crystal display device is driven by a gate driver for selecting a gate line arranged for each row of pixels arranged in a matrix on a liquid crystal panel, and an image signal for each line of the gate line. And a drain driver for supplying the captured image signal to the pixel corresponding to the selected gate line via the drain line. The gate driver and the drain driver are generally composed of a plurality of TFTs, and these TFTs output a signal supplied to the drain to the source based on the gate signal, but output a voltage value according to the voltage value of the gate signal. Will change.

  The gate driver and the drain driver are generally configured by a multistage shift register that sequentially transmits a signal of the previous stage to the next stage. However, in such a shift register, conventionally, the circuit immediately before outputting a signal to the next stage has to have a so-called EE configuration, and it has been difficult to obtain a complete off-resistance. The output voltage gradually decays. Patent Documents 1 and 2 show a scanning circuit composed of a plurality of transistors.

  Some digital still cameras can arbitrarily change the orientation of the imaging lens with respect to the camera body. For example, a lens unit including an imaging lens is rotated with respect to the body to display an image on the photographer side. There are things that allow you to shoot. In this case, for the photographer, for example, when the user's face is displayed on the liquid crystal display device, the mirror display (vertically reversed display or horizontally reversed display) can be performed. However, conventionally, in order to perform mirror display, a controller that supplies an image to a liquid crystal display device has to perform complicated control to change the reading order of image data.

Furthermore, in a digital still camera, when a liquid crystal display device displays an image in which the image is freely inverted depending on the shooting conditions, the controller that supplies the image performs complex control. Thus, the reading order of image data had to be changed.
JP 58-29200 A Japanese Patent Laid-Open No. 52-95961

The present invention provides a shift suitable as a drive circuit for a display device that can transmit an output signal having a high S / N ratio and can be transmitted to the next stage without attenuating the level of the signal input at each stage. It is an object of the present invention to provide a register, a display device, an imaging element driving device, and an imaging device .

In order to achieve the above object, the shift register of the present invention includes:
A shift register having a plurality of stages, each stage of the shift register being
During forward operation, a first or second signal is supplied to the control terminal, a predetermined signal is supplied from one end of the current path, and is turned on by the first or second signal supplied to the control terminal. A first transistor that outputs the predetermined signal to the other end of the current path when
A predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal, and one end of the current path is connected to a signal source via a load, and is supplied to the control terminal. A second transistor for draining a signal supplied from a signal source to ground when turned on by a signal;
When the predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal and turned on by the predetermined signal supplied to the control terminal, the third or fourth signal A third transistor that inputs from one end of the current path and outputs to the other end;
A fourth transistor for discharging a predetermined signal output from the other end of the current path of the first transistor charged in the second transistor or the third transistor of the next stage to the ground ;
In the odd-numbered stages of the shift registers, the fifth signal is supplied to the control terminal during reverse operation, and is output from the other end of the current path of the third transistor in the subsequent stage. A fourth signal is supplied to one end of the current path, and when the supplied signal is turned on by the fifth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A fifth transistor to be supplied to the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor;
In the even stage among the stages of the shift register, the sixth signal is supplied to the control terminal during the backward operation, and the third signal output from the other end of the current path of the third transistor in the subsequent stage. Alternatively, when the fourth signal is supplied to one end of the current path, and the supplied predetermined signal is turned on by the sixth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A sixth transistor that supplies a control terminal of the even-numbered second transistor serving as a subsequent stage and a control terminal of the even-numbered third transistor ;
In the odd stage, during the forward operation, the first signal is supplied to the control terminal of the first transistor, and the third signal is supplied to one end of the current path of the third transistor,
In the even stage, during the forward operation, the second signal is supplied to the control terminal of the first transistor, and the fourth signal is supplied to one end of the current path of the third transistor,
In the first stage, during the forward operation, a signal from the outside is supplied as one end of the current path of the first transistor as the predetermined signal.
After the second stage, during the forward operation, the third transistor or the fourth signal output from the other end of the current path of the third transistor in the previous stage is the first transistor as the predetermined signal. is supplied to one end of the current path,
In the reverse operation, a predetermined signal output from the other end of the current path of the fifth transistor based on the fifth signal is generated from the first transistor of the odd-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor, Until the next transistor is turned on, the control terminal of the second transistor of the odd stage and the control terminal of the third transistor of the odd stage continue to be held,
In the reverse operation, a predetermined signal output from the other end of the current path of the sixth transistor based on the sixth signal is generated by the first transistor of the even-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the even-numbered second transistor and the control terminal of the even-numbered third transistor; Between the time when the first transistor is turned off and the time when the second transistor is turned on, the control terminal of the second transistor of the even-numbered stage and the control terminal of the third transistor of the even-numbered stage continue to be held.
It is characterized by that.

In order to achieve the above object, the display device of the present invention provides:
A display device including a shift register having a plurality of stages, each stage of the shift register includes:
During forward operation, a first or second signal is supplied to the control terminal, a predetermined signal is supplied from one end of the current path, and is turned on by the first or second signal supplied to the control terminal. A first transistor that outputs the predetermined signal to the other end of the current path when
A predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal, and one end of the current path is connected to a signal source via a load, and is supplied to the control terminal. A second transistor for draining a signal supplied from a signal source to ground when turned on by a signal;
When the predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal and turned on by the predetermined signal supplied to the control terminal, the third or fourth signal A third transistor that inputs from one end of the current path and outputs to the other end;
A fourth transistor for discharging a predetermined signal output from the other end of the current path of the first transistor charged in the second transistor or the third transistor of the next stage to the ground ;
In the odd-numbered stages of the shift registers, the fifth signal is supplied to the control terminal during reverse operation, and is output from the other end of the current path of the third transistor in the subsequent stage. A fourth signal is supplied to one end of the current path, and when the supplied signal is turned on by the fifth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A fifth transistor to be supplied to the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor;
In the even stage among the stages of the shift register, the sixth signal is supplied to the control terminal during the backward operation, and the third signal output from the other end of the current path of the third transistor in the subsequent stage. Alternatively, when the fourth signal is supplied to one end of the current path, and the supplied predetermined signal is turned on by the sixth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A shift register comprising: a sixth transistor that supplies a control terminal of the even-numbered second transistor and a control terminal of the even-numbered third transistor ; A display unit that is displayed according to the output of the third transistor,
Have
The shift register is
In the odd stage, during the forward operation, the first signal is supplied to the control terminal of the first transistor, and the third signal is supplied to one end of the current path of the third transistor,
In the even stage, during the forward operation, the second signal is supplied to the control terminal of the first transistor, and the fourth signal is supplied to one end of the current path of the third transistor,
In the first stage, during the forward operation, a signal from the outside is supplied as one end of the current path of the first transistor as the predetermined signal.
After the second stage, during the forward operation, the third transistor or the fourth signal output from the other end of the current path of the third transistor in the previous stage is the first transistor as the predetermined signal. is supplied to one end of the current path,
In the reverse operation, a predetermined signal output from the other end of the current path of the fifth transistor based on the fifth signal is generated from the first transistor of the odd-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor, Until the next transistor is turned on, the control terminal of the second transistor of the odd stage and the control terminal of the third transistor of the odd stage continue to be held,
In the reverse operation, a predetermined signal output from the other end of the current path of the sixth transistor based on the sixth signal is generated by the first transistor of the even-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the even-numbered second transistor and the control terminal of the even-numbered third transistor; Between the time when the first transistor is turned off and the time when the second transistor is turned on, the control terminal of the second transistor of the even-numbered stage and the control terminal of the third transistor of the even-numbered stage continue to be held.
It is characterized by that.

  In the display device, an arbitrary display panel in which pixels are arranged in a matrix, such as a liquid crystal display panel, an electroluminescence display panel, a plasma display panel, or a field emission display panel, can be selected as the display unit.

In order to achieve the above object, an image sensor driving apparatus according to the present invention includes:
An image sensor in which pixels are arranged in a matrix and generates an image signal corresponding to light incident on each pixel;
A shift register having a plurality of stages shifts selection signals supplied from the outside and sequentially outputs the signals from each stage. The selection signals output from the respective stages cause the pixels of the image sensor to be arranged for each line of the matrix. Selection drive means to select;
Signal capturing means for capturing an image signal generated from a pixel of a line selected by the selection driving means;
The selection driving means includes selection control means for selecting and supplying a selection signal supplied from the outside to either the first stage or the last stage of the shift register,
The shift register is
During forward operation, a first or second signal is supplied to the control terminal, a predetermined signal is supplied from one end of the current path, and is turned on by the first or second signal supplied to the control terminal. A first transistor that outputs the predetermined signal to the other end of the current path when
A predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal, and one end of the current path is connected to a signal source via a load, and is supplied to the control terminal. A second transistor for draining a signal supplied from a signal source to ground when turned on by a signal;
When the predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal and turned on by the predetermined signal supplied to the control terminal, the third or fourth signal A third transistor that inputs from one end of the current path and outputs to the other end;
A fourth transistor for discharging a predetermined signal output from the other end of the current path of the first transistor charged in the second transistor or the third transistor of the next stage to the ground ;
In the odd-numbered stages of the shift registers, the fifth signal is supplied to the control terminal during reverse operation, and is output from the other end of the current path of the third transistor in the subsequent stage. A fourth signal is supplied to one end of the current path, and when the supplied signal is turned on by the fifth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A fifth transistor to be supplied to the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor;
In the even stage among the stages of the shift register, the sixth signal is supplied to the control terminal during the backward operation, and the third signal output from the other end of the current path of the third transistor in the subsequent stage. Alternatively, when the fourth signal is supplied to one end of the current path, and the supplied predetermined signal is turned on by the sixth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A sixth transistor that supplies a control terminal of the even-numbered second transistor serving as a subsequent stage and a control terminal of the even-numbered third transistor ;
In the odd stage, during the forward operation, the first signal is supplied to the control terminal of the first transistor, and the third signal is supplied to one end of the current path of the third transistor,
In the even stage, during the forward operation, the second signal is supplied to the control terminal of the first transistor, and the fourth signal is supplied to one end of the current path of the third transistor,
In the first stage, during the forward operation, a signal from the outside is supplied as one end of the current path of the first transistor as the predetermined signal.
After the second stage, during the forward operation, the third transistor or the fourth signal output from the other end of the current path of the third transistor in the previous stage is the first transistor as the predetermined signal. is supplied to one end of the current path,
In the reverse operation, a predetermined signal output from the other end of the current path of the fifth transistor based on the fifth signal is generated from the first transistor of the odd-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor, Until the next transistor is turned on, the control terminal of the second transistor of the odd stage and the control terminal of the third transistor of the odd stage continue to be held,
In the reverse operation, a predetermined signal output from the other end of the current path of the sixth transistor based on the sixth signal is generated by the first transistor of the even-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the even-numbered second transistor and the control terminal of the even-numbered third transistor; Between the time when the first transistor is turned off and the time when the second transistor is turned on, the control terminal of the second transistor of the even-numbered stage and the control terminal of the third transistor of the even-numbered stage continue to be held.
It is characterized by that.

In order to achieve the above object, an imaging apparatus of the present invention provides:
An image sensor in which pixels are arranged in a matrix, and a display that displays an image corresponding to an image captured by the image sensor or an image corresponding to an image captured by the image sensor and recorded in an image memory With the device,
The display device
A display element in which pixels are arranged in a matrix, and
The first shift register is composed of a plurality of stages. The selection signal supplied from the outside is shifted and sequentially output from each stage, and the pixels of the display element are arranged in the matrix by the selection signal output from each stage. A selection drive circuit to select for each line;
A signal drive circuit that captures an image signal supplied from the outside for one line of the display element, and supplies a signal corresponding to the captured image signal to the pixels of the line selected by the selection drive circuit;
A control circuit for controlling the selection drive circuit and the signal drive circuit,
The selection drive circuit includes a first selection control unit that selects and supplies an externally supplied selection signal to either the first stage or the last stage of the first shift register, and is fetched by each stage. Second selection control means for selecting whether to shift the selection signal to the preceding stage or to the subsequent stage,
The shift register is
During forward operation, a first or second signal is supplied to the control terminal, a predetermined signal is supplied from one end of the current path, and is turned on by the first or second signal supplied to the control terminal. A first transistor that outputs the predetermined signal to the other end of the current path when
A predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal, and one end of the current path is connected to a signal source via a load, and is supplied to the control terminal. A second transistor for draining a signal supplied from a signal source to ground when turned on by a signal;
When the predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal and turned on by the predetermined signal supplied to the control terminal, the third or fourth signal A third transistor that inputs from one end of the current path and outputs to the other end;
A fourth transistor for discharging a predetermined signal output from the other end of the current path of the first transistor charged in the second transistor or the third transistor of the next stage to the ground ;
In the odd-numbered stages of the shift registers, the fifth signal is supplied to the control terminal during reverse operation, and is output from the other end of the current path of the third transistor in the subsequent stage. A fourth signal is supplied to one end of the current path, and when the supplied signal is turned on by the fifth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A fifth transistor to be supplied to the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor;
In the even stage among the stages of the shift register, the sixth signal is supplied to the control terminal during the backward operation, and the third signal output from the other end of the current path of the third transistor in the subsequent stage. Alternatively, when the fourth signal is supplied to one end of the current path, and the supplied predetermined signal is turned on by the sixth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A sixth transistor that supplies a control terminal of the even-numbered second transistor serving as a subsequent stage and a control terminal of the even-numbered third transistor ;
In the odd stage, during the forward operation, the first signal is supplied to the control terminal of the first transistor, and the third signal is supplied to one end of the current path of the third transistor,
In the even stage, during the forward operation, the second signal is supplied to the control terminal of the first transistor, and the fourth signal is supplied to one end of the current path of the third transistor,
In the first stage, during the forward operation, a signal from the outside is supplied as one end of the current path of the first transistor as the predetermined signal.
After the second stage, during the forward operation, the third transistor or the fourth signal output from the other end of the current path of the third transistor in the previous stage is the first transistor as the predetermined signal. is supplied to one end of the current path,
In the reverse operation, a predetermined signal output from the other end of the current path of the fifth transistor based on the fifth signal is generated from the first transistor of the odd-numbered stage that is the preceding stage of the subsequent stage. Accumulated in the wiring formed between the other end of the current path and the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor; Until the next transistor is turned on, the control terminal of the second transistor of the odd stage and the control terminal of the third transistor of the odd stage continue to be held,
In the reverse operation, a predetermined signal output from the other end of the current path of the sixth transistor based on the sixth signal is generated by the first transistor of the even-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the even-numbered second transistor and the control terminal of the even-numbered third transistor; Between the time when the first transistor is turned off and the time when the second transistor is turned on, the control terminal of the second transistor of the even-numbered stage and the control terminal of the third transistor of the even-numbered stage continue to be held.
It is characterized by that.

  According to the invention, in the third transistor, the potential of the third or fourth signal output to the other end of the current path is charged to the storage capacitor between the other end and the control terminal and applied to the control terminal. Since the applied voltage increases, the third or fourth signal can be supplied without being attenuated.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following first to eighth embodiments, a case where the present invention is applied to a digital still camera will be described as an example.

[First Embodiment]
FIG. 1 is a perspective view showing an external appearance of a digital still camera according to this embodiment. As shown in the figure, this digital still camera is composed of a camera body 1 and a lens unit 2.

  The camera body 1 includes a display unit 10 and a mode setting key 12a on the front surface thereof. The mode setting key 12a is a key for shooting an image and switching between a shooting mode for recording in an image memory (to be described later) and a playback mode for playing back the recorded image. The display unit 10 is configured by a liquid crystal display device, and functions as a viewfinder for displaying an image captured by a lens before shooting in the shooting mode (monitoring mode), and displays a recorded image in the playback mode. Functions as a display. The configuration of the display unit 10 will be described in detail later.

  The camera body 1 also includes a power key 11, a shutter key 12b, a “+” key 12c, a “−” key 12d, and a serial input / output terminal 29 on the upper surface thereof. The power key 11 is a key for turning on / off the power of the digital still camera by performing a slide operation.

  The shutter key 12b is a key for instructing recording of an image in the photographing mode and instructing determination of selection contents in the reproduction mode. The “+” key 12c and the “−” key 12d are used to select image data to be displayed on the display unit 10 from image data recorded in the image memory in the playback mode, and to set conditions for recording / playback. Used for. The serial input / output terminal 29 is a terminal for inserting a cable for performing data transmission and data reception with an external device (such as a personal computer or a printer).

  The lens unit 2 includes a lens that forms an image to be photographed on the back side of the drawing. The lens unit 2 is attached so as to be capable of rotating 360 ° in the vertical direction about an axis coupled to the camera body 1.

  FIG. 2 is a block diagram showing a circuit configuration of the digital still camera of FIG. As shown in the figure, the circuit of this digital still camera includes a display unit 10, a key input unit 12, a CCD (Charge Coupled Device) 21, a sample hold circuit 22, and an A / D (analog-digital) converter 23. A vertical driver 24, a timing generator 25, a color process circuit 26, a DMA (Direct Memory Access) controller 27, a DRAM (Dynamic Random Access Memory) 28, a serial input / output terminal 29, and a recording memory 30. A CPU (Central Processing Unit) 31, an image compression / decompression circuit 32, a VRAM controller 33, a VRAM (Video Random Access Memory) 34, a digital video encoder 35, and a ROM (Read Only Memory) 36. .

  Among these, the DMA controller 27, the recording memory 30, the CPU 31, the image compression / decompression circuit 32, the VRAM controller 33, and the ROM 36 are connected to each other via the data bus 40.

  The key input unit 12 includes the mode setting key 12a, the shutter key 12b, the “+” key 12c, and the “−” key 12d, and inputs a command corresponding to the operation of each key to the CPU 31. To do. The CCD 21 receives the light imaged by the lens in each of the plurality of pixels arranged in a matrix and accumulates electric charges according to the intensity of the received light. The CPU 31 executes a program stored in the ROM 36 and controls each part of this circuit. The serial input / output terminal 29 is an input / output terminal for the CPU 31 to serially transfer data to / from an external device.

  The operation of the above circuit will be briefly described below. First, the operation in the shooting mode will be described. The shooting mode includes two modes: a monitoring mode in which a captured image is displayed on the display unit 10, and an image recording mode in which the captured image is recorded in the recording memory 30 as image data.

  In the monitoring mode, the CPU 31 drives the CCD 21 by controlling the timing generator 25 and the color process circuit 26 for each preset imaging cycle, and accumulates charges corresponding to the amount of light received at each pixel. Based on the drive signal Sp supplied from the vertical driver 24, the CCD 21 sequentially outputs an electric signal Se corresponding to the electric charge accumulated in each pixel to the sample hold circuit 22.

  The sample hold circuit 22 outputs the effective part Se ′ of the electric signal Se to the A / D converter 23. The A / D converter 23 converts the effective part Se ′ into digital data Sd and outputs it to the color process circuit 26. The color process circuit 26 generates YUV data that is luminance / color difference digital data based on the digital data Sd and outputs the YUV data to the DMA controller 27. The DMA controller 27 sequentially writes YUV data to the DRAM 28.

  The CPU 31 controls the DMA controller 27 every time YUV data for one frame is written in the DRAM 28, causes the YUV data for one frame to be transferred from the DRAM 28 to the VRAM controller 33, and is written in the VRAM 34. Also, the digital video encoder 35 reads out one frame of YUV data from the VRAM 34 via the VRAM controller 33 at regular intervals in a line-sequential manner, generates an analog video signal Sa based on the read YUV data, and displays the display unit 10. Output to.

  On the other hand, in the image recording mode, when the operator presses the shutter key 12b while the CCD 21 is sequentially outputting the electric signal Se to the sample and hold circuit 22 as described above, the CPU 31 is in accordance with the command from the shutter key 12b. The timing generator 25 and the color process circuit 26 are controlled to stop the transfer of the YUV data from the color process circuit 26 when the transfer of the YUV data for one frame is completed.

  The electrical signal Se for one frame until the transfer of YUV data is stopped is converted into YUV data via the sample hold circuit 22, the A / D converter 23, and the color process circuit 26 as in the monitoring mode. And written to the DRAM 28. The CPU 31 controls the DMA controller 27 to input the YUV data written in the DRAM 28 to the image compression / decompression circuit 32. The image compression / decompression circuit 32 compresses the YUV data by a method such as JPEG (Joint Photographic Experts Group) and stores it in the recording memory 30.

  After the storage of the compressed data in the recording memory 30 is completed, the CPU 31 activates the timing generator 25 and the color process circuit 26 again. Thereby, the mode of the digital still camera automatically returns from the image recording mode to the monitoring mode.

  In the playback mode, the CPU 31 causes the image compression / decompression circuit 32 to decompress the compressed data stored in the recording memory 30 in response to an operation on each key 12 a to 12 d of the key input unit 12. The CPU 31 further controls the DMA controller 27 to transfer the YUV data for one frame decompressed by the image compression / decompression circuit 32 from the image compression / decompression circuit 32 to the VRAM controller 33 and write it to the VRAM 34.

  The digital video encoder 35 reads out one frame of YUV written in the VRAM 34 in a line sequential manner, and generates an analog video signal Sa based on the read YUV data. Then, the digital video encoder 35 supplies the generated analog video signal Sa to the display unit 10. In addition, after the image capturing is finished in the image recording mode and the compressed data is recorded in the recording memory 30, the operation mode of the digital still camera is switched from the image recording mode to the reproduction mode, and the image is displayed on the display unit 10. The displayed image may be displayed.

  Hereinafter, the configuration of the display unit 10 of FIGS. 1 and 2 will be described in detail with reference to the block diagram of FIG. The display unit 10 includes a liquid crystal display device. As shown in FIG. 3, the display unit 10 includes a chroma circuit 111, a phase comparator 112, a level shifter 113, a liquid crystal controller 101, a liquid crystal panel 102, and a gate driver 103. And a drain driver 104.

  The chroma circuit 111 generates analog RGB signals SR1, SG1, and SB1 based on the analog video signal Sa output from the digital video encoder 35 in both the monitoring mode and the image recording mode. The analog video signals SR1, SG1, and SB1 are gamma corrected in accordance with the visual characteristics of the liquid crystal panel 102. The chroma circuit 111 also generates a common voltage VCOM described later. The chroma circuit 111 also performs synchronization separation processing to separate the vertical synchronization signal VD and the horizontal synchronization signal HD from the analog video signal Sa, and supplies them to the phase comparator 112 and the liquid crystal controller 101, respectively.

  The level shifter 113 sets the polarity of the analog RGB signals SR1, SG1, SB1 generated by the chroma circuit 111 to one line or one in order to AC drive the liquid crystal of the liquid crystal panel 102 and adjust the brightness of the displayed image. The analog RGB signals SR2, SG2, and SB2 subjected to level shift processing are output by inverting each frame and controlling the amplitude.

  The liquid crystal controller 101 incorporates an oscillation circuit, and synchronizes in the vertical direction with the vertical synchronization signal VD supplied from the chroma circuit 111. The liquid crystal controller 101 configures a PLL (Phase Locked Loop) based on the output of the phase comparator 112 based on the phase comparison signal CKH, and synchronizes in the horizontal direction based on the configured PLL and the horizontal synchronization signal HD. The liquid crystal controller 101 also outputs a polarity inversion control signal CKF to the level shifter 113, outputs a control signal group DCNT to the drain driver 104, and outputs a control signal group GCNT to the gate driver 103.

  The control signal group GCNT supplied to the gate driver 103 includes signals Φ1, Φ2, CK1, ¬CK1 (¬ represents logic negation, the same applies hereinafter) and a start signal IN, which will be described later.

  The liquid crystal panel 102 is of an active matrix type constituted by (m × n) pixels, and is configured by sealing liquid crystal between a pair of substrates. One substrate of the liquid crystal panel 102 is applied with a common voltage VCOM generated by the chroma circuit 111 and subjected to AC level amplification and DC level amplification (VCOM may be displaced with time). An electrode is formed.

  On the other substrate of the liquid crystal panel 102, pixel electrodes corresponding to pixels and thin film transistors (TFTs) 102a whose semiconductor layers are made of amorphous silicon or polysilicon are formed in a matrix. On the other substrate of the liquid crystal panel 102, n gate lines GL1 to GLn and m drain lines DL1 to DLm are formed orthogonally between the pixel electrodes, and are parallel to the gate lines GL1 to GLn. The capacitor lines CL1 to CLn are provided. On the other substrate of the liquid crystal panel 102, red (R), green (G), and blue (B) color filters corresponding to the analog RGB signals SR2, SG2, and SB2 are formed in a predetermined arrangement. Yes.

  An equivalent circuit diagram of the liquid crystal panel 102 is shown in FIG. The TFT 102a has a gate connected to the gate line GL, a drain connected to the drain line DL, and a source connected to the pixel electrode. The pixel capacitor 102b includes a pixel electrode, a common electrode, and liquid crystal sealed therebetween. A display signal from the drain line DL is written into the pixel capacitor 102b via the TFT 102a corresponding to the selected gate line GL. The alignment state of the liquid crystal constituting the pixel capacitor 102b is controlled according to the display signal written in the pixel capacitor 102b, and the liquid crystal panel 102 displays an image by changing the amount of light transmitted through the liquid crystal depending on the alignment state.

  The capacitor 102c includes capacitor lines CL1 to CLn, a gate insulating film and a pixel electrode overlapping with the capacitor lines CL1 to CLn. The capacitor voltage VCS is constantly applied to the capacitor lines CL1 to CLn. A variable common voltage VCOM is constantly applied to all the common electrodes for each line.

  The gate driver 103 is configured by an n-stage shift register corresponding to the number of pixels in the vertical direction of the liquid crystal panel, and the signals Φ1, Φ2, CK1, ¬CK1, and start in the control signal group GCNT supplied from the liquid crystal controller 101. According to the signal IN, any one of the gate lines GL1 to GLn is sequentially selected to be active (high level). The configuration of the gate driver 103 will be described later in detail.

  As shown in FIG. 4, the drain driver 104 includes a shift register 104a, a level shifter 104b, a sample hold buffer 104c, and a multiplexer 104d.

  The shift register 104a has an m-stage configuration corresponding to the number of pixels in the horizontal direction of the liquid crystal panel 102, and receives analog clock signals CLK, an inverted clock signal ¬CLK, and a start signal IND included in the control signal group DCNT. A sampling signal for sampling the signal is generated. The level shifter 104b is a circuit for converting the sampling signal into the operation level of the sample hold buffer 104c.

  The multiplexer 104d aligns and outputs the analog video signals SR2, SG2, and SB2 from the level shifter 113 in the order corresponding to the RGB arrangement of the pixels of each line based on the arrangement signal AR in the control signal group DCNT. The sample hold buffer 104c samples and holds the analog video signals SR2, SG2, and SB2 based on the sampling signal from the level shifter 104b, amplifies them by the buffer, and outputs them to the drain lines DL1 to DLm.

  Hereinafter, the gate driver 103 of FIG. 3 will be described in detail with reference to the circuit diagram of FIG. Each stage RS3 (i) (i = 1, 2,..., N, where n is a positive integer) of the gate driver 103 includes five n-channel MOS field effect transistors (hereinafter referred to as n-MOS) 201. , 202, 203, 205, 206. The semiconductor layers of the n-MOSs 201, 202, 203, 205, and 206 are made of amorphous silicon or polysilicon. The n-MOSs 201, 202, 203, 205, 206 may be formed together with the TFT 102 a of the display unit 10.

  However, in the odd-numbered stages RS1 (i) (i = 1, 3,...) And the even-numbered stages RS1 (i) (i = 2, 4,...) Of the gate driver 103, the gates of the n-MOS 201 and The signals applied to the drain of the n-MOS 205 are different from each other. That is, in the odd-numbered stage, the signal Φ1 is applied to the gate of the n-MOS 201, and the signal CK1 is applied to the drain of the n-MOS 205. In the even stages, the signal Φ2 is applied to the gate of the n-MOS 201, and the signal ¬CK1 is applied to the drain of the n-MOS 205.

  The signal Φ1 rises alternately when the signal CK1 is at a low level, and the signal Φ2 alternately rises when the signal CK1 is at a high level (ie, the signal ¬CK1 is at a low level), and the gates of the odd-numbered n-MOS 201 and the even-numbered stages. Applied to the gate of the n-MOS 201.

  Hereinafter, the configuration and function of the odd-numbered stage RS1 (1) will be described using the first stage RS1 (1) as an example. In the first stage RS1 (1) of the shift register, the signal Φ1 is applied to the gate of the n-MOS 201, and the start signal IN is applied to the drain. When the gate of the n-MOS 201 is turned on, currents flowing between the drain and the source charge the wiring capacitances C2 and C5 formed in the wiring between the source of the n-MOS 201 and the gates of the n-MOSs 202 and 205, respectively. After the n-MOS 201 is turned off, the wiring capacitors C2 and C5 are held at a high level until the signal Φ1 is next applied and the n-MOS 201 is turned on.

  A reference voltage Vdd is applied to the gate and drain of the n-MOS 203, and the n-MOS 203 is always in an on state. When the wiring capacitor C2 is not charged and the n-MOS 202 is turned off, the reference voltage Vdd is charged to the wiring capacitor C6 formed in the wiring between the n-MOS 206 and the gate. When the wiring capacitor C <b> 2 is charged, the n-MOS 202 is turned on, and a through current flows between the drain and source of the n-MOS 202. At this time, since the n-MOSs 202 and 203 have an EE type configuration, the n-MOS 203 does not become a complete off-resistance, so the wiring capacitance C6 may not be completely discharged. The voltage is sufficiently lower than the threshold voltage Vth.

  The signal CK1 is supplied to the drain of the n-MOS 205, and when the signal CK1 is at a high level, the wiring capacitance C1 formed in the wiring between the drain of the second-stage n-MOS 201 is charged. As a result, a high-level output signal OUT1 is output from the output terminal OT1 of the first stage RS1 (1).

  At this time, since the signal Φ1 is at a low level, the n-MOS 201 is in an off state, and thus the wiring capacitor C5 is kept charged by the start signal IN. The n-MOS 205 outputs to the output terminal OT1 to increase the storage capacity between its gate and source, and according to this increase, the gate voltage of the n-MOS 205 is such that the current flowing between its drain and source is a saturation current. Charged up until. Then, as the gate voltage of the n-MOS 205 rises, the potential of the output signal OUT1 rises, the n-MOS 205 becomes fully on-resistance, and the level of the signal CK1 is output as it is with almost no attenuation as the level of the output signal OUT1. Is done. Then, while the output signal OUT1 is being output, the signal Φ2 is applied to the gate of the n-MOS 201 at the next stage, and the wiring capacitors C2 and C5 at the next stage are charged. When the signal CK1 changes from the high level to the low level, the first-stage output signal OUT1 output from the output terminal OT1 also becomes the low level.

  The even stage RS1 (i) is substantially the same as the odd stage RS3 (1) if the signal Φ1 is replaced with the signal Φ2, the signal CK1 is replaced with ¬CK1, and the signal ¬CK1 is replaced with CK1. However, the output signals OUT1 to OUT (n−1) of the previous stage are supplied to the n-MOS 201 of the stage RS1 (i) after the second stage (both even and odd stages). Since the gate voltage of the n-MOS 205 in each stage is saturated by the wiring capacitance C5 held between the n-MOSs 201 and 205 and the signal CK1 or ¬CK1, the output signals OUT1 to OUTn are gradually reduced. There is nothing.

  The wiring capacitors C2 and C5 are discharged via the n-MOS 201 and the previous n-MOS 206 when the signal Φ1 (in the case of an odd number) and the signal Φ2 (in the case of an even number) are subsequently set to a high level. Is done. Thereafter, the wiring capacities C2 and C5 of each stage RS (i) are not charged until the signal Φ1 or the signal Φ2 becomes high level in the same horizontal period within the next vertical period, and the wiring capacity C6 is never discharged. As a result, the n-MOS 206 remains on until that time, so that even if the signal CK1 or the signal ¬CK1 becomes high level, the wiring capacitance C1 is not discharged, and the output terminals OT1, OT2,. The output signals OUT1, OUT2,... Output from are not at a high level.

  The operation of the digital still camera according to this embodiment will be described below. When the mode of the digital still camera is set to the photographing mode (monitoring mode and image recording mode) by the mode setting key 12a, charges are accumulated in each pixel of the CCD 21 in accordance with the image formed by the lens. The The CCD 21 generates an electric signal Se corresponding to the electric charge accumulated in each pixel in accordance with the drive signal supplied from the vertical driver 24 and sequentially supplies it to the sample hold circuit 22.

  The analog electric signal Se ′ of the effective portion of the electric signal Se is input from the sample and hold circuit 22 to the A / D converter 23, converted into digital data Sd by the A / D converter 23, and the color process circuit 26. To be supplied. In the color process circuit 26, YUV data that is luminance / color difference digital data is generated from the digital data Sd and supplied to the DMA controller 27. Then, the DMA controller 27 sequentially writes YUV data to the DRAM 28.

  When YUV data for one frame is written, the DMA controller 27 controlled by the CPU 31 transfers the YUV data for each frame from the DRAM 28 to the VRAM 34 via the VRAM controller 33. Further, the digital video encoder 35 reads out one frame of YUV data from the VRAM 34 via the VRAM controller 33 at regular intervals in a line sequential manner, generates an analog video signal Sa, and outputs the analog video signal Sa to the display unit 10. At this time, the display unit 10 operates as described later and displays an image captured by the lens.

  Here, when the shutter key 12b is operated by the user, the transfer operation of the timing generator 25 and the color process circuit 26 is stopped under the control of the CPU 31 in response to the corresponding command. The electric signal Se for the last one frame is converted into YUV data through the sample and hold circuit 22, the A / D converter 23, and the color process circuit 26, and is written in the DRAM 28. The YUV data for one frame is input to the image compression / decompression circuit 32 by the DMA controller 27 and compressed. The compressed data is stored in the recording memory 30.

  On the other hand, when the mode of the digital still camera is set to the playback mode by the mode setting key 12a, the CPU 31 controls the DMA controller 27 to instruct by operating the “+” key 12c or the “−” key 12d. The compressed data is transferred from the recording memory 30 to the image compression / decompression circuit 32. The compressed data is decompressed by the image compression / decompression circuit 32 and written to the VRAM 34 under the control of the VRAM controller 33. Based on the YUV data written in the VRAM 34, an analog video signal Sa is generated by the digital video encoder 35 and output to the display unit 10. At this time, the display unit 10 operates as described later to display the recorded image selected by operating the “+” key 12 c or the “−” key 12 d.

  Regardless of the shooting mode or the playback mode, the analog video signal Sa is input to the chroma circuit 111 and is subjected to gamma correction by the chroma circuit 111 in the display unit 10. The signals SR1, SG1, and SB1, and the vertical synchronizing signal VD and the horizontal synchronizing signal HD are separated. The phase comparator 112 measures the horizontal timing based on the horizontal synchronization signal HD from the chroma circuit 111 and the phase comparison signal CKH from the liquid crystal controller 101, and outputs a predetermined timing signal to the liquid crystal controller 101.

  The liquid crystal controller 101 outputs a control signal group DCNT to the drain driver 104, outputs a control signal group GCNT to the gate driver 103, and further outputs a polarity inversion control signal CKF in response to the timing signal and the vertical synchronization signal VD. It outputs to 113. In accordance with the polarity inversion control signal CKF, the analog video signals SR1, SG1, SB1 output from the chroma circuit 111 are inverted by the level shifter 113 for each line or every frame. The analog video signals SR2, SG2, and SB2 whose polarities are appropriately inverted are input to the drain driver 104 in accordance with the control signal group DCNT.

  Here, the control signal group GCNT generated by the liquid crystal controller 101 includes a start signal IN, signals Φ1, Φ2, CK1, and ¬CK1, and each is supplied to the gate driver 103 at a timing shown in a timing chart described later. When the start signal IN in the control signal group GCNT generated by the liquid crystal controller 101 is supplied to the gate driver 103, the gate driver 103 starts its operation.

  FIG. 6 is a timing chart showing the operation of the gate driver 103. Between timings T0 and T1, a high level start signal IN is supplied from the liquid crystal controller 101 to the drain of the n-MOS 201 in the first stage. Next, during a certain period between timings T0 and T1, the signal Φ1 rises and the odd-stage n-MOS 201 is turned on. As a result, the first-stage wiring capacitors C2 and C5 are charged, and the signal level thereof becomes a high level.

  At this time, the potential of the gate of the first-stage n-MOS 202 becomes high level, and the first-stage n-MOS 202 is turned on. When the first-stage n-MOS 202 is off, the signal level of the wiring capacitor C6 is at a high level by the reference voltage Vdd supplied via the first-stage n-MOS 203. When the -MOS 202 is turned on, the reference voltage Vdd supplied via the first-stage n-MOS 203 is dropped to the ground. That is, the charge accumulated in the first-stage wiring capacitor C6 is discharged, the signal level becomes low, and the first-stage n-MOS 206 is turned off.

  At the same time, the potential of the gate of the first-stage n-MOS 205 becomes high level, and the first-stage n-MOS 205 is also turned on. As described above, when the signal levels of the wiring capacitors C2 and C5 in the first stage are high and the signal level of the wiring capacitor C6 is low, the signal Φ1 rises between timings T2 and T3. This continues until the wiring capacitors C2 and C5 are discharged via the first-stage n-MOS 201.

  Next, at timing T1, the signal CK1 becomes high level, and at the same time, the signal ¬CK1 becomes low level. Here, since the first-stage n-MOS 205 is on and the first-stage n-MOS 206 is off, a high-level output signal OUT1 is output from the first-stage output terminal OT1, and the first stage n-MOS 205 is off. It is supplied to the drain of the two-stage n-MOS 201. Here, when the high level voltage of the signal CK1 is VH, the gate voltage of the first-stage n-MOS 205 is increased with the boosting of the output signal OUT1, and the drain current flowing through the first-stage n-MOS 205 is saturated. The output signal OUT1 becomes the voltage VH without being attenuated. The output signal OUT1 becomes low level when the signal CK1 changes to low level at the timing T2.

  On the other hand, even if the signal Φ1 rises between the timings T0 and T1, a high-level signal is not supplied to the drains of the n-MOS 201 in the third and subsequent stages even in the odd stages, so the odd stages in the third and subsequent stages. The wiring capacitances C2 and C5 are not charged at this time. Therefore, the output signals OUT3, 5,... Remain at the low level even in the odd-numbered stages and after the third stage. Next, for a certain period between timings T1 and T2, the signal Φ2 rises, and the n-MOS 201 in the even-numbered stage is turned on. As a result, the output signal OUT1 is also charged to the wiring capacitors C2 and C5 in the second stage, and the signal level becomes high.

  At this time, the potential of the gate of the second-stage n-MOS 202 becomes high level, and the second-stage n-MOS 202 is turned on. When the second-stage n-MOS 202 is off, the signal level of the wiring capacitor C6 is at a high level by the reference voltage Vdd supplied via the second-stage n-MOS 203. When the -MOS 202 is turned on, the reference voltage Vdd supplied via the second-stage n-MOS 203 is dropped to the ground. That is, the second-stage wiring capacitance C6 is discharged, the signal level thereof becomes low level, and the second-stage n-MOS 206 is turned off.

  At the same time, the potential of the gate of the second-stage n-MOS 205 becomes high level, and the second-stage n-MOS 205 is also turned on. As described above, when the signal levels of the second-stage wiring capacitors C2 and C5 are high and the signal level of the wiring capacitor C6 is low, the signal Φ2 rises between timings T3 and T4. This continues until the second-stage wiring capacitors C2 and C5 are discharged via the second-stage n-MOS 201 and the first-stage n-MOS 206.

  Next, at timing T2, the signal CK1 becomes low level, and at the same time, the signal ¬CK1 becomes high level. Here, since the second-stage n-MOS 205 is on and the second-stage n-MOS 206 is off, the high-level output signal OUT2 is output from the second-stage output terminal OT2, and the second-stage n-MOS 206 is also off. It is supplied to the drain of the three-stage n-MOS 201. Here, when the high level voltage of the signal ¬CK1 is VH, the gate voltage of the second-stage n-MOS 205 held by the second-stage wiring capacitance C5 is increased with the boosting of the output signal OUT2, and the second-stage wiring capacitance C5 is increased. The drain current flowing through the n-MOS 205 is saturated, and the output signal OUT2 becomes the voltage VH with almost no attenuation. The output signal OUT2 becomes low level when the signal CK1 becomes low level at timing T3.

  On the other hand, even if the signal Φ2 rises between the timings T1 and T2, since the high level signal is not supplied to the drains of the n-MOSs 201 in the fourth and subsequent stages even in the even stages, the wiring capacitors C2 and C5 are charged. It will never be done. Therefore, the output signals OUT4, 6,... Remain at the low level even in the even stages and after the fourth stage.

  Similarly, any one of the output signal OUT1 of the first-stage output terminal OT1 to the output signal OUTn of the n-th output terminal OTn is sequentially set to the high level until the timing T (n + 1). The gate lines GL1 to GLn are selected corresponding to the output signals OUT1 to OUTn that are at the high level. Then, at the timing T0 of the next vertical period, the start signal IN is similarly supplied from the liquid crystal controller 101, and the same processing is repeated.

  Note that in the stage RS1 (i) in which the output signal OUTi has already passed a high level within one vertical period, a high level signal is supplied to the gate of the n-MOS 201 even if the signal Φ1 or Φ2 rises. Never happen. That is, within one vertical period, any one of the gate lines GL1 to GLn is sequentially selected.

  In addition, the drain driver 104 performs the following in accordance with the control signal group DCNT generated by the liquid crystal controller 101 during the period (one horizontal period) when any one of the gate lines GL1 to GLn is selected by the gate driver 103. Works.

  A clock signal CLK is sequentially supplied from the liquid crystal controller 101. At this time, a sampling signal is transferred to each stage by a start signal IND output for each gate line GL. The transferred sampling signal is converted into an operation level by the level shifter 104b and sequentially output. The analog video signals SR2, SG2, and SB2 are input to the multiplexer 104d in parallel, and are output after being arranged in the order corresponding to the RGB array of the pixels of each line based on the array signal AR in the control signal group DCNT. . Analog video signals SR2, SG2, and SB2 output from the multiplexer 104d are sequentially sampled in the sample hold buffer 104c in accordance with the sampling signal from the level shifter 104b, and are parallel to the drain lines DL1 to DLm via the internal buffer. Is output.

  The display signals supplied to the drain lines DL1 to DLm are written to the pixel capacitor 102b via the TFT 102a which is turned on according to the selection by the gate driver 103, and are held for one horizontal period.

  The display unit 10 writes a display signal in the pixel capacitor 102b of each pixel of the liquid crystal panel 102 by repeating the above operation. The alignment state of the liquid crystal changes according to the display signal, and an image in which each pixel is represented by “dark” or “bright” is displayed on the liquid crystal panel 102.

  As described above, in this embodiment, in each stage RS1 (i) in the gate driver 103 included in the display unit 10, the part immediately before the next stage is not configured as a so-called EE configuration. Therefore, the high levels of the signals CK1 and ˜CK1 can be output as the output signals OUT1 to OUTn almost as they are. For this reason, since the gate voltage output to the gate lines GL1 to GLn can be output to the TFT 102a without being reduced, it is possible that a failure display based on the displacement of the drain current of the TFT 102a caused by the displacement of the gate voltage of the TFT 102a occurs. Can be prevented.

[Second Embodiment]
The appearance and circuit configuration of the digital still camera according to this embodiment are substantially the same as those of the first embodiment. However, in the digital still camera of this embodiment, the control signal group GCNT supplied from the liquid crystal controller 101 to the gate driver includes the signal CK2 instead of the signal ¬CK1, and the signal CK2 It is supplied to the drain of the n-MOS 205 in the even-numbered stage RS1 (i) (i = 2, 4, 6,..., N−1 or n).

  The operation of the digital still camera according to this embodiment will be described below. In this embodiment, the liquid crystal controller 101 generates the signal CK2 as a signal included in the control signal group GCNT, and the operation of the gate driver 103 is caused by the difference in the signal included in the control signal group GCNT. Different from that of form.

  FIG. 7 is a timing chart showing the operation of the gate driver 103 in this embodiment.

  This operation is almost the same as that of the first embodiment described with reference to the timing chart of FIG. Between the timings T′1 and T′2, the period in which the signal CK1 is at the high level does not reach one horizontal period 1H, and the period in which the first stage output signal OUT1 is at the high level is also the signal CK1. It is limited to the period when is at a high level. The same applies to odd-numbered stages after the third stage.

  In the second stage, the signal CK <b> 2 is supplied to the drain of the n-MOS 205. In the second stage, the output signal OUT2 is at a high level only when the signal CK2 is substantially at a high level between timings T'2 and T'3. The same applies to even-numbered stages RS1 (i) after the fourth stage.

  As described above, in the digital still camera according to this embodiment, by using the signal CK2 instead of the signal ¬CK1, a signal is supplied to the drain of the n-MOS 205 at the odd and even stages of the gate driver 103. The period to be made is shorter than one horizontal period 1H. Therefore, the selection period of the gate lines GL1 to GLn by the gate driver 103 can be arbitrarily selected by changing the period during which the signals CK1 and CK2 are set to the high level.

[Third Embodiment]
The appearance and circuit configuration of the digital still camera according to this embodiment are substantially the same as those of the first embodiment. However, the digital still camera of this embodiment is different from that of the first embodiment in the configuration of the gate driver 103. Accordingly, the signals Φ3 and Φ4 are added to the control signal group GCNT supplied from the liquid crystal controller 101 to the gate driver 103.

  FIG. 8 is a circuit diagram of the gate driver 103 in the digital still camera according to this embodiment. In each stage of the gate driver 103, an n-MOS 207 is added to the one shown in the first embodiment (FIG. 5), and the gate driver 103 is provided separately from each stage. Two n-MOSs 208 are provided.

  The n-MOS 208 is turned on when the signal Φ3 is at a high level, and supplies the start signal IN supplied from the liquid crystal controller 101 to the wiring capacitors C2 and C5 of the final stage RS2 (n). When the signal ¬CK1 becomes high level, the signal OUTn having substantially the same level as the signal ¬CK1 is output from the output terminal OTn of the final stage RS2 (n) to the gate line GLn. When the signal OUTn is output, the signal Φ4 is output, the n-MOS 207 of the stage RS2 (n−1) is turned on, and the signal OUTn is charged to the wiring capacitors C2 and C5 of the previous stage RS2 (n−1). The signal Φ3 output from the liquid crystal controller 101 turns on the n-MOS 207 of the even-numbered stage RS2 (2k) (where k is an integer of 1 or more), and then outputs the signal OUT (2k + 1) of the odd-numbered stage RS2 (2k + 1) which is the subsequent stage. Is charged to the wiring capacitors C2 and C5 of the even-numbered stage RS2 (2k). The signal Φ4 output from the liquid crystal controller 101 turns on the n-MOS 207 of the odd-numbered stage RS2 (2k−1) (where k is an integer of 1 or more) simultaneously with the switching of the n-MOS 208, and is the subsequent stage. The signal OUT (2k) of the even-numbered stage RS2 (2k) is charged to the wiring capacitors C2 and C5 of the odd-numbered stage RS2 (2k-1).

  If the final stage RS2 (n) is an even number stage, the liquid crystal controller 101 inverts the signal CK1 during forward operation and the signal CK1 during backward operation, which will be described later, with respect to the start signal IN, or The liquid crystal controller 101 is set so that the phase is shifted and the signal ¬CK1 during forward operation and the signal signal ¬CK1 during backward operation are inverted or shifted from each other. If the final stage RS2 (n) is an odd stage, the forward operation signal CK1 and the backward operation signal CK1 are in phase with each other with respect to the start signal IN. The liquid crystal controller 101 is set so that the signal ¬CK1 and the signal signal ¬CK1 during reverse operation are in phase with each other.

  Note that when the keys 12a to 12d of the key input unit 12 of the digital still camera according to this embodiment are selectively operated, the selection direction of the gate lines GL1 to GLn by the gate driver 103 can be set. Alternatively, instead of providing such a key, the selection direction of the gate lines GL1 to GLn may be set according to the angle of the lens unit 2 with respect to the camera body 1.

  The operation of the digital still camera according to this embodiment will be described below. In the present embodiment, the driving operation when the final stage RS2 (n) is an even stage is shown. The digital still camera according to this embodiment is different from that of the first embodiment only in the operation of the gate driver 103 and the liquid crystal controller 101 shown in FIG. 8, and the gate driver 103 operates in the forward direction (GL1, GL2 according to the setting). ,... GLn) and the gate lines GL1 to GLn are sequentially selected so as to be able to scan both in the reverse direction (GLn, GL (n−1),..., GL1).

  First, the forward scanning operation of the gate driver 103 in this embodiment will be described with reference to the timing chart of FIG. As shown in the figure, the signals Φ3 and Φ4 are always at a low level. For this reason, the n-MOSs 207 and 208 are always off, and the operation of the gate driver 103 in this case is substantially the same as that in the first embodiment shown in FIG.

  Next, the reverse operation of the gate driver 103 in this embodiment will be described with reference to the timing chart of FIG. As shown in the figure, the signals Φ1 and Φ2 are always at a low level. The timings at which the signals Φ3 and Φ4 become high level are staggered in the same manner as the signals Φ1 and Φ2 in the forward operation.

  When the signal Φ3 becomes high level between the timings T0 and T1, the start signal IN is charged to the wiring capacitors C2 and C5 of the final stage (n-th stage). At this time, the n-MOSs 202 to 206 in the n-th stage operate in the same manner as described in the first embodiment, and finally, when the signal ¬CK1 becomes high level between the timing T1 and the timing T2. The output signal OUTn of the stage becomes high level.

  When the signal Φ4 becomes a high level between the timings T1 and T2, the (n−1) th stage n-MOS 207 is turned on, and the output signal OUTn is the previous (n−1) th stage wiring capacitance C2, C5. Is charged. At this time, the n-MOSs 202 to 206 in the (n−1) th stage operate in the same manner as described in the first embodiment, and the signal CK1 is set to the high level between the timing T2 and the timing T3. Then, the output signal OUT (n-1) becomes high level and is output from the (n-1) th stage.

  Thereafter, by repeating the same operation, OUTn, OUT (n−1),..., OUT3, OUT2, OUT1 are sequentially set to the high level every horizontal period, and the gate lines GLn, GL (n−1) ,..., GL3, GL2, and GL1 are selected in this order.

  The operation of the digital still camera according to this embodiment will be described below with a specific example. Here, a case where the mode setting key 12a is set to the shooting mode will be described as an example.

  First, as shown in FIG. 11A, the operation of the digital still camera when shooting an image of an object on the front side as viewed from the photographer will be described. In this case, the photographer rotates the lens 2a of the lens unit unit 2 to the same side as the display unit 10 of the camera main body unit 1, that is, the lens unit unit 2 and the camera main unit unit 1 are moved to substantially 0 ° positions. To take an image. In this state, the keys 12a, 12b, 12c and 12d of the key input unit 12 are operated to set the scanning direction of the gate lines GL1 to GLn by the gate driver 103 to the forward direction. At this time, as shown in FIG. 11A, the arrangement of the pixels P (1, 1) to P (n, m) of the liquid crystal panel 102 matches the original vertical and horizontal directions of the liquid crystal panel 102. .

  In this state, the vertical direction of the lens unit 2 matches the vertical direction of the image. For this reason, the charges corresponding to the image formed by the lens 2a arranged in the lens unit 2 are horizontally scanned from left to right in FIG. 11A and vertically scanned so as to be vertically scanned from top to bottom. When the CCD 21 driven by the driver 24 is driven, it is taken into each pixel of the CCD 21. At this time, the electrical signal Se 'of the effective portion of each pixel output from the sample and hold circuit 22 is the same as this scanning order.

  On the other hand, in the display unit 10, the analog RGB signals SR2, SG2, SB2 generated based on the analog video signal Sa supplied from the digital video encoder 35 and level-shifted by the level shifter 113 are sequentially supplied to the multiplexer 104d. The The analog RGB signals SR2, SG2, and SB2 output from the multiplexer 104d are sequentially taken into the sample and hold buffer 104c along the horizontal arrow direction of the display unit 10 shown in FIG. Display signals are sequentially supplied to the drain lines DL1 to DLm every period 1H.

  On the other hand, according to the control signal group GCNT from the liquid crystal controller 101, the gate driver 103 sequentially selects the gate lines GL1, GL2,..., GLn from top to bottom as shown in FIG. . By such an operation, the liquid crystal panel 102 is driven, and an image in the same direction as the captured image as shown in FIG. 11B is displayed.

  Next, as shown in FIG. 12A, for example, the operation of the digital still camera when an image is taken when the subject is on the display unit 10 side so that the photographer itself becomes the subject will be described. In this case, the photographer places the lens 2a of the lens unit 2 on the same side as the display unit 10 of the camera body 1, that is, either the lens unit 2 or the camera body 1 with respect to the forward arrangement. The image is taken by rotating it up and down to approximately 180 °. Accordingly, as shown in FIG. 12A, the pixels P (1, 1) to P (n, m) of the liquid crystal panel 102 are opposite to the vertical and horizontal directions in FIG. Further, by operating the keys 12a, 12b, 12c and 12d of the key input unit 12, the scanning direction of the gate lines GL1 to GLn by the gate driver 103 is set in the reverse direction.

  In this state, the CCD 21 is driven so as to perform horizontal scanning from right to left in FIG. 12A and vertical scanning from bottom to top. As a result, the charge taken by each pixel of the CCD 21 in accordance with the image formed by the lens 2a disposed in the lens unit 2 is reversed up, down, left and right. When the analog video signal Sa is supplied from the digital video encoder 35 by the same operation as that in the forward driving, the analog RGB signals SR 2, SG 2, and SB 2 that are reversed in the vertical and horizontal directions are output from the level shifter 113. This is supplied to the multiplexer 104d. At this time, the multiplexer 104d outputs the analog RGB signals SR2, SG2, and SB2 to the sample and hold buffer 104c in the order indicated by the horizontal arrows in FIG. That is, if the analog RGB signals SR2, SG2, and SB2 supplied to the sample hold buffer 104c are output in the same direction as in FIG. 11B, as a result, the left and right directions in FIG. It is reversed. Then, the sample hold buffer 104c supplies display signals whose left and right directions are reversed to the data lines DL1, DL2,..., DLm.

  On the other hand, the gate driver 103 sequentially selects the gate lines GLn,..., GL2, GL1 in accordance with the control signal group GCNT from the liquid crystal controller 101 as shown in FIG. By such an operation, the liquid crystal panel 102 is driven, and a mirror image of the captured image as shown in FIG. 12B is displayed.

  As described above, in the digital still camera according to this embodiment, the scanning order of the gate lines GL1 to GLn is reversed by controlling the signals Φ1 to Φ4 supplied from the liquid crystal controller 101 to the gate driver 103. With this alone, it is possible to display an image on the liquid crystal panel 102 with a mirror-inverted image. Therefore, according to the digital still camera of this embodiment, even if the display unit 10 faces the lens 2a, the same image as the photographer can visually recognize the subject can be displayed on the display unit 10, and For example, when the photographer himself / herself is displayed on the display unit 10, when the display unit 10 faces the same side as the lens 2 a, mirror display can be performed without inverting the top and bottom of the image. It is not necessary to perform complicated control for reading out the image, and the configuration of the multiplexer 104d for displaying the image in a mirror-like and upside down manner can be simplified.

[Fourth Embodiment]
The circuit configuration of the digital still camera according to this embodiment is the configuration of the drain driver 104 ′ shown in FIG. 13, unlike the configurations of the drain driver 104 in the first and third embodiments. Accordingly, signals φ1, φ2, φ3, and φ4 are added to the signal group DCNT supplied from the liquid crystal controller 101 to the drain driver 104 ′.

  The circuit configuration of the shift register 104a 'according to this embodiment is an m-stage configuration as shown in FIG. The configuration of each stage rs1 (i) (i = 1, 2,..., M) is substantially the same as the configuration of the gate driver 103 in FIG. In the digital still camera according to this embodiment, a key for switching the selection direction of the gate lines GL1 to GLn by the gate driver 103 to the key input unit 12 and the selection direction of the drain lines DL1 to DLm by the drain driver 104 ′. It has a key for setting.

  The operation of the digital still camera according to this embodiment will be described below. The digital still camera according to this embodiment differs from that of the third embodiment only in the operation of the shift register 104a ′, and the clock signal CLK and the inverted clock signal ¬CLK supplied from the liquid crystal controller 101 are set according to the settings. The data is sequentially captured in either the forward direction (out1 to outm) or the reverse direction (outm to out1).

  First, the forward operation of the shift register 104a 'in this embodiment will be described with reference to the timing chart of FIG. As shown in the figure, the signals φ3 and φ4 are always at a low level. Therefore, the n-MOSs 307 and 308 are always turned off, and the operation of the shift register 104a ′ in this case is performed by the signals Φ1, Φ2, CK1, ¬CK1, and the signals Φ1, Φ2, CK1, ¬CK1, and the like described in the gate driver 103 of the third embodiment. If the start signal IN is replaced with φ1, φ2, ck1, ck1, and the start signal IND of the drain driver 104 ′, respectively, and if one vertical period in FIG. 6 is replaced with one horizontal period, it is shown in the third embodiment. This is substantially the same as the forward operation of the gate driver 103. In other words, the shift register 104a 'is driven in one horizontal period 1H in the driving performed by the gate driver 103 in FIG. 6 in one vertical period 1V. Therefore, since the n-MOSs 301 to 308 of the shift register 104 a ′ are driven at a higher frequency than the gate driver 103, a semiconductor layer made of polysilicon is desirable.

  Next, an operation in the reverse direction of the shift register 104a 'in this embodiment will be described with reference to a timing chart of FIG. As shown in the figure, the signals φ1 and φ2 are always at a low level. For this reason, the n-MOSs 307 and 308 are always turned off, and the operation of the shift register 104a ′ in this case is the same as the operations of Φ3, Φ4, CK1, ¬CK1, and the start signal IN described in the third embodiment. If the vertical signal is replaced with φ3, φ4, ck1, ck1, start signal IND, and one vertical period is replaced with one frame period as in the forward direction, the reverse operation of the gate driver 103 shown in the third embodiment Is substantially the same.

  The operation of the digital still camera according to this embodiment will be described below with a specific example. Here, a case where the mode setting key 12a is set to the shooting mode and shooting is performed in the state of FIG. 12A shown in the third embodiment will be described as an example. At this time, a display signal similar to that in the case of FIG. 12B shown in the third embodiment is supplied to the display unit 10.

  First, when the user operates the keys 12a, 12b, 12c, and 12d of the key input unit 12, the scanning direction of the gate lines GL1 to GLn by the gate driver 103 becomes the forward direction, and the drain lines DL1 to DLm by the drain driver 104 ′. A case where the scanning direction is set to the forward direction will be described.

  In this case, the operations of the gate driver 103 and the drain driver 104 ′ are substantially the same as in the case of FIG. 12B shown in the third embodiment, and an image as shown in FIG. Displayed on the panel 102.

  Next, when the user operates the keys 12a, 12b, 12c, and 12d of the key input unit 12 in a state where the lens 2a of the lens unit unit 2 is disposed on the opposite side of the display unit 10 of the camera body unit 1, the gate driver When the scanning direction of the gate lines GL1 to GLn by the gate 103 is set in the reverse direction and the scanning direction of the drain lines DL1 to DLm by the drain driver 104 ′ is set to the forward direction, as shown in FIG. This is substantially the same as the case of FIG. 12B shown in the third embodiment. If the lens 2a of the lens unit 2 is rotated to the same side as the display 10 of the camera body 1, the display is turned upside down in FIG.

  Next, when the user operates the keys 12a, 12b, 12c, and 12d of the key input unit 12 in a state where the lens 2a of the lens unit unit 2 is disposed on the opposite side of the display unit 10 of the camera body unit 1, the gate driver The case where the scanning direction of the gate lines GL1 to GLn by the 103 is set to the forward direction and the scanning direction of the drain lines DL1 to DLm by the drain driver 104 ′ is set to the reverse direction will be described.

  In this case, the method of taking in the analog RGB signals SR2, SG2, and SB2 supplied from the liquid crystal controller 101 is from right to left as indicated by the arrows in FIG. 17B, and the multiplexer 104d takes in the taken-in analog RGB signals. SR2, SG2, and SB2 are output in the forward direction in the same manner as in FIG. At this time, since the shift register 104a ′ sequentially outputs the sampling signals from DLm to DL1, the sample hold buffer 104c takes in the analog RGB signals SR2, SG2, SB2 in the order of DLm to DL1, and drain line DL1 every horizontal period. ~ Supply to DLm. On the other hand, the gate driver 103 sequentially selects the gate lines GL1, GL2,..., GLn in accordance with the control signal group GCNT from the liquid crystal controller 101, as shown in FIG. By such an operation, the liquid crystal panel 102 is driven, and a photographed image and a symmetrical image are displayed as shown in FIG. In other words, the same image as when the subject is seen in the mirror can be seen from the photographer side.

  Next, the user operates the keys 12a, 12b, 12c, and 12d of the key input unit 12 in a state where the lens 2a of the lens unit unit 2 is disposed on the same side as the display unit 10 of the camera main body unit 1, thereby the gate driver. The case where the scanning direction of the gate lines GL1 to GLn by 103 is set in the reverse direction and the scanning direction of the drain lines DL1 to DLm by the drain driver 104 ′ is set in the reverse direction will be described.

  In this case, the method of taking in the analog RGB signals SR2, SG2, SB2 supplied from the level shifter 113 is scanned as shown by the solid line arrows in FIG. 17C, and the drain driver 104 ′ SG2 and SB2 are supplied to the drain lines DLm to DL1 every horizontal period 1H. On the other hand, the gate driver 103 sequentially selects the gate lines GLn,..., GL2, GL1 in accordance with the control signal group GCNT from the liquid crystal controller 101 as shown in FIG. By such an operation, the liquid crystal panel 102 is driven, and a photographed image as shown in FIG. 17C is displayed. That is, the same image as when the photographer looks at the subject can be seen from the subject side.

  As described above, in the digital still camera according to this embodiment, the liquid crystal controller 101 controls the signals Φ1 to Φ4 supplied to the gate driver 103 so that the scanning order of the gate lines GL1 to GLn is forward or reverse. Either can be done. Further, by controlling the signals φ1 to φ4 supplied to the drain driver 104 ′, the direction in which the shift register 104a ′ of the drain driver 104 ′ takes in the analog RGB signals SR2, SG2, and SB2 is set to either the forward direction or the reverse forward direction. You can also With this alone, the direction of the image displayed on the liquid crystal panel 102 can be arbitrarily set. Therefore, according to the digital still camera of this embodiment, it is not necessary to perform complicated control for reading image data from the frame memory, and the liquid crystal controller 101 for displaying an image in an arbitrary direction. The configuration can be simplified.

[Fifth Embodiment]
The appearance and circuit configuration of the digital still camera according to this embodiment are substantially the same as those of the first embodiment. However, in the digital still camera of this embodiment, the configuration of the gate driver 103 is different from that of the first embodiment.

  FIG. 18 is a circuit diagram of the gate driver 103 in this embodiment. Each stage RS3 (i) (i = 1, 2,..., N, where n is a positive integer) of the gate driver 103 includes six n-MOSs 201 to 206. However, the odd-numbered stages RS3 (i) (i = 1, 3,...) And the even-numbered stages RS3 (i) (i = 2, 4,. The signals applied to the gate of the n-MOS 204 and the drain of the n-MOS 205 are different. That is, in the odd-numbered stage, the signal Φ1 is applied to the gate of the n-MOS 201, the signal ¬CK1 is applied to the gate of the n-MOS 204, and the signal CK1 is applied to the drain of the n-MOS 205. In the even stages, the signal Φ2 is applied to the gate of the n-MOS 201, the signal CK1 is applied to the gate of the n-MOS 204, and the signal ¬CK1 is applied to the drain of the n-MOS 205.

  The signal Φ1 rises alternately when the signal CK1 is at a low level and the signal Φ2 is alternately applied when the signal CK1 is at a high level, and is applied to the gates of the odd-numbered n-MOS 201 and the even-numbered n-MOS 201. The

  Hereinafter, the configuration and function of the odd-numbered stage RS3 (i) will be described using the first stage RS3 (1) as an example. In the first stage RS3 (1) of the shift register, the signal Φ1 is applied to the gate of the n-MOS 201, and the start signal IN is applied to the drain. When the gate of the n-MOS 201 is turned on, currents flowing between the drain and the source charge the wiring capacitances C2 and C5 formed in the wiring between the source of the n-MOS 201 and the gates of the n-MOSs 202 and 205, respectively. After the n-MOS 201 is turned off, the wiring capacitors C2 and C5 are held at a high level until the signal Φ1 is next applied and the n-MOS 201 is turned on.

  A reference voltage Vdd is applied to the gate and drain of the n-MOS 203, and the n-MOS 203 is always in an on state. When the wiring capacitor C2 is not charged and the n-MOS 202 is turned off, the wiring capacitor C6 formed in the wiring with the n-MOS 206 is charged. When the wiring capacitor C <b> 2 is charged, the n-MOS 202 is turned on, and a through current flows between the drain and source of the n-MOS 202. At this time, since the n-MOSs 202 and 203 have an EE type configuration, the n-MOS 203 does not become a complete off-resistance, so the wiring capacitance C6 may not be completely discharged. The voltage is sufficiently lower than the threshold voltage Vth.

  The signal CK1 is supplied to the drain of the n-MOS 205. When the signal CK1 is high level, the signal ¬CK1 is low level and the n-MOS 204 is turned off. The wiring capacitance C1 formed in the wiring between is charged. As a result, the high-level output signal OUT1 is output from the output terminal OT1 of the first stage RS3 (1).

  At this time, since the signal Φ1 is at a low level, the n-MOS 201 is in an off state, and thus the wiring capacitor C5 is kept charged by the start signal IN. The n-MOS 205 outputs to the output terminal OT1 to increase the storage capacity between its gate and source, and according to this increase, the gate voltage of the n-MOS 205 is such that the current flowing between its drain and source is a saturation current. Charged up until. Then, as the gate voltage of the n-MOS 205 rises, the potential of the output signal OUT1 rises, the n-MOS 205 becomes fully on-resistance, and the level of the signal CK1 is output as it is with almost no attenuation as the level of the output signal OUT1. Is done. Then, while the output signal OUT1 is being output, the signal Φ2 is applied to the gate of the n-MOS 201 at the next stage, and the wiring capacitors C2 and C5 at the next stage are charged.

  When the signal CK1 changes from high level to low level, the signal ¬CK1 becomes high level, and the gate of the n-MOS 204 is turned on. As a result, the wiring capacitor C1 is discharged, and the first-stage output signal OUT1 becomes low level. That is, in the first embodiment, the output signal OUT1 is set to the low level when the signal CK1 becomes the low level, but in the fifth embodiment, the signal is output to the gate of the n-MOS 204 in addition to that. Since the signal ¬CK1 becomes high level, the output signal OUT1 is forcibly set to low level.

  Here, the n-MOSs 204 and 205 do not have an EE configuration, and when the output signal OUT1 is at a high level, the n-MOS 205 has a complete on-resistance and the n-MOS 204 has a substantially complete off-resistance. Can do. Therefore, the high level of the signal CK1 is output as it is as the output signal OUT1.

  The even stage RS3 (i) is substantially the same as the odd stage rs (1) if the signal Φ1 is replaced with the signal Φ2, the signal CK1 is replaced with ¬CK1, and the signal ¬CK1 is replaced with CK1. However, any one of the output signals OUT1 to OUT (n−1) of the previous stage is supplied to the n-MOS 201 of the stage rs (i) after the second stage (both the even stage and the odd stage) instead of the start signal IN. Is done.

  The wiring capacitors C2 and C5 are discharged via the n-MOS 201 and the previous n-MOS 206 when the signal Φ1 (in the case of an odd number) and the signal Φ2 (in the case of an even number) are subsequently set to a high level. Is done. Thereafter, the wiring capacities C2 and C5 of each stage RS (i) are not charged until the signal Φ1 or the signal Φ2 becomes high level in the same horizontal period within the next vertical period, and the wiring capacity C6 is never discharged. As a result, the n-MOS 206 remains on until that time, so that even if the signal CK1 or the signal ¬CK1 becomes high level, the wiring capacitance C1 is not discharged, and the output terminals OT1, OT2,. The output signals OUT1, OUT2,... Output from are not at a high level.

  Hereinafter, the operation of the gate driver 103 in this embodiment will be described. In the digital still camera according to this embodiment, only the operation of the gate driver 103 is different from that of the first embodiment. However, as a result, the timing chart of the input signal and output signal to the gate driver 103 is the same as that shown in FIG. 6 in the first embodiment.

  Between timings T0 and T1, a high level start signal IN is supplied from the liquid crystal controller 101 to the drain of the n-MOS 201 in the first stage. Next, during a certain period between timings T0 and T1, the signal Φ1 rises and the odd-stage n-MOS 201 is turned on. As a result, the first-stage wiring capacitors C2 and C5 are charged, and the signal level thereof becomes a high level.

  At this time, the potential of the gate of the first-stage n-MOS 202 becomes high level, and the first-stage n-MOS 202 is turned on. When the first-stage n-MOS 202 is off, the signal level of the wiring capacitor C6 is at a high level by the reference voltage Vdd supplied via the first-stage n-MOS 203. -When the MOS 202 is turned on, the reference voltage Vdd supplied via the first-stage n-MOS 203 is dropped to the ground, the charge accumulated in the first-stage wiring capacitance C6 is discharged, and its signal level Becomes low level, and the first-stage n-MOS 206 is turned off.

  Further, the potential of the gate of the first stage n-MOS 205 becomes high level, and the first stage n-MOS 205 is also turned on. As described above, when the signal levels of the wiring capacitors C2 and C5 in the first stage are high and the signal level of the wiring capacitor C6 is low, the signal Φ1 rises between timings T2 and T3. This continues until the wiring capacitors C2 and C5 are discharged via the first-stage n-MOS 201.

  Next, at timing T1, the signal CK1 becomes high level, and at the same time, the signal ¬CK1 becomes low level. As a result, the first-stage n-MOS 204 is turned off, and the high-level signal CK1 is supplied to the drain of the first-stage n-MOS 205. Here, since the first-stage n-MOS 205 is on, the first-stage n-MOS 204 is off, and the first-stage n-MOS 206 is off, the high-level output signal OUT1 is output from the first-stage n-MOS 204. In addition to being output from the output terminal OT1, it is supplied to the drain of the second-stage n-MOS 201. The output signal OUT1 is kept at the high level until the signal ¬CK1 becomes the high level at the timing T2 and the first-stage n-MOS 204 is turned on. Here, when the high level voltage of the signal CK1 is VH, the gate voltage of the first-stage n-MOS 205 is increased with the boosting of the output signal OUT1, and the drain current flowing through the first-stage n-MOS 205 is saturated. The output signal OUT1 becomes the voltage VH without being attenuated.

  On the other hand, even if the signal Φ1 rises between the timings T0 and T1, a high-level signal is not supplied to the drains of the n-MOS 201 in the third and subsequent stages even in the odd stages, so the odd stages in the third and subsequent stages. The wiring capacitances C2 and C5 are not charged at this time. Therefore, the output signals OUT3, 5,... Remain at the low level even in the odd-numbered stages and after the third stage. Next, for a certain period between timings T1 and T2, the signal Φ2 rises, and the n-MOS 201 in the even-numbered stage is turned on. As a result, the second-stage wiring capacitors C2 and C5 are charged, and the signal level thereof becomes a high level.

  At this time, the potential of the gate of the second-stage n-MOS 202 becomes high level, and the second-stage n-MOS 202 is turned on. When the second-stage n-MOS 202 is off, the signal level of the wiring capacitor C6 is at a high level by the reference voltage Vdd supplied via the second-stage n-MOS 203. When the -MOS 202 is turned on, the reference voltage Vdd supplied via the second-stage n-MOS 203 is dropped to the ground, the second-stage wiring capacitance C6 is discharged, and the signal level becomes low level. The two-stage n-MOS 206 is turned off.

  At the same time, the potential of the gate of the second-stage n-MOS 205 becomes high level, and the second-stage n-MOS 205 is also turned on. As described above, when the signal levels of the second-stage wiring capacitors C2 and C5 are high and the signal level of the wiring capacitor C6 is low, the signal Φ2 rises between timings T3 and T4. This continues until the second-stage wiring capacitors C2 and C5 are discharged via the second-stage n-MOS 201 and the first-stage n-MOS 206.

  Next, at timing T2, the signal CK1 becomes low level, and at the same time, the signal ¬CK1 becomes high level. As a result, the second-stage n-MOS 204 is turned off and a high-level signal ¬CK1 is supplied to the drain of the second-stage n-MOS 205. Here, since the second-stage n-MOS 205 is on and the second-stage n-MOS 206 is off, a high-level output signal OUT2 is output from the second-stage output terminal OT2, and It is supplied to the drain of the three-stage n-MOS 201. The output signal OUT2 is kept at a high level until the signal CK1 becomes a high level at timing T3 and the second-stage n-MOS 204 is turned on. Here, when the high level voltage of the signal ¬CK1 is VH, the gate voltage of the second stage n-MOS 205 is increased with the boost of the output signal OUT2, and the drain current flowing through the second stage n-MOS 205 is saturated, The output signal OUT2 becomes the voltage VH with almost no attenuation.

  On the other hand, even if the signal Φ2 rises between the timings T1 and T2, since the high level signal is not supplied to the drains of the n-MOSs 201 in the fourth and subsequent stages even in the even stages, the wiring capacitors C2 and C5 are charged. It will never be done. Therefore, the output signals OUT4, 6,... Remain at the low level even in the even stages and after the fourth stage.

  Similarly, any one of the output signal OUT1 of the first-stage output terminal OT1 to the output signal OUTn of the n-th output terminal OTn is sequentially set to the high level until the timing T (n + 1). The gate lines GL1 to GLn are selected corresponding to the output signals OUT1 to OUTn that are at the high level. Then, at the timing T0 of the next vertical period, the start signal IN is similarly supplied from the liquid crystal controller 101, and the same processing is repeated.

  As described above, in this embodiment, in each stage RS3 (i) in the gate driver 103 included in the display unit 10, the n-MOSs 204 and 205 immediately before the next stage are not configured as an EE. For this reason, the off-resistance of the n-MOS 205 and the on-resistance of the n-MOS 204 can be achieved almost completely.

  Further, since the wiring capacitance C5 is held, the n-MOS 205 outputs to the output terminal OT, thereby increasing the storage capacitance between its gate and source, and the gate voltage of the n-MOS 205 is increased according to this increase. It is charged up until the current flowing between the drain and source reaches a saturation current. As the gate voltage of the n-MOS 205 rises, the potential of the output signal OUT rises, the n-MOS 205 becomes fully on-resistance, and the high level of the signal CK1 can be output almost as it is as the output signal OUT. For this reason, since the gate voltage output to the gate lines GL1 to GLn can be output to the TFT 102a without decreasing, it is possible to prevent a failure display based on the displacement of the drain current of the TFT 102a due to the displacement of the gate voltage. .

  Further, in the fifth embodiment, similarly to the second embodiment, the signal CK2 can be output instead of the signal ¬CK1 in FIG. 18 and driven by a waveform chart as shown in FIG.

[Sixth Embodiment]
The appearance and circuit configuration of the digital still camera according to this embodiment are substantially the same as those of the first embodiment. However, the digital still camera of this embodiment is different from that of the first embodiment in the configuration of the gate driver 103. In accordance with this, CK2 and ¬CK2 are added to the signal group GCNT supplied from the liquid crystal controller 101 to the gate driver 103.

  FIG. 19 is a circuit diagram of the gate driver 103 in the digital still camera according to this embodiment. Each stage RS4 (i) (i = 1, 2,..., N, where n is a positive integer) of the gate driver 103 includes six n-MOSs 201 to 206. In this embodiment, the gate driver 103 is different from that of the fifth embodiment in the even-numbered stages RS4 (i) (i = 2, 4,..., N−1 or n). The gate is supplied with the signal ¬CK2 instead of the signal CK1, and the drain of the n-MOS 205 is supplied with the signal CK2 instead of the signal ¬CK1.

  The operation of the digital still camera according to this embodiment will be described below. In the digital still camera according to this embodiment, only the operation of the gate driver 103 shown in FIG. 19 is different from that of the first embodiment. The operation of the gate driver 103 according to this embodiment will be described with reference to the timing chart of FIG.

  This operation is almost the same as that of the first embodiment described with reference to the timing chart of FIG. Between the timings T′1 and T′2, the period in which the signal CK1 is at the high level does not reach one horizontal period 1H, and the period in which the first stage output signal OUT1 is at the high level is also the signal CK1. It is limited to the period when is high. The same applies to odd-numbered stages after the third stage.

  In the second stage, the signal CK2 is supplied to the drain of the n-MOS 205, and the signal ¬CK2 is supplied to the gate of the n-MOS 204. The period during which the signal CK1 is at a high level does not reach one horizontal period 1H. In the second stage, when the signal CK2 is at the high level between the timings T′2 and T′3, the output signal OUT2 is at the high level. The same applies to even-numbered stages RS4 (i) after the fourth stage.

  As described above, in the digital still camera according to this embodiment, by using the signals CK1 and CK2 (and their inverted signals), the gates of the n-MOS 204 and n The period during which a signal is supplied to the drain of the MOS 205 is shorter than one horizontal period 1H. Therefore, the selection period of the gate lines GL1 to GLn by the gate driver 103 can be arbitrarily selected by changing the period during which the signals CK1 and CK2 are set to the high level.

[Seventh embodiment]
The appearance and circuit configuration of the digital still camera according to this embodiment are substantially the same as those of the third embodiment. However, in the digital still camera of this embodiment, the configuration of the gate driver 103 is different from that of the third embodiment.

  FIG. 21 is a circuit diagram of the gate driver 103 in the digital still camera according to this embodiment. In each stage of the gate driver 103, an n-MOS 207 is added to the one shown in the fifth embodiment (FIG. 18), and the gate driver 103 is a 1 provided separately from each stage. There are two n-MOSs 208.

  The n-MOS 208 is turned on when the signal Φ3 is at the high level, and supplies the start signal IN supplied from the liquid crystal controller 101 to the wiring capacitors C2 and C5 of the final stage RS5 (n). When the signal ¬CK1 becomes high level, the signal OUTn having substantially the same level as the signal ¬CK1 is output from the final stage RS5 (n). When the signal OUTn is output, the signal Φ4 is output, the n-MOS 207 of the stage RS5 (n−1) is turned on, and the signal OUTn is charged to the wiring capacitors C2 and C5 of the previous stage RS5 (n−1). The signal Φ3 output from the liquid crystal controller 101 turns on the n-MOS 207 of the even-numbered stage RS5 (2k) (where k is an integer of 1 or more), and then outputs the signal OUT (2k + 1) of the odd-numbered stage RS5 (2k + 1) as the subsequent stage. ) To the wiring capacitors C2 and C5 of the even-numbered stage RS5 (2k). The signal Φ4 output from the liquid crystal controller 101 turns on the n-MOS 207 of the odd-numbered stage RS (2k−1) (where k is an integer of 1 or more) simultaneously with the switching of the n-MOS 208, and is the subsequent stage. The signal OUT (2k) of the even-numbered stage RS5 (2k) is charged to the wiring capacitors C2 and C5 of the odd-numbered stage RS5 (2k-1).

  If the final stage RS5 (n) is an even stage, the liquid crystal controller 101 inverts the phase CK1 during the forward operation and the signal CK1 during the backward operation with respect to the start signal IN, respectively, or changes the phase. The liquid crystal controller 101 is set so that the signal ¬CK1 during forward operation and the signal ¬CK1 during backward operation are inverted or shifted from each other. If the final stage RS5 (n) is an odd stage, the signal CK1 during forward operation and the signal CK1 during reverse operation are in phase with each other with respect to the start signal IN. The liquid crystal controller 101 is set so that the signal ¬CK1 and the signal ¬CK1 during reverse operation are in phase with each other.

  The operation of the digital still camera according to this embodiment will be described below. In this embodiment, the operation of the gate driver 103 is “operating in the same way as described in the first embodiment” in the description of the third embodiment in both the forward and reverse directions. Is rewritten as “operating in the same manner as described in the fifth embodiment”. Except this, everything is the same as that described in the third embodiment.

  As described above, in the digital still camera according to this embodiment, the liquid crystal controller 101 controls the signals Φ1 to Φ4 supplied to the gate driver 103, so that the scanning order of the gate lines GL1 to GLn is forward or reverse. Can be any of them. With this alone, it is possible to display an image on the liquid crystal panel 102 with a mirror-inverted image. Therefore, according to the digital still camera of this embodiment, even if the display unit 10 faces the lens 2a, the same image as the photographer can visually recognize the subject can be displayed on the display unit 10, and For example, when the photographer himself / herself is displayed on the display unit 10, when the display unit 10 faces the same side as the lens 2 a, mirror display can be performed without inverting the top and bottom of the image. It is not necessary to perform complicated control for reading out the image, and the configuration of the multiplexer 104d for displaying the image in a mirror-like and upside down manner can be simplified.

[Eighth Embodiment]
The appearance and circuit configuration of the digital still camera according to this embodiment are substantially the same as those of the fourth embodiment. However, in the digital still camera of this embodiment, the configuration of the gate driver 103 is different from that of the fourth embodiment, and the configuration of the shift register 104a ′ in the drain driver 104 ′ is that of the fourth embodiment. And different.

  In this embodiment, the circuit configuration of the gate driver 103 is the same as that shown in the seventh embodiment (FIG. 21). The shift register 104a 'has an m-stage configuration as shown in FIG. The configuration of each stage rs2 (i) (i = 1, 2,..., M) is substantially the same as the configuration of the gate driver 103 in FIG.

  The operation of the digital still camera according to this embodiment will be described below. In this embodiment, the signals Φ1, Φ2, CK1, ¬CK1, and the start signal IN are changed to φ1, φ2, ck1, ¬ck1, and the start signal IND of the drain driver 104 ′, respectively, and one vertical period is set to one horizontal period. If one horizontal period is replaced with one vertical period, the operation of the gate driver 103 shown in the seventh embodiment is substantially the same in both the forward and reverse directions.

  As described above, in the digital still camera according to this embodiment, the liquid crystal controller 101 controls the signals Φ1 to Φ4 supplied to the gate driver 103 so that the scanning order of the gate lines GL1 to GLn is forward or reverse. Either can be done. Further, by controlling the signals φ1 to φ4 supplied to the drain driver 104 ′, the direction in which the shift register 104a ′ of the drain driver 104 ′ takes in the analog RGB signals SR2, SG2, and SB2 is set to either the forward direction or the reverse forward direction. You can also With this alone, the direction of the image displayed on the liquid crystal panel 102 can be arbitrarily set. Therefore, according to the digital still camera of this embodiment, it is not necessary to perform complicated control for reading image data from the frame memory, and the liquid crystal controller 101 for displaying an image in an arbitrary direction. The configuration can be simplified.

[Modification of Embodiment]
The present invention is not limited to the above first to eighth embodiments, and various modifications and applications are possible. Hereinafter, modifications of the first to eighth embodiments will be described.

  In the first to eighth embodiments, the gates and drains of the n-MOSs 203 and 303 are supplied from the voltage source in each stage of the shift registers 104a and 104a ′ of the gate driver 103 or the drain drivers 104 and 104 ′. Although a load is provided by supplying a voltage, a resistor may be used instead.

  In the second and sixth embodiments, only the gate driver 103 is configured differently from the first and third embodiments, and the signal CK2 (and the signal ¬CK2) is supplied from the liquid crystal controller 101. It was. The shift register 104a of the drain driver 104 of the first, second, fifth, and sixth embodiments may be configured as shown in FIG. In this case, the shift register 104a outputs the output signals out1 to outm in one horizontal period 1H. In the shift registers of the gate driver 103 and the drain driver 104 that operate in both the forward and reverse directions as described in the third, fourth, seventh, and eighth embodiments, the second, As in the fifth embodiment, signals having different timings may be supplied to even stages and odd stages. In the present invention, the combination of the shift register 104a of the gate driver 103 and the drain driver 104 can be arbitrarily selected from those described above.

  In the first to eighth embodiments, n-channel MOS field effect transistors are used as elements constituting the shift registers 104a and 104a ′ of the gate driver 103 or the drain drivers 104 and 104 ′. Can be used, a p-channel MOS field effect transistor may be used. Further, a field effect transistor other than the MOS type may be used.

  In the above first to eighth embodiments, the gate driver 103 (including the reverse direction in the third and fourth embodiments) does not skip the gate lines GL1 to GLn and operates one line at a time. We selected sequentially. On the other hand, for example, when one frame is composed of two fields of even-numbered gate line scanning and odd-numbered gate line scanning and a jumping operation is performed within one field, FIG. 5, FIG. 8, FIG. 18 or FIG. The circuits shown in the figure may be provided corresponding to two fields, and a start signal may be supplied to each of the circuits in accordance with the fields to perform interlace scanning.

  In the above first to eighth embodiments, the liquid crystal display device is used for the display unit 10 for displaying an image captured by the CCD 21 or an image recorded in the recording memory 30. However, other flat panel displays such as an organic / inorganic electroluminescence display device, a plasma display device, or a field emission display can be used for the display unit 10. In any of these cases, the gate driver and drain driver shown in the first to eighth embodiments can be used as a drive circuit. In addition, the circuit illustrated in FIG. 5, FIG. 8, FIG. 18, or FIG. 19 can be used as a shift register in applications other than the driver circuit of the display device.

  In the first to eighth embodiments, the case where the present invention is applied to a digital still camera has been described. However, the present invention can be similarly applied to a video camera using a liquid crystal display device or the like as a finder. Also in this case, when the gate drivers shown in the third and seventh embodiments are used, mirror display is possible, and the gate driver and drain driver 104 shown in the fourth and eighth embodiments can be used. When used, it is possible to display the image by arbitrarily setting the top, bottom, left and right of the image. In addition, the present invention may be applied to display devices of other devices (such as portable terminals).

  In the above first to eighth embodiments, the case where the present invention is applied to the shift registers 104 a and 104 a ′ of the gate driver 103 or the drain driver 104 included in the display unit 10 has been described. However, the present invention can also be used to read out image data from an image sensor in which photosensors are arranged in a matrix.

  FIG. 23 is a diagram showing such an image sensor and its drive system. The photo sensor array 500 includes photodiodes 501 as light receiving elements and n-MOSs 502 connected to the photodiodes 501 arranged in a matrix. Each gate of the n-MOS 502 is a gate line provided for each row. It is connected to the gate driver via GL, and the drain of the n-MOS 502 is connected to the priming transfer unit 520 via the drain line DL provided for each column. The priming transfer unit 520 injects the charges supplied from the photodiodes 501 in the selected row through the n-MOS 502 and the drain line DL into the horizontal scanning CCD 530. Then, the horizontal scanning CCD 530 horizontally scans the charge injected from the drain line DL and outputs an imaging signal from the output terminal OT.

  Here, as the gate driver 510, the one described in FIGS. 5, 8, 18, 19, or 21 described in the first to eighth embodiments can be applied. In particular, when the gate driver 510 shown in FIG. 8 or FIG. 21 is applied, the selection order of the gate lines GL is reversed by simply changing the control signal supplied to the gate driver 510. For this reason, it is possible to easily obtain a mirror image that is upside down as an image based on the imaging signal output from the output terminal OT, for example, pattern matching that compares a captured image with an image stored in advance in a memory, etc. Can be applied to.

1 is a perspective view showing an external appearance of a digital still camera according to a first embodiment of the present invention. It is a block diagram which shows the circuit structure of the digital still camera of FIG. It is a block diagram which shows the structure of the display part of FIG. 1, FIG. FIG. 4 is a block diagram illustrating a configuration of the drain driver of FIG. 3. FIG. 4 is a circuit diagram of the gate driver of FIG. 3. It is a timing chart which shows operation | movement of the gate driver concerning the 1st Embodiment of this invention. It is a timing chart which shows operation | movement of the gate driver concerning the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the gate driver in the digital still camera concerning the 3rd Embodiment of this invention. It is a timing chart which shows the forward direction operation | movement of the gate driver concerning the 3rd Embodiment of this invention. It is a timing chart which shows the reverse direction operation | movement of the gate driver concerning the 3rd Embodiment of this invention. It is a figure which shows the operation example of the forward direction of the digital still camera in the 3rd Embodiment of this invention, (a) is a imaging | photography state, (b) is along the scanning procedure at the time of imaging | photography, and the scanning procedure at the time of a display. Each display state of the display unit is shown. It is a figure which shows the operation example of the reverse direction of the digital still camera in the 3rd Embodiment of this invention, (a) is a imaging | photography state, (b) is along the scanning procedure at the time of imaging | photography, and the scanning procedure at the time of a display. Each display state of the display unit is shown. It is a block diagram which shows the structure of the drain driver of the 4th Embodiment of this invention. It is a circuit diagram which shows the shift register concerning the 4th Embodiment of this invention. It is a timing chart which shows the forward direction operation | movement of the shift register of the drain driver concerning the 4th Embodiment of this invention. It is a timing chart which shows the reverse direction operation | movement of the shift register of the drain driver concerning the 4th Embodiment of this invention. It is a figure which shows the operation example of the digital still camera in the 4th Embodiment of this invention, (a) is the display state of the display part in which a gate driver and a drain driver are both forward directions, (b) is a gate. (C) Scanning procedure when the gate driver and the drain driver are photographed in the reverse direction. The display state of the display unit in accordance with the scanning procedure at the time of display, (d) is the display of the display unit in accordance with the scanning procedure at the time of photographing in the reverse direction of the gate driver and the forward direction of the drain driver Each state is shown. It is a circuit diagram which shows the gate driver concerning the 5th Embodiment of this invention. It is a circuit diagram which shows the gate driver concerning the 6th Embodiment of this invention. It is a timing chart which shows operation | movement of the gate driver concerning the 6th Embodiment of this invention. It is a circuit diagram which shows the gate driver concerning the 7th Embodiment of this invention. It is a circuit diagram which shows the shift register concerning the 8th Embodiment of this invention. It is a figure which shows the image pick-up element concerning the deformation | transformation of embodiment of this invention, and its drive system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Camera body part 2 Lens unit part 2a Lens 10 Display part 11 Power key 12 Key input part 12a Mode setting key 12b Shutter key 12c "+" key 12d "-" key 21 CCD
22 Sample hold circuit 23 A / D converter 24 Vertical driver 25 Timing generator 26 Color process circuit 27 DMA controller 28 DRAM
29 Serial I / O terminal 30 Memory for recording 31 CPU
32 Image compression / decompression circuit 33 VRAM controller 34 VRAM
35 Video encoder 101 Liquid crystal controller 102 Liquid crystal panel 102a Thin film transistor 102b Pixel capacity 102c Compensation capacity 103 Gate driver 104 Drain driver 104a, 104a 'Shift register 104b Level shifter 104c Sample hold buffer 201-208 n channel MOS type field effect transistor 301-308 n channel MOS type field effect transistor 500 Photo sensor array 501 Photo diode 502 n channel MOS type field effect transistor 510 Gate driver 520 Call water transfer unit 530 Horizontal scanning CCD
C2, C5, C6, c2, c5, c6 Wiring capacitance GL, GL1 to GLn Gate line DL, DL1 to DLm Drain line OT, OT1 to OTn Output terminal ot1 to otm Output terminal

Claims (13)

A shift register having a plurality of stages, each stage of the shift register being
During forward operation, a first or second signal is supplied to the control terminal, a predetermined signal is supplied from one end of the current path, and is turned on by the first or second signal supplied to the control terminal. A first transistor that outputs the predetermined signal to the other end of the current path when
A predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal, and one end of the current path is connected to a signal source via a load, and is supplied to the control terminal. A second transistor for draining a signal supplied from a signal source to ground when turned on by a signal;
When the predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal and turned on by the predetermined signal supplied to the control terminal, the third or fourth signal A third transistor that inputs from one end of the current path and outputs to the other end;
A fourth transistor for discharging a predetermined signal output from the other end of the current path of the first transistor charged in the second transistor or the third transistor of the next stage to the ground ;
In the odd-numbered stages of the shift registers, the fifth signal is supplied to the control terminal during reverse operation, and is output from the other end of the current path of the third transistor in the subsequent stage. A fourth signal is supplied to one end of the current path, and when the supplied signal is turned on by the fifth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A fifth transistor to be supplied to the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor;
In the even stage among the stages of the shift register, the sixth signal is supplied to the control terminal during the backward operation, and the third signal output from the other end of the current path of the third transistor in the subsequent stage. Alternatively, when the fourth signal is supplied to one end of the current path, and the supplied predetermined signal is turned on by the sixth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A sixth transistor that supplies a control terminal of the even-numbered second transistor serving as a subsequent stage and a control terminal of the even-numbered third transistor ;
In the odd stage, during the forward operation, the first signal is supplied to the control terminal of the first transistor, and the third signal is supplied to one end of the current path of the third transistor,
In the even stage, during the forward operation, the second signal is supplied to the control terminal of the first transistor, and the fourth signal is supplied to one end of the current path of the third transistor,
In the first stage, during the forward operation, a signal from the outside is supplied as one end of the current path of the first transistor as the predetermined signal.
After the second stage, during the forward operation, the third transistor or the fourth signal output from the other end of the current path of the third transistor in the previous stage is the first transistor as the predetermined signal. is supplied to one end of the current path,
In the reverse operation, a predetermined signal output from the other end of the current path of the fifth transistor based on the fifth signal is generated from the first transistor of the odd-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor, Until the next transistor is turned on, the control terminal of the second transistor of the odd stage and the control terminal of the third transistor of the odd stage continue to be held,
In the reverse operation, a predetermined signal output from the other end of the current path of the sixth transistor based on the sixth signal is generated by the first transistor of the even-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the even-numbered second transistor and the control terminal of the even-numbered third transistor; Between the time when the first transistor is turned off and the time when the second transistor is turned on, the control terminal of the second transistor of the even-numbered stage and the control terminal of the third transistor of the even-numbered stage continue to be held.
A shift register characterized by that. During the forward operation, the predetermined signal output from the other end of the current path of the first transistor is the other end of the current path of the first transistor, the control terminal of the second transistor, and the It is stored in a wiring formed between the control terminal of the third transistor and the control terminal of the second transistor and the third transistor from when the first transistor is turned off until when it is turned on next time. The shift register according to claim 1, wherein the shift register continues to be held at a control terminal of the transistor. The level of each of the third and fourth signals is inverted at a predetermined period,
In the first and second signals, the level of one of the signals is inverted every half period of the level inversion period of the third or fourth signal for a part of the half period. The shift register according to claim 1 or 2, wherein Each stage of the shift register is supplied with a signal obtained by inverting the third or fourth signal at the control terminal, and is turned on by a signal obtained by inverting the third or fourth signal supplied to the control terminal. And a signal output from the other end of the current path of the third transistor is input from one end of the current path, and output from the other end to be discharged to ground. Item 4. The shift register according to any one of Items 1 to 3 . The shift register according to any one of claims 1 to 3 , wherein the fourth signal is a signal obtained by inverting the level of the third signal. Wherein each stage of the shift register of any of claims 1 to 5, further comprising an output terminal for outputting a signal outputted from the other end of the current path of said third transistor to the outside The shift register described in the paragraph. Each of the signals is a voltage signal,
The shift register according to any one of claims 1 to 6 , wherein each of the transistors is configured by the same channel field effect transistor. A display device including a shift register having a plurality of stages, each stage of the shift register includes:
During forward operation, a first or second signal is supplied to the control terminal, a predetermined signal is supplied from one end of the current path, and is turned on by the first or second signal supplied to the control terminal. A first transistor that outputs the predetermined signal to the other end of the current path when
A predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal, and one end of the current path is connected to a signal source via a load, and is supplied to the control terminal. A second transistor for draining a signal supplied from a signal source to ground when turned on by a signal;
When the predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal and turned on by the predetermined signal supplied to the control terminal, the third or fourth signal A third transistor that inputs from one end of the current path and outputs to the other end;
A fourth transistor for discharging a predetermined signal output from the other end of the current path of the first transistor charged in the second transistor or the third transistor of the next stage to the ground ;
In the odd-numbered stages of the shift registers, the fifth signal is supplied to the control terminal during reverse operation, and is output from the other end of the current path of the third transistor in the subsequent stage. A fourth signal is supplied to one end of the current path, and when the supplied signal is turned on by the fifth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A fifth transistor to be supplied to the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor;
In the even stage among the stages of the shift register, the sixth signal is supplied to the control terminal during the backward operation, and the third signal output from the other end of the current path of the third transistor in the subsequent stage. Alternatively, when the fourth signal is supplied to one end of the current path, and the supplied predetermined signal is turned on by the sixth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A shift register comprising: a sixth transistor that supplies a control terminal of the even-numbered second transistor and a control terminal of the even-numbered third transistor ; A display unit that is displayed according to the output of the third transistor,
Have
The shift register is
In the odd stage, during the forward operation, the first signal is supplied to the control terminal of the first transistor, and the third signal is supplied to one end of the current path of the third transistor,
In the even stage, during the forward operation, the second signal is supplied to the control terminal of the first transistor, and the fourth signal is supplied to one end of the current path of the third transistor,
In the first stage, during the forward operation, a signal from the outside is supplied as one end of the current path of the first transistor as the predetermined signal.
After the second stage, during the forward operation, the third transistor or the fourth signal output from the other end of the current path of the third transistor in the previous stage is the first transistor as the predetermined signal. is supplied to one end of the current path,
In the reverse operation, a predetermined signal output from the other end of the current path of the fifth transistor based on the fifth signal is generated from the first transistor of the odd-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor, Until the next transistor is turned on, the control terminal of the second transistor of the odd stage and the control terminal of the third transistor of the odd stage continue to be held,
In the reverse operation, a predetermined signal output from the other end of the current path of the sixth transistor based on the sixth signal is generated by the first transistor of the even-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the even-numbered second transistor and the control terminal of the even-numbered third transistor; Between the time when the first transistor is turned off and the time when the second transistor is turned on, the control terminal of the second transistor of the even-numbered stage and the control terminal of the third transistor of the even-numbered stage continue to be held.
A display device characterized by that. An image sensor in which pixels are arranged in a matrix and generates an image signal corresponding to light incident on each pixel;
A shift register having a plurality of stages shifts selection signals supplied from the outside and sequentially outputs the signals from each stage. The selection signals output from the respective stages cause the pixels of the image sensor to be arranged for each line of the matrix. Selection drive means to select;
Signal capturing means for capturing an image signal generated from a pixel of a line selected by the selection driving means;
The selection driving means includes selection control means for selecting and supplying a selection signal supplied from the outside to either the first stage or the last stage of the shift register,
The shift register is
During forward operation, a first or second signal is supplied to the control terminal, a predetermined signal is supplied from one end of the current path, and is turned on by the first or second signal supplied to the control terminal. A first transistor that outputs the predetermined signal to the other end of the current path when
A predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal, and one end of the current path is connected to a signal source via a load, and is supplied to the control terminal. A second transistor for draining a signal supplied from a signal source to ground when turned on by a signal;
When the predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal and turned on by the predetermined signal supplied to the control terminal, the third or fourth signal A third transistor that inputs from one end of the current path and outputs to the other end;
A fourth transistor for discharging a predetermined signal output from the other end of the current path of the first transistor charged in the second transistor or the third transistor of the next stage to the ground ;
In the odd-numbered stages of the shift registers, the fifth signal is supplied to the control terminal during reverse operation, and is output from the other end of the current path of the third transistor in the subsequent stage. A fourth signal is supplied to one end of the current path, and when the supplied signal is turned on by the fifth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A fifth transistor to be supplied to the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor;
In the even stage among the stages of the shift register, the sixth signal is supplied to the control terminal during the backward operation, and the third signal output from the other end of the current path of the third transistor in the subsequent stage. Alternatively, when the fourth signal is supplied to one end of the current path, and the supplied predetermined signal is turned on by the sixth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A sixth transistor that supplies a control terminal of the even-numbered second transistor serving as a subsequent stage and a control terminal of the even-numbered third transistor ;
In the odd stage, during the forward operation, the first signal is supplied to the control terminal of the first transistor, and the third signal is supplied to one end of the current path of the third transistor,
In the even stage, during the forward operation, the second signal is supplied to the control terminal of the first transistor, and the fourth signal is supplied to one end of the current path of the third transistor,
In the first stage, during the forward operation, a signal from the outside is supplied as one end of the current path of the first transistor as the predetermined signal.
After the second stage, during the forward operation, the third transistor or the fourth signal output from the other end of the current path of the third transistor in the previous stage is the first transistor as the predetermined signal. is supplied to one end of the current path,
In the reverse operation, a predetermined signal output from the other end of the current path of the fifth transistor based on the fifth signal is generated from the first transistor of the odd-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor, Until the next transistor is turned on, the control terminal of the second transistor of the odd stage and the control terminal of the third transistor of the odd stage continue to be held,
In the reverse operation, a predetermined signal output from the other end of the current path of the sixth transistor based on the sixth signal is generated by the first transistor of the even-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the even-numbered second transistor and the control terminal of the even-numbered third transistor; Between the time when the first transistor is turned off and the time when the second transistor is turned on, the control terminal of the second transistor of the even-numbered stage and the control terminal of the third transistor of the even-numbered stage continue to be held.
An image sensor driving apparatus characterized by the above. An image sensor in which pixels are arranged in a matrix and a display that displays an image corresponding to an image captured by the image sensor or an image corresponding to an image captured by the image sensor and recorded in an image memory With the device,
The display device
A display element in which pixels are arranged in a matrix;
The first shift register is composed of a plurality of stages. The selection signal supplied from the outside is shifted and sequentially output from each stage, and the pixels of the display element are arranged in the matrix by the selection signal output from each stage. A selection drive circuit to select for each line;
A signal drive circuit that captures an image signal supplied from the outside for one line of the display element, and supplies a signal corresponding to the captured image signal to the pixels of the line selected by the selection drive circuit;
A control circuit for controlling the selection drive circuit and the signal drive circuit,
The selection drive circuit includes a first selection control unit that selects and supplies an externally supplied selection signal to either the first stage or the last stage of the first shift register, and is fetched by each stage. Second selection control means for selecting whether to shift the selection signal to the preceding stage or to the subsequent stage,
The shift register is
During forward operation, a first or second signal is supplied to the control terminal, a predetermined signal is supplied from one end of the current path, and is turned on by the first or second signal supplied to the control terminal. A first transistor that outputs the predetermined signal to the other end of the current path when
A predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal, and one end of the current path is connected to a signal source via a load, and is supplied to the control terminal. A second transistor that drains a signal supplied from a signal source to ground when turned on by a signal;
When the predetermined signal output from the other end of the current path of the first transistor is supplied to the control terminal and turned on by the predetermined signal supplied to the control terminal, the third or fourth signal A third transistor that inputs from one end of the current path and outputs to the other end;
A fourth transistor for discharging a predetermined signal output from the other end of the current path of the first transistor charged in the second transistor or the third transistor of the next stage to the ground ;
In the odd-numbered stages of the shift registers, the fifth signal is supplied to the control terminal during operation in the reverse direction, and is output from the other end of the current path of the third transistor in the subsequent stage. The fourth signal is supplied to one end of the current path, and when the supplied signal is turned on by the fifth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A fifth transistor to be supplied to the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor;
In the even stage among the stages of the shift register, the sixth signal is supplied to the control terminal during the backward operation, and the third signal output from the other end of the current path of the third transistor in the subsequent stage. Alternatively, when the fourth signal is supplied to one end of the current path, and the supplied predetermined signal is turned on by the sixth signal supplied to the control terminal, the fourth signal is output from the other end of the current path, A sixth transistor that supplies a control terminal of the even-numbered second transistor serving as a subsequent stage and a control terminal of the even-numbered third transistor ;
In the odd stage, during the forward operation, the first signal is supplied to the control terminal of the first transistor, and the third signal is supplied to one end of the current path of the third transistor,
In the even stage, during the forward operation, the second signal is supplied to the control terminal of the first transistor, and the fourth signal is supplied to one end of the current path of the third transistor,
In the first stage, during the forward operation, an external signal is supplied as one end of the current path of the first transistor as the predetermined signal.
After the second stage, during the forward operation, the third transistor or the fourth signal output from the other end of the current path of the third transistor in the previous stage is the first transistor as the predetermined signal. is supplied to one end of the current path,
In the reverse operation, a predetermined signal output from the other end of the current path of the fifth transistor based on the fifth signal is generated from the first transistor of the odd-numbered stage that is the preceding stage of the subsequent stage. Accumulated in the wiring formed between the other end of the current path and the control terminal of the odd-numbered second transistor and the control terminal of the odd-numbered third transistor; Between the time when the first transistor is turned off and the time when the second transistor is turned on, the control terminal of the odd-numbered second transistor and the control signal of the odd-numbered third transistor continue to be held.
In the reverse operation, a predetermined signal output from the other end of the current path of the sixth transistor based on the sixth signal is a signal of the first transistor of the even-numbered stage that is the preceding stage of the subsequent stage. Accumulated in a wiring formed between the other end of the current path and the control terminal of the even-numbered second transistor and the control terminal of the even-numbered third transistor; Between the time when the first transistor is turned off and the second time when it is turned on, the control terminal of the second transistor of the even-numbered stage and the control terminal of the third transistor of the even-numbered stage continue to be held.
An imaging apparatus characterized by that. Further comprising a vertical direction setting means for setting a vertical direction of an image to be displayed on the display element;
The first selection control means sends an externally supplied selection signal to the first stage or the last stage of the first shift register according to the vertical direction of the image set by the vertical direction setting means. Choose to supply,
The second selection control means selects whether to shift the selection signal fetched in each stage to the previous stage or the subsequent stage according to the vertical direction of the image set by the vertical direction setting means. The imaging apparatus according to claim 10 , wherein the imaging apparatus is characterized. The signal driving circuit is composed of a plurality of stages for capturing an image signal for one line supplied for each pixel from the outside while sequentially shifting to each stage within a selection period for one line by the selection driving circuit. A second shift register, third selection control means for selecting and supplying an externally supplied selection signal to either the foremost stage or the last stage of the second shift register, and the respective stages are fetched the image pickup apparatus according to claim 10 or 11, characterized in that it comprises a fourth selection control means a selection signal for selecting whether to shift to the subsequent stage or shifting in front. A horizontal direction setting means for setting a horizontal direction of an image to be displayed on the display element;
The third selection control means sends an externally supplied selection signal to the first stage or the last stage of the first shift register according to the vertical direction of the image set by the vertical direction setting means. Choose to supply,
The fourth selection control means selects whether to shift the selection signal fetched in each stage to the previous stage or the subsequent stage according to the vertical direction of the image set by the vertical direction setting means. The imaging apparatus according to claim 12 , characterized in that:

Images