JP4923858B2 - Shift register and electronic device - Google Patents

Description

  The present invention relates to a shift register, and an electronic device such as a display device and an imaging device using the shift register as a driver.

  In an active matrix liquid crystal display device such as a TFT liquid crystal display device, display pixels arranged in a matrix are selected line by line, and a desired display is obtained by writing display data to the pixel capacity of the selected pixel. . As a driver for selecting this line, a shift register that sequentially shifts an output signal in accordance with an external control signal is generally used.

  Japanese Unexamined Patent Publication No. 2000-35772 discloses such a shift register. FIG. 27 is a diagram showing a circuit configuration of the shift register disclosed in the above publication. As shown in the figure, this shift register is composed of n stages RS (1) to RS (n), and each of the stages RS (1) to RS (n) is composed of five TFTs 101 to 105. Yes. The TFTs 101 to 105 are all n-channel field effect transistors.

  Next, the operation of this shift register will be described with reference to the timing chart of FIG. First, between the timings T0 and T1, the start signal Dst becomes high level, and the control signal φ1 becomes high level. During this time, the TFT 101 of the first stage RS (1) is turned on, and charges are accumulated at the node A1. As a result, the TFTs 102 and 105 are turned on, and the TFT 105 is turned on, whereby the gate voltage of the TFT 103 changes to a low level, and the TFT 103 is turned off.

  Next, when the clock signal CK1 changes to the high level at the timing T1, the level of this signal is output as it is as the output signal OUT1 of the first stage RS (1). The high-level output signal OUT1 is supplied to the TFT 101 of the second stage RS (2) between the timings T1 and T2, and the control signal φ2 becomes high level, so that this time the second stage RS (2) of the second stage RS (2). Charge is accumulated in the node A2, the TFTs 102 and 105 are turned on, and the TFT 103 is turned off.

  Next, when the clock signal CK2 changes to the high level at the timing T2, the level of this signal is output as it is as the output signal OUT2 of the second stage RS (2). The high-level output signal OUT2 is supplied to the TFT 101 of the third stage RS (3) between the timings T2 and T3, and the control signal φ1 becomes high level. Charge is accumulated in the node A3, the TFTs 102 and 105 are turned on, and the TFT 103 is turned off.

  Further, the charge accumulated at the node A1 of the first stage RS (1) is released by the control signal φ1 which has become high level during this period, the TFTs 102 and 105 are turned off, and the TFT 103 is turned on. Thereafter, no charge is accumulated in the node A1 of the first stage RS (1) until the next start signal Dst is supplied. Even if the clock signal CK1 changes to high level, the output signal OUT1. Does not go high.

  After timing T3, the third and subsequent stages RS (1) to RS (n) perform the same operation, so that the output signals OUT1 to OUT1 are output every time the clock signals CK1 and CK2 become high level for each period of 1T. OUTn sequentially goes high and the output signal shifts.

  By the way, in the lower part of the timing chart of FIG. 28, the third stage RS (3) will be described as an example. When the output signal is shifted from the first stage RS (1) to the nth stage RS (n), The control signal φ1 or φ2 applied to the gate of the TFT 101 becomes high level n / 2 times. In other words, a high level voltage is applied to the gate of the TFT 101 only two times for the purpose of accumulating and discharging charges, but in reality, a high level voltage is applied n / 2 times. The Rukoto. In most of these cases, the voltage level of the drain and source of the TFT 101 is low.

  In this way, since the gate voltage of the TFT 101 is relatively positive with respect to the drain and source voltages, the gate threshold voltage characteristic of the TFT 101 changes from positive. As a result, when used for a long period of time, the TFT 101 that should be turned on originally does not turn on, and charge may not be accumulated in the nodes A1 to An, or the accumulated charge may not be released. sell. That is, the conventional shift register shown in FIG. 27 has a first problem that it causes a malfunction and the durability becomes low.

  Further, in the shift register shown in FIG. 27, since the start signal Dst or the previous stage output signals OUT1 to OUTn-1 is transferred to the nodes A1 to An via the TFT 101, these signal levels Vdd are supplied to the nodes A1 to An. Thus, a voltage lower than the threshold voltage of the TFT 101 is held.

  However, as shown in FIG. 28, while the clock signal CK1 or CK2 is at the high level, the signal levels of the nodes A1 to An rise to a level higher than Vdd due to the so-called bootstrap effect. For this reason, the TFTs 101, 102, and 105 connected to the nodes A1 to An are subjected to a very large voltage stress, and the element characteristics are deteriorated. When used for such a long period of time, the TFTs 101, 102, and 105 may fail, resulting in a second problem that durability is lowered.

  Further, the above publication discloses that output signals OUT1, OUT2,... Are added by adding TFTs to the stages RS (1) to RS (n) of the shift register shown in FIG. Also disclosed is a shift register that can perform both a forward shift for sequentially setting the output level to OUTn and a reverse shift for sequentially setting the output signals OUTn, OUTn-1,. .

However, by adding TFTs to the respective stages RS (1) to RS (n), the area is increased by the amount of the added TFTs as compared with the shift register capable of performing only one-way shift shown in FIG. There was a third problem. The third problem further causes a problem that when the shift register is formed on the same substrate as the substrate of the liquid crystal display element as a driver, the relative area of the image display area is reduced. .
JP 2000-35772 A

  The present invention has been made to solve the above-described problems of the prior art, and has as its first object to provide a shift register that can operate stably for a long period of time by preventing transistor characteristic fluctuations. .

  It is a second object of the present invention to provide a shift register that can operate stably for a long period of time by preventing a large voltage stress from being applied to the shift registers constituting each stage.

  A third object of the present invention is to provide a shift register that can perform a shift operation in both the forward direction and the reverse direction with substantially the same area as a shift register that can perform only one-way shift.

  A fourth object of the present invention is to provide an electronic device such as a display device or an imaging device using such a shift register as a driver for selecting display pixels or imaging pixels.

In order to achieve the above object, a shift register according to the first aspect of the present invention provides:
A shift register having a plurality of stages, each stage of the shift register being
A first transistor in which an output signal of a stage adjacent to one side (for example, the previous stage) is supplied to the control terminal, and a first voltage signal is supplied to one end of the current path;
A second transistor in which an output signal of a stage adjacent to the other side (for example, a subsequent stage) is supplied to the control terminal, and a second voltage signal is supplied to one end of the current path;
A control terminal is connected to the other end of each current path of the first and second transistors, and the first or second voltage signal supplied to the wiring between them through the first or second transistor In addition to accumulating charges, the first or second clock signal supplied to one end of the current path is output as the output signal of the stage from the other end of the current path when being turned on by the accumulated charge. A third transistor;
When switching to the forward shift, the charge is accumulated in the wiring by the high-level first voltage signal supplied through the first transistor, and the low level supplied through the second transistor. The charge accumulated in the wiring is released by the second voltage signal of
When switching to the reverse shift, the charge is accumulated in the wiring by the high-level second voltage signal supplied via the second transistor, and the low level supplied via the first transistor. The charge accumulated in the wiring is released by the first voltage signal of
One of the first and second transistors at one end of the plurality of stages is turned on when a first control signal is supplied to the control terminal from the outside, and charges are accumulated in the wiring.
The other of the first and second transistors at the other end of the plurality of stages is turned on when a second control signal is supplied to the control terminal from the outside, and the charge accumulated in the wiring is discharged,
The high level of the first and second voltage signals is lower than the high level of the first and second clock signals.

Here, one of the first and second transistors at one end of the plurality of stages is turned on when a first control signal is supplied to the control terminal from the outside, and charges are accumulated in the wiring.
The other of the first and second transistors at the other end of the plurality of stages is turned on when a second control signal is supplied to the control terminal from the outside, and the charge accumulated in the wiring is discharged. It can be.

  In the shift register, since the signal supplied to the control terminal of the first or second transistor is an output signal of an adjacent stage, the potential of the control terminal is not stable while sequentially shifting from end to end. It does not go on level as necessary. For this reason, the characteristics of the first or second transistor do not fluctuate so much, and can operate stably for a long period of time.

Thus, the shift register is
When switching to the forward shift, charges are accumulated in the wiring by the high-level first voltage signal supplied through the first transistor, and supplied through the second transistor. Discharging the charge accumulated in the wiring by the second voltage signal at a level;
When switching to the reverse shift, a charge is accumulated in the wiring by the high-level second voltage signal supplied through the second transistor, and the low voltage supplied through the first transistor. The charge accumulated in the wiring can be discharged by the first voltage signal at a level.

  In this case, the first and second voltage signals may be switched in level so that one of them is maintained at a low level.

By such voltage signal switching, charges can be accumulated in the wiring by the output signal of the previous stage, or charges can be accumulated in the wiring by the output signal of the subsequent stage .

In other words, if charge is accumulated by the output signal of the previous stage, the output signal shifts toward the subsequent stage, and if charge is accumulated by the output signal of the subsequent stage, it shifts toward the previous stage. As a result, a shift register capable of bidirectional shift can be provided.

In the above shift register,
When switched to the forward shift, each period in which the first voltage signal is at a high level is equal to each period in which the first or second clock signal is at a high level, and the reverse direction When switching to a shift, each period in which the second voltage signal is at a high level is preferably equal to each period in which the first or second clock signal is at a high level.

  In this way, the first and second voltage signals are set to a high level lower than the first and second clock signals, or the period during which the first and second voltage signals are high is limited. In addition, voltage stress applied to the second transistor can be reduced. As a result, the first and second transistors are less likely to fail and can operate stably for a long period of time.

In the above shift register,
The first clock signal and the second clock signal may be 180 degrees out of phase with each other.

In the above shift register,
Each transistor constituting each of the plurality of stages can be a co-channel field effect transistor.

The shift register is
A control terminal is connected to the other end of each current path of the first and second transistors, and the first or second voltage signal supplied to the wiring between them through the first or second transistor And a fourth transistor that discharges a signal supplied from a voltage source through a load to one end of the current path from the other end of the current path when the charge is stored by
A control terminal is connected to the voltage source via the load, and is turned on by a signal connected from the voltage source when the fourth transistor is turned off, and one end of a current path is connected to the third transistor And a fifth transistor connected to the other end of the current path.

In order to achieve the above object, an electronic device according to a second aspect of the present invention includes:
A driver composed of a plurality of stages and configured to include a driver that sequentially outputs a signal of a predetermined level from each stage by shifting an output signal and a plurality of pixels, and is driven by an output signal output from each stage of the driver With elements,
Each stage of the driver
A first transistor in which an output signal of a stage adjacent to one side is supplied to the control terminal, and a first voltage signal is supplied to one end of the current path;
A second transistor in which an output signal of a stage adjacent to the other side is supplied to the control terminal, and a second voltage signal is supplied to one end of the current path;
A control terminal is connected to the other end of each current path of the first and second transistors, and the first or second voltage signal supplied to the wiring between them through the first or second transistor In addition to accumulating charges, the first or second clock signal supplied to one end of the current path is output as the output signal of the stage from the other end of the current path when being turned on by the accumulated charge. A third transistor;
When switching to the forward shift, the charge is accumulated in the wiring by the high-level first voltage signal supplied through the first transistor, and the low level supplied through the second transistor. The charge accumulated in the wiring is released by the second voltage signal of
When switching to the reverse shift, the charge is accumulated in the wiring by the high-level second voltage signal supplied via the second transistor, and the low level supplied via the first transistor. The charge accumulated in the wiring is released by the first voltage signal of
One of the first and second transistors at one end of the plurality of stages is turned on when a first control signal is supplied to the control terminal from the outside, and charges are accumulated in the wiring.
The other of the first and second transistors at the other end of the plurality of stages is turned on when a second control signal is supplied to the control terminal from the outside, and the charge accumulated in the wiring is discharged,
One of the first and second transistors at one end of the plurality of stages is turned on when a first control signal is supplied to the control terminal from the outside, and charges are accumulated in the wiring.
The other of the first and second transistors at the other end of the plurality of stages is turned on when a second control signal is supplied to the control terminal from the outside, and the charge accumulated in the wiring is discharged,
The high level of the first and second voltage signals is lower than the high level of the first and second clock signals.

In the electronic device,
The drive element includes, for example, a sixth transistor in which an output signal of any one of the stages of the driver is supplied to a control terminal and image data is supplied from the outside to one end of a current path. It can be set as an element.

In addition, the electronic device is
An imaging unit including an imaging device that captures an optical image formed by the imaging lens, and a rotation unit that is rotatable with respect to the imaging unit about a direction substantially perpendicular to the imaging direction, and is displayed as the drive element You may further provide the display part containing an element and the said driver which drives this.
In this case, the display unit may display an image corresponding to an image captured by the imaging device on the display element.

And in the case of such an electronic device,
Setting means for setting whether to accumulate charges in the wiring via any one of the first and second transistors and to release the accumulated charges;
Angle detecting means for detecting an angle of the imaging unit with respect to the display unit;
The setting means performs setting according to the detection result of the angle detection means, and switches the level of the first and second voltage signals to thereby charge the wiring via one of the first and second transistors. It is preferable that the charge accumulated in the wiring can be discharged through the other of the first and second transistors.
In this case, the driver can perform a shift operation in both directions by switching between the forward direction and the reverse direction. When the driver performs a shift operation in the reverse direction, the top and bottom of the image displayed on the display unit can be easily reversed. Thereby, the mirror image of the image captured by the imaging device can be displayed on the display unit without performing complicated control for reading the image to be displayed.

In the electronic device,
The driving element is provided on one side of the semiconductor layer via a semiconductor layer that generates carriers by excitation light, a drain electrode and a source electrode that are respectively connected to both ends of the semiconductor layer, and a first gate insulating film. The first gate electrode and the second gate electrode provided on the other side of the semiconductor layer with the second gate insulating film interposed therebetween may be used as an imaging device provided for each pixel.
In this case, the driver may include a first driver that outputs an output signal to the first gate electrode, and a second driver that outputs an output signal to the second gate electrode.

  The electronic device as described above includes a driver having the same configuration as the shift register according to the first aspect as a driver for driving the driving element. For this reason, since the durability of the driver is high, it is possible to provide the entire electronic device with excellent durability.

As described above, the shift register of the present invention can operate stably for a long period of time with little variation in characteristics of the first or second transistor.
Further, by adjusting the high level level and the period of the first and second voltage signals, the first and second transistors are less likely to fail, and can operate stably for a long time. become.
In addition, it is possible to switch between the first and second transistors to store charges in the wiring and to release the stored charges, thereby shifting in both the forward and reverse directions. Can be performed.

Furthermore, an electronic device to which the shift register of the present invention is applied as a driver is also excellent in durability.
In addition, by applying a driver that can perform a shift operation in both the forward and reverse directions, an image in which the vertical direction is inverted can be easily displayed.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a diagram showing an external configuration of a digital still camera according to this embodiment. As shown in the figure, this digital still camera is composed of a camera body unit 01 and a lens unit unit 02.

  The camera body unit 01 includes a display unit 10 and a mode setting key 12a on the front surface thereof. The mode setting key 12a is a key for shooting an image and switching between a shooting mode for recording in an image memory (to be described later) and a playback mode for playing back the recorded image. The display unit 10 is configured by a liquid crystal display device, and functions as a viewfinder for displaying an image captured by the lens 02a before shooting in the shooting mode (monitoring mode), and displays a recorded image in the playback mode. Function as a display for. The configuration of the display unit 10 will be described in detail.

  The camera body unit 01 also includes a power key 11, a shutter key 12 b, a “+” key 12 c, a “−” key 12 d, and a serial input / output terminal 13 on the upper surface. The power key 11 is a key for turning on / off the power of the digital still camera by performing a slide operation. The shutter key 12b, the “+” key 12c, and the “−” key 12d constitute the key input unit 12 together with the mode setting key 12a.

  The shutter key 12b is a key for instructing recording of an image in the photographing mode and instructing determination of selection contents in the reproduction mode. The “+” key 12c and the “−” key 12d are used to select image data to be displayed on the display unit 10 from image data recorded in the image memory in the shooting mode and to set conditions for recording / playback. Used for. The serial input / output terminal 13 is a terminal for inserting a cable for transmitting / receiving data to / from an external device (personal computer, printer, etc.).

  The lens unit unit 02 includes a lens 02a that forms an image to be photographed on the back side of the drawing. The lens unit 02 is attached so as to be able to rotate 360 ° up and down around an axis coupled to the camera body 01.

  FIG. 2 is a block diagram showing a circuit configuration of the digital still camera according to this embodiment. As shown in the figure, this digital still camera includes a CCD (Charge Coupled Device) imaging device 20, an A / D (Analogue / Digital) converter 21, a CPU (Central Processing Unit) 22, a ROM (Read Only Memory) 23, a RAM (Random Access Memory) 24, a compression / expansion circuit 25, an image memory 26, the display unit 10, the key input unit 12, and the serial input / output terminal 13 described above. These are connected to each other via a bus 30. The CCD imaging device 20 and the A / D converter 21 are also connected by a dedicated line. In addition, the angle sensor 40 shown with a broken line is not included as a structure in this embodiment (refer to 2nd Embodiment mentioned later).

  The CCD imaging device 20 has a plurality of imaging pixels formed in a matrix, photoelectrically converts light imaged by the imaging lens 02a, and outputs an electrical signal corresponding to the light intensity of each pixel. The A / D converter 21 converts the analog electric signal output from the CCD image pickup device 20 into a digital signal and outputs the digital signal.

  The CPU 22 controls a circuit of each part of the digital still camera by executing a program stored in the ROM 23 in accordance with an input from the key input part 12. The ROM 23 stores programs executed by the CPU 22 and also stores fixed data. The RAM 24 is used as a work area when the CPU 22 executes a program. The RAM 24 is also provided with a VRAM area for expanding image data to be displayed on the display unit 10.

  The compression / decompression circuit 25 compresses the image data photographed by the CCD imaging device 20 and converted into a digital signal by the A / D converter 21 when the shutter key 12 b is operated, and records the compressed image data in the image memory 26. . The compression / decompression circuit 25 also decompresses the image data that has been compressed and recorded in the image memory 26 when instructed to display a captured image from the key input unit 12.

  The image memory 26 is composed of a non-volatile storage medium capable of erasing data such as a flash memory, and records image data that has been shot and compressed as described above. The image memory 26 may be configured to be detachable from the digital still camera.

  FIG. 3 is a block diagram illustrating a configuration of a liquid crystal display device that constitutes the display unit 10. As shown in the figure, this liquid crystal display device includes a liquid crystal controller 50, a liquid crystal display element 51, a gate driver 52, and a drain driver 53. The gate driver 52 is supplied with a control signal group Gcnt, and the drain driver 53 is supplied with a control signal group Dcnt and display data data from the liquid crystal controller 50.

  The liquid crystal controller 50 generates control signal groups Gcnt and Dcnt in accordance with control signals from the CPU 22 and supplies them to the gate driver 52 and the drain driver 53, respectively. The liquid crystal controller 50 also reads the image data developed in the VRAM area of the RAM 24 in accordance with a control signal from the CPU 22 and supplies it to the drain driver 53 as display data data.

  The liquid crystal display element 51 is configured by enclosing liquid crystal in a pair of substrates, and on one substrate, TFTs 61 for active drive using a-Si as a semiconductor layer are formed in a matrix. The gate of each TFT 61 is connected to the gate line GL, the drain is connected to the drain line DL, and the source is connected to a pixel electrode similarly formed in a matrix. A common electrode to which a predetermined voltage Vcom is applied is formed on the other substrate, and a pixel capacitor 62 is formed by the common electrode, each pixel electrode, and liquid crystal therebetween. The liquid crystal display element 51 displays an image by controlling the amount of light to be transmitted by changing the alignment state of the liquid crystal due to the charge accumulated in the pixel capacitor 62.

  The gate driver 52 includes a shift register that operates according to a control signal group Gcnt from the liquid crystal controller 50. The gate driver 52 sequentially selects the gate lines GL according to the control signal group Gcnt from the liquid crystal controller 50 and outputs a predetermined voltage. The shift register constituting the gate driver 52 will be described in detail later.

  The drain driver 53 sequentially fetches display data data from the liquid crystal controller 50 according to the control signal group Dcnt from the liquid crystal controller 50. When the display data data for one line is accumulated, the drain driver 53 outputs this to the drain line DL according to the control signal group Dcnt from the liquid crystal controller 50 and is connected to the gate line GL selected by the gate driver 52. The pixel capacitance 62 is accumulated via the TFT 61 (ON state).

  FIG. 4 is a diagram showing a circuit configuration of a shift register applied as the gate driver 52 of FIG. As shown in the figure, this shift register is composed of n stages RS (1) to RS (n) (n: even number) equal to the number of gate lines GL of the liquid crystal display element 51.

  When applied as the gate driver 52, the shift register includes a clock signal CK1, CK2, a power supply voltage Vdd, a reference voltage Vss (<Vdd), a start signal Dst, and an end signal as a control signal group Gcnt from the liquid crystal controller 50. Dend is supplied. Among them, the power supply voltage Vdd and the reference voltage Vss are applied to all stages RS (1) to RS (n), and the clock signal CK1 is an odd-numbered stage RS (1), RS (3),. ), The clock signal CK2 is in even-numbered stages RS (2), RS (4),..., RS (n), the start signal Dst is only in the first stage RS (1), and the end signal Dend is n-th. Are supplied only to the stage RS (n).

  Since the configuration of each stage is almost the same, the first stage RS (1) will be described as an example. This stage RS (1) is composed of six TFTs 1 to 6 made of an a-Si semiconductor layer like the TFT 61. have. The TFTs 1 to 6 are all the same channel type (here, n-channel type) field effect transistors.

  A start signal Dst is supplied to the gate of the TFT 1. A power supply voltage Vdd is supplied to the drain of the TFT 1. The source of TFT 1 is connected to the gate of TFT 2, the gate of TFT 5, and the drain of TFT 6. A wiring surrounded by the source of TFT1, the gate of TFT2, the gate of TFT5, and the drain of TFT6 is referred to as a node A1 (note that the second and subsequent stages are A2 to An, respectively. ). When the start signal Dst becomes a high level and the TFT 1 is turned on, the power supply voltage Vdd is output from the source, whereby charges are accumulated in the node A1.

  The clock signal CK1 is supplied to the drain of the TFT2, and when the TFT2 is turned on, the level of the clock signal CK1 is output as it is as the output signal OUT1 from the source to the gate line GL of the first line. The source of TFT2 is connected to the drain of TFT3.

  The power supply voltage Vdd is supplied to the gate and drain of the TFT 4 and is always on. The TFT 4 functions as a load when supplying the power supply voltage Vdd, and supplies the power supply voltage Vdd from the source to the drain of the TFT 5 almost as it is. The TFT 4 can be replaced with a resistance element other than the TFT. The reference voltage Vdd is supplied to the source of the TFT 5, and when the TFT 5 is turned on, the electric charge accumulated between the source of the TFT 4 and the drain of the TFT 5 is released.

  The gate of the TFT 3 is connected to the source of the TFT 4 and the drain of the TFT 5, and is turned on by the power supply voltage Vdd supplied through the TFT 4 when the TFT 5 is turned off. While the TFT 5 is on, charges accumulated in the wiring between the source of the TFT 4 and the TFT 5 are released, so that the gate voltage of the TFT 3 becomes low level and turns off.

  The output signal OUT2 of the second stage RS (2), which is the next stage, is supplied to the gate of the TFT6. The drain of the TFT 6 is connected to the node A1, and the reference voltage Vss is supplied to the source. When the output signal OUT2 becomes high level, the TFT 6 is turned on, and the charge accumulated in the node A1 is released.

  The odd-numbered stages RS (3), RS (5),..., RS (n−1) other than the first are configured in the previous stage RS (2), RS (4),. .., OUTn-2 are the same as those in the first stage RS (1) except that the output signals OUT2, OUT4,.

  The odd-numbered stages RS (2), RS (4),..., RS (n-2) other than the n-th are arranged in the previous stage RS (1), RS (3),. The same as the first stage RS (1) except that the output signals OUT1, OUT3,..., OUTn-3 of (n-3) are supplied and the clock signal CK2 is supplied to the drain of the TFT2. is there. The configuration of the n-th stage RS (n) is that the even-numbered stages RS (2), RS (4),..., RS (n−2) except that the end signal Dend is supplied to the gate of the TFT 6. Is the same.

  The shift register constituting the gate driver 52 is configured by a combination of TFTs 1 to 6, and the TFTs 1 to 6 have substantially the same structure as the TFT 61 included in the liquid crystal display element 51. Therefore, the gate driver 52 can be collectively formed on the substrate on the TFT 61 side of the liquid crystal display element 51 by the same process.

  The operation of the digital still camera according to this embodiment will be described below. Before explaining the overall operation, first, the operation of the shift register constituting the gate driver 52 will be described with reference to the timing chart of FIG. When used as the gate driver 52, each control signal is supplied from the liquid crystal controller 50 as a control signal group Gcnt.

  In this timing chart, the high levels of the clock signals CK1, CK2, the start signal Dst, and the end signal Dend are all equal to the power supply voltage Vdd. On the other hand, the low level of these signals is equal to the reference voltage Vss. The 1T period is one horizontal period in the display unit 10.

  Further, before starting the shift operation according to this timing chart (before T0), the output signals OUT1 to OUTn are all at the low level. In any of the stages RS (1) to RS (n), no charges are accumulated in the nodes A1 to An, and the TFT2 and the TFT5 are on and the TFT3 is off.

  When the start signal Dst becomes high level between timings T0 and T1, the TFT1 of the first stage RS (1) is turned on, and the power supply voltage Vdd is output from the drain to the source of the TFT1. As a result, charges are accumulated in the node A1 of the first stage RS (1), the potential becomes high level, and the TFT2 and the TFT5 are turned on. When the TFT 5 is turned on, the electric charge accumulated between the source of the TFT 4 and the drain of the TFT 5 is released, and the TFT 3 is turned off. During this period, the TFT2 of the first stage RS (1) is turned on, but the level of the output signal OUT1 remains low because the clock signal CK1 is low.

  Next, when the clock signal CK1 changes to high level at the timing T1, this is output from the drain of the TFT 2 of the first stage RS (1) to the source, and the level of the output signal OUT1 changes to high level. At this time, the potential of the node A1 rises to about twice the power supply voltage Vdd due to the so-called bootstrap effect, and thus reaches the saturation gate voltage of the TFT2, so that the drain current of the TFT2 becomes a saturation current, and the level of the output signal OUT1 Quickly becomes almost equal to the high level of the clock signal CK1. That is, the high level of the output signal OUT1 is substantially the power supply voltage Vdd. Thereafter, when the clock signal CK1 falls until the timing T2, the output signal OUT1 shifts to a low level.

  In the period of timing T1 to T2, the TFT1 of the second stage RS (2) is turned on by the output signal OUT1 of the first stage RS (1) that has become high level. As a result, the power supply voltage Vdd is output from the source of the TFT1 of the second stage RS (2), so that the potential of the node A2 becomes high level, and the TFT2 and TFT5 of the second stage RS (2) are turned on. Then, the TFT 3 is turned off.

  Next, when the clock signal CK2 changes to high level at the timing T2, this is output from the drain of the TFT2 of the second stage RS (2) to the source, and the level of the output signal OUT2 changes to high level. As a result, the TFT 6 of the first stage RS (1) is turned on, and the accumulated charge is discharged from the node A1 via the TFT 6 to become the reference voltage Vss. Therefore, the output signal OUT1 is in the low level state. As a result, the TFTs 2 and 5 in the first stage RS (1) are turned off, and the TFT 3 is turned on. For this reason, the potential of the output signal OUT1 is reliably the reference voltage Vss, and this state continues at least until the timing Tn + 1. Thereafter, when the clock signal CK2 falls until the timing T3, the output signal OUT2 becomes low level.

  Further, during the period of timing T2 to T3, the TFT1 of the third stage RS (3) is turned on by the output signal OUT2 of the second stage RS (2) that has become high level. As a result, the power supply voltage Vdd is output from the source of the TFT1 of the third stage RS (3), so that the potential of the node A3 becomes high level, and the TFT2 and TFT5 of the third stage RS (3) are turned on. Then, the TFT 3 is turned off.

  Next, when the clock signal CK1 changes to high level at the timing T3, this is output from the drain of the TFT 2 of the third stage RS (3) to the source, and the level of the output signal OUT3 changes to high level. As a result, the TFT 6 of the second stage RS (2) is turned on this time, and the charge accumulated in the node A2 is applied to the TFT1 of the second stage RS (2) and the TFT3 of the first stage RS (1). Since it is discharged via the TFT 6 without passing through and becomes the reference voltage Vss, the output signal OUT1 is maintained in the low level state, and accordingly, the TFT 2 and TFT 5 of the second stage RS (2) are turned off. , TFT3 is turned on. That is, in the second stage RS (2), the gate voltage of the TFT2 becomes a low level and the TFT3 is turned on, so that the potential of the output signal OUT2 surely becomes the reference voltage Vss, and this state continues at least until the timing Tn + 1. Thereafter, when the clock signal CK1 falls until the timing T3, the output signal OUT3 becomes a low level.

  In the period from the timing T3 to T4, the TFT1 of the fourth stage RS (4) is turned on by the output signal OUT3 of the third stage RS (3) that has become high level. As a result, the power supply voltage Vdd is output from the source of the TFT1 of the fourth stage RS (4), so that the potential of the node A4 becomes high level, and the TFT2 and TFT5 of the fourth stage RS (4) are turned on. Then, the TFT 3 is turned off.

  In the following, the fourth and subsequent stages RS (4), RS (5),... Operate in the same manner as described above for each 1T period, so that the output signals OUT4, OUT5,. It gradually changes to a high level. In the period of timing Tn−1 to Tn, the TFT 1 of the nth stage RS (n) is turned on by the output signal OUTn−1 of the (n−1) th stage RS (n−1) that has become high level. . As a result, the power supply voltage Vdd is output from the source of the TFT1 of the nth stage RS (n), so that the potential of the node An becomes high level, and the TFT2 and TFT5 of the nth stage RS (n) are turned on. Then, the TFT 3 is turned off.

  Next, when the clock signal CK2 changes to high level at the timing Tn, this is output from the drain of the TFT 2 of the nth stage RS (n) to the source, and the level of the output signal OUTn changes to high level. Thereafter, when the clock signal CK2 falls until timing Tn + 1, the output signal OUTn becomes low level.

  At the timing Tn + 1, the level of the end signal Dend changes to a high level this time. As a result, when the TFT 1 of the nth stage RS (n) is turned on, the charge accumulated in the node A2 is released, the TFT2 and the TFT5 of the second stage RS (2) are turned off, and the TFT3 is turned on. . Until the next high level start signal Dst is supplied, no charge is accumulated in the nodes A1 to An in any of the stages RS (1) to RS (n), and the TFT2 and the TFT5 are The on state and the TFT 3 are kept off.

  As described above, how the potential of the gate, drain, and source of one TFT 1 changes while the output signal is shifted from the first stage RS (1) to the nth stage RS (n). This will be described by taking the TFT 1 of the third stage RS (3) as an example. The lower three stages in FIG. 5 show changes in the gate, drain, and source potential levels of the TFT 1 in the third stage RS (3).

  As shown in the figure, the gate voltage of TFT1 is at a high level (approximately Vdd) only when the output signal OUT2 of the second stage RS (2) is at a high level in the period of timing T2 to T3. Since the power supply voltage Vdd is always supplied to the drain of the TFT1, the drain voltage is always the power supply voltage Vdd. When charge is accumulated in the node A3 at the timing T2, the source voltage of the TFT1 becomes a voltage level lower than Vdd by the threshold voltage. When the clock signal CK1 is at the high level during the period from the timing T3 to T4, the level is about twice the power supply voltage Vdd due to the bootstrap effect described above. After the output voltage of the fourth stage RS (4) becomes high level at timing T4, it becomes low level again.

  As described above, the gate voltage of the TFT 1 of the k-th stage RS (k) in one scan of the shift register is always at a low level (reference) at least when the start signal Dst or the output signal OUTk-1 of the previous stage is once at a high level. Voltage Vss), the clock signals CK1, CK2, the start signal Dst, and the end signal Dend are all high during the period in which the gate voltage of each TFT1 is relatively positive with respect to the lower one of the drain voltage and the source voltage. When the level voltage is equal to the power supply voltage Vdd and the low level voltage is equal to the reference voltage Vss, it is only a period in which the clock signal CK1 or CK2 is once at a high level.

  Further, the high level voltages of the clock signals CK1, CK2, the start signal Dst, and the end signal Dend are lower than the voltage attenuated by the parasitic capacitance between the gate and the drain of the TFT 1, for example, the potential of the node A3 in the period from the timing T3 to T4. In this case, the gate voltage of the TFT 1 is always lower than the source voltage and the drain voltage. For this reason, the shift in the positive direction of the gate threshold voltage of the TFT 1 of the k-th stage RS (k) can be suppressed.

  Next, the operation of the entire digital still camera according to this embodiment will be described. This digital still camera has two types, a case where it operates in a shooting mode and a case where it operates in a playback mode, and these operation modes are determined according to the operation of the mode setting key 12a. Hereinafter, the operation of this digital still camera will be described separately for the shooting mode and the playback mode.

  In the case of the shooting mode, electric charges are accumulated in each pixel of the CCD image pickup device 20 in accordance with the light image formed by the imaging lens 02a. The CCD imaging device 20 sequentially reads out the electric charges accumulated in each pixel in accordance with an instruction from the CPU 22 and supplies it to the A / D converter 21. The A / D converter 21 converts this into digital data and temporarily stores it in a predetermined area of the RAM 24.

  Next, the CPU 22 performs predetermined processing on the captured image data temporarily stored in a predetermined area of the RAM 24 to generate image data corresponding to the image to be displayed on the display unit 10. Then, the generated image data is expanded in the VRAM area of the RAM 24. By sequentially repeating this operation, image data corresponding to the image captured by the imaging lens 02a is always developed in the VRAM area.

  Here, when the user operates the shutter key 12b, the image data stored in the RAM 24 and the image data developed in the VRAM area are fixed in accordance with an instruction from the CPU 22. That is, the image stored in the predetermined area of the RAM 24 does not change with the image captured by the imaging lens 02a when the shutter key 12b is operated, and the imaging lens 02a captures when the shutter key 12b is operated. The image data corresponding to the previously stored image is expanded in the VRAM area.

  Next, the CPU 22 sends an instruction to the compression / decompression circuit 25 to compress the image data stored in a predetermined area of the RAM 24. Then, the compressed image data is transferred from the compression / decompression circuit 25 to the image memory 26 and stored. For example, after a predetermined time has elapsed since the shutter key 12b was operated, or when the user performs a predetermined operation on the key input unit 12, the CPU 22 moves the A / D converter 21 from the CCD imaging device 20. The digital still camera is returned to the operation so that the image data read out via the memory is stored and the corresponding image data is developed in the VRAM area.

  In the playback mode, the user operates the “+” key 12 c or the “−” key 12 d to select image data to be displayed on the display unit 10 from among the image data stored in the image memory 26. To do. The selected image data is transferred from the image memory 26 to the compression / expansion circuit 25 and decompressed. The CPU 22 performs predetermined processing on the decompressed image data, generates image data to be displayed on the display unit 10, and develops it in the VRAM area of the RAM 24.

  The display unit 10 reads out the image data developed in the VRAM area of the RAM 24 and displays the corresponding image in any of the above-described shooting modes and playback modes. Hereinafter, an operation for displaying an image on the display unit 10 will be described.

  The liquid crystal controller 50 of the display unit 10 reads the image data developed in the VRAM area of the RAM 24 in a predetermined order in accordance with a control signal from the CPU 22. The order of reading is controlled so as to be different between a case where an image substantially the same as an image taken by the CCD imaging device 20 is displayed and a case where a mirror image of the image taken by the CCD imaging device 20 is displayed.

  The liquid crystal controller 50 causes the drain driver 53 to capture the image data read from the VRAM area as display data data in accordance with the control signal group Dcnt. When the drain driver 53 fetches the display data data for one line, the drain driver 53 outputs a voltage signal corresponding thereto to each drain line DL of the liquid crystal display element 51 in accordance with the control signal group Dcnt from the liquid crystal controller 50.

  On the other hand, the liquid crystal controller 50 sequentially shifts the output signal of the gate driver 52 according to the control signal group Gcnt, and sequentially selects the gate lines GL of the liquid crystal display elements 51. That is, the gate driver 52 selects the gate line GL corresponding to the display data data output from the drain driver 53.

  The potential of the gate line GL selected by the gate driver 52 becomes a high level in accordance with the output signal, whereby the TFT 61 connected to the gate line GL is turned on. Then, a voltage signal output from the drain driver 53 to each drain line DL via the turned-on TFT 61 is written to the pixel capacitor 62.

  Then, the alignment state of the liquid crystal changes according to the voltage signal written in the pixel capacitor 62, and the amount of transmitted light in the pixel changes. Such a selection operation is sequentially performed for the first to nth gate lines GL, and a voltage signal is written to each pixel capacitor 62 by outputting a voltage signal corresponding to the display data data to each drain line DL. The image data developed in the area, that is, the image captured by the CCD imaging device 20 or the image selected from the image memory 26 is displayed on the display unit 10.

  As described above, in this embodiment, the shift register constituting the gate driver 52 has a short period in which the gate voltage of the TFT 1 in each stage is relatively positive with respect to the drain and source voltages. Due to its characteristics, when the gate voltage becomes relatively positive with respect to the drain and source voltages, the threshold characteristic tends to shift more than positive, but the gate voltage becomes relatively negative with respect to the drain and source voltages. Even so, the threshold characteristic does not shift to minus.

  In other words, even if the shift register of this embodiment is used for a long period of time, the characteristics of the TFT 1 are less likely to change compared to the shift register of the conventional example. It is difficult to cause a case where charges cannot be accumulated in the nodes A1 to An. For this reason, it operates stably for a long time and becomes highly durable.

  Further, the failure of the display unit 10 to which this shift register is applied as the gate driver 52 is naturally reduced, and the durability of the digital still camera including the failure is also high.

  In this embodiment, the gate driver 52 applied to the liquid crystal display device constituting the display unit 10 has the configuration shown in FIG. 4, and the timing chart shown in FIG. 5 according to the control signal output from the liquid crystal controller 50. It is assumed that it is constituted by a shift register that operates according to However, the shift register applicable as the gate driver 52 is not limited to this.

  FIG. 6 is a diagram showing a circuit configuration of another shift register applicable as the gate driver 52. The difference from the shift register shown in FIG. 4 will be described. The clock signal CK1 in the odd-numbered stages RS (1), RS (3),. The clock signal CK2 is supplied to each of the stages RS (2), RS (4),..., RS (n). The clock signals CK1, CK2, the start signal Dst, and the end signal Dend all have a high level voltage equal to the power supply voltage Vdd and a low level voltage equal to the reference voltage Vss.

  Next, the operation of the shift register of FIG. 6 will be described with reference to the timing chart of FIG. When the start signal Dst becomes high level and the TFT1 of the first stage RS (1) is turned on during the period of timing T0 to T1, the clock signal CK2 supplied to the drain of the TFT1 becomes high level. Charge is accumulated in the node A1.

  When the output signal OUT1 of the first stage RS (1) becomes high level and the TFT1 of the second stage RS (2) is turned on during the period from the timing T1 to T2, it is supplied to the drain of the TFT1. The clock signal CK1 becomes high level and charges are accumulated in the node A2. Similarly, during the period from timing Tn-1 to Tn, the output signal OUTn-1 of the (n-1) th stage RS (n-1) becomes high level, and the TFT1 of the nth stage RS (n) When turned on, the clock signal CK2 supplied to the drain of the TFT1 becomes high level, and charges are accumulated at the node An.

  In this shift register, as shown in the lower three stages of FIG. 7, the change in the potential level of the gate, drain, and source of the TFT 1 will be described by taking the third stage RS (3) as an example. Only when the output signal OUT2 of the second stage RS (2) is at a high level, it is at a high level (approximately Vdd). The drain voltage is at a high level (approximately Vdd) only when the clock signal CK2 is at a high level. When the electric charge is accumulated in the node A3 at the timing T2, the source voltage becomes a voltage level lower than the threshold voltage by Vdd, and the power supply voltage is maintained while the clock signal CK1 is at the high level in the period from the timing T3 to T4. It is about twice the level of Vdd.

  Here, if the period during which the drain voltage of the TFT 1 is higher than the gate voltage is sufficiently long, the gate threshold voltage shifts to the negative side, and the potential at the node A may increase due to the leakage current at the time of OFF, causing malfunction. However, in this shift register, the period during which the drain voltage of the TFT 1 is at a high level is shorter than that in the shift register shown in FIG. That is, the period in which the potential difference between the gate and drain and the source and drain of the TFT 1 occurs is short. For this reason, the voltage stress applied to the TFT 1 is smaller than that of the shift register shown in FIG. 4, the leakage current is also small, and the element characteristics of the TFT 1 are not easily deteriorated.

  FIG. 8 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 52. The difference from the shift register shown in FIG. 4 will be described. The voltage signal V1 is supplied. The high level of the voltage signal V1 is lower than the level of the power supply voltage Vdd, but is a level that can accumulate enough charges to turn on the TFTs 2 and 5 in the nodes A1 to An. On the other hand, the low level is the same as the reference voltage Vss. The clock signals CK1, CK2, the start signal Dst, and the end signal Dend all have a high level voltage equal to the power supply voltage Vdd and a low level voltage equal to the reference voltage Vss.

  Next, the operation of the shift register of FIG. 8 will be described with reference to the timing chart of FIG. In the operation according to this timing chart, the voltage signal V1 is constantly maintained at a high level.

  When the start signal Dst becomes high level and the TFT1 of the first stage RS (1) is turned on during the period from the timing T0 to T1, the voltage signal V1 is output from the drain to the source of the TFT1, and the node A1 The charge is accumulated in the. At this time, the potential of the node A1 is lower than the voltage signal V1 lower than the power supply voltage Vdd by the threshold voltage of the TFT1, but is higher than the threshold voltages of the TFT2 and TFT5. As a result, the TFT2 and the TFT5 in the first stage RS (1) are turned on, and the TFT3 is turned off. Then, when the clock signal CK1 rises at the timing T1, the level of the output signal OUT1 becomes a high level.

  Similarly, during the period from timing Tn−1 to Tn, the output signal OUTn−1 of the (n−1) th stage RS (n−1) becomes high level, and the TFT1 of the nth stage RS (n) Turn on. As a result, electric charges that are lower than the voltage signal V1 by the threshold voltage of the TFT 1 are accumulated at the node An, the TFTs 2 and 5 of the nth stage RS (n) are turned on, and the TFT 3 is turned off. Then, when the clock signal CK2 rises at the timing Tn, the level of the output signal OUTn becomes a high level.

  In this shift register, how the potential of the gate, drain, and source of one TFT 1 changes will be described with reference to the lower three stages of FIG. 9, taking the TFT 1 of the third stage RS (3) as an example. . As shown in the figure, the gate voltage of the TFT1 is at a level substantially equal to the power supply voltage Vdd only when the output signal OUT2 of the second stage RS (2) is at the high level during the period of timing T2 to T3.

  The drain voltage of the TFT 1 is maintained at a level slightly lower than the level of the voltage signal V1, that is, the power supply voltage Vdd. When charge is accumulated in the node A3 at the timing T2, the source voltage of the TFT1 becomes a voltage level lower by the threshold voltage than the voltage signal V1, and the clock signal CK1 is at the high level during the period from the timing T3 to T4. Sometimes, it becomes a level higher than this by the power supply voltage Vdd.

  That is, the source voltage of the TFT 1 at this time is slightly higher than the power supply voltage Vdd, but is sufficiently lower than a voltage twice as high as the power supply voltage Vdd. Therefore, in the TFT 1, the potential difference between the gate and the drain when the gate is off is smaller, and the potential difference between the gate and the source when the source voltage is maximum is smaller. Similarly, the gate voltage of the TFT 2, the gate voltage of the TFT 5, and the drain voltage of the TFT 6 are not increased as in the case of the shift register of FIG. Therefore, a large voltage stress is not applied to the TFTs 1, 2, 5, and 6, and the element characteristics of the TFTs 1, 2, 5, and 6 are less likely to deteriorate compared to the shift register of FIG. 4. It becomes difficult to break down.

  The shift register of FIG. 8 can also operate according to the timing chart of FIG. In the operation according to this timing chart, the voltage signal V1 changes to a high level only during a period in which either the clock signal CK1 or CK2 is at a high level. The difference between the operation according to the timing chart and the operation according to the timing chart of FIG. 9 will be described.

  Only when the start signal Dst is at the high level during the period from the timing T0 to T1, the voltage signal V1 is at the high level and charges are accumulated in the node A1. Only when the output signal OUT1 is at the high level during the period from the timing T1 to T2, the voltage signal V1 is at the high level, and charges are accumulated in the node A2. Similarly, during the period from timing Tn-1 to Tn, the voltage signal V1 becomes high level and charges are accumulated in the node An only when the output signal OUTn-1 is high level.

  In the case of this operation, as shown by taking the third stage RS (1) in the lower three stages of FIG. 10 as an example, the time during which a potential difference is generated between the gate and drain of the TFT 1 and between the source and drain is shown in FIG. And the voltage stress applied to the TFT 1 is small. For this reason, the element characteristics of the TFT 1 are less likely to deteriorate than in the case of the operation of FIG.

  FIG. 11 is a diagram showing a circuit configuration of still another shift register applicable as the gate driver 52. The difference from the shift register shown in FIG. 6 will be described. The clock signal CK1 ′ in the odd-numbered stages RS (1), RS (3),. , RS (n) are supplied with a clock signal CK2 ′. The high level of the clock signals CK1 ′ and CK2 ′ is lower than the level of the power supply voltage Vdd, but is a level that can store charges enough to turn on the TFT2 and TFT5 in the nodes A1 to An. It is.

  Next, the operation of the shift register in FIG. 11 will be described with reference to the timing chart in FIG. When the start signal Dst becomes high level at timings T0 to T1, the clock signal CK2 'becomes high level, and charges are accumulated in the node A1. When the output signal OUT1 becomes high level at the timing T1 to T2, the clock signal CK1 'becomes high level, and charges are accumulated in the node A2. Similarly, when the output signal OUTn-1 becomes high level at timings Tn-1 to Tn, the clock signal CK1 'becomes high level, and charges are accumulated in the node An.

  As shown in the lower three stages of FIG. 12 as an example of the third stage RS (3) TFT1, the source voltage of each TFT1 is slightly higher than the power supply voltage Vdd even at the maximum level. The voltage level is sufficiently lower than twice the voltage Vdd. Similarly, the gate voltage of the TFT 2, the gate voltage of the TFT 5, and the drain voltage of the TFT 6 are not increased as in the case of the shift register of FIG. For this reason, a large voltage stress is not applied to the TFTs 1, 2, 5, and 6. Further, as compared with the shift register of FIG. 8, the period in which the potential difference is generated between the gate and drain and the source and drain of the TFT 1 is short. Compared with the shift register of FIG. 6 and FIG. 8, the device characteristics of the TFTs 1, 2, 5, and 6 are less likely to be deteriorated.

[Second Embodiment]
The digital still camera according to this embodiment is substantially the same as that shown in the first embodiment, except that it has an angle sensor 40 indicated by a dotted line in FIG. Further, unlike the first embodiment, the shift register applied as the gate driver 52 of the display unit 10 is one that can shift the output signal in both the forward direction and the reverse direction. In accordance with this, the signals output from the liquid crystal controller 50 as the control signal group Gcnt are also slightly different.

  The angle sensor 40 detects an angle of the lens unit unit 02 with respect to the camera body unit 01. The detection signal of the angle sensor 40 is input to the CPU 22, and the CPU 22 determines whether the display scanning direction (the shift operation direction of the shift register applied as the gate driver 52) is the forward direction or the reverse direction according to the detection signal. Is sent to the display unit 10.

  FIG. 13 is a diagram showing a circuit configuration of a shift register applied as the gate driver 52 in this embodiment. This shift register is also composed of n stages RS (1) to RS (n) that are the same as the number of gate lines GL of the liquid crystal display element 51. Each of the stages RS (1) to RS (n) is shown in FIG. Similarly to the shift register shown in FIG. 4, the TFT is composed of six TFTs 1 to 6. Again, the TFTs 1 to 6 are all n-channel field effect transistors.

  The difference between the shift register shown in FIG. 13 and that shown in FIG. 4 will be described. The voltage signal V1 is supplied to the drain of the TFT 1 in each stage RS (1) to RS (n) instead of the power supply voltage Vdd. The Instead of the reference voltage Vss, the voltage signal V2 is supplied to the source of the TFT 6 of each stage RS (1) to RS (n).

  A control signal D1 is supplied to the gate of the TFT1 in the first stage RS (1) instead of the start signal Dst. A control signal D2 is supplied to the gate of the TFT 6 in the n-th stage RS (n) instead of the end signal Dend. The voltage signals V1 and V2 have different levels between the forward operation and the reverse operation, and the control signals D1 and D2 have different high timings between the forward operation and the reverse operation.

  The operation of the digital still camera according to this embodiment will be described below. First, the operation of the shift register that constitutes the gate driver 52 will be described with reference to timing charts of FIGS.

  In these timing charts, the high levels of the clock signals CK1 and CK2, the voltage signals V1 and V2, and the control signals D1 and D2 are all equal to the power supply voltage Vdd. On the other hand, the low level of these signals is equal to the reference voltage Vss. The 1T period is one horizontal period in the display unit 10.

  Further, before starting the shift operation according to these timing charts (before T0), the output signals OUT1 to OUTn are all at the low level. In any of the stages RS (1) to RS (n), no charges are accumulated in the nodes A1 to An, and the TFT2 and the TFT5 are on and the TFT3 is off.

  FIG. 14 is a timing chart showing the operation when shifting in the forward direction. In this case, the level of the voltage signal V1 is maintained at a high level equal to the power supply voltage Vdd, and the level of the voltage signal V2 is maintained at a low level equal to the reference voltage Vss. Further, the control signal D1 becomes high level only for a certain period between timings T0 and T1. The control signal D2 is at a high level for a certain period from timing Tn to timing Tn + 1.

  In other words, in the first embodiment, if the control signal D1 is replaced with the start signal Dst and the control signal D2 is replaced with the end signal Dend, the operation of the shift register described with reference to the timing chart of FIG. 5 is the same. Therefore, the output signals OUT1 to OUTn are sequentially shifted to the high level and shifted in a certain period within the 1T period.

  On the other hand, FIG. 15 is a timing chart showing the operation when shifting in the reverse direction. In this case, the level of the voltage signal V1 is maintained at a low level equal to the reference voltage Vss, and the level of the voltage signal V2 is maintained at a high level equal to the reference voltage Vdd. Further, the control signal D2 becomes high level only for a certain period between timings T0 and T1. The control signal D1 is at a high level for a certain period from timing Tn to timing Tn + 1.

  When the control signal D2 becomes high level between timings T0 and T1, the TFT 6 of the nth stage RS (n) is turned on, and the high level voltage signal V2 is output from the source to the drain of the TFT6. As a result, charges are accumulated in the node An of the nth stage RS (n), the TFT2 and TFT5 are turned on, and the TFT3 is turned off. During this period, the TFT2 of the nth stage RS (n) is turned on, but the level of the output signal OUT2 remains low because the clock signal CK2 is at low level.

  Next, when the clock signal CK2 changes to high level at the timing T1, it is output from the drain of the TFT 2 of the nth stage RS (n) to the source, and the level of the output signal OUTn changes to high level. Thereafter, when the clock signal CK2 falls until the timing T2, the output signal OUTn becomes low level.

  In the period from the timing T1 to the timing T2, the TFT 6 of the (n−1) th stage RS (n−1) is turned on by the output signal OUTn of the nth stage RS (n) that has become high level. As a result, the high level voltage signal V2 is output from the drain of the TFT 6 of the (n−1) th stage RS (n−1), so that the potential of the node An−1 becomes high level, and the (n−1) th stage. The TFTs 2 and 5 in the stage RS (n−1) are turned on, and the TFT 3 is turned off.

  Next, when the clock signal CK1 changes to the high level at the timing T2, this is output from the drain of the TFT2 of the (n-1) th stage RS (n-1) to the source, and the level of the output signal OUTn-1 is high. Change to level. As a result, the TFT 1 of the nth stage RS (n) is turned on this time, the charge accumulated in the node An is released, the TFT2 and TFT5 of the nth stage RS (n) are turned off, and the TFT3 is turned on. . Thereafter, when the clock signal CK1 falls until the timing T3, the output signal OUTn-1 becomes a low level.

  Further, during the period from the timing T1 to the timing T2, the output signal OUTn-1 of the (n-1) th stage RS (n-1) that has become high level causes the TFT 6 of the (n-2) th stage RS (n-2) to be turned on. Turn on. As a result, a high level voltage signal V2 is output from the drain of the TFT 6 of the (n−2) th stage RS (n−2), so that the potential of the node An−2 becomes a high level, and the (n−2) th stage. The TFTs 2 and 5 in the stage RS (n-2) are turned on, and the TFT 3 is turned off.

  In the following, by repeating the same operation as above for each stage of 1T in the direction of the previous stage, the (n−2) th stage RS (n−2), RS (n−3),. The output signals OUTn-2, OUTn-3,... Change to the high level every predetermined period within the 1T period. Then, in the period of timing Tn−1 to Tn, the TFT 6 of the first stage RS (1) is turned on by the output signal OUT2 of the second stage RS (2) that has become high level. As a result, charges are accumulated in the node A1 of the first stage RS (1), the TFT2 and TFT5 are turned on, and the TFT3 is turned off.

  Next, when the clock signal CK1 changes to high level at the timing Tn, this is output from the drain of the TFT 2 of the first stage RS (1) to the source, and the level of the output signal OUT1 changes to high level. Thereafter, when the clock signal CK1 falls until timing Tn + 1, the output signal OUT1 becomes low level.

  Then, at timing Tn + 1, the level of the control signal D1 changes to a high level this time. As a result, when the TFT1 of the first stage RS (1) is turned on, the charge accumulated in the node A1 is released, the TFT2 and the TFT5 of the second stage RS (2) are turned off, and the TFT3 is turned on. . Until the control signal D2 changes to the high level, no charge is accumulated in the nodes A1 to An in any of the stages RS (1) to RS (n), the TFT2 and the TFT5 are on, the TFT3 Remains off.

  Next, the operation of the entire digital still camera according to this embodiment will be described. The operation is the same as that of the first embodiment except for the following points. The difference from the first embodiment will be described. The angle sensor 40 detects the angle of the lens unit unit 02 with respect to the camera body unit 01 and inputs the detection signal to the CPU 22. Then, the CPU 22 supplies a control signal corresponding to the input detection signal to the display unit 10.

  In the display unit 10, the liquid crystal controller 50 gates so as to shift forward when a control signal indicating that the imaging lens 02 a of the lens unit unit 02 is on the opposite side of the display unit 10 is supplied from the CPU 22. The control signals D1 and D2 and voltage signals V1 and V2 supplied to the driver 52 as the control signal group Gcnt are switched. When the control signal indicating that the imaging lens 02a is on the display unit 10 side is supplied from the CPU 22, the control signals D1 and D2 supplied to the gate driver 52 as the control signal group Gcnt so as to shift in the reverse direction. The voltage signals V1 and V2 are switched.

  Hereinafter, the operation when taking an image with the digital still camera according to this embodiment, in particular, the relationship between the orientation of the lens unit unit 02 and the image displayed on the display unit 10 will be described with a specific example. Here, it is assumed that the mode setting key 12a is set to the photographing mode, and the CPU 22 changes the scanning direction of the liquid crystal display element 51 (the shift direction of the shift register constituting the gate driver 52) according to the detection signal of the angle sensor 40. It is assumed that a control signal for changing is sent to the display unit 10.

  First, as shown in FIG. 16A, the operation of the digital still camera when shooting an image of an object on the front side as viewed from the photographer will be described. In this case, the photographer places the imaging lens 02a of the lens unit unit 02 on the same side as the display unit 10 of the camera body unit 01, that is, the lens unit unit 02 is substantially 0 ° with respect to the camera body unit 01. The image is taken by rotating it so that it is in position. At this time, the scanning direction of the liquid crystal display element 51 by the gate driver 52 is the forward direction.

  In this state, as shown in FIG. 16A, the arrangement of the pixels P (1, 1) to P (n, m) of the liquid crystal display element 51 is the same as the original vertical and horizontal directions of the liquid crystal display element 51. I'm doing it. Further, the up / down / left / right direction of the lens unit portion 02 matches the original up / down / left / right direction of the image. At this time, according to the image formed by the imaging lens 02a, horizontal scanning is performed from left to right in FIG. 16A, and vertical scanning is performed from top to bottom. A signal is output, and the corresponding image data is developed in the VRAM area of the RAM 24.

  On the other hand, the display unit 10 takes in the developed image data in accordance with the direction of the horizontal arrow shown in FIG. 16B, and the first to mth drain lines of the liquid crystal display element 51 within one horizontal period. Output to DL. Further, the gate driver 52 sequentially selects the gate lines GL in the first to nth order of the liquid crystal display element 51 (from top to bottom in FIG. 16B).

  As a result, the image data corresponding to the signal output from the pixel that is originally above in the CCD image pickup device 20 is captured on the pixel that is essentially above the liquid crystal display element 51 (upper side of FIG. 16B). In the device 20, image data corresponding to the signal output from the pixel originally on the left is displayed on the original left pixel (left side of FIG. 16B) of the liquid crystal display element 51. As shown in (b), an image in the same direction as the photographed image is displayed.

  Next, as shown in FIG. 17A, the operation of the digital still camera when an image is taken when the subject is on the display unit 10 side, for example, the photographer himself is the subject will be described. In this case, the photographer places the imaging lens 02a of the lens unit unit 02 on the opposite side of the display unit 10 of the camera body unit 01, that is, the lens unit unit 02 is approximately 180 ° with respect to the camera body unit 01. The image is taken by rotating it so that it is in position. At this time, the scanning direction of the liquid crystal display element 51 by the gate driver 52 is reversed.

  In this state, as shown in FIG. 17A, the arrangement of the pixels P (1, 1) to P (n, m) of the liquid crystal display element 51 is opposite to the original vertical and horizontal directions of the liquid crystal display element 51. It has become. In addition, the up / down / left / right direction of the lens unit unit 02 matches the up / down / left / right direction of the image. At this time, according to the image formed by the imaging lens 02a, horizontal scanning is performed from right to left in FIG. 17A and vertical scanning is performed from top to bottom, and an electrical signal is output from each pixel of the CCD imaging device 20. The corresponding image data is output to the VRAM area of the RAM 24.

  On the other hand, in the display unit 10, the developed image data is taken in according to the direction of the horizontal arrow shown in FIG. 17B, and the first to mth drain lines of the liquid crystal display element 51 within one horizontal period. Output to DL. Further, the gate driver 52 sequentially selects the gate lines GL in the order from the first to the n-th of the liquid crystal display element 51 (from the bottom to the top in FIG. 17B).

  As a result, image data corresponding to the signal output from the pixel that is inherently upper in the CCD imaging device 20 is transferred to the original lower pixel of the liquid crystal display element 51 (lower side in FIG. 17B). The image data corresponding to the signal output from the pixel essentially left in the imaging device 20 is displayed on the original right pixel (right side in FIG. 17B) of the liquid crystal display element 51. As shown in FIG. 17 (b), a mirror image of the captured image is displayed.

  As described above, in the shift register applied as the gate driver 52 of the digital still camera according to this embodiment, when operating in the forward direction, the TFT 1 is a transistor for accumulating charges at the nodes A1 to An. The TFT 6 functions as a transistor for discharging the accumulated electric charge. On the other hand, when operating in the reverse direction, the TFT 1 functions as a transistor for discharging charges accumulated in the nodes A1 to An, and the TFT 6 functions as a transistor for storing charges.

  Since the TFTs 1 and 6 can have such a function, the number of TFTs 1 to 6 constituting each stage RS (1) to RS (n) is applied as the gate driver 52 in the first embodiment. It can be the same as the shift register. For this reason, the area is not so large compared to that of the first embodiment, and even if the gate driver 52 is formed on the same substrate as the liquid crystal display element 51, the relative area of the image display region is small. Don't be.

  Further, by applying a shift register capable of performing a shift operation in both the forward and reverse directions to the gate driver 52, it is only necessary to control the control signal group Gcnt supplied to the liquid crystal controller 50 to the gate driver 52. The mirror image of the image captured by the CCD imaging device 20 can be displayed on the display unit 10. That is, the digital still camera according to this embodiment can display a mirror image on the display unit 10 without performing complicated control for reading the image data developed in the VRAM area.

  In this embodiment, the gate driver 52 has the configuration shown in FIG. 13 and is configured by a shift register that operates according to the timing chart shown in FIG. 14 or 15 by a control signal output from the liquid crystal controller 50. I was trying. However, in this embodiment, the shift register driving method applicable as the gate driver 52 is not limited to this, and the configuration of the shift register is not limited to this.

  18 and 19 are timing charts showing other operations of the shift register shown in FIG. In the forward operation, as shown in FIG. 18, the voltage signal V2 is maintained at the low level as in FIG. 14, but the voltage signal V1 is the clock signal CK1 or CK2 at the high level. High level only when For example, during the period from timing T0 to T1, when the control signal D1 becomes high level, the clock signal CK1 also becomes high level, the TFT1 of the first stage RS (1) is turned on, and the charge is applied to the node A1. Accumulated.

  On the other hand, in the reverse operation, as shown in FIG. 19, the voltage signal V1 is maintained at the low level as in FIG. 15, but the voltage signal V2 is high when the clock signal CK1 or CK2 is high. It becomes high level only when it is level. For example, during the period from timing T0 to T1, when the control signal D2 becomes high level, the clock signal CK2 also becomes high level, the TFT 1 of the nth stage RS (n) is turned on, and the charge is applied to the node An. Accumulated.

  In these cases, the time during which the potential difference occurs between the gate and drain of TFT1 and TFT6 and between the source and drain is shorter than when the operation is performed according to the timing charts of FIGS. As a result, voltage stress applied to the TFT 1 and the TFT 6 can be reduced, and characteristic deterioration is unlikely to occur, so that it can withstand long-term use.

  FIG. 20 is a diagram showing a circuit configuration of another shift register applicable as the gate driver 52 in this embodiment. The difference from the shift register shown in FIG. 13 will be described. In the odd-numbered stages RS (1), RS (3),..., RS (n−1), the voltage signal V2 is supplied to the drain of the TFT1 and the source of the TFT6 is used. Is supplied with a voltage signal V1. In the even-numbered stages RS (2), RS (4),..., RS (n), the voltage signal V1 is supplied to the drain of the TFT1, and the voltage signal V2 is supplied to the source of the TFT6.

  Next, operation of the shift register in FIG. 20 is described with reference to timing charts in FIGS. In the case of forward operation, during the period from timing T0 to T1, when the control signal D1 becomes high level, the TFT1 of the first stage RS (1) turns on, and the voltage signal V2 that has become high level charges the node A1. Is accumulated. When the clock signal CK1 becomes high level during the period of timing T1 to T2, the output signal OUT1 of the first stage RS (1) becomes high level. As a result, the TFT1 of the second stage RS (2) is turned on, and charges are accumulated in the node A2 by the voltage signal V1 that has become high level.

  When the clock signal CK2 becomes high level during the next timing T2-T3, the output signal OUT2 of the second stage RS (2) becomes high level. As a result, the TFT 1 of the third stage RS (3) is turned on, and charges are accumulated in the node A3 by the voltage signal V2 which has become high level. Further, the TFT 6 of the first stage RS (1) is turned on by the output signal OUT2 that has become high level. At this time, since the voltage signal V1 is at a low level, the charge accumulated in the node A1 is released.

  Similarly, when the clock signal CK2 becomes high level in the period from timing Tn to Tn + 1, the output signal OUTn of the nth stage RS (n) becomes high level. As a result, the TFT 6 of the (n−1) th stage RS (n−1) is turned on and the voltage signal V1 is at the low level, so that the charge accumulated at the node An−1 is released. At timing Tn + 1, the control signal D2 becomes high level and the TFT 6 of the nth stage RS (n) is turned on. At this time, since the voltage signal V2 is at a low level, the charge accumulated in the node An is released.

  On the other hand, when the reverse operation is performed, when the control signal D2 becomes high level during the period of timing T0 to T1, the TFT 6 of the nth stage RS (n) is turned on, and the voltage signal V2 that has become high level causes the node to turn on. Charge is accumulated in An. When the clock signal CK2 becomes high level in the period of timing T1 to T2, the output signal OUTn of the nth stage RS (n) becomes high level. As a result, the TFT 6 of the (n-1) th stage RS (n-1) is turned on, and charges are accumulated in the node An-1 by the voltage signal V2 which has become high level.

  When the clock signal CK1 becomes high level during the next timing T2 to T3, the output signal OUTn-1 of the (n-1) th stage RS (n-1) becomes high level. As a result, the TFT 1 of the nth stage RS (n) is turned on and the voltage signal V1 is at a low level, so that the charge accumulated at the node An is released.

  Similarly, when the clock signal CK1 becomes high level during the period of timing Tn to Tn + 1, the output signal OUT1 of the first stage RS (1) becomes high level. As a result, the TFT 1 of the second stage RS (2) is turned on and the voltage signal V1 is at a low level, so that the charge accumulated at the node A2 is released. At timing Tn + 1, the control signal D1 becomes high level, and the TFT 1 of the first stage RS (1) is turned on. At this time, since the voltage signal V2 is at a low level, the charge accumulated in the node A1 is released.

  FIG. 23 is a diagram showing a circuit configuration of another shift register applicable as the gate driver 52 in this embodiment. The difference from the shift register shown in FIG. 13 will be described. In the odd-numbered stages RS (1), RS (3),..., RS (n−1), the voltage signal V2 is supplied to the drain of the TFT1 and the source of the TFT6 is used. Is supplied with a voltage signal V4. In the even-numbered stages RS (2), RS (4),..., RS (n), the voltage signal V1 is supplied to the drain of the TFT1, and the voltage signal V3 is supplied to the source of the TFT6.

  Next, operation of the shift register in FIG. 23 is described with reference to timing charts in FIGS. The operation of this shift register replaces the voltage signal supplied to the source of the TFT 6 with V4 in the odd-numbered stages RS (1), RS (3),. If the voltage signal supplied to the source of the TFT 6 in 2), RS (4),..., RS (n) is replaced with V3, it is almost the same as that of the shift register of FIG.

  However, when the forward operation shown in FIG. 24 is performed, the source voltages (voltage signals V3 and V4) of the TFTs 6 of the respective stages RS (1) to RS (n) are maintained at a low level. In the case of performing the reverse operation shown in FIG. 25, the drain voltages (voltage signals V1, V2) of the TFTs 1 of the respective stages RS (1) to RS (n) are maintained at a low level. That is, the time for generating a potential difference between the gate and the drain and between the source and the drain is short for the TFT 1 in the forward operation and for the TFT 6 in the reverse operation. For this reason, the voltage stress applied to the TFT1 and TFT6 can be made smaller than that of the shift register shown in FIG. 20, so that the element characteristics of the TFT1 and TFT6 are not easily deteriorated and are not easily broken down even after long-term use. .

  Note that in each shift register described in this embodiment, the high level of the voltage signals V1 to V4 supplied to the drain of the TFT1 or the source of the TFT6 turns on the TFT2 and the TFT5 by the charges accumulated in the nodes A1 to An. As long as the voltage level is sufficient, the voltage may be lower than the power supply voltage Vdd. As a result, the voltage stress applied to the TFTs 1 and 6, and further the TFTs 2 and 5 can be made smaller than when the shift register is operated according to the timing charts described above.

[Other embodiments]
The present invention is not limited to the first and second embodiments, and various modifications and applications can be made. Hereinafter, other embodiments to which the present invention is applied will be described.

  In the second embodiment described above, whether the shift register applied as the gate driver 52 is shifted in the forward direction or the backward direction is determined by whether the angle sensor 40 detects the camera body portion of the lens unit portion 02. It is assumed that it is automatically set according to the angle with respect to 01. However, the user may select whether to operate in the forward direction or the reverse direction by operating a key of the key input unit 12.

  In the first and second embodiments, the shift register shown in FIGS. 4, 6, 8, 11, 13, 20, and 23 is applied as the gate driver 52 of the liquid crystal display device. Was described as an example. However, it can also be used as a driver for selecting a line of a display device other than a liquid crystal display device, such as a plasma display, a field emission display, or an organic EL display device. Furthermore, these shift registers can also be used as a driver for driving an imaging element in which imaging pixels are arranged in a predetermined arrangement (for example, matrix arrangement) in the vertical and horizontal directions.

  FIG. 26 is a block diagram illustrating a configuration of an image pickup apparatus having an image pickup element using a double gate transistor as a photosensor. This image pickup apparatus is used as a fingerprint sensor, for example, and includes a controller 70, an image pickup element 71, a top gate driver 72, a bottom gate driver 73, and a drain driver 74 as shown in the figure.

  The image sensor 71 is composed of a plurality of double gate transistors 81 arranged in a matrix. The top gate electrode 91 of the double gate transistor 81 is connected to the top gate line TGL, the bottom gate electrode 92 is connected to the bottom gate line BGL, the drain electrode 93 is connected to the drain line DL, and the source electrode 94 is connected to the ground line GrL. ing. A backlight that emits light in a wavelength region that excites the semiconductor layer of the double gate transistor 81 is placed below the image sensor 71.

  The double gate transistor 81 constituting the image sensor 71 has a top gate voltage when the voltage applied to the top gate electrode 91 is +25 (V) and the voltage applied to the bottom gate electrode 92 is 0 (V). Holes accumulated in the gate insulating film made of silicon nitride and the semiconductor layer disposed between the electrode 91 and the semiconductor layer are discharged and reset. In the double gate transistor 81, the voltage between the source electrode 94 and the drain electrode 93 is 0 (V), the voltage applied to the top gate electrode 91 is −15 (V), and the voltage applied to the bottom gate electrode 92 is It becomes 0 (V), and it becomes a photo-sensitive state in which holes of the hole-electron pairs generated by the incidence of light on the semiconductor layer are accumulated in the semiconductor layer and the gate insulating film. The amount of holes accumulated during this predetermined period depends on the amount of light.

  In the photo-sensitive state, the backlight irradiates light toward the double gate transistor 81. However, since the bottom gate electrode 92 located below the semiconductor layer of the double gate transistor 81 shields light in this state, sufficient carriers are present in the semiconductor layer. Not generated. At this time, when a finger was placed on the insulating film above the double gate transistor 81, the semiconductor layer of the double gate transistor 81, which is directly below the concave portion of the finger (corresponding to a groove that determines the fingerprint shape), was reflected by the insulating film or the like. Not much light is incident.

  In this way, a sufficient amount of holes with a small amount of incident light is not accumulated in the semiconductor layer, and the voltage applied to the top gate electrode 91 is −15 (V) and applied to the bottom gate electrode 92. When the applied voltage becomes +10 (V), the depletion layer spreads in the semiconductor layer, the n-channel is pinched off, and the semiconductor layer becomes high resistance. On the other hand, light reflected by an insulating film or the like is incident on the semiconductor layer of the double gate transistor 81 that is directly below the convex portion of the finger (the peak between the finger grooves) in the photo-sensitive state. When such a voltage is applied in a state where the holes are accumulated in the semiconductor layer, the accumulated holes are attracted to and held by the top gate electrode 91, so that the bottom gate electrode of the semiconductor layer is retained. An n-channel is formed on the 92 side, and the semiconductor layer has a low resistance. The difference in the resistance value of the semiconductor layer in these read states appears as a change in the potential of the drain line DL.

  The top gate driver 72 is connected to the top gate line TGL of the image sensor 71 and selectively applies a signal of +25 (V) or −15 (V) to each top gate line TGL according to the control signal group Tcnt from the controller 70. Output. The top gate driver 72 is substantially the same as the shift register constituting the gate driver 52 described above except for the difference in the level of the output signal, the difference in the level of the input signal corresponding to this, and the difference in the phase of the output signal and the input signal. Have the same configuration.

  The bottom gate driver 73 is connected to the bottom gate line BGL of the image sensor 71 and outputs a signal of +10 (V) or 0 (V) to each bottom gate line BGL according to the control signal group Bcnt from the controller 70. The bottom gate driver 73 is substantially the same as the shift register constituting the gate driver 52 except for the difference in the level of the output signal, the difference in the level of the input signal corresponding to this, and the difference in the phase of the output signal and the input signal. Have the same configuration.

  The drain driver 74 is connected to the drain line DL of the image sensor 71 and outputs a constant voltage (+10 (V)) to all the drain lines DL in a predetermined period to be described later according to a control signal group Dcnt from the controller 70. Precharge the charge. The drain driver 74 reads out the potential of each drain line DL that changes depending on whether or not a channel is formed in the semiconductor layer of the double gate transistor 81 in accordance with whether light is incident or not in a predetermined period after precharging. , And supplied to the controller 70 as image data DATA.

  The controller 70 controls the top gate driver 72 and the bottom gate driver 73 by the control signal groups Tcnt and Bcnt, respectively, and causes the drivers 72 and 73 to output signals of a predetermined level for each line at a predetermined timing. Thereby, each line of the image sensor 71 is sequentially brought into a reset state, a photo sensing state, and a reading state. The controller 70 also causes the drain driver 74 to read out the potential change of the drain line DL by the control signal group Dcnt, and sequentially captures it as image data DATA.

  In addition, the shift register shown in FIGS. 4, 6, 8, 11, 13, 20, and 23 may be applied for purposes other than as a driver for driving an image sensor or a display element. it can. For example, these shift registers can be applied to applications such as converting serial data to parallel data in a data processing device or the like.

  In the first and second embodiments, the TFTs 1 to 6 constituting the shift registers shown in FIGS. 4, 6, 8, 11, 13, 20, and 23 are all n-channel type. It was a thing. On the other hand, a p-channel type can also be used. For example, when all p-channel type signals are used, the high and low levels of each signal may be inverted compared to the n-channel type signals.

  In the first and second embodiments, the case where the present invention is applied to a digital still camera that captures a still image has been described as an example. However, in order to capture a moving image and visually recognize the captured image. The present invention can also be applied to a video camera using a liquid crystal display device or the like in the viewfinder. When the video camera is configured so that the orientation of the liquid crystal display device can be rotated with respect to the imaging lens, the shift register shown in the second embodiment is used as a gate driver of the liquid crystal display device to display a mirror image. Can do.

It is a figure which shows the external appearance structure of the digital still camera concerning the 1st Embodiment of this invention. It is a block diagram which shows the circuit structure of the digital still camera of FIG. It is a block diagram which shows the circuit structure of the display part of FIG. It is a figure which shows the circuit structure of the shift register used as a gate driver of FIG. 5 is a timing chart showing the operation of the shift register of FIG. It is a figure which shows the other circuit structure of the shift register used as a gate driver of FIG. 7 is a timing chart showing an operation of the shift register of FIG. 6. It is a figure which shows the other circuit structure of the shift register used as a gate driver of FIG. 9 is a timing chart showing an operation of the shift register of FIG. 8. 9 is another timing chart showing the operation of the shift register of FIG. 8. It is a figure which shows the other circuit structure of the shift register used as a gate driver of FIG. 12 is a timing chart showing the operation of the shift register of FIG. FIG. 4 is a diagram showing a circuit configuration of a shift register used as the gate driver in FIG. 3 in the second embodiment of the present invention. 14 is a timing chart showing a forward operation of the shift register of FIG. 14 is a timing chart showing a reverse operation of the shift register of FIG. In the 2nd Embodiment of this invention, it is a figure which shows the use condition in the forward direction of the digital still camera shown in FIG. 1, (a) shows an imaging state, (b) shows the display state of a display part. . In the 2nd Embodiment of this invention, it is a figure which shows the use condition in the reverse direction of the digital still camera shown in FIG. 1, (a) shows an imaging state, (b) shows the display state of a display part. . 14 is another timing chart showing a forward operation of the shift register of FIG. 14 is another timing chart showing the backward operation of the shift register of FIG. FIG. 4 is a diagram showing another circuit configuration of the shift register used as the gate driver of FIG. 3 in the second embodiment of the present invention. FIG. 21 is a timing chart showing a forward operation of the shift register of FIG. 20. FIG. 21 is a timing chart showing a reverse operation of the shift register of FIG. 20. FIG. 4 is a diagram showing another circuit configuration of the shift register used as the gate driver of FIG. 3 in the second embodiment of the present invention. FIG. 21 is a timing chart showing a forward operation of the shift register of FIG. 20. FIG. 21 is a timing chart showing a reverse operation of the shift register of FIG. 20. It is a block diagram which shows the structure of the imaging device concerning other embodiment of this invention. It is a figure which shows the circuit structure of the shift register of a prior art example. It is a timing chart which shows operation | movement of the shift register of a prior art example.

Explanation of symbols

1-6 ... TFT
DESCRIPTION OF SYMBOLS 01 ... Camera body part 02 ... Lens unit part 02a ... Imaging lens 10 ... Display part 11 ... Power key 12 ... Key input part 12a ... Mode setting key 12b ... Shutter key 12c ... "+" key 12d ... "-" key 13 ... Serial input / output terminal 20 ... CCD imaging device 21 ... A / D converter 22 ... CPU
23 ... ROM
24 ... RAM
25 ... Compression / decompression circuit 26 ... Image memory 30 ... Bus 40 ... Angle sensor 50 ... Liquid crystal controller 51 ... Liquid crystal display element 52 ... Gate driver 53 ... Drain driver 61 ... TFT
62 ... Pixel capacity 70 ... Controller 71 ... Image sensor 72 ... Top gate driver 73 ... Bottom gate driver 74 ... Drain driver 81 ... Double gate transistor 91 ... Top gate electrode 92 ... Bottom gate electrode 93 ... Drain electrode 94 ... Source electrode RS ( 1) to RS (n): stage GL: gate line DL: drain line TGL: top gate line BGL: bottom gate line GrL: ground line

Claims (7)

A shift register having a plurality of stages, each stage of the shift register being
A first transistor in which an output signal of a stage adjacent to one side is supplied to the control terminal, and a first voltage signal is supplied to one end of the current path;
A second transistor in which an output signal of a stage adjacent to the other side is supplied to the control terminal, and a second voltage signal is supplied to one end of the current path;
A control terminal is connected to the other end of each current path of the first and second transistors, and the first or second voltage signal supplied to the wiring between them through the first or second transistor In addition to accumulating charges, the first or second clock signal supplied to one end of the current path is output as the output signal of the stage from the other end of the current path when being turned on by the accumulated charge. A third transistor;
When switching to the forward shift, the charge is accumulated in the wiring by the high-level first voltage signal supplied through the first transistor, and the low level supplied through the second transistor. The charge accumulated in the wiring is released by the second voltage signal of
When switching to the reverse shift, the charge is accumulated in the wiring by the high-level second voltage signal supplied via the second transistor, and the low level supplied via the first transistor. The charge accumulated in the wiring is released by the first voltage signal of
One of the first and second transistors at one end of the plurality of stages is turned on when a first control signal is supplied to the control terminal from the outside, and charges are accumulated in the wiring.
The other of the first and second transistors at the other end of the plurality of stages is turned on when a second control signal is supplied to the control terminal from the outside, and the charge accumulated in the wiring is discharged,
The shift register according to claim 1, wherein a high level of the first and second voltage signals is smaller than a high level of the first and second clock signals. When switching to the forward shift, each period in which the first voltage signal is at a high level is equal to each period in which the first or second clock signal is at a high level,
When switching to the reverse shift, each period in which the second voltage signal is at a high level is equal to each period in which the first or second clock signal is at a high level. The shift register according to claim 1. A driver composed of a plurality of stages and configured to include a driver that sequentially outputs a signal of a predetermined level from each stage by shifting an output signal and a plurality of pixels, and is driven by an output signal output from each stage of the driver With elements,
Each stage of the driver
A first transistor in which an output signal of a stage adjacent to one side is supplied to the control terminal, and a first voltage signal is supplied to one end of the current path;
A second transistor in which the control terminal is supplied with the other output signal of the stage adjacent to the other side, and a second voltage signal is supplied to one end of the current path;
A control terminal is connected to the other end of each current path of the first and second transistors, and the first or second voltage signal supplied to the wiring between them through the first or second transistor In addition to accumulating charges, the first or second clock signal supplied to one end of the current path is output as the output signal of the stage from the other end of the current path when being turned on by the accumulated charge. A third transistor;
When switching to the forward shift, the charge is accumulated in the wiring by the high-level first voltage signal supplied through the first transistor, and the low level supplied through the second transistor. The charge accumulated in the wiring is released by the second voltage signal of
When switching to the reverse shift, the charge is accumulated in the wiring by the high-level second voltage signal supplied via the second transistor, and the low level supplied via the first transistor. The charge accumulated in the wiring is released by the first voltage signal of
One of the first and second transistors at one end of the plurality of stages is turned on when a first control signal is supplied to the control terminal from the outside, and charges are accumulated in the wiring.
The other of the first and second transistors at the other end of the plurality of stages is turned on when a second control signal is supplied to the control terminal from the outside, and the charge accumulated in the wiring is discharged,
The electronic device according to claim 1, wherein a high level of the first and second voltage signals is smaller than a high level of the first and second clock signals. The drive element is a display element provided with a display transistor for each pixel in which an output signal of any of the stages of the driver is supplied to a control terminal, and image data is supplied to one end of a current path from the outside The electronic device according to claim 3. An imaging unit including an imaging device that captures an optical image formed by the imaging lens, and a rotation unit that is rotatable with respect to the imaging unit about a direction substantially perpendicular to the imaging direction, and is displayed as the drive element A display unit including an element and the driver for driving the element;
The electronic device according to claim 3, wherein the display unit displays an image corresponding to an image captured by the imaging device on the display element. Setting means for setting whether to accumulate charges in the wiring via any one of the first and second transistors and to release the accumulated charges;
Angle detecting means for detecting an angle of the imaging unit with respect to the display unit;
The setting means performs setting according to the detection result of the angle detection means, and switches the level of the first and second voltage signals to thereby charge the wiring via one of the first and second transistors. The electronic device according to claim 5, wherein the electric charge accumulated in the wiring can be discharged through the other of the first and second transistors. The driving element is provided on one side of the semiconductor layer via a semiconductor layer that generates carriers by excitation light, a drain electrode and a source electrode that are respectively connected to both ends of the semiconductor layer, and a first gate insulating film. The first gate electrode and a second gate electrode provided on the other side of the semiconductor layer with a second gate insulating film interposed therebetween for each pixel,
4. The driver according to claim 3, wherein the driver includes a first driver that outputs an output signal to the first gate electrode, and a second driver that outputs an output signal to the second gate electrode. 5. Electronic equipment.

Images