JPH02246585A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To transmit a signal in both directions without increasing the number of external terminals by using an initial pulse as the pulse which indicates the signal transmission direction. CONSTITUTION:An initial pulse HINR which indicates the shift operation in the right direction (reverse) is supplied to the gate of a MOSFET Q4, and an initial pulse HINF which indicates the shift operation in the left direction (forward) is supplied to the gate of a MOSFET Q5. An output signal OUT1 of a first circuit in the next stage is supplied to the gate of a MOSFET Q6. Since initial pulses are used as pulses which indicate signal transmission directions in this manner, the signal is transmitted selectively in both directions from one to the other or inversely without increasing the number of external terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is effective for use in, for example, a MOS type solid-state image device including a dynamic shift register.

[Conventional technology]

Traditionally, photodiodes and switch MOSFETs
(Insulated gate field effect transistor) A MO5 type solid-state imaging device is known. Regarding such solid-state imaging devices, for example, Coronasha RTI Imaging Engineering, pages 126 to 147, September 1985, ``Television Society Technical Report 1, pages 49 to 54, and Japanese Patent Application Laid-Open No. 1986-1
There are publications such as No. 52382.

[Problem to be solved by the invention]

In solid-state imaging devices such as those described above, dynamic shift registers are used to perform horizontal scanning operations and vertical scanning operations. By using a dynamic shift register in such a scanning circuit, it becomes possible to simplify the circuit, increase its density, and reduce power consumption.

However, as a dynamic shift register, one that performs bidirectional shifting operations like a static shift register has not been developed, so in the above-mentioned solid-state imaging device, the scanning direction is uniquely determined. 0 Currently, in solid-state imaging devices used in ordinary video table recorders and the like, no particular problem has been pointed out due to the above-mentioned scanning direction being uniquely determined. However, in monitoring devices, it is often necessary to use a mirror to take pictures in order to hide the camera body. When photographing using a mirror, the left and right sides of the subject are reversed. therefore,
When monitoring this or playing back what was recorded on a video tape recorder, the left and right images are swapped. Therefore, it is possible to form a solid-state imaging device with the scanning direction reversed. However, because its uses are limited, mass production is poor and costs are high. Furthermore, when providing a bidirectional shift function to the dynamic shift register as described above, it is desirable not to increase the number of external terminals in order to reduce the size of the package of the semiconductor integrated circuit device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device including a dynamic signal transmission circuit that enables bidirectional signal transmission.

Another object of the present invention is to provide a semiconductor integrated circuit device including a bidirectional dynamic shift register without increasing the number of external terminals.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a first timing pulse and a second timing pulse having different phases under non-overlapping conditions are respectively supplied to the drains, and the gate capacitance is used as a storage means, and an output signal is sent from the source.
A plurality of circuits including a pair of first and second circuits each including a T, a capacitive means provided between the gate and the source of the MOSFET, and a unidirectional element that transmits a signal from the source of the MOSFET. and a MOSFET of a first or second circuit disposed in the previous stage or the next stage, each of which is switch-controlled by a control signal that selectively instructs the direction of signal transmission, and which transmits the signal passed through the unidirectional element. A signal transmission circuit is constituted by a pair of MO5FET switches that transmit signals to the gates of the MO5FET and a pair of input circuits that are selectively activated by the control signal to the unit circuits disposed at one end and the other end. A MOS FET that stores a signal transmission direction in which a control signal instructing the transmission direction is supplied to the gate, and an initial pulse which also serves as a signal transmission instruction is supplied to the drain, through a unidirectional element. output from the source.

[For production]

According to the above-mentioned means, since the initial pulse can be used as a pulse for instructing the signal transmission direction, the signal transmission operation can be performed selectively from one side to the other side or in the opposite direction while preventing an increase in the number of external terminals. becomes possible.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment in which the present invention is applied to a dynamic shift register. Each circuit element in the figure may be made of a material such as single-crystal silicon, although it is not particularly limited by known semiconductor integrated circuit manufacturing technology.
formed on a single semiconductor substrate. In the figure, a 4-bit dynamic shift register consisting of 0UTI to 0UT4 is exemplarily shown to avoid complicating the drawing.

MOSFETQI performs a storage operation and an output operation, that is, MOSFETQI uses its gate capacitance as storage means. When the gate capacitance is held at a high level,
MOS FETQ 1 is turned on and transmits the high level of the timing pulse H1 supplied to its drain to its source side. The signal on the source side is the output signal 0UTI. At this time, in order to prevent the level of the output signal 0UTI from decreasing due to the threshold voltage of the MOSFETQI, a bootstrap capacitor C1 is provided between the gate and source of the MOSFETQI.

A diode-shaped MOSFETQ3 is provided at the source of the MO5FETQI to perform a signal transmission operation. This MOSFETQ3 is MO5FETQI
The output signal 0UTI is reset at high speed between the source of the MOSFET QI and the ground potential point of the circuit, although it is not particularly limited. A reset MO5FETQ2 is provided for causing the oscillation to occur. This reset M
The above timing pulse H is applied to the gate of O5FETQ2.
A timing pulse H2 is supplied which has a non-overlapping period such that the high level does not overlap with that of the timing pulse H1 and the timing pulse H2 has a phase different from that of the timing pulse H1.

The source side (node N4) of MOSFETQ3 in the form of a diode is connected to the output signal 0UTI of MOSFETQI.
A transmission circuit is provided for transmitting. In this embodiment, since this circuit is provided at the left end, a switch MOSFET QI 2 is used to realize a shift operation in the right direction.
is provided.

That is, in other unit circuits, a switch MOSFET is provided to perform a bidirectional shift operation, but in the above circuit, this is omitted. A signal from a node N6 as described later is supplied to the gate of the MOSFET Q12.

Further, the node N4 of the first circuit and the ground potential H of the circuit
Reset MOSFETs Q4 to Q6 are provided between the transistors and S.

The gate of MOS FETQ 4 has an initial pulse HIN that instructs a rightward (reverse) shift operation.
R is supplied to the gate of MOSFETQ5 in the left direction (
An initial pulse HINF instructing a shift operation to forward) is supplied. Then, the output signal 0UTI of the first circuit at the next stage is supplied to the gate of MOSFETQ6.

The unit circuit (first circuit) for half a bit is composed of MOS FETQ 1 to Q6 as described above,
A similar second circuit is depicted vertically symmetrical to the first circuit.

The second circuit for half a bit, which is a pair of the first circuit, is:
MOSFETQ? It consists of Qll, etc. However, the timing pulse H2 is supplied to the drain of MOSFET Q7 that performs storage and output operations. Furthermore, a timing pulse H1 is supplied to the gate of the reset MOSFET Q8 provided on the output side N2. And MOSFETQ9 as a unidirectional element of the second circuit
The output signal passed through is supplied to the first circuit as a human input signal. No FNl&, which is the input of the second circuit:
is supplied with forward initial pulse (IINF) via MOSFET QI OO, Ql 01, and M
The output signal of the first circuit in the next stage unit circuit is transmitted via OSFETQ35. Above MOSFETQ35
is the initial pulse HI for reverse as described later.
It is controlled by storage information N13 stored in N R.

The other unit circuits corresponding to the output signals 0UT2 to 0UT4 are also basically composed of the same circuit as the unit circuit of the output terminal 0UTI. Therefore, the circuit symbol attached to the MOSFET is omitted. However, output 0UT2
and 0UT3 perform bidirectional shift operation, so the configuration of the reset circuit provided at the output node via the diode MOS FET of each first and second circuit and the configuration of the MOSFET that determines the signal transmission direction are slightly different. It is a material. That is, in the unit circuit consisting of the first circuit and the second circuit corresponding to the outputs 0UT2 and 0UT3, each of the reset MOSFETs is composed of four pieces, and the initial pulses HINF and HINR and the output signal of the adjacent hundred unit circuit A reset is performed. The signal transmission MOSFETs are both provided with MOSFETs that are switch-controlled by the forward or reverse recontrol signal and the timing pulse H1. Since the unit circuit corresponding to the output 0UT4 is placed at the right end and performs a shift operation only in the left direction (reverse), the reset circuit and the signal transmission MOSFET are connected to the unit circuit corresponding to the output 0UTI. is the opposite.

In this embodiment, the shift direction is also determined using the initial pulse. That is, the circuit A shown by the dotted line in the figure forms a control signal that determines the shift operation in the forward direction. Initial pulse HIN for forward
F is connected to the gate of MOS FETQ112 (node N5
).

This MO5F'ETQ112 uses its gate capacitor as a storage means and stores the input of the above-mentioned initial pulse HINF. A timing pulse H1 is supplied to the drain of each MOSFET QI 12.

A bootstrap capacitor is provided between the gate and source of MOSFET QI 12.

To reset the input circuit A, between the node N5 and the ground potential H5 of the circuit, a MOS FETQ114 receiving the reverse initial pulse HINR and a MOS FETQ! receiving the output 0UT4 are connected. 15 are provided. That is, when the reverse initial pulse HTNR is supplied and when the shift operation in the forward direction is performed up to the final stage 0UT4, the stored information (N5) instructing the forward shift is reset.

The storage MOSFET QI 12 switches the MOSFET that determines the shift direction in synchronization with the timing pulse) 11. Therefore, node N6 is reset to low level by the MOSFET receiving timing pulse H2 when timing pulse H2 is high level. As a result, a shift operation for half a bit when the timing pulse H2 is set to a high level, as will be described later, is performed.

A circuit B indicated by a dotted line in the figure forms a control signal that determines the shift operation in the reverse direction. The reverse C initial pulse 141 N R is MO5F in diode form.
It is transmitted to the gate (node N12) of MOSFETQ102 via ETQI O3. This MOSFETQI
O2 uses its gate capacitance as a storage means to store the input of the initial pulse HENR. This MOSFE
A timing pulse H1 is supplied to the drain of TQ102. A bootstrap capacitor is provided between the gate and source of MOSFET QI O2. In order to reset the input circuit B, a MO5FET QI 04 is connected between the node N12 and the ground potential H3 of the circuit to receive the forward initial pulse HINF.
and a MOSFET Q105 that receives the output 0UTI. In other words, the forward initial pulse HI
When NF is supplied and when the shift operation is performed to the final stage 0UTI in the reverse direction shift operation,
The stored information (N12) instructing the reverse shift is reset.

The storage MOSFET QI 02 switches the MOSFET that determines the shift direction in synchronization with the timing pulse H1. Therefore, the node N13 is reset to low level by the MOSFET receiving timing pulse H2 when timing pulse H2 is high level.

As a result, a half-bit shift operation is performed when the timing pulse H2 is set to a high level, as will be described later.

An example of the forward direction operation of the Guinamisoku type shift register shown in FIG. 1 will now be described with reference to the timing diagram shown in FIG. 2.

When performing a shift operation in the forward direction, the forward initial pulse HINF is set to a high level. As a result, each reset MOSFET turns on and each node is reset, and the node N5 also becomes high level (Vcc-Vth) via the diode-type MOSFET QI13. timing pulse H1
When becomes a high level, the MOSFET Q in the on state
Node N6 is pulled high via I13. The high level of this node N6 turns on the MOS FET that transmits signals in the forward direction between each unit circuit. Also, forward initial pulse HI
The high level of NF turns on the MOS FETQ 101, and a high level is set at the node Nl, which is the input of the second circuit in the unit circuit corresponding to the output 0UTI. At this time, in the second circuit, MOSFET QB is turned on due to the high level of the timing pulse H1, and is in a reset state.

When the timing pulse H2 becomes high level, the reset MOSFET is turned on and the node N6 becomes low level. As a result, the MOSFETs that transmit signals in the forward direction between each unit circuit are turned off. Due to the high level of the evening timing pulse H2, the second circuit raises the node N2 to a high level through the storage MOSFET Q7. The high level of this node N2 is transmitted to the node N3, which is the power of the first circuit, through a diode-type MOSFET Q9. At this time, the first circuit is in a reset state with MOSFET Q2 turned on by the high level of the timing pulse H2.

When the timing pulse H1 becomes high level, the MOS turned on due to the high level of the node N3
Output 0UTI is set to high level through FETQI. The high level of the timing pulse H1 resets the node N2 of the second circuit to the low level through the MOSFET Q8. In addition, the node N5 is bootstrapped with the timing pulse H1 to a high level, and transmits the high level of the timing pulse H1 to the node N6. As a result, MOSFETQ12, which transmits signals in the forward direction, is turned on.

Therefore, the high level of the output 0UTI is transmitted to the input node N7 of the second circuit of the output 0UT2 through the diode-type MOSFET Q3 and the MOSFET Q12. Further, the high level of the output OUT turns on the MOSFET QI 08 and resets the node N1 to the low level.

When the timing pulse H2 becomes high level, the reset MOSFET is turned on and the node N6 becomes low level, similarly to the operation of the second circuit in the unit circuit corresponding to the output 0UTI. This allows the MOSFE to transmit signals in the forward direction between each unit circuit.
T is turned off. Due to the high level of the timing pulse H2, the second circuit corresponding to the output 0UT2 raises the output node to a high level through the storage MOS FET. The high level of this output node is transmitted to the input node of the first circuit through a diode-type MOSFET. At this time, the first circuit resets the reset MOSFE by the high level of the timing pulse H2.
T is in the on state and in the reset state.

Then, when the timing pulse H1 becomes high level,
Similarly to the operation of the first circuit corresponding to the output 0UTI, the output 0UT2 is brought to a high level through the storage MOSFET which is turned on by the high level of the input node.

The input node N7 of the second circuit that sets the timing pulse H1 to a high level is connected to the MOSFET Q12 and the MOSFET Q12.
It is reset to low level with NO PN4 through SFETQ6. The output node of the second circuit is reset by the reset MOSFET turned on by the high level of the timing pulse H1.

Thereafter, by repeating similar operations, a half-bit shift operation is performed in the forward direction up to the output 0UT4 in synchronization with the timing pulses H1 and H2.

An example of the operation of the dynamic shift register shown in FIG. 1 in the reverse direction will now be described with reference to the timing diagram shown in FIG. 3.

When performing a shift operation in the reverse direction, the reverse initial pulse HINR is set to a high level. As a result, each reset MOSFET turns on and each node is reset, and the diode-type MOSFET
The timing pulse H causes the node N12 to also go to high level (Vcc-Vth) via ETQI O3.
When 1 becomes high level, the MOSFET in the on state
Node N13 is driven high via QI 03. The high level of this node N13 turns on the MOSFETs that transmit signals in the reverse direction between each unit circuit. In addition, the initial pulse HIN for reverse
MOSFET QI L8 and MOSFET QIII are turned on by the high L/H/L/ of the timing pulse H1 and the high level is set at the node N8, which is the input of the second circuit in the unit circuit corresponding to the output 0UT4. Ru. At this time, in the second circuit, the reset MOSFET is turned on due to the high level of the timing pulse H1, and a reset is applied.

When the timing pulse H2 becomes high level, the reset MOSFET is turned on and the node N13 becomes low level. As a result, the MOSFETs that transmit signals in the reverse direction between each unit circuit are turned off. Due to the high level of the timing pulse H2, the second circuit raises the node N9 to a high level through the storage MO5FET. The high level of this node N9 is transmitted to the node NIO, which is the input of the first circuit, through a diode-type MOSFET. At this time, the first circuit is reset with the reset MO5FET turned on by the high level of the timing pulse H2.

When the timing pulse H1 becomes high level, the output 0UT4 is made high level through the storage MOS FET which is turned on due to the high level of the node NIO. Due to the high level of the timing pulse H1, the nodes N8 and N9 of the second circuit are connected to the MOSFET QI
18 and reset MOSFET to a low level.

Further, the node N12 is bootstrapped to a high level by the high level of the timing pulse H1, and
The high level of timing pulse H1 is transmitted to node N13. This allows MO to transmit signals in the reverse direction.
SFET turns on. Therefore, the output 0U
The high level of T4 is transmitted to the input node N14 of the second circuit of the output 0UT3 through the diode-type MOSFET and the MOSFET that performs signal transmission in the reverse direction.

When the timing pulse H2 becomes high level, the reset MO8FET is turned on and the node N13 becomes low level, similarly to the operation of the second circuit in the unit circuit corresponding to the output 0UT4. This allows the MOSFET to transmit signals in the reverse direction between each unit circuit.
is turned off. The second circuit corresponding to the output 0UT3 due to the high level of the timing pulse H2,
The output node is raised to high level through the storage MOS FET. The high level of this output node is transmitted to the input node of the first circuit through a diode-type MOS FET. At this time, the first circuit is activated by the reset MOS due to the high level of the timing pulse H2.
The FET is in the on state and in the reset state.

Then, when the timing pulse H1 becomes high level,
Similarly to the operation of the first circuit corresponding to the output 0UT4, the high level of the input node causes the output 0UT3 to go high through the storage MOSFET which is in the on state.

Due to the high level of the timing pulse H1, the input node N14 of the second circuit is reset to the low level together with the node Nil through the MOSFET for transmitting signals in the reverse direction and the reset MOSFET. The output node of the second circuit is connected to a reset M that is turned on by the high level of the timing pulse H1.
Reset by OS FET.

Thereafter, by repeating similar operations, a shift operation of half bits at a time is performed in the reverse direction in synchronization with timing pulses H1 and H2 up to the output 0UTl.

FIG. 4 shows a circuit diagram of a main part of an embodiment of a solid-state imaging device in which the dynamic shift register described above is used. In the figure, a circuit for three rows and two columns is exemplarily shown as a representative circuit. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques. Although some of the circuit symbols given to the MOS FET in the figure overlap with the circuit symbols of the MOS FET shown in FIG. 1, it should be understood that they each have separate circuit functions.

One pixel cell includes a photodiode Di and a switch MO5FETQ whose gate is coupled to the vertical scanning line v1.
It consists of a series circuit of MOSFET I01 and a switch MOSFET QIO2 whose gate is coupled to the horizontal scanning line H1. Above photodiode DI and switch MOSFE
Other similar pixel cells (D2.Q1) arranged in the same row (horizontal direction) as the pixel cell consisting of TQI O1, Q102
Output nodes such as 03°Q104) are coupled to a horizontal signal line H3I extending in the horizontal direction in the figure.

Pixel cells similar to those described above are similarly combined for other rows. Vertical scanning lines Vl corresponding to the horizontal signal lines HSI and the like are arranged in parallel.

For this vertical scanning &iVl, the corresponding pixel cell switch MOSFETQI 01, Q10 is used as described above.
3rd class will be combined. This also applies to the vertical scanning lines (2) and (3) of the other rows shown as examples.

The horizontal scanning line extends vertically in the figure, and the switch MOSFET QI 0 of the pixel cells arranged in the same column.
2. The gates of QI O6, and Qllo are coupled to a common horizontal scan mH1. Pixel cells arranged in other columns are also coupled to the corresponding horizontal scanning line H2 etc. in the same manner as described above.

The vertical scanning lines mV1, v2, and v3 are connected to the horizontal signal line H3I or a switch MOSFET QI that connects HS3 to the output line ■S extending in the vertical direction.
It is also coupled to the gates of Q13 through Q115. A read load resistor R is provided between this output line S and the bias voltage VB.

When a pixel cell is selected through this load resistance R,
By flowing a current corresponding to the optical signal accumulated in the photodiode, a read operation from the pixel cell and a reset (precharge) operation for the next read operation are performed simultaneously. The voltage signal obtained by the load resistor R is amplified by the preamplifier PA and outputted through an output circuit (not shown).

In this embodiment, the horizontal signal lines H3I to H of each row are
33 is a reset MOS FET Q12Q or Q in order to remove false signals such as smear and blooming.
122 is provided. These MO5FETQI 20
Q122 to Q122 are turned on during the horizontal retrace period according to the timing relationship described later, and are connected to each horizontal signal line H.
It supplies bias voltage VB to 3L to H83, etc.

These reset MOSFETQI 20 to Q1
The operation of 22 is as follows. When vertical scanning line ■1 is at high level, the read operation of the first row is performed on horizontal scanning line H1.
, H2, . . . are sequentially brought to a high level in time series.

In other words, by flowing a current corresponding to the optical signal accumulated in the photodiode of the pixel cell selected one after another in this way, the readout operation from that pixel cell and the reset (preparation) for the next readout operation are performed. (charging) operation is performed at the same time. A voltage signal corresponding to the photocurrent obtained by the load resistor R is sent to the preamplifier PA.
The signal is amplified by and output through an output circuit (not shown).

When the reading of one row is completed, a horizontal retrace period begins. During this period, the vertical scanning line V1 is
level to low level, and is switched to a non-selected state. Then, the reset signal R8 is set to high level,
Each of the above reset MO5FETQ120 to QI22
Turn on.

As a result, the above-mentioned false signals generated in the non-selected horizontal signal line H32 etc. are reset.

Horizontal scanning lines H1゜H2... of the solid-state imaging device as described above.
A bidirectional dynamic shift register as shown in FIG. 1 is used as the horizontal shift register HSR that forms a selection signal for sequentially selecting . Since the bidirectional dynamic shift register performs shift operations in the forward and reverse directions as described above, it is possible to arbitrarily specify the scanning direction of the horizontal scanning line. With this, for example, when a shift operation in the forward direction is specified, normal pixel signal reading is performed. On the other hand, if a shift operation in the reverse direction is specified, it becomes possible to read out an image signal with the left and right sides reversed. For example, when applied to a surveillance camera, when the surveillance camera body is fitted into the ceiling or wall and the subject is photographed through a mirror, the left and right can be reversed by specifying the shift operation in the reverse direction. You can get a video signal.

Note that the vertical scanning lines Vl, V2 . If a bidirectional dynamic shift register is used in the same way as above as the vertical shift register VSR that forms the selection signals such as V3...,
It is also possible to obtain a video signal with the top and bottom reversed. As described above, if two-way dynamic shift registers are used as the horizontal and vertical shift registers and both are instructed to shift in the reverse direction, the subject will be moved to 180".
A rotated video signal can be obtained.

For example, if the above function is provided in a solid-state imaging device for a video tape recorder and can be specified arbitrarily by operating a switch, it will be possible to use it to take images with left/right inversion, up/down inversion, and 180@ rotation. , and allows you to play games such as trick photography.

The effects obtained from the above examples are as follows. That is, (1) the first timing pulse and the second timing pulse having different phases under non-overlap are respectively supplied to the drain, the gate capacitance is used as a storage means, and an output signal is sent from the source. A plurality of units each including a pair of first and second circuits each including a MOSFET, a capacitor provided between the gate and the source of the MOSFET, and a unidirectional element that transmits a signal from the source of the MOSFET. The circuit is controlled by a switch and a control signal that selectively instructs the direction of signal transmission, and the signal passing through the unidirectional element is transmitted to a first stage disposed in the previous stage or the next stage.
or by a pair of switches MO5FET that transmits information to the gate of the MOS FET of the second circuit, and a pair of input circuits that are selectively activated by the control signal to the unit circuits arranged at one end and the other end. An initial pulse that constitutes a signal transmission circuit and also serves as a signal transmission direction is supplied to the gate through a unidirectional element, and a control signal indicating the signal transmission direction is supplied to the gate, and the first timing pulse is supplied to the drain. MOS that remembers signal transmission direction
By outputting from the source of the FET, it is possible to achieve the effect that bidirectional signal transmission operation becomes possible.

(2) By using the initial pulse as a pulse that indicates the direction of signal transmission, it is possible to selectively perform a shift operation from one side to the other or the opposite direction while preventing an increase in the number of external terminals. You can get the effect of

(3) By using the dynamic shift register described above as a shift register that forms the scanning timing signal of a solid-state imaging device, it is possible to capture images equivalent to images where the subject is flipped horizontally or vertically, and the package in which it is mounted can be made smaller. This has the effect of making it possible.

(4) According to (3) above, even if you use a mirror to take pictures, it is possible to obtain a video signal with a reversed subject returned to its original state.
, the effect of being able to obtain a normal video signal can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment circuit of FIG. 1, the reset MOS FET may be omitted. In this case, for example, the logic "1"
It is possible to configure a signal transmission circuit in which the signal ``is transmitted selectively and sequentially in both directions in accordance with the timing pulses H1 and H2.

The vertical signal lines of the solid-state imaging device shown in FIG. 4 may be shifted by one line for odd-numbered fields and one for even-numbered fields, so that pairs of vertical signal lines are selected.

This makes it possible to obtain an image signal whose spatial center of gravity is moved up and down with respect to the interlace.

In this case, a pair of output lines may be provided corresponding to the horizontal signal lines selected one by one. In this way, the specific configuration of the solid-state imaging device can take various embodiments.

In addition to the solid-state imaging device, the present invention can be widely applied to various semiconductor integrated circuit devices including signal transmission circuits and dynamic shift registers that are capable of selectively transmitting signals in both directions as described above. .

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a first timing pulse and a second timing pulse having different phases under non-overlapping conditions are supplied to the drains of the MOS F, the gate capacitance of which is used as a storage means, and an output signal is sent from the source.
ET, capacitive means provided between the gate and source of the MOSFET, and a unidirectional element for transmitting a signal from the source of the MOSFET, respectively.
A plurality of unit circuits each having a pair of circuits, and a first circuit which is switch-controlled by a control signal that selectively instructs the direction of signal transmission, and which transmits the signal passed through the unidirectional element at the previous stage or the next stage. Or a signal is transmitted to the gate of the MOS FET of the second circuit by a pair of switch MOSFETs and a pair of input circuits that are selectively activated by the control signal to the unit circuits arranged at one end and the other end. A system that configures a transmission circuit and instructs the direction of signal transmission? 11 signal is outputted from the source of a MOS FET which stores the signal transmission direction in which the gate is supplied with an initial pulse that also serves as the signal transmission direction and the drain is supplied with the first timing pulse. This enables bidirectional signal transfer operations.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a dynamic shift register to which the present invention is applied; FIG. 2 is a timing diagram for explaining an example of forward direction operation of the dynamic shift register; FIG. 3 is a timing diagram for explaining an example of the operation of the dynamic shift register in the reverse direction, and FIG. 4 is a main circuit diagram showing an example of a solid-state imaging device to which the dynamic shift register is applied. It is a diagram. VSR...Vertical shift register, H3R...Horizontal shift register, PA...Preamplifier 0U-2 0LIT3 Figure Figure

Claims (1)

[Claims] 1. A first MOSFET whose drain is supplied with a first timing pulse, whose gate capacitance is used as a storage means, and whose source outputs an output signal;
A first circuit including capacitive means provided between the gate and source of the T and a unidirectional element for transmitting a signal of the source of the first MOSFET, and the first timing pulse are mutually connected to each other. a second MOSFET whose drain is supplied with a second timing pulse having a different phase, whose gate capacitance is used as a storage means, and whose source outputs an output signal;
A plurality of units each pairing a second circuit including a capacitive means provided between the gate and the source of the second MOSFET and a unidirectional element that transmits a signal from the source of the second MOSFET. a first MOSFET that stores a signal transmission direction whose gate is supplied with a pulse indicating one signal transmission direction through a unidirectional element and whose drain is supplied with the first timing pulse; a second MOSFET whose gate is supplied with a pulse instructing the other signal transmission direction via the directional element, and whose drain stores the signal transmission direction in which the first timing pulse is supplied;
and first and second MOSFs that store the signal transmission direction.
Each switch is controlled by a control signal selectively output from the source of the ET, and the signal passed through the unidirectional element is transmitted to the M of the first or second circuit disposed at the previous stage or the next stage.
A pair of switches MOSFE that communicates to the gate of OSFET
T, a second circuit in a unit circuit disposed at one end, and a second circuit in a unit circuit disposed at the other end, which receives the first timing pulse and transmits a pulse instructing one or the other transmission direction. 2nd MOSFET of circuit 2
1. A semiconductor integrated circuit device comprising a signal transmission circuit comprising a pair of input circuits for supplying an initial signal to the gate of the semiconductor integrated circuit device. 2. The signals passed through the unidirectional elements in the first and second circuits are connected to the first and second M circuits that store the signal transmission direction.
Switch MOSFEs each controlled according to a control signal selectively output from the source of the OSFET
The signal is transmitted through T to the gate of a reset MOSFET that resets the signal passed through the unidirectional element in the corresponding first and second circuits of the unit circuit arranged in the previous stage or the next stage. 2. The semiconductor integrated circuit device according to claim 1, wherein the transmission circuit operates as a bidirectional dynamic shift register. 3. The signal transmission circuit that operates as the bidirectional dynamic shift register forms a scanning signal that performs a photoelectric conversion signal readout operation in a MOS solid-state imaging device. 2. The semiconductor integrated circuit device according to item 2.