JP2001101889A - Shift register and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shift a signal to a poststage without attenuating the level of an output signal and to prevent destruction and a malfunction caused by the parasitic capacity of a transistor. SOLUTION: This device is constituted by connecting stages consisting of TFT 21-25, 31. The TFTY 21 is turned on by a control signal from a terminal Φ, and makes a capacitor A accumulate electric charges by inputting an output signal (high level) of the preceding stage from a terminal IN. Thereby, the TFT 22, 24 are turned on, the TFT 25 is turned off, a clock signal from a terminal c1k is made a high level, then, this signal is outputted from a terminal OUT through the TFT 24 as an output signal of the stage. At the time, a potential of the capacitor A is raised by that parasitic capacity of the TFT 24 is charged. When an output signal of the preceding stage inputted to a terminal IN is varied to a low level, as a potential of the capacitor A is divided by the THT 31, voltage between a drain and a source of the TFT 21 is suppressed to the fixed value or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a shift register,
In addition, the present invention relates to an electronic device such as an imaging device and a display device to which the shift register is applied as a driver.

[0002]

2. Description of the Related Art A driver for selecting and scanning an image pickup element or a display element in which pixels are arranged in a matrix in a line-sequential manner includes a shift register for sequentially shifting an output signal from a previous stage to a subsequent stage. Used. Conventionally, among such shift registers, there has been one in which the output signal from the preceding stage is attenuated each time it is shifted to the subsequent stage.

[0003] Particularly, in recent years, demands for higher definition of image pickup devices and display devices have necessitated increasing the number of stages of such shift registers. When the number of stages increases, a problem arises in that signal attenuation in the later stage becomes severe. Therefore, conventionally, such a shift register is usually provided with a buffer for amplifying an output signal from each stage to a predetermined level. But,
The provision of the buffer has a problem that the size of the shift register is increased.

In order to sequentially shift the output signal by such a shift register, there is a type in which a control signal is externally supplied to the electrode of the field effect transistor. However, since a field-effect transistor has a parasitic capacitance, the voltage of a control signal supplied from the outside may increase to the voltage of another electrode of the transistor. For this reason, there has been a problem that a large voltage is applied to another element connected to the other electrode and the other element is destroyed, or a malfunction is caused by the accumulated charge.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a shift register capable of shifting a level of an output signal to a subsequent stage without attenuating the level, and an electronic device to which the shift register is applied. And

Another object of the present invention is to provide a shift register capable of preventing destruction or malfunction due to parasitic capacitance of a transistor, and an electronic device to which the shift register is applied.

[0007]

In order to achieve the above object, a shift register according to a first aspect of the present invention is a shift register having a plurality of stages, wherein each stage of the shift register is externally provided. A first transistor which is turned on by the first or second signal supplied to the control terminal, and outputs a signal of a predetermined level supplied from one adjacent stage to one end of the current path to the other end of the current path; It is turned on by the electric charge stored in the capacitance between the control terminal and the other end of the current path of the first transistor, and emits a signal supplied to one end of the current path via the load from the other end of the current path. The third transistor or the fourth transistor is turned on by the electric charge accumulated in the capacitor between the second transistor and the control terminal and the other end of the current path of the first transistor, and is supplied to one end of the current path from outside.
Output from the other end of the current path as the output signal
And the second transistor is turned on by a signal supplied to a control terminal via a load when the second transistor is off, and a signal supplied from the outside to one end of the current path is used as an output signal to output the other of the current path. A fourth transistor output from one end of the first transistor and a current path of the first transistor, which is provided between the other end of the current path of the first transistor and the capacitor to divide the voltage of the capacitor; And a voltage dividing element to be applied to both ends.

Here, the first stage of the shift register does not have one of the adjacent stages. In this case, a signal of a predetermined level supplied from one end of the current path of the first transistor can be replaced with a signal corresponding thereto supplied from an external control device or the like, for example.

In the shift register according to the first aspect, the level of the output signal from each stage is substantially equal to the level of an externally supplied signal when the third and fourth transistors are on. Things. Therefore, it is possible to sequentially shift the output signal without attenuating the level.

When the third transistor is turned on and a high-level third or fourth signal is supplied to one end of the current path, the parasitic capacitance is charged up and the voltage of the capacitance is increased. It can happen to rise. But,
In the shift register according to the first aspect, since a voltage dividing element is provided in each stage, it is possible to prevent the voltage between one end and the other end of the current path of the first transistor from becoming unnecessarily large. Can be. Therefore, it is possible to prevent the first transistor from being broken and the shift register from being broken.

In the shift register according to the first aspect, a predetermined voltage is applied to a control terminal of the voltage dividing element, and both ends of the current path are respectively connected to the other end of the current path of the first transistor and the other end of the current path. Connected to the capacitor.

In the shift register according to the first aspect, a third signal of the third and fourth signals is externally supplied to an odd-numbered stage, and a third signal is supplied to an even-numbered stage. , The fourth signal among the fourth signals may be supplied from the outside. In this case, each of the third and fourth signals may alternately have a drive level for each time slot during a predetermined period among time slots in which the output signal of the shift register is shifted.

In this case, the first and second signals can be set to the on level for a certain period of time while the third and fourth signals are at the drive level, respectively.

In order to achieve the above object, a shift register according to a second aspect of the present invention is a shift register including a plurality of stages, wherein each stage of the shift register has a predetermined level from one of adjacent stages. A first transistor that is turned on when an output signal of the current path is supplied to the control terminal and outputs a signal of a predetermined level supplied from the previous stage to one end of the current path to the other end of the current path; The transistor is turned on by the electric charge stored in the capacitor between the other end of the current path of the control terminal of the transistor and the control terminal, and emits a signal supplied to one end of the current path through the load from the other end of the current path. 2 and the first transistor, which is turned on by the electric charge accumulated in the capacitor between the other end of the current path of the control terminal of the first transistor and the control terminal, and is supplied to one end of the current path from outside.
Or a third transistor that outputs a second signal as an output signal of the stage from the other end of the current path, and a signal supplied to a control terminal via a load when the second transistor is off. A fourth transistor that turns on and outputs a signal of a constant voltage externally supplied to one end of the current path as an output signal of the stage from the other end of the current path, and an output signal of a predetermined level from the other adjacent stage. It is turned on by being supplied to the control terminal, and discharges the electric charge accumulated in the capacitance formed between the other end of the current path of the first transistor and the control terminals of the second and third transistors. A fifth transistor is provided between the other end of the current path of the first transistor and the capacitor, and divides the voltage of the capacitor so that the voltage is applied to both ends of the current path of the first transistor. To Characterized in that it comprises a first voltage dividing element that.

Here, the first stage and the last stage of the shift register do not have one of the adjacent stages. In this case, the signal of a predetermined level supplied from one end of the current path of the first transistor and the signal supplied to the control terminal of the fifth transistor are supplied from, for example, an external control device. A predetermined signal can be used instead.

In the shift register according to the second aspect, the level of the output signal from each stage is substantially equal to the level of an externally supplied signal when the third and fourth transistors are on. Things. Therefore, it is possible to sequentially shift the output signal without attenuating the level.

When a third or fourth high level signal is supplied to one end of the current path while the third transistor is on, the parasitic capacitance is charged up and the voltage of the capacitance is increased. It can happen to rise. But,
In the shift register according to the second aspect, since the first voltage-dividing element is provided at each stage, the voltage between one end and the other end of the current path of the first transistor may be unnecessarily large. Can be prevented. Therefore, it is possible to prevent the first transistor from being broken and the shift register from being broken.

In the shift register according to the second aspect, a predetermined voltage is applied to a control terminal of the first voltage dividing element, and both ends of the current path are connected to the other ends of the current path of the first transistor. It may be connected to an end and the capacitor.

The shift register according to the second aspect is provided between one end of a current path of the fifth transistor and the capacitor, and divides the voltage of the capacitor to generate the fifth transistor. A second voltage-dividing element may be further provided across both ends of the current path of the transistor.

By providing the second voltage dividing element in each stage as described above, even if the parasitic capacitance of the third transistor is charged up and the voltage of the capacitance increases, the current path of the fifth transistor is increased. It is possible to prevent the voltage between one end and the other end from becoming unnecessarily large. Therefore, it is possible to prevent the fifth transistor from being broken and the shift register from being broken.

In order to achieve the above object, a shift register according to a third aspect of the present invention is a shift register including a plurality of stages, wherein each stage of the shift register has a predetermined level from one of adjacent stages. A first transistor that is turned on when an output signal of the current path is supplied to the control terminal and outputs a signal of a predetermined level supplied from the previous stage to one end of the current path to the other end of the current path; The transistor is turned on by the electric charge stored in the capacitor between the other end of the current path of the control terminal of the transistor and the control terminal, and emits a signal supplied to one end of the current path through the load from the other end of the current path. 2 and the first transistor, which is turned on by the electric charge accumulated in the capacitor between the other end of the current path of the control terminal of the first transistor and the control terminal, and is supplied to one end of the current path from outside.
Or a third transistor that outputs a second signal as an output signal of the stage from the other end of the current path, and a signal supplied to a control terminal via a load when the second transistor is off. A fourth transistor that turns on and outputs a signal of a constant voltage externally supplied to one end of the current path as an output signal of the stage from the other end of the current path, and an output signal of a predetermined level from the other adjacent stage. It is turned on by being supplied to the control terminal, and discharges the electric charge accumulated in the capacitance formed between the other end of the current path of the first transistor and the control terminals of the second and third transistors. A fifth transistor, which is provided between one end of a current path of the fifth transistor and the capacitor and divides a voltage of the capacitor so as to be applied to both ends of the current path of the fifth transistor. Characterized in that it comprises a second voltage dividing element that.

Here, the first stage and the last stage of the shift register do not have one of the adjacent stages. In this case, the signal of a predetermined level supplied from one end of the current path of the first transistor and the signal supplied to the control terminal of the fifth transistor are supplied from, for example, an external control device. A predetermined signal can be used instead.

In the shift register according to the third aspect, the level of the output signal from each stage is substantially equal to the level of an externally supplied signal when the third and fourth transistors are on. Things. Therefore, it is possible to sequentially shift the output signal without attenuating the level.

Further, when the third or fourth signal at a high level is supplied to one end of the current path while the third transistor is on, the parasitic capacitance is charged up and the voltage of the capacitance is increased. It can happen to rise. But,
In the shift register according to the third aspect, since the second voltage-dividing element is provided in each stage, the voltage between one end and the other end of the current path of the fifth transistor may be unnecessarily large. Can be prevented. Therefore, it is possible to prevent the fifth transistor from being broken and the shift register from being broken.

In the shift register according to the second and third aspects, a predetermined voltage is applied to a control terminal of the second voltage dividing element, and both ends of the current path are respectively connected to the current path of the fifth transistor. Are connected to one end of the capacitor and the capacitor.

In the shift register according to the second and third aspects, the third of the third and fourth signals is externally supplied to the odd-numbered stage, and the even-numbered stage is supplied to the even-numbered stage. , The third signal, and the fourth signal may be supplied from the outside. In this case, each of the third and fourth signals may alternately have a drive level for each time slot during a predetermined period among time slots in which the output signal of the shift register is shifted.

In the shift register according to the first to third aspects, it is preferable that each transistor constituting each of the plurality of stages is the same channel type field effect transistor.

In order to achieve the above object, a shift register according to a fourth aspect of the present invention is a shift register including a plurality of stages, wherein each stage of the shift register is internally provided by an external signal. A first transistor for storing charge in a provided capacitor; and forming the capacitor between the first transistor and a first transistor from one end of a current path when turned on by the charge stored in the capacitor. A second transistor that outputs the supplied voltage as an output signal from the other end of the current path, and a second transistor that is provided between the capacitor and the first transistor and divides a voltage due to electric charge accumulated in the capacitor. , A voltage dividing element to be applied to both ends of the current path of the first transistor.

In order to achieve the above object, a shift register according to a fifth aspect of the present invention is a shift register including a plurality of stages, wherein each stage of the shift register is internally provided by an external signal. A first transistor for storing charge in a provided capacitor; and forming the capacitor between the first transistor and a first transistor from one end of a current path when turned on by the charge stored in the capacitor. A second transistor that outputs the supplied voltage as an output signal from the other end of the current path, and a third transistor that has one end of the current path connected to the capacitor and releases charges accumulated in the capacitor by a signal from the outside. And a third transistor, which is provided between the capacitor and the third transistor, divides a voltage by the electric charge accumulated in the capacitor to generate a voltage of the third transistor. Characterized in that it comprises a dividing element which rests on the ends of the road.

To achieve the above object, an electronic device according to a sixth aspect of the present invention comprises a plurality of stages, a driver for sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, A driving element constituted by a plurality of pixels and driven by an output signal output from each stage of the driver, wherein each stage of the driver is provided with a first or second signal supplied to a control terminal from outside. A first transistor that is turned on by the first stage and outputs a signal of a predetermined level supplied from one of the adjacent stages to one end of the current path to the other end of the current path; and a control terminal and the other of the current path of the first transistor. A second transistor that is turned on by the electric charge stored in the capacitor between the first and second terminals and emits a signal supplied to one end of the current path through the load from the other end of the current path; Is turned on by the electric charge accumulated in the capacitance between the other end of the current path of the transistor and the third or fourth signal supplied from the outside to one end of the current path as an output signal and output from the other end of the current path. A third transistor to be turned on by a signal supplied to a control terminal via a load when the second transistor is off, and a signal supplied from the outside to one end of the current path as an output signal. A fourth transistor that outputs from the other end of the path, and a fourth transistor that is provided between the other end of the current path of the first transistor and the capacitor; A voltage dividing element that is applied to both ends of the current path.

To achieve the above object, an electronic device according to a seventh aspect of the present invention comprises a plurality of stages, a driver for sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, A driving element configured by a plurality of pixels and driven by an output signal output from each stage of the driver, wherein each stage of the driver receives an output signal of a predetermined level from one of adjacent stages to a control terminal. A first transistor that is turned on by being supplied and outputs a signal of a predetermined level supplied from a previous stage to one end of the current path to the other end of the current path; and a current path of a control terminal of the first transistor. A second transistor that is turned on by the charge accumulated in the capacitor between the other end of the current path and the control terminal, and emits a signal supplied to one end of the current path via the load from the other end of the current path; The first transistor is turned on by the charge accumulated in the capacitor between the other end of the current path of the control terminal of the first transistor and the control terminal, and the first or second signal supplied from the outside to one end of the current path is supplied to the first transistor A third transistor which outputs the output signal of the stage from the other end of the current path;
Is turned on by a signal supplied to the control terminal via the load when the transistor is turned off, and a constant voltage signal supplied from the outside to one end of the current path is used as an output signal of the corresponding stage, the other end of the current path. A fourth transistor output from
It is turned on when an output signal of a predetermined level is supplied to the control terminal from the other adjacent stage, and is turned on between the other end of the current path of the first transistor and the control terminals of the second and third transistors. A fifth transistor for discharging the charge accumulated in the formed capacitor, and a fifth transistor provided between the other end of the current path of the first transistor and the capacitor, dividing the voltage of the capacitor, A voltage dividing element that is applied to both ends of the current path of the first transistor.

In order to achieve the above object, an electronic device according to an eighth aspect of the present invention comprises a plurality of stages, a driver for sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, A driving element configured by a plurality of pixels and driven by an output signal output from each stage of the driver, wherein each stage of the driver receives an output signal of a predetermined level from one of adjacent stages to a control terminal. A first transistor that is turned on by being supplied and outputs a signal of a predetermined level supplied from a previous stage to one end of the current path to the other end of the current path; and a current path of a control terminal of the first transistor. A second transistor that is turned on by the charge accumulated in the capacitor between the other end of the current path and the control terminal, and emits a signal supplied to one end of the current path via the load from the other end of the current path; The first transistor is turned on by the charge accumulated in the capacitor between the other end of the current path of the control terminal of the first transistor and the control terminal, and the first or second signal supplied from the outside to one end of the current path is supplied to the first transistor. A third transistor which outputs the output signal of the stage from the other end of the current path;
Is turned on by a signal supplied to the control terminal via the load when the transistor is turned off, and a constant voltage signal supplied from the outside to one end of the current path is used as an output signal of the corresponding stage, the other end of the current path. A fourth transistor output from
It is turned on when an output signal of a predetermined level is supplied to the control terminal from the other adjacent stage, and is turned on between the other end of the current path of the first transistor and the control terminals of the second and third transistors. A fifth transistor for discharging the charge accumulated in the formed capacitor, and a fifth transistor provided between one end of a current path of the fifth transistor and the capacitor; And a voltage dividing element to be applied to both ends of the current path of the transistor of No. 5.

In the electronic device according to the sixth to eighth aspects, the driving element can be, for example, an image pickup element.

In this case, the image pickup device includes a semiconductor layer that generates carriers by excitation light, a drain electrode and a source electrode connected to both ends of the semiconductor layer, and the semiconductor layer via a first gate insulating film. A first gate electrode provided on one side of the layer and a second gate electrode provided on the other side of the semiconductor layer via a second gate insulating film may be provided for each pixel. The driver may include a first driver that outputs an output signal to the first gate electrode, and a second driver that outputs an output signal to the second gate electrode.

Here, from the configuration of each pixel of the image sensor, the first
A structure excluding the gate electrode or the second gate electrode can be applied to each transistor included in the driver. Therefore, a driver can be formed in the same process on the same substrate as the substrate on which the imaging element is formed.

In the electronic device according to the sixth to eighth aspects, the driving element can be a display element.

In this case, the display element includes a sixth transistor to which a control terminal is supplied with an output signal of any one of the stages of the driver and one end of a current path to which image data is supplied from outside. It can be provided for each.

At this time, as the sixth transistor included in the display element, a transistor having the same structure as each transistor forming the driver can be applied. For this reason,
A driver can be formed in the same process on the same substrate as the substrate on which the imaging element is formed.

[0039]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram showing a configuration of an image pickup apparatus according to this embodiment.
As shown in the figure, the imaging apparatus includes an imaging device 1 for capturing an image, and a top gate driver 2, a bottom gate driver 3, and a drain driver 4 for driving the imaging device 1 according to a control signal from a controller. I have.

The image sensor 1 is composed of a plurality of double gate transistors 10 arranged in a matrix. The top gate electrode of the double gate transistor 10 is on the top gate line TGL, the bottom gate electrode is on the bottom gate line BGL, and the drain electrode is the drain line D
L, the source electrode is a ground line GrL
Connected to each other. The details of the double gate transistor 10 constituting the imaging device 1 will be described later.

The top gate driver 2 is connected to the top gate line TGL of the image sensor 1, and outputs a signal of +25 (V) or -15 (V) to each top gate line TGL according to a control signal Tcnt from the controller. . The top gate driver 2 is configured by a shift register that sequentially and selectively outputs a signal of +25 (V) to each top gate line TGL according to a signal supplied from the controller. Details of the top gate driver 2 will be described later.

The bottom gate driver 3 is connected to the bottom gate line BGL of the image sensor 1 and outputs a signal of +10 (V) or 0 (V) to each bottom gate line BGL according to a control signal Bcnt from the controller. The bottom gate driver 3 includes a shift register that sequentially and selectively outputs a signal of +10 (V) to each bottom gate line BGL according to a signal supplied from the controller. Details of the bottom gate driver 3 will be described later.

The drain driver 4 is connected to the drain line DL of the image sensor 1, and outputs a constant voltage (+10 (V)) to all the drain lines DL in a predetermined period described later according to a control signal Dcnt from the controller. , And precharge the charge. Drain driver 4
Reads the potential of each drain line DL that changes depending on whether a channel is formed in the semiconductor layer of the double gate transistor 10 in a predetermined period after the precharge, and supplies the potential as image data DATA to the controller.

Next, the structure of the double gate transistor 10 constituting the image pickup device 1 shown in FIG. 1 and its driving principle will be described.

FIG. 2 is a sectional view showing a schematic structure of the double gate transistor 10. As shown, a bottom gate electrode 10 made of chrome or the like is formed on a substrate 10a.
b is formed. Bottom gate insulating film 1 made of silicon nitride so as to cover bottom gate electrode 10b.
0c is formed.

A semiconductor layer 10d made of amorphous silicon or polysilicon is formed on the bottom gate insulating film 10c at a position facing the bottom gate electrode 10b. Then, the semiconductor layer 10 is formed via a blocking layer and an n-type semiconductor layer (not shown) on the semiconductor layer 10d.
A drain electrode 10e and a source electrode 10f made of chromium are formed to extend from d to the bottom gate insulating film 10c. The semiconductor layer 10d and the drain electrode 1
A top gate insulating film 10g made of silicon nitride is formed so as to cover 0e and source electrode 10f.

Semiconductor layer 1 on top gate insulating film 10g
In the position opposite to 0d, ITO (Indium Tin Oxide)
Is formed. An insulating protective film 10i made of silicon nitride is formed so as to cover the top gate electrode 10h.
In this double-gate transistor 10, light is incident on the semiconductor layer 10d through an insulating protective film 10i, a top gate electrode 10h, and a top gate insulating film 10g, each formed of a transparent material.

FIGS. 3A to 3D are schematic views showing the driving principle of the double gate transistor 10. FIG.

As shown in FIG. 3A, the voltage applied to the top gate electrode (TG) is +25 (V), and the voltage applied to the bottom gate electrode (BG) is 0.
(V), a continuous n-channel is not formed in the semiconductor layer 10d, and the drain electrode (D) 10e has +10
(V) is supplied, the source electrode (S) 10f
No current flows between In this state, the holes accumulated in the upper part of the semiconductor layer 10d in the photo-sensing state described later are projected by being repelled by the voltage of the top gate electrode 10h having the same polarity. Hereinafter, this state is referred to as a reset state.

As shown in FIG. 3B, the semiconductor layer 10d
Is incident on the semiconductor layer 10d according to the amount of light.
A hole-electron pair is generated inside. At this time, the voltage applied to the top gate electrode (TG) 10h is -15 (V).
When the voltage applied to the bottom gate electrode (BG) 10b is 0 (V), the holes of the generated hole-electron pairs are transferred to the blocking layer (upper part in the figure) in the semiconductor layer 10d. Stored. Hereinafter, this state is referred to as a photosense state. The holes accumulated in the semiconductor layer 10d are:
No ejection is performed from the semiconductor layer 10d until the reset state is reached.

As shown in FIG. 3C, a sufficient amount of holes are not accumulated in the semiconductor layer 10d in the photo-sensing state, and the voltage applied to the top gate electrode (TG) 10h becomes -15 ( V), the bottom gate electrode (BG) 1
When the voltage applied to 0b is +10 (V), the depletion layer spreads in the semiconductor layer 10d, the n-channel is pinched off, and the semiconductor layer 10d has a high resistance. For this reason,
Even when a voltage of +10 (V) is supplied to the drain electrode (D) 10e, no current flows between the source electrode (S) 10f. Hereinafter, this state is referred to as a first read state.

As shown in FIG. 3D, a sufficient amount of holes is accumulated in the semiconductor layer 10d in the photo-sensing state, and the voltage applied to the top gate electrode (TG) 10h is -15 (V). ), The bottom gate electrode (BG) 10
If the voltage applied to b is +10 (V), the accumulated holes are attracted to and held by the top gate electrode 10h to which the negative voltage is applied, and the negative voltage of the top gate electrode 10h is changed to the semiconductor. The effect on the layer 10d is reduced. Therefore, the bottom gate electrode 1 of the semiconductor layer 10d
An n-channel is formed on the 0b side, and the semiconductor layer 10d has low resistance. Therefore, the drain electrode (D) has +10
When the voltage of (V) is supplied, the source electrode (S) 10f
A current flows between. Hereinafter, this state is referred to as a second read state.

Next, the top gate driver 2 shown in FIG.
The details of the bottom gate driver 3 will be described.
FIG. 4 is a block diagram showing the entire configuration of the shift register applied as the top gate driver 2 and the bottom gate driver 3. Assuming that the number of rows (the number of top gate lines TGL) of the double-gate transistors 10 arranged in the image sensor 1 is n, this shift register has n stages when applied as any of the drivers 2 and 3. RS1 (1) to RS1 (n).

Each stage RS1 (k) (k: an integer from 1 to n)
Are input signal terminal IN, output signal terminal OUT, control signal terminal Φ, constant voltage input terminal SS, reference voltage input terminal DD,
And a clock signal input terminal clk. The output signal terminal OUT is connected to the output signal out of each stage RS1 (k).
(K) output terminal. Output signal out (k)
Are the respective top gate lines TGL of the image sensor 1
(When applied as top gate driver 2) or each bottom gate line BGL (bottom gate driver 3)
Is applied to the output.

The input signal terminal IN is output from the start signal Vst from the controller (in the case of the first stage RS1 (1)) or the previous stage RS (k-1) (k: an integer of 2 to n). This is a terminal to which the output signal out (k-1) (for the second and subsequent stages) is input.

The constant voltage input terminal SS is a terminal to which a constant voltage Vss is supplied from the controller. The level of the constant voltage Vss supplied to the constant voltage input terminal SS is -15
(V) (when applied as top gate driver 2),
Alternatively, it is 0 (V) (when applied as the bottom gate driver 3). The reference voltage input terminal DD is a terminal to which a predetermined reference voltage Vdd is supplied. Reference voltage input terminal D
The level of the reference voltage supplied to D is +25 (V).

The clock signal input terminal clk is a terminal to which a clock signal CK1 (for an odd-numbered stage) or a clock signal CK2 (for an even-numbered stage) from the controller is supplied. Clock signals CK1, C
K2 alternately becomes the drive level for each time slot during a predetermined period of the time slots in which the output signal of the shift register is shifted. When applied as the top gate driver 2, the clock signals CK1 and C
K2 has a high level (ON voltage level in an n-channel transistor) of +25 (V) and a low level (OFF voltage level in an n-channel transistor) of -15.
(V). On the other hand, when applied as the bottom gate driver 3, the high level (ON voltage level in the n-channel transistor) is +10 (V) and the low level (OFF voltage level in the n-channel transistor) is 0 (V).

A control signal terminal φ is a control signal φ1 from the controller (in the case of an odd-numbered stage) or a control signal φ.
2 (in the case of an even-numbered stage). As described later, the high level of the control signals φ1 and φ2 is a predetermined value at which the n-channel TFT to which the control signal is supplied is turned on, and the low level is a predetermined value at which the TFT is turned off.

FIG. 5 is a diagram showing a circuit configuration of each stage RS1 (1) to RS1 (n) of the shift register having the above configuration. As shown, each stage RS1 (1) to RS1 (n)
Consists of five TFTs (Thin Film Transistor)
or) 21 to 25, and one TFT 31 as an additional configuration. TFTs 21 to 25 and 31 each have n
The bottom gate electrode 10b or the top gate electrode 10h of the double gate transistor 10 shown in FIG.
The structure is excluded.

The gate electrode (control terminal) of the TFT 21 is connected to the control signal terminal Φ, the drain electrode (one end of the current path) is connected to the input signal terminal IN, and the source electrode (the other end of the current path) is connected to the TFT.
22 and 24 are connected to gate electrodes (control terminals). The gate electrode (control terminal) and the drain electrode (one end of the current path) of the TFT 23 are connected to the reference voltage input terminal DD. Drain electrode of TFT 22 (one end of current path)
Is connected to the source electrode (the other end of the current path) of the TFT 23, and the source electrode (the other end of the current path) is connected to the constant voltage input terminal SS. The drain electrode (one end of the current path) of the TFT 24 is connected to the clock signal input terminal clk, and the source electrode (the other end of the current path) is connected to the drain electrode (one end of the current path) of the TFT 25 and the output signal terminal OUT. The gate electrode (control terminal) of the TFT 25 is connected to the source electrode (the other end of the current path) of the TFT 23, and the source electrode (the other end of the current path) is connected to the constant voltage input terminal SS.

The source electrode of the TFT 21 and the TFT 2
The capacitance A for accumulating charges is formed by the wiring between the gate electrodes 2 and 24 and the parasitic capacitance of the TFTs 21, 22 and 24 related thereto.

The control signal φ1 or φ2 from the controller is supplied to the gate electrode of the TFT 21. TFT
The output signal out (k-1) from the previous stage RS1 (k-1) is supplied to the drain electrode 21. TFT21
Is turned on when a high-level (on-level) signal φ1 or φ2 is supplied, and a current flows between the drain electrode and the source electrode by the output signal out (k−1).
Thus, the capacitor A is charged with electric charge via the TFT 31.

A reference voltage Vdd is supplied to the gate electrode and the drain electrode of the TFT 23. This allows
The TFT 23 is always on. TFT23
Has a function as a load for dividing the reference voltage Vdd.

The TFT 22 is turned off when the capacitor A is not charged, and supplies the reference voltage Vdd supplied via the TFT 23 to the gate electrode of the TFT 25. Further, the TFT 22 is turned on when the capacitor A is charged, and causes a through current to flow between the drain electrode and the source electrode. Where TF
Since T22 and T23 have a so-called EE-type configuration, the TFT 23 does not have a complete off-resistance, so
Although the electric charge accumulated between the source electrode of the FT 23 and the gate electrode of the TFT 25 may not be completely discharged, the voltage becomes sufficiently lower than the threshold voltage of the TFT 25.

The TFT 24 is turned on when the capacitor A is charged (ie, when the TFT 25 is off), and the inputted clock signals CK1 and CK2 are inputted.
As a result, the parasitic capacitance composed of the gate electrode and the source electrode and the gate insulating film therebetween is charged up.
By charging up the parasitic capacitance due to the gate electrode and the drain electrode of the TFT 24 and the gate insulating film therebetween, the potential of the capacitance A rises as described later, and when it reaches the gate saturation voltage, the source-drain The current saturates. As a result, the output signal out
(K) has substantially the same potential as the clock signals CK1 and CK2. The TFT 24 is turned off when the capacitor A is not charged (that is, when the TFT 25 is turned on), and cuts off the output of the clock signals CK1 and CK2 supplied to the drain electrode.

A constant voltage V is applied to the drain electrode of the TFT 25.
ss is supplied. The TFT 25 is turned off when the capacitor A is not charged (ie, when the TFT 25 is on), and the level of the signal output from the source electrode of the TFT 24 is changed to the output signal out of the stage.
(K). The TFT 25 also has a capacitance A
Is charged (ie, TFT2
5 is in the off state), and the level of the constant voltage Vss supplied to the drain electrode is output from the source electrode as the output signal out (k) of the stage.

The TFT 31 is always supplied with the reference voltage Vdd to the gate electrode (control terminal) and is always on. The drain electrode (one end of the current path) is connected to the source electrode of the TFT 21 and the source electrode (current T at one end of the road)
It is connected to the gate electrodes of the FTs 22 and 24. TFT
31 divides the voltage of the capacitance A, which has risen due to the parasitic capacitance of the TFT 24, by the on-resistance thereof, and
1 has a function as a load for suppressing the voltage between the drain electrode and the source electrode. The role of the TFT 31 of the additional configuration will be described later in more detail.

Hereinafter, the operation of the imaging apparatus according to this embodiment will be described. First, the operation of the top gate driver 2 and the bottom gate driver 3 will be described. Note that the top gate driver 2 and the bottom gate driver 3 differ only in the level and timing of input / output signals, respectively. Therefore, in the following description, the operation of the bottom gate driver 3 will be described in the following. It will be stopped only at the part different from 2.

FIG. 6 is a timing chart showing the operation of the shift register of this embodiment when applied as top gate driver 2. In the figure, a period of 1t is one selection period. Here, odd-numbered stages other than the first-order stage RS1 (k) (k: 3, 5,..., N-
1), but the first stage also outputs the output signal out.
If (k-1) is a start signal Vst from the controller, it is the same as the other odd-numbered stages. The even-numbered stage performs the same operation as the odd-numbered stage if the control signal φ1 is the control signal φ2 and the clock signal CK1 is the clock signal CK2. However, as described above, the level of the constant voltage Vss supplied from the normal controller to the constant voltage input terminal SS of each stage of the top gate driver 2 is −15.
(V), but the operation is substantially the same even when the level of the constant voltage Vss is 0 (V).

When the clock signal CK2 goes to the high level (25 (V)) during the timing t0 to t1, the previous stage R
From S1 (k-1) to the input terminal IN of the stage RS1 (k)
Of the output signal out (k-1) supplied to the
(V) (indicated by a dashed line in the figure). During this period, when the control signal φ1 input from the control signal terminal Φ changes to a high level for a certain period, the TFT for only this certain period
21 turns on and the output signal ou supplied to the input terminal IN
25 (V) of t (k−1) is output from the source electrode of the TFT 21.

As a result, the source electrode of the TFT 21 and T
The potential of the wiring C between the FT31 and the drain electrode (in the figure,
(Indicated by the dotted line) rises, and the TF that is always on
When this is output from the potential of T31, the capacitance A
(Indicated by a solid line in the figure) rises. When the potential of the capacitor A rises and exceeds the threshold voltage of the TFTs 22 and 24, the TFTs 22 and 24 of the stage RS1 (k) are turned on and the TFT 2
5 turns off.

Next, between timings t1 and t2, the clock signal CK1 input from the clock signal input terminal clk changes to 25 (V). Then, TFT
The parasitic capacitance consisting of the 24 gate electrodes and source electrodes and the gate insulating film between them is charged up.
When the potential of the parasitic capacitance reaches the gate saturation voltage, the current flowing between the drain electrode and the source electrode of the TFT 24 is saturated. Thereby, the corresponding stage RS1 (k)
Output signal out (k) output from the output terminal OUT
Is 25 which is almost the same potential as the level of the clock signal CK1.
(V) (shown by a broken line in the figure).

Further, during this timing t1 to t2,
When the above-described parasitic capacitance of the TFT 24 is charged up, the potential of the capacitance A also reaches approximately 45 (V). At this time, the level of the constant voltage Vss supplied to the constant voltage input terminal SS of each stage of the top gate driver 2 is -1.
In the case of 5 (V), the output signal o supplied to the input terminal IN
Since ut (k-1) also changes to -15 (V), the actual voltage between the input terminal IN and the capacitor A is substantially 60 (V). When the level of the constant voltage Vss is 0
In the case of (V), the difference is 45 (V). However, such a voltage is applied to the TFT 31 acting as a load.
And the TFT 21 is divided, and the potential of the wiring C is 25
(V). That is, the voltage between the drain electrode and the source electrode of the TFT 21 is suppressed by the TFT 31.

Next, at timing t2, the level of the clock signal CK1 changes to -15 (V). As a result, the level of the output signal out (k) is also substantially -15.
(V). Further, the charges charged to the parasitic capacitance of the TFT 24 are released, and the potential of the capacitance A decreases. The potential of the wiring C also decreases to about the same level as the potential of the capacitor A. Further, when the control signal φ1 is at the high level for a certain period until the timing t3, the TFT 21 is turned on again, and the electric charge accumulated in the capacitor A is transferred to the TFTs 31 and 21 and the previous stage R
It is emitted via the TFT 25 (on state) of S1 (k-1). Accordingly, when the potential of the capacitor A and the wiring C is -15 (V) when the level of the constant voltage Vss is -15 (V).
When the level of the constant voltage Vss is 0 (V),
(V).

The control signal φ1 supplied to the gate electrode of the TFT 21 of the previous stage RS1 (k) is maintained even during the period when the output signal out (k−1) of the previous stage RS1 (k−1) does not become high level. High level, and TFT2
The level of the clock signal CK1 supplied to the drain electrode of No. 4 may be high. At this time, TFT2
Since a charge is charged to the parasitic capacitance of the gate electrode and the source electrode of the TFT 24 and the gate insulating film between them, or the parasitic capacitance of the gate electrode and the drain electrode of the TFT 24 and the gate insulating film between them, the capacitance A
Potential slightly fluctuates as shown in the figure.

By repeating such an operation sequentially for both the odd-numbered stages and the even-numbered stages, the output signal out of each stage RS1 (k) (k: 1 to n) of the top gate driver 2 is obtained.
(K) changes to 25 (V) for 1 t for one selection period, and shifts sequentially.

The operation of the bottom gate driver 3 is as follows.
The operation is almost the same as that of the top gate driver 2, but since the high level of the signals CK1 and CK2 supplied from the controller is 10 (V), each stage RS1 (k) (k:
The high level of the output signal out (k) is almost 1
0 (V), and the level of the capacitance A at this time is 18 (V).
It is about. The period during which the clock signals CK1 and CK2 are at the high level is a predetermined period shorter than one selection period 1t.

Next, the overall operation for driving the image pickup device 1 to capture an image will be described with reference to the schematic diagrams shown in FIGS. In the following description, the 1T period has the same length as one horizontal period. In addition, for simplicity, only the first three rows of the double gate transistors 10 arranged in the image sensor 1 will be considered.

First, 1T from timing T1 to T2
7A, the top gate driver 2 selects the top gate line TGL in the first row, outputs +25 (V), and outputs the second and third rows (all other rows). ) Is output to the top gate line TGL. On the other hand, the bottom gate driver 3 outputs 0 (V) to all the bottom gate lines BGL. During this period, the double-gate transistors 10 in the first row are in a reset state, and the double-gate transistors 10 in the second and third rows are in a state in which the reading state in the previous vertical period has been completed (a state that does not affect photo sensing). .

Next, 1T from timing T2 to T3
7B, the top gate driver 2 selects the top gate line TGL in the second row, outputs +25 (V), and outputs -15 (V) to the other top gate lines TGL. V). On the other hand, the bottom gate driver 3 outputs 0 (V) to all the bottom gate lines BGL. During this period, the double-gate transistor 10 in the first row enters the photo-sensing state,
The double-gate transistor 10 in the second row is in a reset state, and the double-gate transistor 10 in the third row is in a state in which the reading state in the previous vertical period has been completed (a state that does not affect the photo sensing).

Next, 1T from timing T3 to T4
7C, the top gate driver 2 selects the top gate line TGL in the third row, outputs +25 (V), and outputs -15 (V) to the other top gate lines TGL. V). On the other hand, the bottom gate driver 3 outputs 0 (V) to all the bottom gate lines BGL. During this period, the double-gate transistors in the first and second rows enter the photo-sensing state,
The double-gate transistor 10 in the third row is reset.

Next, during a period of 0.5T from timing T4 to T4.5, as shown in FIG. 7D, the top gate driver 2 applies -15 (V) to all top gate lines TGL. Output. On the other hand, the bottom gate driver 3 sets 0 to all the bottom gate lines BGL.
(V) is output. Further, the drain driver 4 outputs +10 (V) to all the drain lines DL. During this period, the double gate transistors 10 in all rows are in the photo sensing state.

Next, during the period of 0.5T from timing T4.5 to T5, as shown in FIG. 7E, the top gate driver 2 applies -15 (V) to all the top gate lines TGL. Output. On the other hand, the bottom gate driver 3 selects the bottom gate line BGL in the first row and outputs +10 (V), and outputs 0 (V) to the other bottom gate lines BGL. During this period, the double-gate transistors 10 in the first row are in the first or second read state, and the double-gate transistors 10 in the second and third rows remain in the photo-sensing state.

Here, the timing T at which the double-gate transistor 10 in the first row is in the photo-sensing state
If the semiconductor layer is irradiated with sufficient light during the period from 2 to T4.5, the semiconductor layer enters the second read state, and an n-channel is formed in the semiconductor layer. Is discharged. On the other hand, if sufficient light is not irradiated to the semiconductor layer during the period from timing T2 to T4.5, the semiconductor device enters the first reading state and the n-channel in the semiconductor layer is pinched off. The upper charge is not discharged. The drain driver 4 starts timing T4.5 to T
During the period up to 5, the potential on each drain line DL is read out and supplied to the controller as image data DATA detected by the double gate transistor 10 in the first row.

Next, during a period of 0.5T from timing T5 to T5.5, as shown in FIG. 7F, the top gate driver 2 applies -15 (V) to all the top gate lines TGL. Output. On the other hand, the bottom gate driver 3 sets 0 to all the bottom gate lines BGL.
(V) is output. Further, the drain driver 4 outputs +10 (V) to all the drain lines DL. During this period, the double-gate transistor 1 in the first row
0 indicates that the reading has been completed, and the double gate transistors 10 in the second and third rows are in the photo sensing state.

Next, during a period of 0.5T from timing T5.5 to timing T6, as shown in FIG. 7 (g), the top gate driver 2 applies -15 (V) to all top gate lines TGL. Output. On the other hand, the bottom gate driver 3 selects the second bottom gate line BGL and outputs +10 (V), and outputs 0 (V) to the other bottom gate lines BGL. During this period, the double-gate transistors 10 in the first row have completed reading, and the double-gate transistors 10 in the second row have been read out.
Are in the first or second read state, and the double-gate transistor 10 in the third row is in the photo sense state.

Here, the timing T at which the double-gate transistor 10 in the second row is in the photo-sensing state
If the semiconductor layer is irradiated with sufficient light during the period from 3 to T5.5, the semiconductor layer enters the second read state, and an n-channel is formed in the semiconductor layer. Is discharged. On the other hand, if sufficient light is not irradiated to the semiconductor layer during the period from timing T3 to T5.5, the semiconductor device enters the first read state, and the n-channel in the semiconductor layer is pinched off. The upper charge is not discharged. The drain driver 4 starts timing T5.5 to T
During the period up to 6, the potential on each drain line DL is read and supplied to the controller as image data DATA detected by the double gate transistor 10 in the second row.

Next, during a period of 0.5T from timing T6 to T6.5, as shown in FIG. 7H, the top gate driver 2 applies -15 (V) to all top gate lines TGL. Output. On the other hand, the bottom gate driver 3 sets 0 to all the bottom gate lines BGL.
(V) is output. Further, the drain driver 4 outputs +10 (V) to all the drain lines DL. In this period, the double-gate transistors 10 in the first and second rows are in a state where reading has been completed, and the double-gate transistors 10 in the third row are in a photo-sensing state.

Next, during a period of 0.5T from timing T6.5 to T7, as shown in FIG. 7 (i), the top gate driver 2 applies -15 (V) to all top gate lines TGL. Output. On the other hand, the bottom gate driver 3 selects the third bottom gate line BGL and outputs +10 (V), and outputs 0 (V) to the other bottom gate lines BGL. During this period, 1,
The double-gate transistor 10 in the second row is in a state where reading has been completed, and the double-gate transistor 10 in the third row is in the first or second reading state.

Here, the timing T at which the double-gate transistor 10 in the third row is in the photo-sensing state
If sufficient light is irradiated to the semiconductor layer in the period from 4 to T6.5, the semiconductor layer enters the second read state, and an n-channel is formed in the semiconductor layer. Is discharged. On the other hand, if sufficient light is not irradiated to the semiconductor layer during the period from timing T4 to timing T6.5, the semiconductor device enters the first read state, and the n-channel in the semiconductor layer is pinched off. The upper charge is not discharged. The drain driver 4 starts from timing T6.5 to T
The potential on each drain line DL is read in a period up to 7, and is supplied to the controller as image data DATA detected by the double gate transistor 10 in the third row.

The controller performs predetermined processing on the image data DATA supplied from the drain driver 4 for each row, thereby generating image data of the object to be imaged.

Hereinafter, the role played by the TFT 31 having the additional configuration will be described in detail. Here, the role will be described with reference to a comparative example. FIG. 8 is a circuit diagram showing a configuration of one stage of a shift register applied as the top gate driver 2 and the bottom gate driver 3 in this comparative example. This is because the circuit shown in FIG.
, Except that the source electrode 10f of the TFT 21 is directly connected to the capacitor A. The overall configuration of the shift register is the same as that shown in FIG.

Next, the operation of the shift register of the comparative example will be described as an example in which the operation is applied to the top gate driver 2. FIG. 9 is a timing chart showing the operation of the shift register of this comparative example when applied as the top gate driver 2. Here, the period of 1t is one selection period, and the odd-numbered stages RS1 (k) (k: 3, 5,..., N−1) other than the first are exemplified.

The shift register of this comparative example has a timing t at which the level of the output signal out (k) becomes high.
The operation between 1 and t2 is significantly different from that in the shift register of the above embodiment.

Between the timings t1 and t2, the TFT 24
Is charged up, and the potential of the capacitor A also reaches approximately 45 (V).
At this time, the output signal out supplied to the input terminal IN is output.
(K-1) also changes to -15 (V), and the voltage between the input terminal IN and the capacitor A becomes approximately 60 (V).

The voltage of 60 (V) is applied to the TF of the additional configuration.
Since there is no T31, the TFT 21 is not divided.
Between the drain electrode and the source electrode, and the TFT 21 is more easily damaged than in the case of the above embodiment.
Further, the characteristic variation of the TFT 21 due to long-time use is larger than that in the above-described embodiment. For this reason, the shift register of this comparative example is more likely to fail than the shift register of the above embodiment.

Further, the absence of the TFT 31 of the additional configuration allows the above-described parasitic capacitance of the TFT 24 or TF
The fluctuation of the potential of the capacitor A due to the parasitic capacitance due to the gate electrode and the source electrode of T21 and the gate insulating film between them is not buffered. For this reason, the amount of charge accumulated in the capacitor A due to long-term use becomes larger than that in the above-described embodiment, and the time until the threshold voltage of the TFTs 22 and 24 exceeds the above-described threshold voltage is obtained. It is shorter than that of the embodiment. In addition, the potential of the gate electrodes of the TFTs 22 and 24 fluctuates greatly, and the TFTs 2
The characteristics of 2 and 24 are more likely to fluctuate than those of the above embodiment.

As described above, in the imaging apparatus according to this embodiment, each stage RS1 (k) (k: an integer of 1 to n) of the shift register applied as the top gate driver 2 and the bottom gate driver 3 From the signal CK1,
The high level of CK2 can be output almost as it is as the level of the output signal. For this reason, each stage RS1
Even without providing a buffer or the like in (k), the output signal can be shifted sequentially without attenuating the level.

Each stage of the shift register RS1 (k)
Has a TFT 31 having an additional configuration in addition to the TFTs 21 to 25 having a basic configuration. For this reason, when the TFT 24 is on, the clock signals CK1 and CK2 supplied to the drain electrode of the TFT 24 become high level, and even if the parasitic capacitance is charged up and the potential of the capacitance A rises, the TFT 31 remains active. Therefore, the voltage between the drain electrode and the source electrode of the TFT 21 does not increase so much. For this reason, the potential of the capacitor A increases and the TFT 21
Can be prevented from being destroyed and the shift register from malfunctioning.

The shift registers applied as the top gate driver 2 and the bottom gate driver 3 are as follows.
The configuration can be made using only the TFTs 21 to 25 and 31 without using other elements. Here, TFTs 21 and 2
Reference numerals 5 and 31 each have a structure in which the bottom gate electrode 10b or the top gate electrode 10h of the double gate transistor 10 constituting the image sensor 1 is removed. For this reason, when forming the imaging element 1 on the substrate 10a, the same substrate 1
On TFT 0a, TFTs 21 to 25 and 31 are formed in the same process,
That is, the top gate driver 2 and the bottom gate driver 3 can be formed.

Further, as can be seen by comparing FIG. 6 and FIG. 9, in this embodiment, the top gate driver 2
And the shift register applied as the bottom gate driver 3 is different from the shift register of the comparative example in that each stage RS
During a period in which the high-level output signal out (k) is not output from 1 (k), the variation in the potential of the capacitor A is small. In other words, the shift register applied in this embodiment has a smaller amount of charge that is unintentionally accumulated in the capacitor A than the shift register of the comparative example even when used for a long time. For this reason, it is possible to operate stably for a long period of time.

[Second Embodiment] The configuration of an imaging apparatus according to this embodiment is substantially the same as that according to the first embodiment. However, in this embodiment, the configuration of the top gate driver 2 and the bottom gate driver 3 is different from that of the first embodiment, and the signals included in the control signals Tcnt and Bcnt supplied from the controller are different from those of the first embodiment. This is different from that of the first embodiment.

FIG. 10 is a block diagram showing the overall configuration of a shift register applied as top gate driver 2 and bottom gate driver 3 in this embodiment. This shift register is applied to any of the drivers 2 and 3, where n is the number of rows (the number of top gate lines TGL) of the double gate transistors 10 arranged in the image sensor 1, and n shift registers are provided. Step RS2
(1) to RS2 (n).

Each stage RS2 (k) (k: an integer from 1 to n)
Has an input signal terminal IN, an output signal terminal OUT, a constant voltage input terminal SS, a reference voltage input terminal DD, a clock signal input terminal clk, and a reset signal input terminal RST. The functions of the input signal terminal IN, the output signal terminal OUT, the constant voltage input terminal SS, the reference voltage input terminal DD, and the clock signal input terminal clk, and the content of the supplied signal are the same as those of the first embodiment. is there.

The reset signal input terminal RST is connected to the output signal out (k + 1) from the subsequent stage RS2 (k + 1) (k: an integer from 1 to n-1) (in the case of the (n-1) th stage) or the controller. Is a terminal to which the reset signal Vrst (in the case of the first stage RS2 (1)) is input.

FIG. 11 is a diagram showing a circuit configuration of each stage RS2 (1) to RS2 (n) of the shift register having the above configuration. As shown, each stage RS2 (1) to RS2 (n)
Has six TFTs 22 to 27 as a basic configuration and one TFT 32 as an additional configuration. TFT22
25 are similar to those of the first embodiment. The TFTs 26, 27, and 32 are also TFTs 22 to 2
As in the case of No. 5, it is composed of an n-channel MOS type field effect transistor.

The gate electrode and the drain electrode of the TFT 26 are connected to the input signal terminal IN, and the source electrodes are connected to the TFTs 22 and 24.
Is connected to the gate electrode of The gate electrode (control terminal) of the TFT 27 is connected to the reference voltage input terminal DD, and the drain electrode (one end of the current path) is connected to a capacitor A formed as described later.
The source electrode (the other end of the current path) is connected to the constant voltage input terminal SS. The source electrode of the TFT 26 and T
The wiring between the gate electrodes of the FTs 22 and 24 and the drain electrode of the TFT 27 includes a TFT related to the wiring itself.
The parasitic capacitances 22, 24, 26, and 27 form a capacitance A for storing charges.

The output signal out from the previous stage RS2 (k-1) is connected to the gate electrode and the drain electrode of the TFT 26.
(K-1) is supplied. The TFT 26 is turned on when a high-level (control-level) output signal out (k-1) is supplied, and a current flows between the drain electrode and the source electrode by the output signal out (k-1). Thus, the capacitor A is charged with electric charge via the TFT 32.

The gate electrode of the TFT 27 is connected to the rear stage R
An output signal out (k + 1) of S2 (k + 1) is supplied. The TFT 27 outputs an output signal o supplied to the gate electrode.
It turns on when ut (k + 1) becomes high level, and discharges the electric charge accumulated in the capacitor A.

The TFT 32 is always supplied with the reference voltage Vdd to the gate electrode (control terminal) and is always on. The drain electrode (one end of the current path) is connected to the source electrode of the TFT 26, and the source electrode (current The other end of the road)
Source electrode of TFT 27 (the other end of the current path) and TFT
22 and 24 are connected to gate electrodes (control terminals). The TFT 32 has a function as a load that divides the voltage of the capacitance A, which has increased due to the parasitic capacitance of the TFT 24, by its on-resistance, so as to reduce the voltage between the drain electrode and the source electrode of the TFT 21. The role of the additional TFT 32 will be described later in more detail.

Hereinafter, the operation of the imaging apparatus according to this embodiment will be described. The difference from the first embodiment is
Only the operation of the top gate driver 2 and the bottom gate driver 3 will be described. Also in this embodiment, the top gate driver 2 and the bottom gate driver 3 differ only in the level and timing of input / output signals supplied as control signals Tcnt and Bcnt, respectively. The description of the operation will be limited to only the portion different from the top gate driver 2.

FIG. 12 is a timing chart showing the operation of the shift register of this embodiment when applied as top gate driver 2. However, as described above, the constant voltage V supplied from the normal controller to the constant voltage input terminal SS of each stage of the top gate driver 2
The level of ss is −15 (V).
(V). In the figure, a period of 1t is one selection period. Here, even-numbered stages RS2 other than the last stage
(K) (k: 2, 4,..., N−2) is taken as an example. The final stage is the same as the other even-numbered stages, provided that the output signal out (k + 1) is the reset signal Vrst from the controller. In addition, the odd-numbered stages also receive the clock signal C
If K2 is the clock signal CK1 and the output signal out (k-1) in the first stage is the start signal Vst from the controller, the operation is the same as that of the even-numbered stage.

When the clock signal CK2 goes high (25 (V)) for a certain period between timings t0 and t1, the clock signal CK2 is supplied from the previous stage RS2 (k-1) to the input terminal IN of the current stage RS2 (k). The level of the output signal out (k-1) is 25 (V) (indicated by a dashed line in the figure).
During this time, the potential of the gate electrode of the TFT 26 is 25 (V).
Turns on, and the output signal out (k−1) 25
(V) is output from the source electrode of the TFT 26.

As a result, the source electrode of the TFT 26 and T
The potential of the wiring C between the FT32 and the drain electrode (in the figure,
(Indicated by the dotted line) rises, and the TF that is always on
When this is output from the potential of T32, the capacitance A
(Indicated by a solid line in the figure) rises. When the potential of the capacitor A rises and exceeds the threshold voltage of the TFTs 22 and 24, the TFTs 22 and 24 of the stage RS2 (k) are turned on and the TFT 2
5 turns off.

Next, the clock signal CK2 input from the clock signal input terminal clk changes to 25 (V) for a certain period between timings t1 and t2. Then, TFT
The parasitic capacitance consisting of the 24 gate electrodes and source electrodes and the gate insulating film between them is charged up.
When the potential of the parasitic capacitance reaches the gate saturation voltage, the current flowing between the drain electrode and the source electrode of the TFT 24 is saturated. Thereby, the corresponding stage RS2 (k)
Output signal out (k) output from the output terminal OUT
Is 25 which is almost the same potential as the level of the clock signal CK2.
(V) (shown by a broken line in the figure).

During this period, the potential of the capacitor A reaches almost 45 (V) by charging up the above-mentioned parasitic capacitance of the TFT 24. At this time, the constant voltage Vss
Is -15 (V), the output signal out (k-1) supplied to the input terminal IN also changes to -15 (V). The voltage is approximately 60 (V). When the level of the constant voltage Vss is 0 (V), the voltage between the input terminal IN and the capacitor A is 45 (V). However, such a voltage is divided between the TFT 32 and the TFT 26 acting as a load, and the potential of the wiring C is suppressed to about 25 (V). That is, the TFT 32 suppresses an increase in voltage between the drain electrode and the source electrode of the TFT 26.

Next, in the end period between the timings t1 and t2, the level of the clock signal CK2 becomes-
15 (V). As a result, the output signal out
The level of (k) is also approximately -15 (V). Also, TF
The charges charged to the parasitic capacitance of T24 are released, and the potential of the capacitance A decreases. The potential of the wiring C also decreases to about the same level as the potential of the capacitor A.

Further, at timing t3, the output signal out (k + 1) (high level) of the succeeding stage RS2 (k + 1) is input to the reset signal input terminal RST.
As a result, the TFT 27 is turned on, and the electric charge accumulated in the capacitor A is released through the TFT 27. As a result, the potential of the capacitor A and the potential of the wiring C are reduced to the level of the constant voltage Vss of -1.
When the voltage is 5 (V), the voltage drops to -15 (V), and when the level of the constant voltage Vss is 0 (V), the voltage drops to almost 0 (V).

By repeating such an operation sequentially for both the odd-numbered stages and the even-numbered stages, the output signal out of each stage RS2 (k) (k: 1 to n) of the top gate driver 2 is obtained.
(K) changes to 25 (V) for 1 t for one selection period, and shifts sequentially.

The operation of the bottom gate driver 3 is as follows.
The operation is almost the same as that of the top gate driver 2, but since the high level of the signals CK1 and CK2 supplied from the controller is 10 (V), each stage RS1 (k) (k:
The high level of the output signal out (k) is almost 1
0 (V), and the level of the capacitance A at this time is 18 (V).
It is about. The period during which the clock signals CK1 and CK2 are at a high level is a predetermined period shorter than the case where the clock signals CK1 and CK2 are applied as the top gate driver 2.

Hereinafter, the role of the TFT 32 of the additional configuration will be described in detail. Here, the role will be described with reference to a comparative example. FIG. 13 is a circuit diagram showing a configuration of one stage of a shift register applied as the top gate driver 2 and the bottom gate driver 3 in this comparative example. This is because the TFT shown in FIG.
32 except that the source electrode 10f of the TFT 27 is directly connected to the capacitor A. The overall configuration of the shift register is the same as that shown in FIG.

Next, the operation of the shift register of the comparative example will be described as an example in which the operation is applied to the top gate driver 2. FIG. 14 is a timing chart showing the operation of the shift register of this comparative example when applied as the top gate driver 2. Again, 1t
The minute period is one selection period, and an even-numbered stage RS2 (k) (k: 2, 4,..., N) other than the first period is taken as an example.

During the period from timing t1 to t2, the TFT 24
Is charged up, and the potential of the capacitor A also reaches approximately 45 (V).
At this time, if the level of the constant voltage Vss is −15 (V), the output signal out (k−1) supplied to the input terminal IN
Also changes to −15 (V), and the voltage between the input terminal IN and the capacitor A becomes approximately 60 (V). When the level of the constant voltage Vss is 0 (V), the voltage between the input terminal IN and the capacitor A is 45 (V).

The voltage of 60 (V) or 45 (V) is applied between the drain electrode and the source electrode of the TFT 26 without being divided, since the additional TFT 32 is not provided. TFT 26
Is easily damaged. In addition, TFT2
6 also becomes larger than in the above embodiment. For this reason, the shift register of this comparative example is more likely to fail than the shift register of the above embodiment.

As described above, in the image pickup apparatus according to this embodiment, the shift registers applied as the top gate driver 2 and the bottom gate driver 3 also include the shift registers RS2 (k) (k: 1 to n). The output signal can be sequentially shifted without attenuating the level of the output signal.

Each stage of the shift register RS2 (k)
Has a TFT 32 having an additional configuration in addition to the TFTs 22 to 27 having a basic configuration. For this reason, when the TFT 24 is on, the clock signals CK1 and CK2 supplied to the drain electrode of the TFT 24 become high level, and even if the parasitic capacitance is charged up and the potential of the capacitance A rises, the TFT 32 is still connected. Therefore, the voltage between the drain electrode and the source electrode of the TFT 26 does not increase so much. For this reason, the rise in the potential of the capacitor A causes the TFT 26
Can be prevented from being destroyed and the shift register from malfunctioning.

Further, the shift register applied as the top gate driver 2 and the bottom gate driver 3 in this embodiment can also be constituted by using only the TFTs 22 to 27 and 32 without using other elements. 1 is formed on the substrate 10a.
A top gate driver 2 and a bottom gate driver 3 can be formed thereon. Further, similarly to the first embodiment, according to the experimental results, the shift register applied in this embodiment can operate stably even when used for a long time.

[Third Embodiment] The configuration of an image pickup apparatus according to this embodiment is substantially the same as that of the first and second embodiments. Further, the entire configuration of the shift register applied as the top gate driver 2 and the bottom gate driver 3 is the same as that of the second embodiment. However, in this embodiment, the configuration of each stage of the shift register applied as the top gate driver 2 and the bottom gate driver 3 is different from that of the second embodiment.

FIG. 15 is a circuit diagram showing a configuration of one stage of a shift register applied as top gate driver 2 and bottom gate driver 3 in this embodiment. As shown, each stage R of this shift register
S2 (k) (k: an integer from 1 to n) has a TFT 33 as an additional configuration in addition to the configuration shown in FIG.

The reference voltage Vdd is always supplied to the gate electrode (control terminal) of the TFT 33, and the TFT 33 is always on. The drain electrode (one end of the current path) is connected to the source electrode of the TFT 27, and the source electrode (current T at one end of the road)
It is connected to the gate electrodes of the FTs 22 and 24. TFT
33 divides the voltage of the capacitor A, which has risen due to the parasitic capacitance of the TFT 24, by the ON resistance thereof, and
7 has a function as a load for suppressing the voltage between the drain electrode and the source electrode.

Hereinafter, the operation of the image pickup apparatus according to this embodiment will be described. The difference from the configuration of the second embodiment shown in FIG. 11 is that the TFT 32 is not provided as an additional configuration.
Since there is a TFT 33, except that the electric charge stored in the capacitor A is discharged via the TFT 33 and the TFT 27, it is only how the potential of the capacitor A is divided. Will be described.

For a fixed period between timings t1 and t2, T
By charging up the gate electrode and the drain electrode of the FT 24 and the parasitic capacitance therebetween, the potential of the capacitance A also reaches approximately 45 (V). At this time, if the level of the constant voltage Vss is -15 (V), the input terminal I
The output signal out (k-1) supplied to N is also -15.
(V), the voltage between the constant voltage input terminal SS and the capacitor A is approximately 60 (V). When the level of the constant voltage Vss is 0 (V), the voltage between the input terminal IN and the capacitor A is 45 (V). However, such a voltage is not applied to the TFT 33 acting as a load.
And the TFT 27 is divided, and the potential of the wiring C is 25
(V). That is, the TFT 33 suppresses an increase in voltage between the drain electrode and the source electrode of the TFT 23.

Next, in the end period between the timings t1 and t2, the level of the clock signal CK2 becomes-
15 (V). As a result, the output signal out
The level of (k) is also approximately -15 (V). Also, TF
The charges charged to the parasitic capacitance of T24 are released, and the potential of the capacitance A decreases. The potential of the wiring C also decreases to about the same level as the potential of the capacitor A. Then, at timing t3, the reset signal input terminal RST is connected to the subsequent stage RS2.
(K + 1) output signal out (k + 1) (high level)
Is entered. As a result, the TFT 27 is turned on, and the electric charge accumulated in the capacitor A is released through the TFT 33 and the TFT 27. Thereby, the potential of the capacitor A and the wiring C becomes -15 when the level of the constant voltage Vss is -15 (V).
(V), and to about 0 (V) when the level of the constant voltage Vss is 0 (V).

As described above, in the imaging apparatus according to the present embodiment, the shift registers applied as the top gate driver 2 and the bottom gate driver 3 also include the shift registers RS2 (k) (k: 1 to n). The output signal can be sequentially shifted without attenuating the level of the output signal.

Each stage of the shift register RS2 (k)
Has an additional configuration TFT 33 in addition to the basic configuration TFTs 22 to 27. For this reason, when the TFT 24 is on, the clock signals CK1 and CK2 supplied to the drain electrode of the TFT 24 become high level, and even if the parasitic capacitance is charged up and the potential of the capacitance A rises, the TFT 33 is still active. Therefore, the voltage between the drain electrode and the source electrode of the TFT 27 does not increase so much. For this reason, the rise in the potential of the capacitor A causes the TFT 27
Can be prevented from being destroyed and the shift register from malfunctioning.

Further, the shift register applied as the top gate driver 2 and the bottom gate driver 3 in this embodiment can also be constituted by using only the TFTs 22 to 27 and 33 without using other elements. 1 is formed on the substrate 10a.
A top gate driver 2 and a bottom gate driver 3 can be formed thereon. Further, similarly to the first embodiment, according to the experimental results, the shift register applied in this embodiment can operate stably even when used for a long time.

[Modification of Embodiment] The present invention is not limited to the above-described first to third embodiments, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the second and third embodiments, unlike the other stages, the n-th stage RS2 (n) of the shift register supplies the reset signal Vrst from the controller to the reset terminal RST. . On the contrary,
The number of stages of the shift register is set to n + 1 which is one more than the number n of stages of the image sensor 1, and the output signal ou of the stage RS2 (n + 1) is provided.
t (n + 1) may be supplied as a reset signal for the stage RS2 (n). In this case, the output signal out (n + 1) of the stage RS2 (n + 1) is used only as a reset signal and is not output to the image sensor 1.

In the second and third embodiments, each stage of the shift register RS2 (k) (k: an integer of 1 to n)
Has one TFT 32 and one TFT 33 as additional components in addition to the TFTs 22 to 27 of the basic configuration. On the other hand, as shown in FIG. 17, each stage RS2 (k) of the shift register may have two TFTs 32 and 33 as an additional configuration. In this case, the combined effects of the above-described second and third embodiments can be obtained.

In the first to third embodiments, each stage of the shift register RS1 (k), RS2 (k) (k: 1
To n) are provided with TFTs 31 to 33 to which a reference voltage Vdd is constantly applied to the gate electrode.
Of the TFT 2 by dividing the voltage of
The potential difference between the gate electrode and the source electrode of 1, 26, and 27 was prevented from becoming an enormous value. However, if the purpose is to divide the voltage, the TFTs 21, 26, 27
It is also possible to apply another element (for example, a resistance element) that matches the characteristics of the above.

In addition, each of the stages RS1 (k), RS2 of the shift register shown in the first to third embodiments.
The configuration of (k) (k: an integer from 1 to n) can be changed as appropriate. For example, the TFT 23 as a basic configuration
May be replaced with a resistance element other than the TFT. Also,
Each stage of the shift register RS1 (k), RS2 (k)
(K: an integer from 1 to n) indicates the clock signal C
A signal in which the levels of K1 and CK2 are inverted, a drain electrode is connected to the source electrode of the TFT 24, and a source electrode is connected to the constant voltage supply terminal SS may be further provided.

Further, each stage of the shift register RS1
(K) and RS2 (k) (k: an integer from 1 to n) are T for pull-up and pull-down to prevent floating.
A configuration in which an FT, a resistance element, or the like is appropriately added may be employed.
Furthermore, a configuration in which a TFT is inserted between the clock signal input terminal clk and the gate electrode of the TFT 25 can be adopted.

In the above-described first to third embodiments, an image pickup device in which the image pickup device 1 in which the double gate transistors 10 are arranged in a matrix is driven by using the top gate driver 2 and the bottom gate driver 3 is taken as an example. explained. However, the present invention is not limited to this, and other types of image pickup devices or display devices in which pixels are arranged in a predetermined arrangement such as a matrix may be the same as the shift registers described in the first to third embodiments. The present invention can also be applied to an imaging device or a display device driven by a driver having the configuration described above.

For example, an application to a liquid crystal display device as shown in FIG. 18 will be described. As shown, the liquid crystal display device includes a liquid crystal display element 5 and a gate driver 6.
And a drain driver 7.

The liquid crystal display element 5 is constructed by enclosing a liquid crystal in a pair of substrates.
50 are formed in a matrix. The gate electrode of each TFT 50 is formed on a gate line GL, the drain electrode is formed on a drain line DL, and the source electrode is formed on a pixel electrode similarly formed in a matrix. A common electrode to which a constant voltage is applied is formed on the other substrate, and a pixel capacitor 51 is provided between the common electrode and each pixel electrode.
Is formed. The liquid crystal display element 5 displays an image by controlling the amount of transmitted light by changing the alignment state of the liquid crystal by the electric charge stored in the pixel capacitance 51.

The gate driver 6 is constituted by any one of the shift registers applied as the top gate driver 2 and the bottom gate driver 3 in the above-described first to third embodiments, or a modified example described above. You. The gate driver 6 sequentially selects the gate lines GL according to a control signal Gcnt from the controller and outputs a predetermined voltage. However, the constant voltage Vss supplied as the control signal Gcnt is 0 (V), and the output voltage follows the characteristics of the TFT 50, and the signals CK1 and C are supplied as the control signal Gcnt from the controller.
The K2 level follows this.

The drain driver 7 sequentially takes in the image data data from the controller according to the control signal Dcnt from the controller. When the image data data for one line is accumulated, the drain driver 7 outputs this to the drain line DL in accordance with the control signal Dcnt from the controller, and the TFT 50 (ON) connected to the gate line GL selected by the gate driver 6. Via the state (state).

In this liquid crystal display device, when displaying an image on the liquid crystal display element 5, first, the gate driver 6 starts outputting a high-level signal from the stage corresponding to the gate line GL of the row in which the image data is to be written. And output
The TFT 50 in the row is turned on. TFT 50 of the row
At the timing when is turned on, the drain driver 7 outputs a voltage corresponding to the accumulated image data data to the drain line DL, and writes the voltage into the pixel capacitor 51 via the turned-on TFT 50. By repeating the above operation, the image data data is written into the pixel capacitor 51, and the orientation state of the liquid crystal changes accordingly, and an image is displayed on the liquid crystal display element 5.

In this liquid crystal display device, the liquid crystal display element 5
Has a structure in which TFTs 50 are formed in a matrix on one substrate. The structure of the TFT 50 is the same as that of the TF constituting the shift register applied to the gate driver 6.
It is basically the same as T21-27, 31-33. Therefore, the gate driver 6 can be formed on one of the substrates constituting the liquid crystal display element 5 in a simultaneous process.

Further, the shift register having the configuration in the above-described first to third embodiments or the configuration modified from the above-described embodiment is used as a driver for driving an image pickup device or a display device. Other than that can be applied. For example, these shift registers
The present invention can also be applied to a case where serial data is converted into parallel data in a data processing device or the like.

[0152]

As described above, according to the shift register of the present invention, it is possible to sequentially shift the output signal without attenuating the level.

Further, by providing a voltage dividing element in each stage, it is possible to prevent a large voltage from being applied to both ends of the current path of a specific transistor and destroying that transistor.

Further, in the electronic device of the present invention, a driver including an element having substantially the same structure as a transistor constituting a driver is applied to a driving element such as an imaging element or a display element, so that the driver can be used as an imaging element. It can be formed on the same substrate by the same process.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an imaging device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a schematic structure of the double gate transistor of FIG.

FIGS. 3A to 3D are schematic diagrams illustrating a driving principle of the double gate transistor of FIG.

FIG. 4 is a block diagram showing an overall configuration of a shift register applied as a top gate driver and a bottom gate driver in the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of one stage of a shift register applied as a top gate driver and a bottom gate driver in the first embodiment of the present invention.

FIG. 6 is a timing chart illustrating an operation when the shift register according to the first embodiment of the present invention is applied as a top gate driver.

FIGS. 7A to 7I are schematic diagrams illustrating an operation of the imaging apparatus according to the first embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of one stage of a shift register applied as a top gate driver and a bottom gate driver in the first comparative example.

FIG. 9 is a timing chart illustrating an operation when the shift register in the first comparative example is applied as a top gate driver.

FIG. 10 is a block diagram showing an entire configuration of a shift register applied as a top gate driver and a bottom gate driver in a second embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of one stage of a shift register applied as a top gate driver and a bottom gate driver in the second embodiment of the present invention.

FIG. 12 is a timing chart illustrating an operation when the shift register according to the second embodiment of the present invention is applied as a top gate driver.

FIG. 13 is a circuit diagram showing a configuration of one stage of a shift register applied as a top gate driver and a bottom gate driver in a second comparative example.

FIG. 14 is a timing chart illustrating an operation when the shift register in the second comparative example is applied as a top gate driver.

FIG. 15 is a circuit diagram showing a configuration of one stage of a shift register applied as a top gate driver and a bottom gate driver in the second embodiment of the present invention.

FIG. 16 is a timing chart showing an operation when the shift register according to the third embodiment of the present invention is applied as a top gate driver.

FIG. 17 is a circuit diagram illustrating another configuration of one stage of a shift register applied as a top gate driver and a bottom gate driver.

FIG. 18 is a block diagram illustrating a configuration of a liquid crystal display device according to a modification of the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Image sensor, 2 ... Top gate driver, 3 ... Bottom gate driver, 4 ... Drain driver, 5 ... Liquid crystal display element, 6 ... Gate driver, 7 ... Drain Driver, 10: double gate transistor, 10a: substrate, 10b: bottom gate electrode, 10c: bottom gate insulating film, 10d: semiconductor layer, 10e: drain electrode, 10f ... · Source electrode, 10g ··· Top gate insulating film, 10h ··· Top gate electrode, 10i ··· Insulating protective film, 21 to 27 ··· TFT (basic configuration), 31 to 33 ···
TFT (additional configuration), 50 TFT, 51 pixel capacitance, TGL top gate line, BGL bottom gate line, DL drain line, GL gate line, GrL ... Ground lines

Claims (20)

[Claims] 1. A shift register comprising a plurality of stages, wherein each stage of the shift register is turned on by a first or second signal supplied to a control terminal from the outside, and receives a current from one of adjacent stages. A first transistor for outputting a signal of a predetermined level supplied to one end of the current path to the other end of the current path; and a charge stored in a capacitor between a control terminal and the other end of the current path of the first transistor. A second transistor, which is turned on by the second transistor and emits a signal supplied to one end of the current path via the load from the other end of the current path, between the control terminal and the other end of the current path of the first transistor A third transistor which is turned on by the electric charge accumulated in the capacitor, and outputs a third or fourth signal externally supplied to one end of the current path as an output signal from the other end of the current path, and the second transistor Is off A fourth transistor that is turned on by a signal supplied to a control terminal via a load when the signal is present, and outputs a signal externally supplied to one end of the current path as an output signal from the other end of the current path; The transistor is provided between the other end of the current path of the transistor and the capacitor, and divides the voltage of the capacitor to form the first capacitor.
And a voltage dividing element to be applied to both ends of the current path of the transistor. 2. The voltage dividing device according to claim 1, wherein a predetermined voltage is applied to a control terminal, and both ends of a current path are connected to the other end of the current path of the first transistor and the capacitor, respectively. The shift register according to claim 1, wherein: 3. An odd-numbered stage of the shift register includes:
A third signal of the third and fourth signals is externally supplied, and an even-numbered stage of the shift register is externally supplied with a fourth signal of the third and fourth signals. 3. The driving signal according to claim 1, wherein the third signal and the fourth signal alternately have a drive level for each time slot during a predetermined period of a time slot in which the output signal of the shift register is shifted. The shift register according to 1. 4. The apparatus according to claim 3, wherein said first and second signals are kept at an on level for a predetermined period while said third and fourth signals are at a drive level. Shift register. 5. A shift register comprising a plurality of stages, wherein each stage of the shift register is turned on when an output signal of a predetermined level is supplied from one of adjacent stages to a control terminal, and the previous stage is A first transistor that outputs a signal of a predetermined level supplied to one end of the current path from the other end of the current path, and a capacitance between the other end of the current path of the control terminal of the first transistor and the control terminal Is turned on by the charge stored in the
A second transistor that emits a signal supplied to one end of the current path via the load from the other end of the current path, and a capacitance between the other end of the current path of the control terminal of the first transistor and the control terminal Is turned on by the charge stored in the
A third transistor that outputs a first or second signal externally supplied to one end of the current path from the other end of the current path as an output signal of the stage, and when the second transistor is off. A fourth transistor which is turned on by a signal supplied to a control terminal via a load, and outputs a constant voltage signal externally supplied to one end of the current path from the other end of the current path as an output signal of the stage; It is turned on when an output signal of a predetermined level is supplied to the control terminal from the other adjacent stage, and is turned on between the other end of the current path of the first transistor and the control terminals of the second and third transistors. A fifth transistor for discharging the charge accumulated in the formed capacitor, and a fifth transistor provided between the other end of the current path of the first transistor and the capacitor, and dividing the voltage of the capacitor, First
Of the current path of both transistors
And a voltage dividing element. 6. A first voltage dividing element, wherein a predetermined voltage is applied to a control terminal, and both ends of a current path are respectively connected to the other end of the current path of the first transistor and the capacitor. The shift register according to claim 5, wherein 7. The fifth transistor is provided between one end of a current path of the transistor and the capacitor, and the voltage of the capacitor is divided so as to be applied to both ends of the current path of the fifth transistor. The shift register according to claim 5, further comprising a second voltage dividing element. 8. A shift register comprising a plurality of stages, wherein each stage of the shift register is turned on when an output signal of a predetermined level is supplied to a control terminal from one of adjacent stages, and A first transistor that outputs a signal of a predetermined level supplied to one end of the current path from the other end of the current path, and a capacitance between the other end of the current path of the control terminal of the first transistor and the control terminal Is turned on by the charge stored in the
A second transistor that emits a signal supplied to one end of the current path via the load from the other end of the current path, and a capacitance between the other end of the current path of the control terminal of the first transistor and the control terminal Is turned on by the charge stored in the
A third transistor that outputs a first or second signal externally supplied to one end of the current path from the other end of the current path as an output signal of the stage, and when the second transistor is off. A fourth transistor which is turned on by a signal supplied to a control terminal via a load, and outputs a constant voltage signal externally supplied to one end of the current path from the other end of the current path as an output signal of the stage; It is turned on when an output signal of a predetermined level is supplied to the control terminal from the other adjacent stage, and is turned on between the other end of the current path of the first transistor and the control terminals of the second and third transistors. A fifth transistor for discharging the charge accumulated in the formed capacitor; and a fifth transistor provided between one end of a current path of the fifth transistor and the capacitor, and dividing the voltage of the capacitor to form the fifth transistor. 5
To be applied to both ends of the current path of the transistor
And a voltage dividing element. 9. A predetermined voltage is applied to a control terminal of the second voltage dividing element, and both ends of a current path are respectively connected to one end of a current path of the fifth transistor and the capacitor. 9. The shift register according to claim 7, wherein: 10. An odd-numbered stage of the shift register is externally supplied with a third signal of the third and fourth signals, and an even-numbered stage of the shift register has a third, A fourth signal of the fourth signal is supplied from the outside, and a third signal and a fourth signal are respectively provided for each time slot for a predetermined period of the time slot for shifting the output signal of the shift register. 10. The shift register according to claim 5, wherein the shift level is alternately set. 11. The shift register according to claim 1, wherein each of the transistors constituting each of the plurality of stages is the same channel type field effect transistor. 12. A shift register comprising a plurality of stages, wherein each stage of the shift register includes a first transistor for accumulating electric charge in a capacitor provided therein in response to an external signal; A second transistor that outputs the voltage supplied from one end of the current path as an output signal from the other end of the current path when the transistor is turned on by the charge stored in the capacitor, And a voltage divider that is provided between the capacitor and the first transistor and that divides a voltage due to the electric charge accumulated in the capacitor to apply the voltage to both ends of a current path of the first transistor. And a shift register. 13. A shift register comprising a plurality of stages, wherein each stage of the shift register comprises: a first transistor for storing a charge in a capacitor provided therein in response to an external signal; A second transistor that outputs the voltage supplied from one end of the current path as an output signal from the other end of the current path when the transistor is turned on by the charge stored in the capacitor, A third transistor having one end of a current path connected to the capacitor, and releasing a charge stored in the capacitor by an external signal; and a third transistor provided between the capacitor and the third transistor. ,
A shift register, comprising: a voltage dividing element that divides a voltage of the electric charge accumulated in the capacitor so as to apply the voltage to both ends of a current path of the third transistor. 14. A driver comprising a plurality of stages and sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, and an output signal comprising a plurality of pixels and outputted from each stage of the driver. Each stage of the driver is turned on by a first or second signal externally supplied to a control terminal, and supplied to one end of a current path from one of the adjacent stages. A first transistor that outputs a signal of a predetermined level to the other end of the current path; and a charge stored in a capacitor between a control terminal and the other end of the current path of the first transistor. A second transistor that emits a signal supplied to one end of the current path from the other end of the current path, and a charge stored in a capacitor between a control terminal and the other end of the current path of the first transistor. And a third transistor that outputs a third or fourth signal externally supplied to one end of the current path as an output signal from the other end of the current path, and the second transistor is off. A fourth transistor which is turned on by a signal supplied to a control terminal via a load, and outputs a signal supplied from one end to one end of the current path as an output signal from the other end of the current path; Is provided between the other end of the current path and the capacitor, and divides the voltage of the capacitor to form the first capacitor.
And a voltage dividing element that is applied to both ends of the current path of the transistor. 15. A driver comprising a plurality of stages and sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, and an output signal comprising a plurality of pixels and outputted from each stage of the driver. Each stage of the driver is turned on when an output signal of a predetermined level is supplied to a control terminal from one of adjacent stages, and supplied to one end of a current path from a previous stage. A first transistor that outputs the signal of the predetermined level to the other end of the current path, and is turned on by the electric charge accumulated in the capacitor between the other end of the current path of the control terminal of the first transistor and the control terminal. And
A second transistor that emits a signal supplied to one end of the current path via the load from the other end of the current path, and a capacitance between the other end of the current path of the control terminal of the first transistor and the control terminal Is turned on by the charge stored in the
A third transistor that outputs a first or second signal externally supplied to one end of the current path from the other end of the current path as an output signal of the stage, and when the second transistor is off. A fourth transistor which is turned on by a signal supplied to a control terminal via a load, and outputs a constant voltage signal externally supplied to one end of the current path from the other end of the current path as an output signal of the stage; It is turned on when an output signal of a predetermined level is supplied to the control terminal from the other adjacent stage, and is turned on between the other end of the current path of the first transistor and the control terminals of the second and third transistors. A fifth transistor for discharging the charge accumulated in the formed capacitor, and a fifth transistor provided between the other end of the current path of the first transistor and the capacitor, and dividing the voltage of the capacitor, First
And a voltage dividing element that is applied to both ends of the current path of the transistor. 16. A driver comprising a plurality of stages and sequentially outputting a signal of a predetermined level from each stage by shifting an output signal, and an output signal comprising a plurality of pixels and outputted from each stage of the driver Each stage of the driver is turned on when an output signal of a predetermined level is supplied to a control terminal from one of adjacent stages, and supplied to one end of a current path from a previous stage. A first transistor that outputs the signal of the predetermined level to the other end of the current path, and is turned on by the electric charge accumulated in the capacitor between the other end of the current path of the control terminal of the first transistor and the control terminal. And
A second transistor that emits a signal supplied to one end of the current path via the load from the other end of the current path, and a capacitance between the other end of the current path of the control terminal of the first transistor and the control terminal Is turned on by the charge stored in the
A third transistor that outputs a first or second signal externally supplied to one end of the current path from the other end of the current path as an output signal of the stage, and when the second transistor is off. A fourth transistor which is turned on by a signal supplied to a control terminal via a load, and outputs a constant voltage signal externally supplied to one end of the current path from the other end of the current path as an output signal of the stage; It is turned on when an output signal of a predetermined level is supplied to the control terminal from the other adjacent stage, and is turned on between the other end of the current path of the first transistor and the control terminals of the second and third transistors. A fifth transistor for discharging the charge accumulated in the formed capacitor; and a fifth transistor provided between one end of a current path of the fifth transistor and the capacitor, and dividing the voltage of the capacitor to form the fifth transistor. 5
And a voltage dividing element that is applied to both ends of the current path of the transistor. 17. The electronic device according to claim 14, wherein the drive element is an image pickup element. 18. An imaging device comprising: a semiconductor layer that generates carriers by excitation light; a drain electrode and a source electrode connected to both ends of the semiconductor layer; and a first gate insulating film. The first provided on one side
A gate electrode, and a second gate electrode provided on the other side of the semiconductor layer via a second gate insulating film for each pixel, wherein the driver outputs an output signal to the first gate electrode. The electronic device according to claim 17, further comprising: one driver; and a second driver that outputs an output signal to a second gate electrode. 19. The electronic device according to claim 14, wherein the driving element is a display element. 20. A display device comprising: a sixth transistor to which a control terminal is supplied with an output signal of any one of the stages of the driver, and one end of a current path to which image data is supplied from outside, for each pixel. 20. The electronic device according to claim 19, comprising: