JP2003032096A - Electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shift an output signal outputted from each stage of a driver and improve balance of electric charges by the output signal. SOLUTION: When a high level output signal out (1) from a stage RS (1) is given to a TFT 21 of a stage RS (2), TFTs 23, 24 of the stage RS (2) are turned on. In this case, when a high level clock signal ϕ2 is given to the electronic device, the high level output signal out (2) is outputted to a stage RS (3). The high level output signal is sequentially outputted from each stage in this way. After a final stage RS (n) outputs a high level output signal out (n), when a set signal SET reaches an on-level, all the stages RS (1) to RS (2) output the high level output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device provided with a shift register that shifts an output signal from a front stage to a rear stage or from a rear stage to a front stage and sequentially outputs the output signal from each stage.

[0002]

2. Description of the Related Art As a driver for driving an image pickup device or a display device in which pixels are arranged in a matrix, by shifting a high-level output signal from the preceding stage to the succeeding stage one after another, A driver that outputs signals line-sequentially is widely used.

Some of the stages of such a driver have a structure as shown in FIG. The kth stage (each stage) is a field effect transistor (hereinafter referred to as FET) 101 to which the output signal out (k−1) from the previous stage is input to the gate electrode and the drain electrode, and the FET 101.
The gate electrode is connected to the source electrode of, the clock signal is input to the drain electrode, the source electrode serves as the output of the stage, and the power supply voltage Vdd (high level, for example, +25 [V]) is applied to the gate electrode and the drain electrode. And the gate electrode is connected to the source electrode of the FET 106 and the source electrode is connected to the reference voltage Vss.
FET 105 which is connected to (low level, for example, −15 [V]) and whose drain electrode is the output of the stage,
The gate electrode is connected to the source electrode of 101, and FET1
The drain electrode is connected to the source electrode of the FET 06 and the gate electrode of the FET 105, the drain electrode is connected to the source electrode of the FET 101 and the gate electrodes of the FETs 102 and 104, and the source electrode is connected to the reference voltage Vss. The output signal out (k + 1) is input to the gate electrode of the FET 103.

Then, a high level output signal out (k
When -1) is input, electric charges are accumulated in the wiring capacitance 107, and the FET 104 and the FET 102 are turned on. When the FET 104 is turned on, the electric charge of the wiring capacitance 108 is discharged, and the FET 105 is turned off. FET104 is turned on and FET10
Since 5 is in the off state, the output signal ou of the relevant stage is
t (k) becomes a clock signal. Here, when the clock signal becomes high level, the output signal out (k) becomes high level, and the high level output signal out (k) is output to the FET 101 in the subsequent stage. Then, when another clock signal becomes high level, the output signal out (k + 1) of the latter stage becomes high level similarly to the stage concerned, the FET 103 is turned on, and the charge of the wiring capacitance 107 is discharged.
This turns off the FETs 102 and 104,
The FET 105 is turned on. When the FET 105 is turned on, the output signal out (k) of the relevant stage is output.
Becomes the level (low level) of the reference voltage Vss, and the low level is maintained thereafter. As described above,
The driver shifts the high-level output signal to sequentially output the high-level output signal from each stage. Here, the low level voltage is VL and the high level voltage is V
Supposing that H is H, the period during which the low level voltage VL is being output on a predetermined line is TL, and the period during which the high level voltage VH is being output is TH, then the following equation (1) is satisfied: (Level voltage VL) | = (Period TH) × | (Level voltage VH) | ... (1) The voltage applied to the line has no deviation in electrical positive / negative.

[0005]

However, such a conventional driver selectively outputs a high level output signal only at a predetermined stage, but the output signal is at a low level at a non-selected stage. The period during which the low-level output signal is output tends to be longer with an increase in the value of, and as a result, the left side of Expression (1) becomes larger than the right side. Due to this positive / negative imbalance, charges of one polarity are accumulated in the parasitic capacitance with the line as one pole, and the S /
The N ratio may be low.

Therefore, an object of the present invention is to improve the balance of charges due to the output signals while the output signals output from the respective stages of the driver are shifted.

[0007]

In order to solve the above-mentioned problems, an electronic device according to a first aspect of the present invention has a plurality of stages (stage RS (1) as shown in FIGS. 1 to 6, for example. ~ Dan R
S (n)) is turned on when the first control signal or the second control signal input to the control terminal is turned on, and selectively turns on when the on level from the previous stage is turned on. Outputs an on-level output signal to another terminal when an output signal is input to one terminal, or outputs an off-level output when an off-level output signal is input to one terminal from the previous stage in the on state. A first transistor (TFT 21) that outputs a signal to another terminal, and a second transistor that outputs a first clock signal or a second clock signal as an output signal of the stage according to an on-level output signal from the first transistor (TFT 24) and a third transistor which is in an off state when the second transistor is in an on state and is in an on state when the second transistor is in an off state. An electronic device including a shift register having a transistor (TFT 25), wherein the second transistor of each stage is the first clock signal or the second clock signal as a first output signal of a predetermined polarity during a forward shift scanning period. Clock signals are sequentially output, the third transistor outputs a second output signal having a polarity opposite to the predetermined polarity in the forward shift scanning period, and a third output having the same polarity as the first output signal in a voltage relaxation period. It is characterized by outputting an output signal.

According to the first aspect of the present invention, the third transistor outputs the second output signal which becomes the off level during the forward shift scanning period, and the third transistor which is at the on level during the period when the second output signal is output. The deviation of the electrical polarity on the side to which the output signal is supplied, which occurs because it is longer than the one output signal, is mitigated by outputting the third output signal of the same polarity as the first output signal during the voltage relaxation period. This bias allows at least a portion of the charge retained by the second output signal to disappear without accumulating,
It is possible to suppress the risk of causing a malfunction. In particular, it is suitable for an electronic device that scans an image sensor, the characteristics of which are greatly affected by the bias of charges. According to the invention described in claim 3, by providing the fourth transistor, not only the forward shift but also the reverse shift is possible. For example, when the electronic device of the present invention is applied as a liquid crystal display device, an image is displayed from a predetermined direction. In order to visually recognize, when the liquid crystal panel displaying the image is physically rotated up and down, the shift register automatically switches so as to convert from the forward shift to the reverse shift, thereby processing the image signal. It is possible to display the top and bottom of the image as it is without any change.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Specific embodiments of an electronic device and a driver driving method according to the present invention will be described below with reference to the drawings. However, the scope of the invention is not limited to the illustrated examples.

As shown in FIG. 1, an image pickup device 1 to which the electronic device according to the present invention is applied has, as a basic configuration, an image pickup element 2 for picking up (acquiring) an image by optically sensing, A controller 3 for outputting a signal for controlling the entire image pickup apparatus 1 and a top gate driver 4, a bottom gate driver 5, and a drain driver 6 for driving the image pickup element 2 in accordance with a control signal group output by the controller 3 are provided. . The top gate driver 4, the bottom gate driver 5, and the drain gate driver 6 are connected to the controller 3 so that data can be input / output.

The image pickup device 2 comprises a plurality of double gate transistors 7 arranged in a matrix on a transparent substrate.
The basic configuration is 7, ... As shown in FIGS. 2 and 3, each double-gate transistor 7 includes a bottom gate electrode 8, a bottom gate insulating film 9, a semiconductor layer 10, block insulating films 11 a and 11 b, and impurity layers 12 a and 12.
b, 13, source electrodes 14a, 14b, a drain electrode 15, a top gate insulating film 16, a top gate electrode 17, and a protective insulating film 18.

The bottom gate electrode 8 is formed on the transparent substrate 19. The transparent substrate 19 is transparent to visible light and has an insulating property. A bottom gate insulating film 9 is provided on the bottom gate electrode 8 and the transparent substrate 19 so as to cover the bottom gate electrode 8 and the transparent substrate 19. A semiconductor layer 10 is provided on the bottom gate insulating film 9 so as to face the bottom gate electrode 8. The semiconductor layer 10 is made of amorphous silicon or the like, and when visible light enters the semiconductor layer 10, electrons-holes are generated in the semiconductor layer 10.

A block insulating film 11 is formed on the semiconductor layer 10.
a and 11b are arranged in parallel so as to be separated from each other. The impurity layer 12a is provided at one end of the semiconductor layer 10 in the channel length direction, and the impurity layer 12b is provided at the other end. Block insulating film 11a and block insulating film 11b
And the impurity layer 13 is provided on the center of the semiconductor layer 10.
It is separated from a and 12b. Then, the impurity layers 12a,
The semiconductor layer 10 is adapted to be covered with 12b, 13 and the block insulating films 11a, 11b. In plan view, a part of the impurity layer 12a overlaps a part of the block insulating film 11a, and a part of the impurity layer 12b overlaps a part of the block insulating film 11b. In addition, the impurity layer 12
a, 12b, and 13 are made of amorphous silicon doped with n-type impurity ions.

A source electrode 14a is provided on the impurity layer 12a, a source electrode 14b is provided on the impurity layer 12b, and a drain electrode 15 is provided on the impurity layer 13. In plan view, the source electrode 14a overlaps a part of the block insulating film 11a, the source electrode 14b overlaps a part of the block insulating film 11b, and the drain electrode 15 of the block insulating films 11a and 11b.
It overlaps the upper part. Also, the source electrodes 14a, 1
4b and the drain electrode 15 are separated from each other. The top gate insulating film 16 is formed so as to cover the bottom gate insulating film 9, the block insulating films 11a and 11b, the source electrodes 14a and 14b, and the drain electrode 15. A top gate electrode 17 is provided on the top gate insulating film 16 so as to face the semiconductor layer 10. A protective insulating film 18 is provided on the top gate insulating film 16 and the top gate electrode 17.

Each of the above double gate transistors 7 is
The following first and second double photo sensors are arranged in parallel on the transparent substrate 19. That is, the first double photo sensor is an upper MOS composed of the semiconductor layer 10, the source electrode 14 a, the drain electrode 15, the top gate insulating film 16 and the top gate electrode 17.
The semiconductor device includes a transistor and a lower MOS transistor including the semiconductor layer 10, the source electrode 14a, the drain electrode 15, the bottom gate insulating film 9, and the bottom gate electrode 8. The upper MOS transistor and the lower MOS transistor include the semiconductor layer 10. It is a common channel area.
On the other hand, the second double photo sensor is an upper MO composed of the semiconductor layer 10, the source electrode 14b, the drain electrode 15, the top gate insulating film 16 and the top gate electrode 17.
S transistor, semiconductor layer 10, source electrode 14b,
The lower MOS transistor includes the drain electrode 15, the bottom gate insulating film 9, and the bottom gate electrode 8, and the upper MOS transistor and the lower MOS transistor use the semiconductor layer 10 as a common channel region.

As shown in FIGS. 1 and 2, the top gate electrode 17 is connected to the top gate line (hereinafter referred to as TGL), and the bottom gate electrode 8 is connected to the bottom gate line (hereinafter referred to as BGL). The drain electrode 15 is connected to a drain line (hereinafter referred to as DL), and the source electrodes 14a and 14b are connected to a ground line (hereinafter referred to as GL) which is grounded.

The block insulating films 11a and 11b, the top gate insulating film 16 and the protective insulating film 18 are made of silicon nitride or the like and have a light transmitting property and an insulating property. Also,
The top gate electrode 17 and TGL are made of ITO (Indium-T
In-Oxide) and the like having a light-transmitting property and conductivity.
On the other hand, the source electrodes 14a and 14b, the drain electrode 15,
The bottom gate electrode 8 and BGL are selected from chromium, chromium alloy, aluminum, aluminum alloy, etc.,
It blocks the transmission of visible light and has conductivity.

Here, as shown in FIG. 1, the top gate driver 4 is connected to each TGL of the image pickup device 2. Then, the top gate driver 4 sequentially and selectively outputs a drive signal (output signal) to each TGL, and appropriately outputs a reset voltage (+25 [V]) to each TGL in accordance with the control signal group Tcnt output from the controller 3. ) Or carrier accumulation voltage (-15 [V]) is applied as a drive signal.

The bottom gate driver 5 is connected to each BGL of the image pickup device 2. Then, the bottom gate driver 5 sequentially and selectively outputs a drive signal (output signal) to each BGL, and appropriately outputs a channel forming voltage (+10) to each BGL according to the control signal group Bcnt output from the controller 3. [V]) or channel non-forming voltage (± 0
[V]) is applied as a drive signal.

The drain driver 6 is provided for each D of the image pickup device 2.
It is connected to L. Then, the drain driver 6
In the predetermined period, the reference voltage (+10) is applied to all DLs according to the control signal group Dcnt output from the controller 3.
[V]) is applied to precharge the charges. Then, the drain driver 6 is configured such that, in a predetermined period after precharge, the drain of each DL changing according to the amount of light incident on each double gate transistor 7 or the drain flowing between the source and drain of each double gate transistor 7. The current is detected and output to the controller 3 as a data signal (image data) DATA.

Next, details of the top gate driver 4 and the bottom gate driver 5 will be described. FIG. 4 is a block diagram showing the top gate driver 4 and the bottom gate driver 5. The number of rows (the number of TGLs) of the double gate transistors 7 arranged in the image pickup device 2 is n.
(However, n is an even number.) Then, the top gate driver 4 and the bottom gate driver 5 have n stages RS.
(1) to RS (n).

The stage RS (k) has a first input signal terminal IN.
1, second input signal terminal IN2, output signal terminal OUT, reference voltage application terminal SS, constant voltage application terminal DD, clock signal input terminal clk, first control signal terminal Φ1, second control signal terminal Φ2, and set signal input terminal Have ST.
Here, k is an integer of 1 to n, stage RS (1) is the first stage, stage RS (2) is the second stage, ..., Stage RS
(N) is the nth stage.

The output signal terminal OUT of the stage RS (k) is a terminal to which the output signal out (k) of the stage RS (k) is output. When the block diagram shown in FIG. 4 is the top gate driver 4, the output signal terminal OU of the stage RS (k)
T is connected to the corresponding TGL (kGL row TGL),
The output signal out (k) is output to the corresponding TGL. On the other hand, when the block diagram shown in FIG. 4 is the bottom gate driver 5, the output signal terminal OU of the stage RS (k)
T is connected to the corresponding BGL (k-th row BGL),
The output signal out (k) is output to the corresponding BGL.

The first input signal terminal IN1 of the first stage RS (1) is a terminal to which the first start signal Din output by the controller 3 is input. When the block diagram shown in FIG. 4 is the top gate driver 4, the high level of the start signal Din (ON voltage level in the n-channel transistor) is +25 [V], and the low level of the start signal Din (in the n-channel transistor). The off-voltage level) is −15 [V]. On the other hand, when the block diagram shown in FIG. 4 shows the bottom gate driver 5, the high level of the start signal Din is +10 [V] and the low level of the start signal Din is ± 0 [V]. The first input signal terminal IN1 of the stage RS (k) other than the first stage RS (1) is connected to the output signal terminal OUT of the previous stage RS (k-1), and Output signal out (k-1) of (k-1)
Is a terminal input as an input signal.

The second input signal terminal IN2 of the stage RS (k) other than the final stage RS (n) is connected to the output signal terminal OUT of the rear stage RS (k + 1), and the rear stage RS (k).
The output signal out (k + 1) of (+1) is a terminal to be input as an input signal. The second input signal terminal IN2 of the final stage RS (n) is a terminal to which the second start signal Rin from the controller 3 is input. When the block diagram shown in FIG. 4 is the top gate driver 4, the high level of the second start signal Rin is +25 [V] and the low level of the second start signal Rin is -15 [V]. On the other hand, when the block diagram shown in FIG. 4 shows the bottom gate driver 5, the high level of the second start signal Rin is +10 [V] and the low level of the second start signal Rin is ± 0 [V]. .

The reference voltage application terminal SS of the stage RS (k) is
This is a terminal to which the reference voltage Vss is applied from the controller 3. When the block diagram shown in FIG. 4 is the top gate driver 4, the level of the reference voltage Vss is −15.
[V]. On the other hand, when the block diagram shown in FIG. 4 shows the bottom gate driver 5, the level of the reference voltage Vss is ± 0 [V]. The constant voltage application terminal DD of the stage RS (k) is a terminal to which the constant voltage Vdd is applied from the controller 3. When the block diagram shown in FIG. 4 is the top gate driver 4, the level of the constant voltage Vdd is +25.
[V]. On the other hand, when the shift register shown in FIG. 4 is the bottom gate driver 5, the level of the constant voltage Vdd is +10 [V].

Odd (where k is odd) stage RS
The clock signal input terminal clk of (k) is a terminal to which the clock signal (first clock signal) CK1 output by the controller 3 is input. The clock signal input terminal clk of the even-numbered stage RS (k) (k is an even number) is a terminal to which the clock signal (second clock signal) CK2 output from the controller 3 is input.

When the shift register shown in FIG. 4 is the top gate driver 4, the high level of the clock signals CK1 and CK2 is +25 [V] and the low level is -15.
[V]. On the other hand, when the shift register shown in FIG. 4 is the bottom gate driver 5, the clock signal CK
The high level of 1 and CK2 is +10 [V] and the low level is ± 0 [V].

The first control signal terminal Φ1 of the odd-numbered stage RS (k) has a control signal φ output from the controller 3.
This is a terminal to which 1 is input. The second control signal terminal of the even-numbered stage RS (k) is a terminal to which the control signal φ2 output by the controller 3 is input.

The second control signal terminal Φ2 of the odd-numbered stage RS (k) has a control signal φ output from the controller 3.
3 is an input terminal. The second control signal terminal Φ2 of the even-numbered stage RS (k) is a terminal to which the control signal φ3 output by the controller 3 is input. When the shift register shown in FIG. 4 is the top gate driver 4,
High level of control signals φ1, φ2, φ3, φ4 is +25
[V], and the low level is -15 [V]. On the other hand, when the shift register shown in FIG. 4 is the bottom gate driver 5, the high level of the control signals φ1, φ2, φ3, φ4 is +10 [V] and the low level is ± 0 [V].
Is.

Set signal input terminal ST of the stage RS (k)
Is a set signal SET output by the controller 3.
Is a terminal to which is input. When the shift register shown in FIG. 4 is the top gate driver 4, the set signal SET
Has a high level of +25 [V] and a low level of -1.
It is 5 [V]. On the other hand, when the shift register shown in FIG. 4 is the bottom gate driver 5, the high level of the set signal SET is +10 [V] and the low level is ± 0.
[V].

Clock signals CK1 and CK2, start signal Din, second start signal Rin, constant voltage Vdd level signal, reference voltage Vss level signal, control signal φ
1, φ2, φ3, φ4 and the set signal SET are included in the control signal group Tcnt or the control signal group Bcnt. That is, the controller 3 shown in FIG. 1 has clock signals CK1 and CK2, a start signal Din, a second start signal Rin, a constant voltage Vdd level signal, and a reference voltage V.
The ss level signal, the control signals φ1, φ2, φ3, φ4 and the set signal SET are controlled.

More specifically, as shown in FIGS. 7 and 8, the controller 3 controls the clock signal CK1, during a predetermined period of time slots (cycle t shown in FIGS. 7 and 8) in which the output signal shifts. CK2 is alternately set to a high level for each time slot. Further, the controller 3 alternately sets the control signals φ1 and φ2 to the high level for each time slot during a predetermined period of the time slot in which the output signal shifts. The controller 3 alternately sets the control signals φ3 and φ4 to the high level for each time slot during a predetermined period of the time slot in which the output signal shifts.
Further, the controller 3 sets the control signal φ2 to the high level when the clock signal CK1 is set to the high level, and sets the control signal φ1 to the high level when the clock signal CK2 is set to the high level. There is.
Further, the controller 3 sets the control signal φ4 to the high level when the clock signal CK1 is set to the high level, and sets the control signal φ3 to the high level when the clock signal CK2 is set to the high level. There is.
Here, the controller 3 controls the control signals φ1, φ2, φ
Clock signal C during the period when 3 and φ4 are high level
It is designed to be shorter than the period when K1 and CK2 are at high level.

Further, the controller 3 has a clock signal C
The K1 and CK2 and the set signal SET are also maintained at a low level or a high level. Further, the controller 3 controls the control signals φ1, φ2, φ
3, φ4, start signal Din and second start signal R
It is designed to keep in at a low level.

Next, the structure of the stage RS (k) will be described. As shown in FIGS. 5 and 6, the stage RS (k) includes six thin film transistors (hereinafter, referred to as TFTs) 21 to 26. Each of the TFTs 21 to 26 is an n-channel MOS type field effect transistor, silicon nitride is used for the gate insulating film, and amorphous silicon is used for the semiconductor layer. Specifically, referring to the cross-sectional structure of the double gate transistor 7 shown in FIG. 3, in the TFTs 21 to 26, the top gate electrode 17 and the protective insulating film 18 are not laminated (the top gate insulating film 16 is the uppermost layer). (Disposed on the upper layer).

As shown in FIGS. 5 and 6, the gate electrode of the TFT 21 is connected to the first control signal terminal Φ1,
The drain electrode is connected to the first input signal terminal IN1. The source electrode of the TFT 21 is connected to the source electrode of the TFT 22, the gate electrode of the TFT 23, and the gate electrode of the TFT 24. TFT24 gate electrode, TFT
23 gate electrode, TFT 22 source electrode and TFT
In the wiring connected to the source electrode of 21, a node A is arranged at an arbitrary position, and a parasitic capacitance having the wiring of the node A as one pole is formed.

The drain electrode of the TFT 24 is connected to the clock signal input terminal clk, and the source electrode of the TFT 24 is connected to the output signal terminal OUT and the drain electrode of the TFT 25. The drain electrode of the TFT 23 is T
It is connected to the source electrode of FT26 and the gate electrode of TFT25, and the source electrode of TFT23 is connected to the reference voltage application terminal SS. Then, in the wiring connected to the drain electrode of the TFT 23, the gate electrode of the TFT 25, and the source electrode of the TFT 26, a parasitic capacitance is formed in which the node A is arranged at an arbitrary position and the wiring of the node B is one pole. .

The drain electrode of the TFT 25 is connected to the output signal terminal OUT, and the source electrode of the TFT 25 is connected to the set signal input terminal ST. The drain electrode and the gate electrode of the TFT 26 are connected to the constant voltage applying terminal DD. The gate electrode of the TFT 22 is connected to the second control signal terminal Φ2, and the drain electrode is connected to the second input signal terminal IN2.

The control signal φ1 or φ2 from the controller 3 is input to the gate electrode of the TFT 21. In addition, the drain electrode of the TFT 21 is
When the output signal out (k-1) from (k-1) is input as an input signal (k is 2 to n), or the start signal Din from the controller 3 is input as an input signal ( If k is 1). When the control signal φ1 or φ2 is at the high level, the TFT 21 is in the ON state, and the current flows between the drain electrode and the source electrode. When a high-level input signal is input to the drain electrode of the TFT 21 when the TFT 21 is in the ON state, a current flows from the drain electrode to the source electrode,
A high level output signal is output to the source electrode. At this time, if the TFT 22 is in the off state, the TFT 2
The high-level input signal output from the source electrode of No. 1 causes the potential of the node A to rise. On the other hand, when a low-level input signal is input to the drain electrode of the TFT 21 when the TFT 21 is in the on state, a current flows from the source electrode to the drain electrode. At this time, when the TFT 25 of the preceding stage RS (k-1) is in the ON state and the set signal SET is at the low level,
The potential of the node A is low level.

The control signal φ3 or φ4 from the controller 3 is input to the gate electrode of the TFT 22. Further, the drain electrode of the TFT 22 has a rear stage RS (k +
If the output signal out (k + 1) from 1) is input as an input signal (k is 1 to n-1), or the second start signal Rin from the controller 3 is input as an input signal (k). Is n). Control signal φ3
Alternatively, when φ4 is at the high level, the TFT 22 is in the ON state, and the current flows between the drain electrode and the source electrode. When a high-level input signal is input to the drain electrode of the TFT 22 when the TFT 22 is on, a current flows from the drain electrode to the source electrode, and a high-level output signal is output from the source electrode. At this time, if the TFT 21 is in the off state,
A high-level input signal output from the source electrode of the TFT 22 raises the potential of the wiring of the node A. On the other hand, when a low level input signal is input to the drain electrode of the TFT 22 while the TFT 22 is in the on state, a current flows from the source electrode to the drain electrode. At this time, the TFT2 of the latter stage RS (k + 1)
When 5 is in the ON state and the set signal SET is at the low level, the charges accumulated in the parasitic capacitance having the wiring of the node A as one pole are discharged.

A constant voltage Vdd is applied to the gate electrode and the drain electrode of the TFT 26. This gives T
The FT 26 has a diode junction, and when the source electrode is at a low level, a current flows through the drain electrode to the source electrode of the TFT 26, and the TFT 26 outputs a signal of a substantially constant voltage Vdd level to the source electrode. T
The FT 26 has a function as a load that divides the constant voltage Vdd.

The TFT 23 is turned off when the potential of the node A is at the low level, and the potential of the node B is set to the high level by the signal of the constant voltage Vdd level output from the source electrode of the TFT 26. On the other hand, T
The FT 23 is turned on when the potential of the node A is at a high level, and a current flows from the drain electrode to the source electrode of the TFT 23, so that the potential of the node B of the TFT 23 becomes low level. The TFT 25 is turned off when the potential of the node B is low level, and is turned on when the potential of the node B is high level. T
The FT 24 is turned on when the potential of the node A is high level, and is turned off when the potential of the node A is low level. Therefore, when the TFT 25 is in the off state, the TFT 24 is in the on state,
The TFT 24 is turned off when 25 is turned on. As described above, the TFT 23 turns on the TFT 24 based on the potential of the node A (that is,
Either turn off the TFT25) or use the TFT2
5 is turned on (that is, the TFT 24 is turned off).

The set signal SET is input to the source electrode of the TFT 25. The TFT 25 in the ON state outputs the set signal SET from the drain electrode to the output signal terminal OUT.
The set signal SET is output as the output signal out (k) of the stage RS (k). That is, the TFT 25 in the ON state outputs the high-level set signal SET as the output signal of the stage RS (k) when the high-level set signal SET is input to the source electrode. On the other hand, the TFT 25 in the on state
When the low level set signal SET is input to the source electrode, the low level set signal SET is input to the stage R
It is adapted to be output as an output signal of S (k).
The TFT 25 in the off state cuts off the output of the set signal SET input to the source electrode and outputs the level of the signal output from the source electrode of the TFT 24 as the output signal out (k) of the stage RS (k). It is like this.

The drain electrode of the TFT 24 has an odd number of stages,
The clock signal CK1 or CK2 is input according to the even-numbered stages. The TFT 24 in the off state cuts off the output of the clock signal CK1 or CK2 input to the drain electrode and sets the level of the signal output from the drain electrode of the TFT 25 to the output signal out (k) of the stage RS (k).
Is output as.

When the low level clock signal CK1 or CK2 is input to the drain electrode of the TFT 24 while the TFT 24 is in the ON state, the TFT 24 outputs the low level clock signal CK1 or CK2 to the source electrode. ing. Here, when the TFT 24 is in the ON state, the TFT 25 is in the OFF state, so that the low-level clock signal CK1 or CK2 is the stage RS
It is output as the output signal out (k) of (k).

On the other hand, when the TFT 24 is on, the high level clock signal CK1 or CK2 is TF.
When input to the drain electrode of T24, an electric current flows between the source and the drain, whereby charges are accumulated in the parasitic capacitance formed of the gate electrode, the source electrode, and the gate insulating film between them. At this time, the TFT 21 and the TFT 2
Since 2 is in the off state, the source-drain current of the TFT 24 is saturated when the potential of the node A further rises to the gate saturation voltage of the TFT 24 due to the bootstrap effect. As a result, the TFT 24 in the ON state has the high-level clock signal CK1 or C
A signal having substantially the same potential as K2 is output to the source electrode. Here, when the TFT 24 is in the ON state, the TFT 25 is in the OFF state, so that the high-level clock signal CK1 or CK2 is applied to the stage RS (k).
Is output as the output signal out (k).

That is, the TFT 23, the TFT 24 and the TFT
Based on the potential of the node A, the transistor group composed of 25 (hereinafter, referred to as output signal switching means) receives the clock signal CK1 or the clock signal CK2 as the output signal out (k) of the stage RS (k). Output
Alternatively, whether to output the set signal as the output signal out (k) of the stage RS (k) is selectively switched. In other words, the output signal switching means outputs the first clock signal C when the potential of the node A is high level.
K1 or the second clock signal CK2 is output as the output signal out (k) of the stage RS (k), and the set signal SET is used as the output signal of the stage RS (k) when the potential of the node A is low level. It is what is output.

The operation of the image pickup apparatus 1 of this embodiment will be described below. First, the operation of the top gate driver 4 and the bottom gate driver 5 will be described with reference to FIG. Note that the top gate driver 4 and the bottom gate driver 5 are different only in the level and timing of the input / output signals. Therefore, in the following description, the operation of the bottom gate driver 5 will be explained Only the part different from 4 will be stopped.

FIG. 7 shows a case where the high-level output signals output from the top gate driver 4 and the bottom gate driver 5 are sequentially shifted from the stage RS (1) to the stage RS (n) (hereinafter, in this case Is referred to as a forward shift.) Is a timing chart. In this case, controller 3
Always outputs the low level second start signal Rin and the control signals φ3 and φ4. At timing T0, the control signals φ1 and φ2 and the set signal SET are low level.

Then, at timing T0, the controller 3
Sets the start signal Din to high level, the clock signal CK1 to low level, and the clock signal CK2 to high level. After that, when the controller 3 sets the control signal φ1 to the high level, the TFT 21 of the stage RS (1) is turned on, and the high-level start signal Din is output from the drain electrode to the source electrode. As a result, the potential of the node A rises, and the TFTs 23, 24 of the stage RS (1)
Turns on. When the TFT 23 is turned on, the constant voltage Vdd level signal output from the source electrode of the TFT 26 of the stage RS (1) is discharged through the TFT 23, and the TFT 25 of the stage RS (1) is turned off. Since the TFT 24 is in the ON state and the TFT 25 is in the OFF state, the clock signal CK1 is output as the output signal out (1) of the stage RS (1), and the output signal out
The level of (1) is a low level.

After that, the controller 3 controls the control signal φ1.
After setting to low level, the start signal Din and the clock signal CK2 are set to low level. When the control signal φ1 becomes low level, the TFT 21 is turned off, and the TFT 21 in the off state cuts off the start signal Din input to the drain electrode of the TFT 21. At this time, the wiring potential of the node A is held, and the TFT
23 and 24 maintain the ON state, the TFT 25 maintains the OFF state, and the output signal out (1) is maintained at the low level.

Next, at timing T1, the controller 3 sets the clock signal CK1 to high level. Then, the parasitic capacitance formed by the gate electrode and the source electrode of the TFT 24 and the gate insulating film between them is charged up, and the potential of the node A further rises due to the bootstrap effect. Then, when the potential of the node A reaches the gate saturation voltage, the current flowing between the drain electrode and the source electrode of the TFT 24 is saturated. As a result, the output signal out (1) output from the output signal terminal OUT of the stage RS (1) becomes +25 [V] having substantially the same potential as the level of the clock signal CK1, and becomes a high level.

After that, the controller 3 controls the control signal φ2.
To high level. Then, the TFT2 of the stage RS (2)
1 is turned on and the high level output signal out
(1) is output from the drain electrode of the TFT 21 of the stage RS (2) to the source electrode, and the potential of the node A of the stage RS (2) rises. Thereby, the TFTs 23, 2 of the stage RS (2) are
4 is turned on, and the TFT 25 of the stage RS (2) is turned off. Therefore, the clock signal CK2 is
Output as the output signal of (2) and output signal out
The level of (2) is a low level.

Next, the controller 3 sets the control signal φ2 to the low level, and the TFT 21 of the stage RS (2) is turned off. As a result, the TFT 21 of the stage RS (2) blocks the output signal out (1) input to the drain electrode. At this time, the potential of the node A of the stage RS (2) is held.

After that, the controller 3 sets the clock signal CK1 to the low level. Then, the output signal out (1) output from the output signal terminal OUT of the stage RS (1)
Becomes low level. Next, at timing T2, the controller 3 sets the clock signal CK2 to high level. Then, due to the bootstrap effect, the step R
The potential of the node A of S (2) further rises, and the stage RS (2)
When the potential of the node A of the node reaches the gate saturation voltage of the TFT 24, the current flowing between the drain electrode and the source electrode of the TFT 24 of the stage RS (2) is saturated. As a result, the output signal out (2) output from the output signal terminal OUT of the stage RS (2) becomes +25 [V], which is substantially the same potential as the level of the clock signal CK2, and becomes high level.

Next, when the controller 3 sets the control signal φ1 to the high level, the TFT 21 of the stage RS (1) and the TFT 21 of the stage RS (3) are turned on. At this time, in the stage RS (1), since the start signal Din is at a low level and the TFT 21 of the stage RS (1) is in the ON state, a current flows from the source electrode to the drain electrode of the TFT 21 of the stage RS (1). Flows, the potential of the node A of the stage RS (1) falls and becomes a low level. By this, the step RS
The TFTs 23 and 24 of (1) are turned off, and the stage RS
The potential of the node B of (1) becomes high level, and the stage RS
The TFT 25 of (1) is turned on. By turning off the TFT 24 of the stage RS (1), the stage RS
The output of the clock signal CK1 input to the drain electrode of the TFT 24 of (1) is cut off. In addition, when the TFT 25 of the stage RS (1) is turned on, the stage RS
The output signal out (1) of (1) is the TF of the stage RS (1).
The set signal SET is input to T25, and the level of the output signal out (1) is a low level that is substantially the same level as the level of the set signal SET. After that, the set signal SET is output as the output signal out (1) of the stage RS (1), and the output signal out (1) is maintained at the low level.

On the other hand, in the stage RS (3), the stage RS
When the TFT 21 of (3) is turned on, the high-level output signal out (2) input to the drain electrode of the TFT 21 of the stage RS (3) is output to the source electrode of the TFT 21 and the stage RS (3). ), The potential of the node A rises. Therefore, the TFTs 23 and 24 of the stage RS (3) are turned on, and the TFT 25 of the stage RS (3) is turned off. As a result, the clock signal CK1 changes to the stage RS (3).
Output signal out (3) of
The level of t (3) is low level.

Next, when the controller 3 sets the control signal φ1 to the low level, the TFT 21 of the stage RS (1) and the TFT 21 of the stage RS (3) are turned off. At this time, the potential of the node A of the stage RS (1) is low level and the potential of the node A of the stage RS (3) is high level.

Next, the controller 3 sets the clock signal CK2 to low level. Then, the output signal out (2) of the stage RS (2) becomes low level. Next, at timing T3, the controller 3 sets the clock signal CK1 to high level. Then, the potential of the node A of the stage RS (3) further rises due to the bootstrap effect, and when the potential of the node A of the stage RS (3) reaches the gate saturation voltage, the drain electrode of the TFT 24 of the stage RS (3) becomes The current flowing between the source electrode and the source electrode is saturated. As a result, the output signal out (3) of the stage RS (3) becomes +25 [V], which is substantially the same potential as the level of the clock signal CK1, and becomes high level.

Next, when the controller 3 sets the control signal φ2 to the high level, the TFT 21 of the stage RS (2) and the TFT 21 of the stage RS (4) are turned on. At this time, in the stage RS (2), the set signal SET is at the low level, and the TFT 21 of the stage RS (2) and the TFT 25 of the stage RS (1) are in the ON state.
A current flows from the source electrode of T21 to the drain electrode,
The potential of the node A of the stage RS (2) falls and becomes low level. As a result, the TFTs 23 and 24 of the stage RS (2) are turned off and the TFT 25 of the stage RS (2) is turned on. When the TFT 24 of the stage RS (2) is turned off, the output of the clock signal CK2 input to the drain electrode of the TFT 24 of the stage RS (2) is cut off. Further, since the TFT 25 of the stage RS (2) is turned on, the output signal out (2) of the stage RS (2) is changed to the stage R.
It is the set signal SET input to the TFT 25 of S (2), and the level of the output signal out (2) is the set signal SE.
The low level is almost the same as the T level.

Thereafter, the clock signals CK1 and CK2 and the control signals φ1 and φ2 output from the controller 3 are periodically changed to the high level and the low level,
The odd-numbered stage RS (k) operates similarly to the stage RS (1), and the even-numbered stage RS (k) operates similar to the stage RS (2). RS at each stage between timing Tn + 1
The output signal out (k) of (k) sequentially becomes high level. Note that odd-numbered stages RS (k) other than the stage RS (1)
Then, the signal input to the drain electrode of the TFT 21 is not the start signal Din but the output signal out (k-1) of the preceding stage RS (k-1).

Timing Tn-timing Tn
During the period of up to +1, the controller 3 sets the control signal φ1 to the high level, so that the TFT of the stage RS (n−1)
21 is turned on, and TFT2 of the stage RS (n-1)
3, 24 are turned off, and the TFT 25 is turned on. After that, timing Tn + 1 to timing Tn + 2
Until then, when the controller 3 sets the control signal φ2 to the high level, the TFT 21 of the stage RS (n) is turned on, the TFTs 23 and 24 of the stage RS (n) are turned off, and the stage RS (n) is turned on. ) The TFT 25 is turned on. Here, in the imaging device 1 according to the present invention, the timing T
One scanning period (hereinafter, referred to as a forward shift scanning period) is set between 1 and the timing Tn + 1, and the timing T is continued.
The period from n + 1 to timing Tn + 2 is the adjustment period.

As described above, in the image pickup apparatus 1 according to the present invention, the controller is used during the forward shift scanning period (that is, from the final stage RS (n) until the on-level output signal out (n) is output). 3 sets the set signal SET to the low level, the first clock signal CK1 to the high level in a predetermined cycle, and the second clock C alternately with the first clock signal CK1.
K2 is at high level. Further, during the forward shift scanning period, the controller 3 sets the control signal φ1 to the high level while the second clock signal CK1 is at the high level,
The control signal φ2 is set to high level when the first clock signal CK1 is on level. As a result, the top gate driver 4 sequentially outputs the high-level output signal out (k) from each stage RS (k), and shifts.

Then, until the timing Tn + 2,
The TFTs 25 of all the stages RS (1) to RS (n) are turned on. Then, the controller 3 sets the timing T
The control signals φ1 and φ2 are maintained at the low level for a predetermined period from n + 2. As a result, all stages RS (1) to RS
The TFT 21 of (n) is turned off, and the preceding stage RS (k-
The input of the output signal out (k−1) from 1) to the stage RS (k) or the input of the start signal Din from the controller 3 to the stage RS (1) is blocked.

Further, at the timing Tn + 2, the controller 3 sets the set signal SET to the high level, maintains the set signal SET at the high level for a predetermined period, and maintains the clock signals CK1 and CK2 at the low level for the predetermined period. As a result, all stages RS (1) to RS
In (n), the parasitic capacitance formed by the gate electrode and drain electrode of the TFT 25 and the gate insulating film between them is charged up, and the potential of the node B is further increased by the bootstrap effect. Then, when the potential of the node B reaches the gate saturation voltage, the current flowing between the source electrode and the drain electrode of the TFT 25 is saturated. Accordingly, the output signals out (1) to out (n) output from the output signal terminals OUT of all the stages RS (1) to RS (n) have substantially the same potential as the level of the set signal SET. It is +25 [V], which is a high level.

After a lapse of a predetermined period, the controller 3
Sets the set signal SET to the low level, sets the start signal Din and the clock signal CK2 to the high level, and causes the high-level output signal from the top gate driver 4 to return to the stages RS (1) to RS as described above.
Shift to (n) sequentially. Here, in the electronic device 1 according to the present invention, the timing relaxation period is from the timing Tn + 2 to the timing T0.

By the way, in the conventional shift register, in the TGL or BGL, the ratio (high level period) / (low level period) of the output signal of each stage is approximately 1 / n during the timing T0 to the timing Tn + 1. When the low level period is relatively long and the shift register operates frequently, holes are gradually accumulated in a nearby insulating film due to a negative voltage of −15 [V] especially near TGL. It was However, in the image pickup apparatus 1 according to the present invention, the controller 3 sets the set signal SET to the high level during the voltage relaxation period (that is, after the final stage RS (n) outputs the high-level output signal out (n)). , Control signal φ
1 and the control signal φ2 are at low level. Therefore,
In the voltage relaxation period, all stages RS (1) to RS (n)
Output signal out from the output signal terminal OUT of
(1) to the output signal out (n) are at high level.
By setting the output signals of all the stages to the high level during the voltage relaxation period, the effect of the relatively negative electric field applied during one scanning period is mitigated to inhibit the accumulation of holes, and thus S / The N ratio can be improved.

In the above, the timing Tn + 2
For a predetermined period, the controller 3 outputs the clock signals CK1,
CK2 was kept at low level, but timing Tn
At +2, the controller 3 sets the clock signals CK1 and CK2 to high level, and the clock signals CK1 and CK for a predetermined period.
2 may be maintained at a high level. After a predetermined period, the controller 3 sets the clock signal CK1 to the low level, the clock signal CK2 to the high level, and the start signal Di.
By setting n to a high level, the top gate driver 4
The high level output signal from is shifted again. Also,
After timing Tn + 2, clock signals CK1 and CK2
Is maintained at a high level, the potential of the drain electrode of the TFT 24 and the potential of the source electrode become almost the same. Therefore, the leak current stops flowing from the source electrode to the drain electrode of the TFT 24, and the set signal SET is set.
The output signal out (k) is output at a level of +25 [V], which is almost the same potential as the level of the above. That is, the timing Tn +
The decrease in the level of the output signal out (k) after 2 is suppressed.

Next, the high level output signal is output to the stage RS.
A case of sequentially shifting from (n) to the stage RS (1) (hereinafter, this case is referred to as reverse shift) will be described. In this case, as shown in FIG. 8, the controller 3 keeps the low-level start signal Din and control signal φ1,
Since φ2 is output, T of the stages RS (1) to RS (n)
The FT 21 is always off. At timing T0, the control signals φ3 and φ4 and the set signal SET are at low level.

Then, at timing T0, the controller 3
Sets the second start signal Rin to high level, the clock signal CK1 to high level, and the clock signal CK2 to low level. After that, the controller 3 causes the control signal φ
4 is set to the high level, the TFT 22 of the stage RS (n) is turned on, and the second start signal Rin of the high level is set.
Is output from the drain electrode to the source electrode. As a result, the TFTs 23 and 24 of the stage RS (n) are turned on and the TFT 25 is turned off. Therefore, the clock signal CK2 is output as the output signal out (n) of the stage RS (n), and its level is low level.

After that, the controller 3 controls the control signal φ4.
After making the low level, the second start signal Rin and the clock signal CK1 are made low level, and the TFT 22 of the stage RS (n) is turned off. TFT 22 in off state
Shuts off the second start signal Rin input to the drain electrode of the stage RS (n). Also, at this time, the step RS
The TFTs 23 and 24 of (n) are maintained in the ON state, the TFT 25 of the stage RS (n) is maintained in the OFF state, and the output signal out (n) is maintained at the low level.

Next, at timing T1, the controller 3 sets the clock signal CK2 to high level. Then, the potential of the node A of the stage RS (n) further rises due to the bootstrap effect, and when the potential of the node A of the stage RS (n) reaches the gate saturation voltage, it is between the drain electrode and the source electrode of the TFT 24. The flowing current is saturated. As a result, the output signal out (n) of the stage RS (n) has a potential of +25 [V] which is substantially the same as the level of the clock signal CK2.
And becomes a high level.

After that, the controller 3 controls the control signal φ3.
To high level. Then, the TF of the stage RS (n-1)
T22 is turned on, and the high-level output signal out
(N) is output from the drain electrode of the TFT 22 of the stage RS (n-1) to the source electrode, and the TFT of the stage RS (n-1) is output.
23 and 24 are turned on and the TF of the stage RS (n-1)
T25 is turned off. As a result, the clock signal C
K1 is the output signal out (n-1) of the stage RS (n-1)
And the output signal out (n-1) is at a low level. Next, the controller 3 sets the control signal φ3 to the low level, and the TFT 22 of the stage RS (n-1) is turned off.

After that, when the controller 3 sets the clock signal CK2 to the low level, the output signal out (n) of the stage RS (n) becomes the low level. Next, at timing T2, the controller 3 causes the clock signal CK1
To high level. Then, the potential of the node A of the stage RS (n-1) rises due to the bootstrap effect, and the current flowing between the drain electrode and the source electrode of the TFT 24 of the stage RS (n-1) is saturated. By this, the step RS
The output signal out (n-1) of (n-1) becomes +25 [V] having substantially the same potential as the level of the clock signal CK1,
High level.

Next, when the controller 3 sets the control signal φ4 to the high level, the TFT 22 of the stage RS (n) and the TFT 22 of the stage RS (n-2) are turned on. At this time, in the stage RS (n), the second start signal Rin
Is at a low level and the TFT 22 of the stage RS (n) is in an ON state, a current flows from the source electrode to the drain electrode of the TFT 22 of the stage RS (n), and the potential of the node A of the stage RS (n) is changed. It goes down to a low level. This allows
The TFTs 23 and 24 of the stage RS (n) are turned off, and the TFT 25 of the stage RS (n) is turned on. Step RS
When the TFT 24 of (n) is turned off, the output of the clock signal CK2 input to the drain electrode of the TFT 24 of the stage RS (n) is cut off. Also, the RS
By turning on the TFT 25 of (n), the output signal out (n) of the stage RS (n) becomes the set signal SET input to the TFT 25 of the stage RS (n), and the output signal out (n) of the output signal out (n). The level is a low level which is almost the same as the level of the set signal SET. After that, the set signal SET is output as the output signal out (n) of the stage RS (n), and the output signal out (n) is maintained at the low level.

On the other hand, in the stage RS (n-2), the stage R
When the TFT 22 of S (n−2) is turned on, the high-level output signal out (n−1) input to the drain electrode of the TFT 22 of the stage RS (n−2) changes to T
It is output to the source electrode of FT22, the TFTs 23 and 24 of the stage RS (n-2) are turned on, and the stage RS (n-2) is turned on.
Of the output signal out (n of the stage RS (n−2) from the low level clock signal CK2.
-2) is output.

Next, when the controller 3 sets the control signal φ4 to the low level, the TFT 22 of the stage RS (n) and the TFT 22 of the stage RS (n-2) are turned off. At this time, the potential of the node A of the stage RS (n) is at a low level and the potential of the node A of the stage RS (n−2) is at a high level.

Then, the controller 3 causes the clock signal C
Set K1 to low level. Then, the output signal out (n-1) of the stage RS (n-1) becomes low level. Next, at timing T3, the controller 3 sets the clock signal CK2 to high level. Then, the potential of the node A of the stage RS (n−2) is further increased by the bootstrap effect, and the current flowing between the drain electrode and the source electrode of the TFT 24 of the stage RS (n−2) is saturated.
Thereby, the output signal out (n- of the stage RS (n-2)
2) is +, which has almost the same potential as the level of the clock signal CK2.
It becomes 25 [V] and becomes high level.

Next, when the controller 3 sets the control signal φ3 to the high level, the TFT 22 of the stage RS (n-1) and the TFT 22 of the stage RS (n-3) are turned on. At this time, in the stage RS (n-1), the set signal SET
Is a low level, and the TFT 22 of the stage RS (n-1) and the TFT 25 of the stage RS (n) are in an ON state, so that a current flows from the source electrode to the drain electrode of the TFT 21 of the stage RS (n-1). , The potential of the node A of the stage RS (n−1) is lowered to the low level. Thereby, the stage RS (n
-1) TFTs 23 and 24 are turned off, and the stage RS
The (n-1) TFT 25 is turned on. As a result, the output of the clock signal CK1 input to the drain electrode of the TFT 24 of the stage RS (n-1) is cut off. The output signal out (n-1) of the stage RS (n-1) is
It is the set signal SET input to the TFT 25 of the stage RS (n-1), and the level of the output signal out (n-1) is a low level that is substantially the same level as the level of the set signal SET.

Thereafter, the clock signals CK1 and CK2 and the control signals φ3 and φ4 output from the controller 3 are periodically changed to the high level and the low level,
The odd-numbered stage RS (k) operates similarly to the stage RS (n), and the even-numbered stage RS (k) operates similar to the stage RS (n-1). This allows the top gate driver 4
From the stage RS (n) to the stage RS (1) in sequence. In the even-numbered stages RS (k) other than the stage RS (n), the signal input to the drain electrode of the TFT 22 is not the second start signal Rin but the output signal out (k + 1) of the subsequent stage RS (k + 1). is there.

Timing Tn to timing Tn
During the period of up to +1, the controller 3 sets the control signal φ4 to the high level, whereby the TFT 22 of the stage RS (2)
Is turned on, the TFTs 23 and 24 of the stage RS (2) are turned off, and the TFT 25 is turned on. After that, during the period from timing Tn + 1 to timing Tn + 2, the controller 3 sets the control signal φ3 to the high level, so that the TFT 21 of the stage RS (1) is turned on and the TFTs 23 and 24 of the stage RS (1) are turned off. Then, the TFT 25 is turned on. As described above, all the stages RS (1) to R during the period up to the timing Tn + 2.
The TFT 25 of S (n) is turned on. Then, the controller 3 maintains the control signals φ3 and φ4 at the low level for a predetermined period from the timing Tn + 2. This allows
The TFTs 22 of all the stages RS (1) to RS (n) are turned off.

Further, at timing Tn + 2, the controller 3 sets the set signal SET to the high level, maintains the set signal SET at the high level for a predetermined period, and maintains the clock signals CK1 and CK2 at the low level for the predetermined period. At timing Tn + 2, the controller 3 sets the clock signals CK1 and CK2 to high level,
The clock signals CK1 and CK2 may be maintained at the high level for a predetermined period.

When the set signal SET becomes high level, the parasitic capacitance composed of the gate electrode and the source electrode of the TFT 25 and the gate insulating film between them is charged in all the stages RS (1) to RS (n). The voltage of the node B is further raised by the bootstrap effect. Then, when the potential of the node B reaches the gate saturation voltage, the current flowing between the source electrode and the drain electrode of the TFT 25 is saturated. Thereby, the output signal out (1) to the output signal out output from the output signal terminals OUT of all the stages RS (1) to RS (n).
(N) is +, which has substantially the same potential as the level of the set signal SET.
It becomes 25 [V], which is a high level. In this way, by setting the output signals of all the stages to the high level during the voltage relaxation period, the influence of the relatively negative electric field applied during one scanning period is mitigated to inhibit the accumulation of holes. ,
The S / N ratio can be improved.

Then, after a lapse of a predetermined period, the controller 3
Sets the set signal SET to the low level, sets the second start signal Rin and the clock signal CK1 to the high level, and sequentially shifts the output signal from the top gate driver 4 again from the stage RS (n) to the stage RS (1). Let
Here, in the imaging device 1 according to the present invention, the timing T1 to
One scanning period (reverse shift scanning period) is set between the timings Tn + 1 and, subsequently, the timings Tn + 1 to T
The period up to n + 2 is the adjustment period, and the timing Tn + 2
Up to timing T0 is the voltage relaxation period.

The operation of the bottom gate driver 5 is as follows.
Although the operation of the top gate driver 4 is almost the same, the clock signals CK1 and CK input from the controller 3 are input.
Since the high level of 2 is +10 [V], each stage RS
The high level of the output signal out (k) of (k) (k: 1 to n) is approximately +10 [V], and the level of the node A at this time is approximately +18 [V]. Further, the clock signals CK1 and CK2 of the bottom gate driver 5 and the control signal φ
The cycles of 1, φ2, φ3, and φ4 are the same as the clock signals CK1 and CK2 and the control signals φ1, φ2, φ3, and φ4 of the top gate driver 4, respectively. The period during which the clock signals CK1 and CK2 of the bottom gate driver 5 are at high level is shorter than the period during which the clock signals CK1 and CK2 of the top gate driver 4 are at high level. Further, when the top gate driver 4 or the bottom gate driver 5 is reversely shifted, the stage RS (1) can be regarded as the final stage and the stage RS (n) can be regarded as the front stage, so that the control signal φ4 can be regarded as the first control signal. The control signal φ3 can be regarded as the second control signal, the clock signal CK2 can be regarded as the first clock signal, and the clock signal CK1 can be regarded as the second clock signal.

Next, the overall operation for driving the image pickup device 2 to capture an image will be described with reference to the schematic diagrams shown in FIGS. Note that, for simplicity of description, the first three rows of the double gate transistors 7 arranged in the image sensor 2 will be mainly described below.

First, between timings T1 and T2, as shown in FIG. 9A, the top gate driver 4 applies +25 [V] to TGL in the first row,
-15 [V] is applied to TGL of the third line (all other lines). That is, the high level output signal out (1) is output from the stage RS (1) of the top gate driver 4,
(2), low level output signal out from RS (3)
(2) and out (3) are output. On the other hand, the bottom gate driver 5 applies 0 [V] to all BGLs. That is, the stages RS (1) to R of the bottom gate driver 5
Low-level output signals out (1) to ou from S (3)
t (3) is output. During this period, the double-gate transistor 7 in the first row is in the reset state,
The double-gate transistor 7 in the third row is in a state where the read state in the previous vertical period is completed (state that does not affect photosense).

Next, between timings T2 and T3, the high-level output signal shifts to the stage RS (2) of the top gate driver 4 as shown in FIG. Is +2 on the second line TGL
5 [V] is applied, and -15 [V] is applied to the other TGL. On the other hand, the bottom gate driver 5 is
0 [V] is applied to. During this period, the double-gate transistor 7 in the first row is in the photosense state,
The double-gate transistor 7 in the second row is in the reset state, and the double-gate transistor 7 in the third row is in the state where the read state in the previous vertical period is completed (state not affecting the photosense).

Next, between timings T3 and T4, as shown in FIG. 9C, the high-level output signal shifts to the stage RS (3) of the top gate driver 4, and the top gate driver 4 Is +2 on the third line TGL
5 [V] is applied, and -15 [V] is applied to the other TGL. On the other hand, the bottom gate driver 5 is
0 [V] is applied to. During this period, the double-gate transistors in the first and second rows are in the photosense state, and the double-gate transistors 7 in the third row are in the reset state.

Next, between timings T4 and T4.5, the top gate driver 4 applies −15 [V] to all TGLs, as shown in FIG. 9D. On the other hand, the bottom gate driver 5 is
0 [V] is applied to. In addition, the drain driver 6
+10 [V] is applied to all DLs. During this period, the double gate transistors 7 in all the rows are in the photosense state.

Next, between timings T4.5 and T5, as shown in FIG. 9E, the top gate driver 4 applies −15 [V] to all TGLs. On the other hand, the bottom gate driver 5 is
+10 [V] is applied to the other BGL, and 0 [V] is applied to the other BGL. That is, the high level output signal out (1) is output from the stage RS (1) of the bottom gate driver 5,
Low-level output signal out from S (2) and RS (3)
(2) and out (3) are output. During this period, the double gate transistors 7 in the first row are in the first or second read state, and the double gate transistors 7 in the second and third rows remain in the photosense state.

Here, in the double-gate transistor 7 in the first row, the timing T which is in the photo-sensing state
When the semiconductor layer 10 is irradiated with sufficient light in the period from 2 to T4.5, the n-channel is formed in the semiconductor layer 10 in the second read state, so that the corresponding DL
The upper charge is discharged. On the other hand, timing T
If the semiconductor layer 10 is not sufficiently irradiated with light in the period from 2 to T4.5, the n-channel in the semiconductor layer 10 is pinched off in the first read state, so that the charge on the corresponding DL is changed. Is not discharged. The drain driver 6 reads the potential on each DL in the period from timing T4.5 to T5, and supplies it to the controller 3 as image data DATA detected by the double gate transistor 7 in the first row.

Next, between timings T5 and T5.5, as shown in FIG. 9 (f), the top gate driver 4 applies −15 [V] to all TGLs. On the other hand, the bottom gate driver 5 is
0 [V] is applied to. In addition, the drain driver 6
+10 [V] is applied to all DLs. During this period, the double-gate transistors 7 in the first row have finished reading, and the double-gate transistors 7 in the second and third rows are in the photosense state. In addition, between the timing T5 and T5.5, the bottom gate driver 5 is
The high level output signal of the stage RS (1) of the stage RS (2)
However, the output signal is not output from the stage RS (2) because the clock signal input to the stage RS (2) is not at the high level.
It is applied to [V].

Next, between timings T5.5 and T6, the top gate driver 4 applies −15 [V] to all TGLs, as shown in FIG. 9 (g). On the other hand, the high-level output signal shifts to the stage RS (2) of the bottom gate driver 5, and the bottom gate driver 5 applies +10 [V] to the second row BGL and 0 [V] to the other BGL. ] Is applied. During this period, the double-gate transistor 7 in the first row is in a read-completed state, the double-gate transistor 7 in the second row is in the first or second read state, and the double-gate transistor 7 in the third row is in the photosense state. Becomes

Here, in the double-gate transistor 7 in the second row, the timing T at which the photo-sensing state has been established.
When the semiconductor layer 10 is sufficiently irradiated with light in the period from 3 to T5.5, the n-channel is formed in the semiconductor layer 10 in the second read state, so that the corresponding DL
The upper charge is discharged. On the other hand, timing T
If the semiconductor layer 10 is not sufficiently irradiated with light in the period from 3 to T5.5, the n-channel in the semiconductor layer 10 is pinched off and the charges on the corresponding DL are brought into the first read state. Is not discharged. The drain driver 6 reads the potential on each DL during the period from timing T5.5 to timing T6, and supplies it to the controller 3 as the image data DATA detected by the double gate transistor 7 in the second row.

Next, between timings T6 and T6.5, as shown in FIG. 9 (h), the top gate driver 4 applies −15 [V] to all TGLs. On the other hand, the bottom gate driver 5 is
0 [V] is applied to. In addition, the drain driver 6
+10 [V] is applied to all DLs. During this period, the double-gate transistors 7 in the first and second rows are in the read-completed state, and the double-gate transistors 7 in the third row are in the photosense state.

Next, between timings T6.5 and T7, the top gate driver 4 applies −15 [V] to all TGLs, as shown in FIG. 9 (i). On the other hand, the high-level output signal shifts to the stage RS (3) of the bottom gate driver 5, and the bottom gate driver 5 applies +10 [V] to the BGL of the third row and 0 [V to the other BGL. ] Is applied. In this period,
The double-gate transistor 7 in the second row is in a state where the reading is completed, and the double-gate transistor 7 in the third row is read.
Becomes the first or second read state.

Here, in the double-gate transistor 7 in the third row, the timing T when it is in the photo-sensing state.
When the semiconductor layer 10 is irradiated with sufficient light in the period from 4 to T6.5, the second read state is set, and an n channel is formed in the semiconductor layer 10, so that the corresponding DL
The upper charge is discharged. On the other hand, timing T
If sufficient light is not applied to the semiconductor layer 10 in the period from 4 to T6.5, the n-channel in the semiconductor layer 10 is pinched off in the first read state, so that the charge on the corresponding DL is changed. Is not discharged. The drain driver 6 reads the potential on each DL in the period from timing T6.5 to T7, and supplies it to the controller 3 as image data DATA detected by the double gate transistor 7 in the third row.

In this way, the controller 3 responds to the image data DATA supplied from the drain driver 6 for each row.
Performs predetermined processing to generate image data of the imaging target. Then, in both the top gate driver 4 and the bottom gate driver 5, the high level output signal is shifted to the final stage RS (n), and all the double gate transistors 7 perform a series of sensing operations of reset, photo sense, precharge and read. After finishing,
As shown in (j), during the period from timing Tn + 1 to timing Tn + 2, the top gate driver 4 operates at all T
-15 [V] is applied to GL. On the other hand, the bottom gate driver 5 applies 0 [V] to all BGLs.

Thereafter, as described above, when the set signal SET becomes high level in the top gate driver 4 and the bottom gate driver 5 during the voltage relaxation period, as shown in FIG.
As shown in (k), the top gate driver applies +25 [V] to all TGLs, and the bottom gate driver 5 applies +10 [V] to all BGLs. However, most of BGL is low level 0 during one scanning period.
Since it is [V], +10 [V] may not be applied during the voltage relaxation period and may be 0 [V]. That is, only the top gate driver 4 operates as described in the present embodiment,
The bottom gate driver 5 may be a conventional shift register that outputs 0 [V] during the voltage relaxation period. Further, the bottom gate driver 5 has a high level of +1.
In order to cancel the accumulation of electrons due to 0 [V], a negative voltage set signal SET may be applied during the voltage relaxation period to operate as described in the present embodiment. Then, after the lapse of a predetermined period, the operations shown in FIGS. 9A to 9J are repeated, and the imaging apparatus 1 again generates the image data DATA of the imaging target. For example, the image pickup apparatus 1 may repeat the operation shown in FIGS. 9A to 9J three times to average the obtained three images DATA.

In the above, the top gate driver 4 is
The case where the high level output signal from the bottom gate driver 5 shifts from the stage RS (1) to the stage RS (n) will be described.
In the case of shifting to, the double gate transistor 7 in the nth row is changed to the photosensing state.

Next, the effect of this embodiment will be described by taking the top gate driver 4 as an example. As shown in FIG. 7, while the top gate driver 4 is scanning (timing T
1 to Tn + 1), the period during which the output signal out (k) output from each stage RS (k) is at the high level is only between timings Tk and Tk + 1. Timing Tk
The output signal out (k) output from each stage RS (k) is at a low level except during the period from to Tk + 1. Therefore,
While the top gate driver 4 is scanning, +25 is applied to the top gate electrode 17 (shown in FIGS. 2 to 3) of the double gate transistor 7 in the kth row (shown in FIGS. 1 to 3).
The period during which -15 [V] is applied is longer than the period during which [V] is applied. Here, if the high-level set signal SET is not input to the top gate driver 4 after the scanning period (after the timing Tn + 2), the top gate electrode 1 of the double gate transistor 7 in the kth row
Since the period during which -15 [V] is applied to 7 is long,
The semiconductor layer 10 and the block insulating films 11a and 11b (see FIGS.
(Illustrated in FIG. 3), the period in which holes are generated is long. Therefore, holes remain in the semiconductor layer 10 and the block insulating films 11a and 11b, and the transistor characteristics (transmission characteristics) of the double gate transistor 7 change. As a result, the current between the drain and source electrodes of the double gate transistor 7 becomes low, which may cause the imaging device 2 to malfunction.

By the way, in the present embodiment, each stage RS
Since the set signal SET is input to the source electrode of the TFT 25 of (k), the controller 3 sets the set signal SE.
By setting T to the high level, the output signal out output from each stage RS (k) of the top gate driver 4
(K) becomes high level at the same time. Therefore, the top gate driver 4 and the bottom gate driver 5 can sequentially output and shift the high level output signal from each stage, and at the same time, output the high level output signal from the final stage RS (n). Is output, all stages RS
It is possible to simultaneously output high-level output signals from (1) to the stage RS (n). Therefore, changes in the transistor characteristics of the double gate transistor 7 can be suppressed.

That is, in the top gate driver 4 of the present embodiment, apart from the period (timing T0 to timing Tn + 1) in which the high-level output signal is sequentially shifted and output, a predetermined period (timing Tn + 2 to next timing T0). ), The output signal out (k) of each stage RS (k) simultaneously becomes high level and is output. Therefore, the top gate electrode of the double gate transistor 7 in the kth row is +
The time when 25 [V] is applied and the time when -15 [V] is applied are averaged. Therefore, even when the imaging device 1 is used for a long time, the change in the transistor characteristics of the double gate transistor 7 is suppressed, and the imaging element 2 is prevented from malfunctioning.

The present invention is not limited to the above embodiments, and various improvements and design changes may be made without departing from the spirit of the present invention. In each of the above-described embodiments, the electronic device including the image pickup device has been described, but the present invention is not limited to this, and a liquid crystal display device including a pixel TFT is provided instead of the image pickup device, and If the gate driver 4 described above is applied as a gate driver for driving a TFT, not only forward shift but also reverse shift is possible. Therefore, for example, when the liquid crystal panel on which the image is displayed is physically rotated up and down so that the image is viewed from a predetermined direction, the shift register can automatically convert from the forward shift to the reverse shift. By switching to, it is possible to display the top and bottom of the image as it is without processing the image signal.

[0106]

As described above, according to the present invention, the second output signal in which the third transistor is at the off level is output during the forward shift scanning period, but is turned on during the period when the second output signal is output. The deviation of the electric polarity on the side supplied with the output signal, which occurs because the level is longer than the first output signal,
By outputting the third output signal having the same polarity as the first output signal during the voltage relaxation period, this can be mitigated, so that at least a part of the charge held by the second output signal is accumulated as it is due to this bias. Since it disappears without any trouble, it is possible to suppress the risk of causing a malfunction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a specific configuration of an imaging device to which an electronic device according to the present invention is applied.

FIG. 2 is a plan view showing a specific mode of a double gate transistor which constitutes an image pickup device provided in the image pickup apparatus.

3 is a view showing a specific mode of the double gate transistor, and is a cross-sectional view showing a cross section taken along the line AA in FIG. 2. FIG.

FIG. 4 is a block diagram showing a specific configuration of an entire top gate driver or bottom gate driver included in the imaging device.

FIG. 5 is a diagram showing a specific mode of an overall circuit configuration of the top gate driver or the bottom gate driver.

FIG. 6 is a diagram showing a circuit configuration of each stage of the top gate driver or the bottom gate driver.

FIG. 7 is a timing chart showing an operation of the top gate driver or the bottom gate driver.

FIG. 8 is a timing chart showing an operation of the top gate driver or the bottom gate driver.

FIG. 9 is a schematic diagram for explaining the operation of the imaging device.

FIG. 10 is a diagram showing a circuit configuration of each stage of a conventional driver.

[Explanation of symbols]

1 Imaging Device (Electronic Device) 2 Imaging Device 3 Controller (Signal Output Means) 4 Top Gate Driver (Shift Register) 5 Bottom Gate Driver (Shift Register) 7 Double Gate Transistor (Constitutes Imaging Device) 21 TFT (Transistor) 22 TFT (fourth transistor) 23 TFT (first transistor) 24 TFT (second transistor) 25 TFT (third transistor) CK1 clock signal (first clock signal) CK2 clock signal (second clock signal) φ1 control signal ( First control signal) φ2 control signal (second control signal) φ3 control signal (third control signal) φ4 control signal (fourth control signal)

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5C006 BB16 BC03 BF03 BF34 BF39                 5C024 CX03 CX51 GX01 GZ01 HX40                 5C080 AA10 BB05 DD09 FF11 JJ02                       JJ03 JJ04 JJ06                 5J056 AA05 BB21 CC18 DD13 DD29                       EE08 FF02 FF07 FF10 GG07                       KK01 KK02

Claims (7)

[Claims] 1. A plurality of stages are turned on when a first control signal or a second control signal input to a control terminal goes to an on level, and selectively from the previous stage when turned on. Outputs an on-level output signal to another terminal when an on-level output signal is input to one terminal, or turns off when an off-level output signal is input to one terminal from the previous stage in the on state. A first transistor that outputs a level output signal to another terminal, and a second transistor that outputs a first clock signal or a second clock signal as an output signal of the stage according to an on-level output signal from the first transistor And a third transistor that is in an off state when the second transistor is in an on state and is in an on state when the second transistor is in an off state. An electronic device including a shift register, wherein the second transistor in each stage sequentially outputs the first clock signal or the second clock signal as a first output signal of a predetermined polarity during a forward shift scanning period, The third transistor outputs a second output signal having a polarity opposite to the predetermined polarity during the forward shift scanning period, and outputs a third output signal having the same polarity as the first output signal during a voltage relaxation period. And electronic device. 2. The first clock signal is output to the second transistors in odd-numbered stages during the forward shift scanning period, and the first clock signal is output to the second transistors in even-numbered stages during the forward shift scanning period. Two clock signals are output, the third output signal is output to the third transistors of the plurality of stages, and the first control signal is output to the first transistors of the odd-numbered stages during the voltage relaxation period. The electronic device according to claim 1, further comprising signal output means for outputting the second control signal to the first transistors of the even-numbered stages. 3. Each of the plurality of stages is turned on by a third control signal or a fourth control signal input to a control terminal being turned on during a reverse shift scanning period,
Alternatively, when an on-level output signal from the subsequent stage is input to one terminal in the on state, the on-level output signal is output to the other terminal, or when the on-level output signal is output from the subsequent stage in the on state. Further comprising a fourth transistor for outputting an off-level output signal to the other terminal when the output signal is input to one terminal, wherein the signal output means includes the fourth transistor in the fourth transistor during the reverse shift scanning period. The electronic device according to claim 2, wherein the electronic device outputs three control signals or the fourth control signal. 4. The signal output means maintains the set signal at an on level and maintains the first control signal and the second control signal at an off level during the predetermined period during the voltage relaxation period. The electronic device according to claim 2. 5. The electronic device according to claim 2, wherein the signal output means maintains the first clock signal and the second clock signal at an off level during the voltage relaxation period. 6. The electronic device according to claim 2, wherein the signal output unit maintains the first clock signal and the second clock signal at an on level during the voltage relaxation period. 7. The electronic device according to claim 1, further comprising an image sensor that operates according to an output signal output from the shift register.