JP2007202126A - Semiconductor device, display device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which operates stably with few malfunctions due to noise, low power consumption, and little variation in characteristics, a display device including the semiconductor device, and electronic equipment including the display device. <P>SOLUTION: An output terminal is connected to a power supply line, thereby reducing a variation in electric potential of the output terminal. In addition, a gate electrode potential which turns ON a transistor is maintained due to the capacitance of the transistor. Further, a change in characteristics of the transistor is reduced by a signal line for reverse biasing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device, a display device, and an electronic device.

The shift register circuit is a circuit that operates to move the content by one digit each time a pulse is given. Utilizing this property, it is used in a circuit for converting a serial signal and a parallel signal into each other. Circuits for serial-parallel conversion of signals are mainly used in networks that connect circuits to each other. In many cases, the number of transmission lines for transmitting signals by connecting circuits to each other via a network is smaller than the amount of data to be transmitted. In such a case, the sending circuit converts the parallel signal to a serial signal and sends the signal in order to the transmission line, and the receiving circuit converts the serial signal sent in turn to a parallel signal. Thus, signals can be exchanged even if the number of transmission paths is small.

The display device displays an image by controlling the luminance of each pixel in accordance with an image signal input from the outside. Here, since it is difficult to use the transmission path of the video signal from the outside for the number of pixels, it is necessary to serial-parallel convert the video signal. Therefore, the circuit on the side that sends the video signal to the display device also has to be used. A shift register circuit is also used for a circuit for driving a display device on the side receiving a video signal.

As the shift register circuit described above, a CMOS circuit in which an N-channel transistor and a P-channel transistor are combined is often used. However, in order to form a CMOS circuit combining an N-channel transistor and a P-channel transistor on the same substrate, it is necessary to form transistors having opposite conductivity types on the same substrate. The process becomes complicated. As a result, the cost of the semiconductor device increases and the yield decreases.

Therefore, a circuit in which all transistors have the same polarity (also referred to as a unipolar circuit) has been devised. A unipolar circuit can suppress an influence of an increase in cost and a decrease in yield by omitting a part of a manufacturing process such as a process of adding an impurity element in the manufacturing process.

For example, consider the case of configuring a logic circuit in which all transistors have N-channel polarities. This circuit has a problem that when the potential of the high potential power supply is output, the voltage of the output signal is attenuated as compared with the voltage of the input signal in accordance with the threshold value of the N-channel transistor. Therefore, in order not to attenuate the voltage of the output signal, a circuit called a bootstrap circuit is widely used. The bootstrap circuit is realized by placing the gate electrode of the transistor capacitively coupled to the output terminal in a floating state after the transistor connected to the power supply on the high potential side is turned on and current begins to flow through the channel. The By doing so, the potential of the gate electrode of the transistor rises as the potential of the output terminal rises, and finally, by making it higher than the potential of the high potential power supply by the threshold voltage or more, The potential of the output terminal can be made approximately equal to the potential of the high potential power source.

With the bootstrap circuit, a semiconductor device in which the output potential is not attenuated even if it is unipolar can be realized. Further, a shift register circuit can be formed by the bootstrap circuit (see, for example, Non-Patent Document 1 and Patent Document 1).
Toshimiyazawa, et al., “Digest of Technical Papers” (USA), 2005, Volume XXXVI, Book I, p. 1050-1053 JP 2002-215118 A

A conventional example in Non-Patent Document 1 is shown in FIG. 37 (however, the reference numerals and the like are changed). In the shift register circuit illustrated in FIG. 37, when an input signal is input to Vin, the potential of the terminal P1 rises, and the transistor connected to the signal line V1 is turned on. Thereafter, when the potential of the signal line V1 rises, this transistor performs a bootstrap operation, and the potential of the signal line V1 is transmitted to the next stage without being attenuated. 37A is a circuit diagram of the shift register circuit up to the fourth stage, and FIG. 37B is surrounded by a broken line in FIG. 37A to help understanding the circuit configuration. This is a range circuit extracted. FIG. 37B is a minimum unit constituting the circuit shown in FIG. 37A. One circuit shown in FIG. 37B is different from the circuit shown in FIG. One output terminal (OUT1-OUT4) corresponds. In this specification, a circuit unit as shown in FIG. 37B with respect to FIG. 37A is referred to as a single-stage circuit. Here, the transistor that turns on and off the connection between the terminal P1 and the power supply line Vss is turned on by the output of the next stage, but the output of the next stage is at a high potential (H level) during the on state. Therefore, the terminal P1 and the terminal OUT1 are in a floating state in most of a period during which a low potential (L level) is to be output to the terminal OUT1 (also referred to as a non-selection period). The same applies to the terminal Px and the terminal OUTx in the subsequent stages. For this reason, there has been a problem that operation failure is caused by noise generated by the clock signal 1 and the clock signal 2 or noise caused by electromagnetic waves from the outside of the circuit.

Therefore, as a countermeasure for this problem, Non-Patent Document 1 uses the configuration shown in FIG. 38 to solve the problem. 38A is a circuit diagram of the shift register circuit up to the sixth stage, and FIG. 38B is surrounded by a broken line in FIG. 38A to help understanding of the circuit configuration. A single stage circuit is extracted. The configuration shown in FIG. 38 is configured such that the time during which the transistor that resets the terminal P1 and the terminal Px in the subsequent stage to the L level is turned on becomes most of the non-selection period. As a result, during the non-selection period, fluctuations in the potential of the terminal P1 and the terminal Px in the subsequent stages are suppressed to some extent.

However, in the configuration illustrated in FIG. 38, in the non-selection period, the terminal OUT1 and the terminal OUTx in the subsequent stage are in a floating state. Therefore, there is a problem that the terminal OUT causes malfunction due to noise generated by the clock signal 1 and the clock signal 2 or noise due to electromagnetic waves from the outside of the circuit. In the configuration shown in FIG. 38, since a capacitive element is provided between the electrode connected to the gate electrode of the transistor for resetting the terminal Px of each stage and the input terminal Vin, the load for driving the input terminal Vin Is big. Therefore, there are problems that the signal waveform is distorted and the power consumption is large. In addition, since the transistor for resetting the terminal Px at each stage is in an on state during most of the non-selection period, there is a problem that the voltage stress applied to the gate electrode is large and the characteristics are easily changed.

In view of such a problem, the present invention provides a semiconductor device that operates stably with less malfunction due to noise, consumes less power, has less characteristic fluctuation, a display device including the semiconductor device, and the display device It is an object to provide an electronic device having the following.

In the present invention, the display panel includes a liquid crystal display panel using a liquid crystal element and a display panel using a light emitting element such as an electroluminescence (EL) element. In addition, the display device includes a display device that includes the display panel and includes a peripheral circuit that drives the display panel.

One embodiment of a semiconductor device according to the present invention includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, and a fourth terminal, and the potential of the first terminal Is connected to the output terminal, the rectifying element that turns on the first transistor according to the potential of the input terminal, and the output terminal and the second terminal according to the potential of the fourth terminal. A third transistor that conducts and fixes the potential of the output terminal; and a third transistor that conducts the third terminal and the second terminal according to the potential of the fourth terminal and fixes the potential of the third terminal. A transistor.

Another embodiment of the semiconductor device according to the present invention includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. A first transistor that transmits the potential of the first terminal to the output terminal, a rectifying element that turns on the first transistor according to the potential of the input terminal, and a potential of the fifth terminal, The third terminal and the second terminal are made conductive according to the potential of the second transistor which makes the output terminal and the second terminal conductive and fixes the potential of the output terminal, and the potential of the fourth terminal. And a circuit that inverts the potential of the third terminal and outputs the inverted potential to the fifth terminal.

Another embodiment of the semiconductor device according to the present invention includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. A first transistor that includes a sixth terminal and transmits the potential of the first terminal to the output terminal; a first rectifying element that turns on the first transistor according to the potential of the input terminal; In accordance with the potential of the fourth terminal, the second terminal that conducts the output terminal and the second terminal and fixes the potential of the output terminal, and the third terminal and the second terminal according to the potential of the fourth terminal A third transistor that conducts the terminal and fixes the potential of the third terminal; a second rectifying element that increases the potential of the fifth terminal according to the potential of the output terminal; and the potential of the third terminal To make the sixth terminal and the second terminal conductive, and And a fourth transistor that makes later.

Another embodiment of the semiconductor device according to the present invention includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. A first transistor having a sixth terminal and a seventh terminal and transmitting the potential of the first terminal to the output terminal; and a first transistor for turning on the first transistor in accordance with the potential of the input terminal And the second transistor that conducts the output terminal and the second terminal and fixes the potential of the output terminal according to the potential of the seventh terminal, and the third transistor according to the potential of the fourth terminal. A third transistor that conducts the first terminal and the second terminal and fixes the potential of the third terminal; a second rectifying element that increases the potential of the fifth terminal according to the potential of the output terminal; In accordance with the potential of the third terminal, the sixth terminal and the second terminal are made conductive. Having a fourth transistor lowering the sixth potential, inverts the potential of the third terminal, and a circuit for outputting a seventh terminal.

Another embodiment of the semiconductor device according to the present invention includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a rectifying element, A first transistor; a second transistor; and a third transistor, wherein one electrode of the rectifying element is electrically connected to an input terminal, and the other electrode of the rectifying element is a third terminal. And the gate electrode of the first transistor is electrically connected to the third terminal, and one of the source electrode and the drain electrode of the first transistor is electrically connected to the first terminal. The other of the source electrode and the drain electrode of the first transistor is electrically connected to the output terminal, and the gate electrode of the second transistor is electrically connected to the fourth terminal. Source or drain electrode One is electrically connected to the second terminal, the other of the source electrode or the drain electrode of the second transistor is electrically connected to the output terminal, and the gate electrode of the third transistor is the fourth terminal One of the source and drain electrodes of the third transistor is electrically connected to the second terminal, and the other of the source and drain electrodes of the third transistor is the third terminal. And electrically connected.

Another embodiment of the semiconductor device according to the present invention includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. , A rectifying element, a first transistor, a second transistor, a third transistor, and a potential inversion circuit, and one electrode of the rectifying element is electrically connected to the input terminal and is rectifying The other electrode of the element is electrically connected to the third terminal, the gate electrode of the first transistor is electrically connected to the third terminal, and one of the source electrode and the drain electrode of the first transistor Is electrically connected to the first terminal, the other of the source electrode or the drain electrode of the first transistor is electrically connected to the output terminal, and the gate electrode of the second transistor is connected to the fifth terminal. Electrically connected second transistor One of the source electrode and the drain electrode is electrically connected to the second terminal, the other of the source electrode and the drain electrode of the second transistor is electrically connected to the output terminal, and the gate electrode of the third transistor Is electrically connected to the fourth terminal, and one of the source and drain electrodes of the third transistor is electrically connected to the second terminal and the other of the source and drain electrodes of the third transistor. Is electrically connected to the third terminal, one electrode of the potential inverting circuit is electrically connected to the third terminal, and the other electrode of the potential inverting circuit is electrically connected to the fifth terminal. Connected.

Another embodiment of the semiconductor device according to the present invention includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. , A sixth terminal, a first rectifying element, a second rectifying element, a first transistor, a second transistor, a third transistor, and a fourth transistor, One electrode of the rectifying element is electrically connected to the input terminal, the other electrode of the first rectifying element is electrically connected to the third terminal, and the gate electrode of the first transistor is , Electrically connected to the third terminal, one of the source electrode or drain electrode of the first transistor is electrically connected to the first terminal, and the other of the source electrode or drain electrode of the first transistor is The second transistor gate electrically connected to the output terminal. The electrode is electrically connected to the fourth terminal, and one of the source electrode and the drain electrode of the second transistor is electrically connected to the second terminal, and the source electrode or the drain electrode of the second transistor The other is electrically connected to the output terminal, the gate electrode of the third transistor is electrically connected to the fourth terminal, and one of the source electrode or the drain electrode of the third transistor is the second terminal. The other of the source and drain electrodes of the third transistor is electrically connected to the third terminal, and one electrode of the second rectifying element is electrically connected to the output terminal. The other electrode of the second rectifying element is electrically connected to the fifth terminal, the gate electrode of the fourth transistor is electrically connected to the third terminal, and the fourth transistor Source of One of the pole or the drain electrode is connected to the second terminal and electrically, the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the sixth terminal.

Another embodiment of the semiconductor device according to the present invention includes an input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. , The sixth terminal, the seventh terminal, the first rectifying element, the second rectifying element, the first transistor, the second transistor, the third transistor, and the fourth transistor A transistor and a potential inversion circuit are provided, and one electrode of the first rectifying element is electrically connected to the input terminal, and the other electrode of the first rectifying element is electrically connected to the third terminal. And the gate electrode of the first transistor is electrically connected to the third terminal, and one of the source electrode and the drain electrode of the first transistor is electrically connected to the first terminal, and The other of the source and drain electrodes of the transistor is electrically connected to the output terminal The gate electrode of the second transistor is electrically connected to the seventh terminal, and one of the source electrode and the drain electrode of the second transistor is electrically connected to the second terminal, The other of the source electrode and the drain electrode of the transistor is electrically connected to the output terminal, the gate electrode of the third transistor is electrically connected to the fourth terminal, and the source electrode or the drain electrode of the third transistor Is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the third transistor is electrically connected to the third terminal, and one electrode of the second rectifying element is connected Is electrically connected to the output terminal, the other electrode of the second rectifying element is electrically connected to the fifth terminal, and the gate electrode of the fourth transistor is electrically connected to the third terminal. Connected to One of the source electrode and the drain electrode of the fourth transistor is electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the sixth terminal. One electrode of the potential inverting circuit is electrically connected to the third terminal, and the other electrode of the potential inverting circuit is electrically connected to the seventh terminal.

With the configuration of the present invention as described above, it is possible to provide a shift register circuit that operates stably and has few malfunctions due to noise.

In the semiconductor device according to the present invention, the rectifying element may be a diode-connected transistor. By doing so, the types of elements to be manufactured on the substrate can be reduced, so that the manufacturing process can be simplified.

The semiconductor device according to the present invention may include a signal line that can turn on the third transistor and the second transistor. Thus, a shift register circuit that can be stopped and initialized at an arbitrary timing can be provided.

The semiconductor device according to the present invention may have a signal line that can apply a reverse bias to the third transistor and the second transistor. By doing so, it is possible to provide a shift register circuit that operates stably with little characteristic variation.

In the semiconductor device according to the present invention, it is preferable that the duty ratio of each of the signals input to the first clock signal line and the second clock signal line is smaller than 50%. Furthermore, the difference between the center time of the period when the signal input to one is at the low level and the center time of the period when the signal input to the other is at the high level is within 10% of the period of the clock signal. Is preferred. Thus, the interval at which the output signal is output is constant between the output terminals, and a highly accurate shift register circuit can be provided.

In the semiconductor device according to the present invention, it is preferable that the average of the area of the gate electrode of the third transistor and the area of the gate electrode of the second transistor is larger than the area of the gate electrode of the first transistor. Thus, a shift register circuit in which the potential of the output terminal is stably fixed and malfunction due to noise can be reduced can be provided.

In the semiconductor device according to the present invention, the power supply line, the first clock signal line, and the second clock signal line are connected to the output terminal of the first transistor, the third transistor, and the second transistor. It may be arranged on the opposite side. Thus, a shift register circuit in which the potential of the output terminal is stably fixed and malfunction due to noise can be reduced can be provided.

The semiconductor device according to the present invention includes a first wiring layer, a second wiring layer, a third wiring layer, an insulating film, and an interlayer film. The interlayer film is formed between the wiring layer and the second wiring layer, the interlayer film is formed between the second wiring layer and the third wiring layer, the interlayer film is formed thicker than the insulating film, and the first film The electrode electrically connected to the terminal (electrode) is formed by at least the second wiring layer, and the electrode electrically connected to the output terminal is formed by at least the first wiring layer and the third wiring layer. In the region where the electrode electrically connected to the output terminal and the electrode electrically connected to the first terminal (electrode) intersect, the electrode electrically connected to the output terminal is the third It may be formed of a wiring layer. Thus, a shift register circuit in which the potential of the output terminal is stably fixed and malfunction due to noise can be reduced can be provided.

In one embodiment of the semiconductor device according to the present invention, the shift register circuit is formed over the same substrate as the substrate in which the pixel region is formed. By doing so, the manufacturing cost of the display panel can be reduced.

In another embodiment of the semiconductor device according to the present invention, the shift register circuit is arranged as an IC on the same substrate as the substrate on which the pixel region is formed, and is connected to wiring on the substrate by a COG (Chip On Glass) method. Has been. Thus, a display panel with little characteristic variation and low power consumption can be provided.

In another embodiment of the semiconductor device according to the present invention, the shift register circuit is arranged as an IC on a connection wiring substrate connected to a substrate forming a pixel region, and the wiring on the substrate and TAB (Tape Automated) are provided. Bonding). Thus, a display panel with less characteristic variation, low power consumption, and high reliability can be provided.

Another embodiment of the semiconductor device according to the present invention includes a first terminal, a second terminal, a third terminal, a transistor, and a rectifying element, and the gate electrode of the transistor is a second terminal. One of the source and drain electrodes of the transistor is electrically connected to the first terminal, and the other of the source and drain electrodes of the transistor is connected to the third terminal and One of the electrodes of the element is electrically connected to the third terminal, and the other of the electrodes of the rectifying element is electrically connected to the second terminal. By doing so, it is possible to provide a display panel that operates stably with little characteristic fluctuation.

Another embodiment of the semiconductor device according to the present invention includes a first terminal, a second terminal, a third terminal, a fourth terminal, a first transistor, and a second transistor, The gate electrode of the first transistor is electrically connected to the second terminal, and one of the source electrode or the drain electrode of the first transistor is electrically connected to the first terminal, and The other of the source electrode and the drain electrode is connected to the third terminal, the gate electrode of the second transistor is electrically connected to the fourth terminal, and one of the source electrode and the drain electrode of the second transistor is , Electrically connected to the second terminal, and the other of the source electrode and the drain electrode of the second transistor is electrically connected to the third terminal. By doing so, it is possible to provide a display panel that operates stably with little characteristic fluctuation.

One embodiment of a display device according to the present invention includes the above-described semiconductor device, an external drive circuit, and a connection wiring board. The display panel and the external drive circuit are connected by a single connection wiring board. Yes. Thus, a display device with a small number of connection points and high reliability can be provided.

Another embodiment of the display device according to the present invention includes the above-described semiconductor device, an external drive circuit, and a plurality of connection wiring boards. The display panel and the external drive circuit include two or more drivers (data). Are connected by connection wiring boards equal to or less than the number of divisions of line drivers and source line drivers. By doing so, even if the display panel is large, the performance of the driver does not have to be so high, so that a highly reliable display device can be provided.

An electronic device according to the present invention is an electronic device using the display device as a display unit of the device.

Note that the switches shown in the specification may be electrical switches or mechanical switches. Anything that can control the current flow can be used. It may be a transistor, a diode (PN diode, PIN diode, Schottky diode, diode-connected transistor, or the like), or a logic circuit that is a combination thereof. Therefore, when a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desirable that the off-state current is small, it is desirable to use a transistor having a polarity with a small off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region and a transistor having a multi-gate structure. In addition, when the source terminal potential of the transistor that operates as a switch is close to the potential of the low-potential side power supply (Vss, GND, 0 V, etc.), the N-channel type is used. In the case of operating in a state close to the potential of the high potential side power supply (Vdd or the like), it is desirable to use the P channel type. This is because the absolute value of the gate-source voltage can be increased, so that it can be easily operated as a switch. Note that both N-channel and P-channel switches may be used as CMOS switches.

In addition, a display element is not limited, For example, EL element (an organic EL element, an inorganic EL element, or an EL element containing an organic substance and an inorganic substance), an electron emission element, a liquid crystal element, electronic ink, a grating light valve (GLV), a plasma display (PDP), a digital micromirror device (DMD), a piezoelectric ceramic display, a carbon nanotube, or the like can be used as a display medium whose contrast is changed by an electromagnetic action. Note that a display device using an EL element is an EL display, and a display device using an electron-emitting device is a liquid crystal display such as a field emission display (FED) or a SED type flat display (SED: Surface-conduction Electron-Emitter Display). There is a liquid crystal display as a display device using an element, and an electronic paper as a display device using electronic ink.

In the present invention, there are no limitations on the types of transistors that can be used, and the transistor is formed using a thin film transistor (TFT) using a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a semiconductor substrate, or an SOI substrate. Transistors, MOS transistors, junction transistors, bipolar transistors, transistors using organic semiconductors or carbon nanotubes, and other transistors can be used. There is no limitation on the kind of the substrate over which the transistor is provided, and the transistor can be provided over a single crystal substrate, an SOI substrate, a glass substrate, or the like.

In the present invention, being connected is synonymous with being electrically connected. Therefore, in the structure disclosed by the present invention, in addition to a predetermined connection relationship, another element that enables electrical connection therebetween (for example, another element (a transistor, a diode, a resistor, a capacitor, or the like), a switch, or the like) May be arranged.

Note that there is no particular limitation on the structure of the transistor. For example, a multi-gate structure in which the number of gates is two or more may be employed, a gate electrode may be disposed above and below the channel, or a gate electrode may be disposed on the channel. It may be a structure, a structure in which a gate electrode is disposed under a channel, a normal staggered structure, or an inverted staggered structure. Further, the channel region may be divided into a plurality of regions, may be connected in parallel, may be connected in series, or a source electrode or a drain electrode may be connected to the channel (or a part thereof). They may overlap or have an LDD region.

Note that in this specification, a semiconductor device refers to a device having a circuit including a semiconductor element (such as a transistor or a diode). In addition, any device that can function by utilizing semiconductor characteristics may be used. The display device is not only a display panel body in which a plurality of pixels including a display element such as a liquid crystal element or an EL element on a substrate and a peripheral drive circuit for driving these pixels are formed, but also a flexible printed circuit ( FPC) and printed wiring board (PWB) attached are also included. A light-emitting device refers to a display device using a self-luminous display element such as an EL element or an element used in an FED.

Further, among transistors in the present invention, a transistor in which a gate electrode and one of a source electrode and a drain electrode are connected may be referred to as a diode-connected transistor. All diode-connected transistors in the present invention can be replaced with other rectifying elements such as PN junction diodes, PIN diodes, and light emitting diodes.

As described above, according to the present invention, the semiconductor device in which the terminal OUT is connected to the power supply line by the second transistor for at least half of one cycle, the malfunction due to noise is small, and the semiconductor A display device including the device and an electronic device including the display device can be provided.

In addition, since the average gate area of the third transistor and the second transistor is larger than the gate area of the first transistor, there is no need to connect a capacitor to the input terminal. A semiconductor device that can be reduced in size, has less waveform rounding, and consumes less power, a display device including the semiconductor device, and an electronic device including the display device can be provided.

Further, by connecting a diode element or a diode-connected transistor to the gate electrode of the transistor having a long ON state, a sufficient reverse bias can be applied to the gate electrode of the transistor having a long ON state. Therefore, it is possible to provide a semiconductor device that operates stably with little characteristic variation, a display device including the semiconductor device, and an electronic apparatus including the display device.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, a circuit configuration of a shift register in which the potential of an output terminal is fixed in a non-selection period and malfunction due to a clock signal or noise is reduced will be described. An example of the circuit configuration of the shift register according to the present invention is shown in FIG. FIG. 1A shows the overall circuit configuration of the shift register according to the present invention. FIG. 1B is a configuration example of a circuit 10 representing a single stage circuit of a shift register according to the present invention. Note that in this specification, a single-stage circuit has a one-to-one correspondence with the output terminals (L (1) to L (n)) of the circuit as shown in FIG. 1B with respect to FIG. It is assumed that this is the minimum unit constituting the circuit. 1C shows the input signal waveform, internal electrode waveform, and output signal waveform of the circuit shown in FIGS. 1A and 1B.

The circuit shown in FIG. 1A includes a start pulse terminal SP, a first clock signal line CLK1 (also referred to as a first wiring), a second clock signal line CLK2 (also referred to as a second wiring), a power source Line Vss, transistor 18, n circuits 10 (n is an integer of 2 or more), and output terminals L (k) arranged corresponding to the circuit 10 (k is an integer of 1 to n) With. In FIG. 1 (all relevant drawings in this specification), k is not shown in the integer k-th stage from 1 to n, but the output terminal L (k) is connected to the output terminal L (1). It is assumed that the terminal P (k) is provided between the terminal P (1) and the terminal P (n) during L (n). A circuit 10 illustrated in FIG. 1B includes a terminal IN, a terminal OUT, a terminal G, a terminal R, a terminal F, a terminal B, and a terminal C, transistors 11, 12, 13, 15, 16, and 17, and a capacitor. 14 and a terminal P. Note that in this specification, a terminal is an electrode electrically connected to the outside in a circuit. Here, the transistor 11 may be another element having a rectifying property, and is used as an input rectifying element (also referred to as a first rectifying element). The transistor 15 may be another element having a rectifying property, and is used as a reset rectifying element (also referred to as a second rectifying element). The transistor 12 is used as a transmission transistor (also referred to as a first transistor). The transistor 13 is used as an internal potential fixing transistor (also referred to as a third transistor). The transistor 17 is used as an output potential fixing transistor (also referred to as a second transistor). The transistor 16 is used as a setting transistor (also referred to as a fourth transistor).

Note that the terminal P in the k-th stage circuit 10 is also referred to as a terminal P (k). In this embodiment, the capacitor 14 is specified. However, the function of the capacitor 14 can be realized by a parasitic capacitance formed between the gate electrode and the drain electrode (or the source electrode) of the transistor 12. The present invention includes not only a case where is formed as an independent electric element but also a case where it is a parasitic capacitance element associated with the transistor 12.

The gate electrode of the transistor 11 in the circuit 10 illustrated in FIG. 1B is connected to the terminal IN, and one of the source electrode and the drain electrode of the transistor 11 is connected to the terminal IN, and the source electrode or the drain electrode of the transistor 11 is connected. Is connected to the terminal P. Further, the gate electrode of the transistor 12 is connected to the terminal P, one of the source electrode and the drain electrode of the transistor 12 is connected to the terminal C, and the other of the source electrode and the drain electrode of the transistor 12 is connected to the terminal OUT. ing.

The gate electrode of the transistor 13 is connected to the terminal R, one of the source electrode and the drain electrode of the transistor 13 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 13 is connected to the terminal P. ing. One electrode of the capacitive element 14 is connected to the terminal P, and the other electrode of the capacitive element 14 is connected to the terminal OUT.

Further, the gate electrode of the transistor 15 is connected to the terminal OUT, one of the source electrode and the drain electrode of the transistor 15 is connected to the terminal OUT, and the other of the source electrode and the drain electrode of the transistor 15 is connected to the terminal B. ing. The gate electrode of the transistor 16 is connected to the terminal P, one of the source electrode and the drain electrode of the transistor 16 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 16 is connected to the terminal F. ing. The gate electrode of the transistor 17 is connected to the terminal R, one of the source electrode and the drain electrode of the transistor 17 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 17 is connected to the terminal OUT. ing.

As shown in FIG. 1A, the terminal IN of the first-stage circuit 10 is connected to the start pulse terminal SP and the gate electrode of the transistor 18. The first-stage electrode SR (1) is connected to the terminal B of the second-stage circuit 10 and one of the source electrode and the drain electrode of the transistor 18. The other of the source electrode and the drain electrode of the transistor 18 is connected to the power supply line Vss. The power supply line Vss is connected to the terminal G of the circuit 10 in all stages. Further, the first clock signal line CLK1 is connected to the terminal C of the odd-numbered stage circuit 10, and the second clock signal line CLK2 is connected to the terminal C of the even-numbered stage circuit 10.

Next, connection of the k-th stage circuit 10 in the circuit shown in FIG. The electrode SR (k) connected to the terminal R of the kth stage circuit 10 is connected to the terminal B of the k + 1 stage circuit 10 and the terminal F of the k−1 stage circuit 10. The output terminal L (k) connected to the terminal OUT of the kth stage circuit 10 is connected to the terminal IN of the k + 1 stage circuit 10. Here, as shown in FIG. 1A, the connection of the circuit 10 at the first stage and the n-th stage may be different from the connection of the circuit 10 at other stages. For example, the electrode SR (n) at the n-th stage may be connected to the electrode SR (n−1).

Here, in this embodiment, the number n of the circuits 10 is an odd number, but in the present invention, n may be an even number. In the present embodiment, the first clock signal line CLK1 is connected to the terminal C of the odd-numbered stage circuit 10, and the second clock signal line CLK2 is connected to the terminal C of the even-numbered stage circuit 10. In the present invention, when the connection between CLK1 and CLK2 is reversed, that is, the first clock signal line CLK1 is connected to the terminal C of the even-numbered stage circuit 10, and the second clock signal line CLK2 may be connected to the terminal C of the odd-numbered stage circuit 10. Further, the number of clock signal lines of the present invention is not limited to two and may be more than two. At that time, the type (number of phases) of signals input to the clock signal line is preferably the same as the number of clock signal lines. For example, when three clock signal lines are used, the clock signal input to the circuit 10 is preferably a three-phase (three types) signal.

Next, the operation of the circuit shown in FIGS. 1A and 1B will be described with reference to FIG. FIG. 1C is a time chart showing signals input to the circuit shown in FIGS. 1A and 1B, output signals thereof, and waveforms of internal electrodes. The vertical axis represents the signal potential, and the input signal and output signal handle a digital signal having either a high level (also referred to as H level or Vdd level) or low level (also referred to as L level or Vss level). It is good. The horizontal axis represents time, and in the present embodiment, description will be made assuming that the input signal is repeatedly input with respect to time T0. However, the present invention is not limited to this, and includes a case where a desired output signal is obtained by variously changing the input signal.

In this embodiment, an operation of sequentially selecting (scanning) the output signals from the output terminals L (1) to OUT (n) will be described. For example, this operation is widely used as a peripheral drive circuit for controlling the on / off state of a switch for selecting a pixel in an active matrix display device. Note that in this embodiment, signals input to the start pulse terminal SP, the first clock signal line CLK1, and the second clock signal line CLK2 in FIG. 1C are collectively referred to as input signals. To do. In the following description, the potential of the power supply line Vss is approximately the same as the L level potential of the input signal. However, the potential of the power supply line Vss is not limited to this in the present invention.

Next, with reference to FIG. 35, how the circuit shown in FIG. 1 operates will be schematically described. FIGS. 35A to 35F illustrate the circuit operation of FIG. 1B along the time series. In FIG. 35, a transistor indicated by a broken line represents a transistor in an off state, and a transistor indicated by a solid line represents a transistor in an on state. Moreover, the arrow in a figure represents the direction of the electric current in the operation | movement at the time. In addition, the potentials of the electrodes and terminals in the drawing at that time are shown enclosed in <>. Note that the potential of the clock signal is expressed as <Vss>, where the lower potential is the potential of the power supply line Vss, and the higher potential is expressed as <Vdd>.

First, with reference to FIG. 35A, an operation of canceling the reset operation of the stage in the previous stage will be described. Here, in this specification, the operation of raising the potential of the terminal R and turning on the internal potential fixing transistor 13 and the output potential fixing transistor 17 is referred to as a reset operation. Conversely, the operation of lowering the potential of the terminal R and turning off the internal potential fixing transistor 13 and the output potential fixing transistor 17 is referred to as a set operation. During the reset operation, the potentials at the terminal P and the terminal OUT are forcibly set to <Vss>. Therefore, in order to operate the circuit 10, first, a set operation must be performed. This may be performed by setting the potential of the terminal R of the stage to <Vss> by the setting transistor 16 of the previous stage at the timing when the potential of the terminal P of the previous stage rises. In the state of FIG. 35A, all of the transistors 11, 12, 13, 15, 16, and 17 may be considered to be in an off state and an initialized state.

Next, the pulse input operation will be described with reference to FIG. When a pulse is input to the terminal IN and the potential of the terminal IN is increased, and the potential of the terminal IN is higher than the potential of the terminal P by a threshold voltage (also referred to as Vth11) of the transistor 11, the transistor 11 is turned on. Then, the potential of the terminal P also rises, and the potential of the terminal P becomes a potential <Vdd− | Vth11 |> lower than the potential <Vdd> of the terminal IN by Vth11. At this time, the transistors 11 and 16 are turned on, and the potential of the terminal OUT becomes equal to the potential <Vss> of the terminal C. Further, the potential of the terminal F becomes <Vss>, whereby the potential of the terminal R in the subsequent stage is set to <Vss>. That is, the subsequent stage is set by the setting transistor 16 of the stage.

Next, the bootstrap operation will be described with reference to FIG. The terminal IN that has increased the potential of the terminal P may return to the potential <Vss> at an arbitrary timing. The transistor 11 is diode-connected, and even when the potential of the terminal IN returns to <Vss>, the transistor 11 is turned off, so that the potential of the terminal P is not affected. That is, the transistor 11 increases the potential of the terminal P as the potential of the terminal IN increases but does not need to decrease it, and is used as an input rectifying element.

When the clock signal is input and the potential at the terminal C becomes <Vdd> with the potential at the terminal P increased, a current flows through the transfer transistor 12 from the terminal C to the terminal OUT, and the potential at the terminal OUT also increases. . At that time, since the terminal P and the terminal OUT are connected by the capacitive element 14, the potential of the terminal P increases as the potential of the terminal OUT increases. The value at which the potential at the terminal P rises depends on the capacitance value of the parasitic capacitive element other than the capacitive element 14 connected to the terminal P, but there is no problem in operation as long as the potential is <Vdd + | Vth11 |> or higher. The potential of the terminal OUT rises to <Vdd>, which is the same as that of the clock signal. Therefore, in the drawing, the potential of the terminal P at this time is described as <Vdd + | Vth11 | (upward arrow)> in the sense of a potential equal to or higher than <Vdd + | Vth11 |>.

Next, with reference to FIG. 35D, an operation for resetting the preceding stage by the stage will be described. When the potential of the terminal OUT is increased to <Vdd> as shown in FIG. 35C, the transistor 15 is turned on and the potential of the terminal B is also increased. Then, when the potential of the terminal B becomes lower than the potential of the terminal OUT by the threshold voltage (also referred to as Vth15) of the transistor 15, the transistor 15 is turned off, so that the increase in the potential of the terminal B stops and the terminal B The potential of B is <Vdd− | Vth15 |>. At this time, since the potential at the terminal R at the previous stage rises to <Vdd− | Vth15 |>, the previous stage performs a reset operation, and the potential at the terminal P and the terminal OUT at the previous stage is fixed at <Vss>. No pulse is input to the.

Next, the operation of returning the clock signal to Vss will be described with reference to FIG. When the potential of the clock signal returns to <Vss> and the potential of the terminal C returns to <Vss>, since the transmission transistor 12 is in an on state, a current flows through the transmission transistor 12 from the terminal OUT to the terminal C. The potential of OUT also returns to <Vss>. At this time, the potential of the terminal P also returns to <Vdd− | Vth11 |>. Further, since the transistor 15 is off, the potential of the terminal B remains <Vdd− | Vth15 |> even if the potential of the terminal OUT returns to <Vss>. That is, the transistor 15 increases the potential of the terminal B as the potential of the terminal OUT increases but does not need to decrease it, and is used as a reset rectifying element.

Next, with reference to FIG. 35F, an operation in which the corresponding stage is reset by a subsequent stage will be described. When the potential of the terminal OUT of the stage is transmitted to the terminal IN of the subsequent stage, the potential of the terminal OUT of the subsequent stage rises, and the potential of the terminal B of the subsequent stage rises by turning on the transistor 15 of the subsequent stage. Since the potential at the terminal R of the current line rises to <Vdd− | Vth15 |>, the corresponding stage is reset. At this time, the internal potential fixing transistor 13 and the output potential fixing transistor 17 in the stage are turned on, and the terminal P and the terminal OUT are each fixed to the potential <Vss>. As described above, the reset operation of the corresponding stage is performed by the subsequent stage operation, so that the transmission transistor 12 is turned off, and the conduction between the terminal OUT and the terminal C is interrupted.

In this state, the potential of the terminal R drops due to the leakage current of the element connected to the terminal R, and the internal potential fixing transistor 13 and the output potential fixing transistor 17 are naturally turned off, or the previous setting transistor 16 Is turned on, the potential of the terminal R becomes <Vss>, and the internal potential fixing transistor 13 and the output potential fixing transistor 17 are forcibly turned off (state (A) in FIG. 35). It ends depending on what. A period from the state of FIG. 35F to the state of FIG. 35A is referred to as a non-selection period in this specification. During this period, the potentials of the terminal P and the terminal OUT are stabilized. It is important to set <Vss>. In other words, it is important how to keep holding the transistor whose gate electrode is connected to the terminal R is in the ON state.

Note that the single stage circuit of the shift register circuit according to the present invention has an output potential fixing transistor, and when the transfer transistor is in an off state, the output terminal is prevented from being in a floating state and is made conductive with a power supply line. Features. Therefore, how the terminal R is reset or set is not limited to the above-described example. That is, the configuration shown in FIGS. 36A and 36C may be used as a single stage circuit.

A circuit 310 illustrated in FIG. 36A includes terminals IN, OUT, R, G, and C, a terminal P, and transistors 311, 312, 313, and 317. The gate electrode of the transistor 311 is connected to the terminal IN, one of the source electrode and the drain electrode of the transistor 311 is connected to the terminal IN, and the other of the source electrode and the drain electrode of the transistor 311 is connected to the terminal P. . The gate electrode of the transistor 312 is connected to the terminal P, one of the source electrode or the drain electrode of the transistor 312 is connected to the terminal C, and the other of the source electrode or the drain electrode of the transistor 312 is connected to the terminal OUT. .

The gate electrode of the transistor 313 is connected to the terminal R, one of the source electrode and the drain electrode of the transistor 313 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 313 is connected to the terminal P. . The gate electrode of the transistor 317 is connected to the terminal R, one of the source electrode and the drain electrode of the transistor 317 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 317 is connected to the terminal OUT. . Note that the transistor 311 may be used as an input rectifying element (first rectifying element).

The transistor 312 may be used as a transmission transistor (first transistor). The transistor 317 may be used as an output potential fixing transistor (second transistor). The transistor 313 may be used as an internal potential fixing transistor (third transistor).

Here, the operation of the circuit shown in FIG. 36A will be described with reference to FIG. FIG. 36B is a time chart illustrating potential changes at the terminals illustrated in FIG. A clock signal is input to the terminal C, a pulse for increasing the potential of the terminal P is input to the terminal IN, the terminal G is fixed at the L level, and a pulse having a reverse phase including a pulse for decreasing the potential of the terminal P to the terminal R The case where is input will be described.

When the potential of the terminal R is low and the internal potential fixing transistor and the output potential fixing transistor are off, and a pulse is input to the terminal IN, the potential of the terminal P rises through the input rectifying element, and the transmission transistor is turned on. Become. Thereafter, when the potential of the terminal C rises, the transmission transistor performs a bootstrap operation, and the potential of the terminal C is transmitted to the terminal OUT as it is. Thereafter, when the potential at the terminal R rises, the internal potential fixing transistor and the output potential fixing transistor are turned on, so that the terminal P and the terminal OUT are fixed at the L level.

In this way, the circuit 310 according to the present invention can transmit a signal input to the terminal C to the terminal OUT only during a period when the potential of the terminal R is low. Further, the terminal P and the terminal OUT can be fixed to the L level during a period in which the potential of the terminal R is high. However, the signal waveform input to the circuit 310 according to the present invention is not limited to this.

A circuit 320 illustrated in FIG. 36C includes terminals IN, OUT, R, G, and C, terminals P and Q, transistors 321, 322, 323, and 327a, an inverter 327b, and a capacitor 324. Prepare. Note that the capacitor 324 is not necessarily connected as illustrated in FIG. The gate electrode of the transistor 321 is connected to the terminal IN, one of the source electrode and the drain electrode of the transistor 321 is connected to the terminal IN, and the other of the source electrode and the drain electrode of the transistor 321 is connected to the terminal P. .

The gate electrode of the transistor 322 is connected to the terminal P, one of the source electrode and the drain electrode of the transistor 322 is connected to the terminal C, and the other of the source electrode and the drain electrode of the transistor 322 is connected to the terminal OUT. . The gate electrode of the transistor 323 is connected to the terminal R, one of the source electrode and the drain electrode of the transistor 323 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 327 is connected to the terminal P. . One electrode of the capacitor 324 is connected to the terminal P, and the other electrode of the capacitor 324 is connected to the terminal OUT. The gate electrode of the transistor 327a is connected to the terminal Q, one of the source electrode and the drain electrode of the transistor 327a is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 327a is connected to the terminal OUT. .

An input electrode of the inverter 327b is connected to the terminal P, and an output electrode of the inverter 327b is connected to the terminal Q. Note that the transistor 321 may be used as an input rectifying element (first rectifying element). The transistor 322 may be used as a transmission transistor (first transistor). The transistor 327a may be used as an output potential fixing transistor (second transistor). The transistor 323 may be used as an internal potential fixing transistor (third transistor).

Here, the operation of the circuit shown in FIG. 36C will be described with reference to FIG. FIG. 36D is a time chart illustrating potential changes at the terminals illustrated in FIG. A clock signal is input to the terminal C, a pulse for increasing the potential of the terminal P is input to the terminal IN, a terminal G is fixed at the L level, and a reverse-phase pulse for decreasing the potential of the terminal P is input to the terminal R. The case will be described.

When the potential of the terminal R is low and the internal potential fixing transistor is in the off state, when a pulse is input to the terminal IN, the potential of the terminal P rises through the input rectifying element, and the transmission transistor is turned on. At this time, the terminal Q becomes L level because the potential of the terminal P is inverted. Therefore, the output potential fixing transistor is in the off state. Thereafter, when the potential of the terminal C rises, the transmission transistor performs a bootstrap operation, and the potential of the terminal C is transmitted to the terminal OUT as it is. Thereafter, when the potential at the terminal R rises, the internal potential fixing transistor is turned on, so that the terminal P is fixed at the L level. As a result, the potential at the terminal Q becomes the H level, so that the output potential fixing transistor is turned on. The terminal OUT is fixed at the L level. In this manner, the circuit 320 according to the present invention can transmit a signal input to the terminal C to the terminal OUT only during a period when the potential of the terminal R is low. Further, the terminal P and the terminal OUT can be fixed to the L level during a period in which the potential of the terminal R is high. However, the signal waveform input to the circuit 320 according to the present invention is not limited to this.

With reference to FIG. 1, the start pulse input to the start pulse terminal SP at time T0 will be described next. The pulse width of the start pulse is arbitrary, but if the period of the signal input to the first clock signal line CLK1 and the second clock signal line CLK2 is Tc, it should be Tc / 2 or more and Tc or less. preferable. Thus, the potential of the terminal P (1) connected to the start pulse terminal SP through the diode-connected transistor 11 can be sufficiently increased, and the transistor 13 of the circuit 10 is turned on. Therefore, when the potential of the terminal P is lowered, a steady current path cannot be formed in the path of the terminal IN, the transistor 11, the terminal P, the transistor 13, and the terminal G, and power consumption is suppressed, which is preferable. .

Next, signals input to the first clock signal line CLK1 and the second clock signal line CLK2 will be described. The first clock signal and the second clock signal preferably have a ratio (duty ratio) of time during which the signal is at the H level during one cycle period smaller than 50%. Further, it is preferable that the difference between the time at the center of the period when it is at the L level and the time at the center of the period when the other signal is at the H level is within 10% of the cycle of the clock signal. By doing so, the output signal can be brought close to a pulse signal composed of a single frequency. Further, it is possible to prevent the H level from overlapping in time at the adjacent output terminals. This is because, in the active matrix display device, when the shift register circuit according to this embodiment is used as a peripheral drive circuit for controlling the on / off state of a switch for selecting a pixel, it is selected simultaneously over a plurality of rows. This is advantageous because it can eliminate malfunctions caused by the occurrence of the error.

Terminal P (1) when the initial potential of terminal P (1) of circuit 10 at the first stage is set to L level and a start pulse is input at time T0, and the potential of terminal IN changes from L level to H level. A change in the potential of is described. At this time, the terminal R is at the L level, and the transistor 13 is off. Accordingly, the transistor 11 is turned on, and the potential of the terminal P (1) increases. Since the transistor 11 is turned off when the potential of the terminal P (1) rises to a potential lower than the H level potential of the start pulse by the threshold voltage of the transistor 11, the potential of the terminal P (1) The rise stops. Once the potential of the terminal P (1) rises, the potential of the terminal P (1) does not drop because the transistor 11 remains off even if the potential of the terminal IN falls and then returns to the L level. It becomes floating state.

At this time, in a state where the potential of the terminal P (1) is increased, the potential of the terminal C is L level, so that the transistor 12 is turned on. That is, the L level is output to the terminal OUT. Thereafter, when the potential of the terminal C rises, the potential of the terminal OUT also rises. Further, since the terminal P (1) is in a floating state, the potential of the terminal P (1) also rises as the potential of the terminal OUT rises through the capacitive element 14. That is, by performing the bootstrap operation by the transistor 12, the change in the potential of the terminal C is transmitted to the terminal OUT without being attenuated.

In this manner, in the period in which the transistor 13 is off and the terminal P (1) is in a floating state while the potential of the terminal P (1) is high, a change in the potential of the terminal C is directly transmitted to the terminal OUT. Therefore, when the clock signal is not output as it is to the output terminal, the potential of the terminal R is increased at a certain timing to turn on the transistor 13, and the potential of the terminal P (1) is set to the L level. Then, since the transistor 12 is turned off, the potential of the terminal C is not transmitted to the terminal OUT as it is.

The terminal OUT is connected to the terminal IN of the second stage circuit 10 via the output terminal L (1). That is, the output of the first-stage circuit 10 replaces the start pulse, and the second-stage circuit 10 operates in the same manner as the operation of the first-stage circuit 10 described above.

Next, the timing for performing the reset operation will be described. The timing of performing the reset operation is arbitrary, but the reset operation may be performed when one pulse of the clock signal is transmitted from the terminal C to the terminal OUT. Specifically, the k-th stage reset operation may be performed at the timing when the potential of the (k + 1) -th stage terminal OUT rises. Further, as a circuit configuration in this case, as shown in FIGS. 1A and 1B, the k + 1 stage terminal OUT and the terminal B are connected via a diode-connected transistor 15, and the electrode SR (k) is connected. It is preferable to use a configuration in which the terminal B at the (k + 1) th stage is connected to the terminal R at the kth stage.

In this configuration, when the clock signal is transmitted to the terminal OUT of the kth stage circuit 10 and this clock signal is input to the terminal IN of the k + 1 stage circuit 10, the terminal of the k + 1 stage circuit 10 is provided. A clock signal having a phase different from that of the output signal of the kth stage circuit 10 is output to OUT. At that time, the potential of the terminal B of the k + 1 stage circuit 10 rises at the same timing as the potential of the terminal OUT of the k + 1 stage circuit 10 rises. That is, the potential of the terminal R of the k-th stage circuit 10 rises at the same timing as the potential of the terminal OUT of the k + 1-th stage circuit 10 rises, and the k-th stage circuit 10 is reset. At the timing when the potential at the terminal OUT of the (k + 1) th stage circuit 10 rises, the output of the kth stage circuit 10 is in the state of outputting the L level after transmitting one pulse of the clock signal. Therefore, there is one pulse at the output terminal. In this manner, since the output terminal of the shift register circuit according to this embodiment becomes H level sequentially from OUT (1), in the active matrix display device, the on / off state of the switch for selecting a pixel is changed. It can be used as a peripheral drive circuit to be controlled.

However, the timing of the reset operation in the present invention is not limited to this, and the reset operation may be performed at any timing. For example, the reset operation may be performed at the timing when the potential of the output terminal of the stage after the second stage rises, or the reset operation may be performed at the timing when the potential of the output terminal after the third stage rises. Also good. At this time, the farther the signal line that defines the timing of the reset operation is from the stage, the longer the distance around which the electrode SR is routed, so that the value of the parasitic capacitance associated with the electrode SR increases. This is advantageous in that

Further, as shown in FIG. 1A, the reset operation in the final stage is performed by connecting the electrode SR (n) and the electrode SR (n−1), and performing the reset operation by the output of the final stage itself. You may do it. As a result, as shown in FIG. 1C, the terminal P (n) and the output terminal L (n) are reset (operation for returning to the potential of the power supply line Vss) even at the nth stage which is the final stage. Will be able to. In addition, a reset operation may be performed by separately inputting a common timing pulse in all stages, or a start pulse may be used as a common timing pulse.

Next, in a period other than the period in which the k-th output terminal L (k) is electrically connected to the clock signal line through the transistor 12 in the on state (in FIG. 1C, the terminal P (k) The operation during the period in which the potential of L is at the L level will be described. In the k + 1 stage circuit 10, when the potential of the terminal OUT rises, the diode-connected transistor 15 is turned on, so that the potential of the terminal B is lower than the H level by the threshold voltage of the transistor 15. After that, when the potential of the terminal OUT decreases, the transistor 15 is turned off, so that the potential of the terminal B does not decrease. That is, the potential of the electrode SR (k) rises but does not fall due to the (k + 1) th stage terminal OUT. That is, the potential of the terminal R after the k-th reset operation is held at the H level, so that the transistors 13 and 17 remain on. Therefore, the potential of the terminal P (k) and the potential of the terminal OUT are fixed at the L level.

Here, when the potential of the terminal R after the reset operation is not held at the H level, the transistors 13 and 17 are turned off, so that the terminal P (k) and the terminal OUT are in a floating state. turn into. Since the terminal P (k) is connected to either the first clock signal line or the second clock signal line through the gate capacitance of the transistor 12, the terminal P (k) is in a floating state. ) Easily fluctuates. In addition, since the terminal OUT is capacitively coupled to the terminal P (k) through the capacitor 14, if the potential of the terminal P (k) fluctuates in the floating state, the potential of the terminal OUT is similarly changed. It will fluctuate. Furthermore, the potential of the output terminal L (k) also varies depending on the parasitic capacitance with the clock signal line. The fluctuation of the potential of the output terminal L (k) makes the operation of the shift register circuit unstable and causes a malfunction. Therefore, the potential of the terminal R is held at the H level in order to fix the potential of the terminal P and the terminal OUT. That is extremely important.

Note that the period during which the potential of the terminal R is held at the H level in order to fix the potentials of the terminal P and the terminal OUT is preferably at least a half of one cycle of the start pulse.

However, in order to hold the potential of the electrode SR and the terminal R at the H level even after the reset operation, the capacitor does not need to be connected. By making the average area of the gate electrodes of the internal potential fixing transistor 13 and the output potential fixing transistor 17 larger than the area of the gate electrode of the transfer transistor 12, the potential of the electrode SR and the terminal R remains at the H level even after the reset operation. Can be held. Further, the length of the electrode SR routed from the k-th stage terminal R is made longer than the pitch between the k-th stage circuit 10 and the (k + 1) -th stage circuit 10, thereby increasing the parasitic capacitance associated with the electrode SR. By doing so, the potential of the electrode SR and the terminal R may be held. Of course, the potential of the electrode SR and the terminal R may be held by connecting a capacitor between the electrode SR and the power supply line Vss and the start pulse terminal SP.

As described above, holding the potentials of the terminal R and the electrode SR at the H level even after the reset operation is extremely important for the stable operation of the shift register circuit. When the start pulse is input and the k-th stage circuit 10 operates again, the transistors 13 and 17 do not operate unless they are in the off state. Therefore, before the k-th stage circuit 10 operates, it is necessary to return the potentials of the terminal R and the electrode SR (k) to the L level. This operation is referred to as a set operation in this specification. The timing for performing the set operation is arbitrary, but the k-th set operation may be performed at the timing when the potential of the terminal P (k-1) at the (k-1) th stage rises. As a circuit configuration in this case, as shown in FIGS. 1A and 1B, the terminal P (k−1) is connected to the gate electrode, one of the source electrode or the drain electrode is connected to the terminal G, and the source It is preferable to connect the terminal F and the electrode SR (k) by using the transistor 16 in which the other of the electrode and the drain electrode is connected to the terminal F.

In this configuration, the potential of the terminal P (k−1) at the (k−1) th stage rises before the pulse is input to the terminal IN at the kth stage. The transistor 16 is turned on and the potential of the terminal F becomes L level. Therefore, at this time, the terminal R at the k-th stage changes from the state holding the H level to the L level, and the transistors 13 and 17 are turned off. Thereafter, the (k−1) th stage output is input to the kth stage terminal IN, and the operation of the kth stage circuit 10 starts.

Here, the gate electrode of the k-1 stage transistor 16 may be connected to the k-1 stage terminal OUT instead of the k-1 stage terminal F. In this case, when the (k−1) th stage output is input to the kth stage terminal IN, the kth stage setting operation is performed.

Further, the timing of performing the k-th set operation may be performed at the timing when the potentials of the terminal P (k-2) and the terminal OUT of the k-2th stage rise. Alternatively, it may be performed at a timing when the potentials of the terminal P and the terminal OUT at the stage before the (k-2) th stage rise. When the farther stage is connected via the electrode SR, the length of the electrode SR routed from the k-th stage terminal R is longer than the pitch between the k-th stage circuit 10 and the (k + 1) -th stage circuit 10. There is an advantage that the value of the parasitic capacitance associated with can be increased, and the potential of the electrode SR and the terminal R can be held more reliably.

In addition, a common timing pulse may be separately input at all stages to perform the set operation, or a start pulse may be used as the common timing pulse. Note that the first-stage electrode SR (1) may be connected to one of the source electrode and the drain electrode of the transistor 18 instead of being connected to the terminal F in the previous stage. By doing so, the first stage set operation is performed when the start pulse is input.

Another circuit configuration of the shift register in this embodiment in which the potential of the output terminal is fixed in the non-selection period and the malfunction due to the clock signal or noise is reduced will be described below. Another circuit configuration example of the shift register according to the present invention is shown in FIG. FIG. 2A shows the overall circuit configuration of the shift register according to the present invention. FIG. 2B is a configuration example of the circuit 20 representing a single stage circuit of the shift register according to the present invention. FIG. 2C illustrates another circuit configuration of the entire shift register using the circuit 20 illustrated in FIG.

The circuit shown in FIG. 2A includes a start pulse terminal SP, a first clock signal line CLK1, a second clock signal line CLK2, a power supply line Vss, a transistor 28, and n circuits. 10 (n is an integer of 2 or more) and an output terminal L (k) arranged corresponding to the circuit 20 (k is an integer of 1 to n).

A circuit 20 illustrated in FIG. 2B includes terminals IN, OUT, G, R, F, B, C, and V, transistors 21, 22, 23, 25, 26, 27a, 27b, and 27c, and a capacitor element. 24 and a terminal P. Here, the transistor 21 may be another element having a rectifying property, and is used as an input rectifying element (also referred to as a first rectifying element). The transistor 25 may be another element having a rectifying property, and is used as a resetting rectifying element (also referred to as a second rectifying element). The transistor 22 is used as a transmission transistor (also referred to as a first transistor). The transistor 23 is used as an internal potential fixing transistor (also referred to as a third transistor). The transistor 27a is used as an output potential fixing transistor (also referred to as a second transistor). The transistor 26 is used as a setting transistor (also referred to as a fourth transistor).

Note that the terminal P in the k-th stage circuit 20 is also referred to as a terminal P (k). In this embodiment, the capacitor 24 is specified, but the function of the capacitor 24 can also be realized by a parasitic capacitance formed between the gate electrode and the drain electrode (or source electrode) of the transistor 22. The present invention includes not only the case where is formed as an independent electric element but also the case where it is a parasitic capacitance element associated with the transistor 22. A circuit illustrated in FIG. 2C represents a circuit in which a power supply line Vdd is added to the circuit illustrated in FIG.

The gate electrode of the transistor 21 in the circuit 20 illustrated in FIG. 2B is connected to the terminal IN, and one of the source electrode and the drain electrode of the transistor 21 is connected to the terminal IN, and the source electrode or the drain electrode of the transistor 21 is connected. Is connected to the terminal P. Further, the gate electrode of the transistor 22 is connected to the terminal P, one of the source electrode and the drain electrode of the transistor 22 is connected to the terminal C, and the other of the source electrode and the drain electrode of the transistor 22 is connected to the terminal OUT. ing.

The gate electrode of the transistor 23 is connected to the terminal R, one of the source electrode and the drain electrode of the transistor 23 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 23 is connected to the terminal P. ing. One electrode of the capacitive element 24 is connected to the terminal P, and the other electrode of the capacitive element 24 is connected to the terminal OUT.

The gate electrode of the transistor 25 is connected to the terminal OUT, one of the source electrode and the drain electrode of the transistor 25 is connected to the terminal OUT, and the other of the source electrode and the drain electrode of the transistor 25 is connected to the terminal B. ing. The gate electrode of the transistor 26 is connected to the terminal P, one of the source electrode and the drain electrode of the transistor 26 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 26 is connected to the terminal F. ing.

The gate electrode of the transistor 27a is connected to the terminal Q, one of the source electrode and the drain electrode of the transistor 27a is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 27a is connected to the terminal OUT. ing. Further, the gate electrode of the transistor 27b is connected to the terminal P, one of the source electrode and the drain electrode of the transistor 27b is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 27b is connected to the terminal Q. ing. The gate electrode of the transistor 27c is connected to the terminal V, one of the source electrode and the drain electrode of the transistor 27c is connected to the terminal V, and the other of the source electrode and the drain electrode of the transistor 27c is connected to the terminal Q. ing.

Next, the connection of the k-th stage circuit 20 in the circuit shown in FIG. 2A will be described. The circuit shown in FIG. Since the circuit is the same as that shown in FIG. The connection of the terminal V may be connected to a clock signal line different from the clock signal line to which the terminal C is connected as shown in FIG. Although not shown, the clock signal line may be connected to the same clock signal line to which the terminal C is connected.

The circuit shown in FIG. 2C is obtained by adding a dedicated power supply line Vdd for connecting the terminal V to the circuit shown in FIG. As shown in FIG. 2C, all the stage terminals V and the power supply line Vdd may be connected. The potential applied to the power supply line Vdd only needs to be larger than the L level and higher than the sum of the threshold voltages of the transistors 27a and 27c.

Next, input signals and output signals in the circuits shown in FIGS. 2A, 2B, and 2C are the same as those in FIG. The circuit of FIG. 2 is different from the circuit of FIG. 1 in that the function of fixing the potential of the terminal OUT to the L level by the transistor 17 in FIG. 1B is realized by the transistors 27a, 27b, and 27c. . That is, the gate electrode of the transfer transistor 22 and the gate electrode of the output potential fixing transistor 27a are connected via a circuit that outputs an inversion signal.

In FIG. 2B, when the circuit does not operate and the potential of the terminal P is fixed to the L level by the transistor 23, the transistor 27b is in an off state. At this time, since the potential of the terminal Q is at the H level, the transistor 27a is in an on state. That is, if the terminal P is fixed at the L level, the terminal OUT is also fixed at the L level, and the malfunction of the output terminal due to capacitive coupling with the clock signal line is reduced.

When the circuit 20 operates, a pulse is input to the terminal IN and the potential at the point P rises, so that the transistor 27b is turned on. Then, since the potential of the terminal Q approaches the L level, the transistor 27a is turned off. That is, when the potential of the terminal P rises and the terminal OUT becomes conductive with the terminal C, the transistor 27a is turned off, so that the circuit 20 can realize an operation similar to that of the circuit 10 in FIG.

In addition, according to the present embodiment, it can be said that the shift register according to the present invention is excellent in that the period during which the terminal OUT is fixed at the low level is long. In other words, the longer the period during which the terminal OUT is fixed at the low level, the lower the malfunction of the terminal OUT due to the operation of other signal lines or external noise, and thus the operation stability is higher. In the shift register according to the present invention, since the signal input to the transistor connected to the terminal OUT is less frequently switched, the potential of the terminal OUT is less likely to fluctuate due to signal feedthrough, and the operation is stable. High nature.

(Embodiment 2)
In the present embodiment, the reset operation of the final stage and the reset operation of all stages of the shift register circuit according to the present invention will be described.

In the circuit configuration described in the first embodiment, it has been described that the reset operation of the stage is performed at the timing when the next stage operates. At this time, since the next stage does not exist in the final stage of the shift register circuit, a pulse defining the timing of the reset operation is not input to the final stage. At this time, the potential of the electrode SR (n) does not become H level due to the reset operation. That is, the clock signal is always output to the terminal OUT at the final stage.

In the first embodiment, in view of this point, as shown in FIG. 1A, FIG. 2A, and FIG. 2C, the electrode SR (n) and the electrode SR (n−1) Is connected. By doing this, the electrode SR (n) can be set to the H level by the output of the terminal OUT of the final stage itself, and the reset operation can be performed. Therefore, the potential of the clock signal line is always applied to the output terminal L (n) of the final stage. Can be prevented from being output. In this case, the pulse width of the output of the final stage becomes smaller than the pulse width of the clock signal. Here, if the circuit configuration is such that the clock signal is always output to the final stage and the output of the final stage is not actively used except for the reset operation of the previous stage of the final stage, it is connected to the output terminal of the final stage. In order to charge and discharge the parasitic capacitance elements, extra power is consumed.

The structure described in this embodiment mode is different from the structure shown in Embodiment Mode 1, and the final stage can also operate as a shift register. 3A, 3B, and 3C are used for the reset operation in the final stage in the configuration shown in FIGS. 1A, 2A, and 2C, respectively. This shows a configuration in which a transistor 29 is added. The gate electrode of the transistor 29 is connected to the start pulse terminal SP, one of the source electrode and the drain electrode of the transistor 29 is connected to the start pulse terminal SP, and the other of the source electrode and the drain electrode of the transistor 29 is the electrode SR ( n).

Further, as shown in FIG. 3, when the transistor 29 is used for the reset operation of the final stage, the reset operation of the final stage may not be performed by the final stage itself, but may be performed at the timing when the start pulse is input. Therefore, the electrode SR (n) and the electrode SR (n−1) need not be connected.

FIG. 4 is a time chart for explaining the operation of the circuit shown in FIG. A difference from FIG. 1C is that the reset operation of the terminal P (n) at the final stage is performed at the timing of input of the start pulse (time T0), so that the output terminal L (n) at the final stage is reset. Also, the operation as a shift register circuit can be performed. Here, in the time chart of FIG. 4, when the period for inputting the start pulse is T, the total number of pulses of all clock signal lines input in the period T is larger than the number n of stages of the shift register circuit. preferable. By doing so, the reset operation at the final stage can be reliably performed within the period T.

Next, a shift register circuit according to the present invention, in which a dedicated signal line is added to perform a reset operation, will be described with reference to FIGS.

5A, 5B, and 5C are dedicated to resetting the configuration shown in FIGS. 1A, 2A, and 2C, respectively. The signal line RES and a transistor RE (k) connected to the signal line RES (k is an integer of 1 to n) are added. The gate electrode of the transistor RE (k) is connected to the signal line RES, and one of the source electrode or drain electrode of the transistor RE (k) is connected to the signal line RES, and the source electrode or drain electrode of the transistor RE (k). Is connected to the electrode SR (k).

5 and 6, transistors RE (k) are additionally connected to all the stages so that all the stages are reset at an arbitrary timing, and the initial state is immediately performed without operating to the final stage. However, the present invention is not limited to this, and the number of transistors RE (k) may be any number. For example, the transistor RE may be provided only in the final stage, the transistor RE may be provided only in the odd or even stages, or the transistor RE may be provided only in the first half or the second half. If the number of transistors RE is reduced, there is an advantage that the circuit scale is reduced accordingly and the proportion of the circuit on the substrate is reduced. Further, if the number of transistors RE is reduced, there is an advantage that the load for driving the signal line RES is reduced and the power consumption can be reduced.

Here, the operation of the shift register circuit according to the present invention, in which a dedicated signal line is added to perform the reset operation, will be described with reference to FIG. FIG. 6 is a time chart showing changes in the input signal and the potentials of the terminal P and the output terminal L when a pulse is input to the signal line RES at the time Tr and all the stages are reset. When a start pulse is input at time T0, the same operation as in FIG. 1C is performed until a pulse is input to the signal line RES. However, when a pulse is input to the signal line RES at time Tr, the potential of the electrode SR becomes H level in all stages, so that the terminal P and the output terminal L are fixed to L level. Here, the transistor 16 or 26 that sets the potential of the electrode SR to the L level is turned off because the potential of the terminal P is set to the L level. Therefore, when a pulse is input to the signal line RES, there is no path through which a current flows from the signal line RES to the power supply line Vss.

As described above, the shift register circuit according to the present invention, in which a dedicated signal line is added to perform the reset operation shown in FIG. 5, resets all the stages at an arbitrary timing and operates to the final stage. It is possible to return to the initial state immediately. When this shift register circuit is used as a drive circuit for a display device, for example, when only a part of the pixels arranged in the display area is used, the operation of the shift register circuit is stopped halfway, There is an advantage that power consumption can be reduced because pixels in unused areas are not driven.

In addition, when a pulse is input to the signal line RES, charges are injected into the electrode SR that is in a floating state, so that a decrease in the potential of the electrode SR due to a leakage current can be prevented. That is, there is an effect that it becomes easy for the transistor in which the gate electrode is connected to the electrode SR to keep the on state.

Note that this embodiment can be freely combined with any of the other embodiments.

(Embodiment 3)
In order to turn on the transistor, a voltage is applied between its gate and source electrodes. Here, when a voltage is continuously applied to the gate electrode of the transistor, charges are trapped in the energy level due to impurities or the like existing in a region between the source electrode or the drain electrode and the gate electrode, and the trapped charges are Since an electric field is formed, the characteristics change with time. In particular, a change occurs in which the threshold voltage shifts (also referred to as threshold shift). This change over time is not only due to the polarity of the voltage that turns on the transistor, but also by applying a reverse polarity voltage (also referred to as reverse bias), the trapped charge is released and the degree of change is reduced. It has been known. The threshold shift is particularly noticeable in a thin film transistor in which amorphous silicon is used for a channel layer having many defect levels in a region between a source electrode or a drain electrode and a gate electrode. Therefore, the shift register circuit according to the present embodiment is particularly effective in a thin film transistor using amorphous silicon for the channel layer. However, the present invention is not limited to this.

In this embodiment mode, an operation for applying a reverse bias to the transistors included in the shift register circuit according to the present invention will be described.

First, FIG. 7 is used to describe a circuit in which a function of applying a reverse bias is added to the shift register circuit shown in FIG. 7A is an overall view of the shift register circuit according to the present invention, FIG. 7B is a circuit 30 for one stage of the shift register circuit according to the present invention, and FIG. It is a time chart of the input signal and output signal of the shift register circuit concerning invention.

FIG. 7B is obtained by adding transistors 39a and 39b, a terminal N, and a terminal S to the circuit shown in FIG. The transistors 31, 32, 35, 36, and 37 and the capacitor 34 correspond to the transistors 11, 12, 15, 16, and 17 and the capacitor 14 in FIG. Same as B). 7B is connected to the terminal S, and one of the source electrode and the drain electrode of the transistor 33 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 33 is connected. Is connected to the terminal P.

Further, the gate electrode of the transistor 37 is connected to the terminal S, one of the source electrode and the drain electrode of the transistor 37 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 37 is connected to the terminal OUT. ing. The gate electrode of the transistor 39a is connected to the terminal S, one of the source electrode and the drain electrode of the transistor 39a is connected to the terminal S, and the other of the source electrode and the drain electrode of the transistor 39a is connected to the terminal N. ing. The gate electrode of the transistor 39b is connected to the terminal N, one of the source electrode and the drain electrode of the transistor 39b is connected to the terminal S, and the other of the source electrode and the drain electrode of the transistor 39b is connected to the terminal R. ing.

7A is obtained by adding signal lines RB connected to the terminals N of the circuits 30 in all stages to the circuit shown in FIG. The transistor 38 corresponds to the transistor 18 in FIG. 1A and has the same connection.

Here, the operation of the circuits shown in FIGS. 7A and 7B will be described with reference to FIG. When a pulse is input to the start pulse terminal SP at time T0, the shift register circuit operates and output signals are output in order from the output terminal L (1). A period until the output signal is output to the output terminal L (n) is referred to as a normal operation period. During the normal operation period, an H-level potential may be input to the signal line RB. At this time, the transistor 39b is on, and the transistor 39a is off. That is, since the terminal R and the terminal S are in a conducting state and the terminal N and the terminal S are in a non-conducting state, (B) in FIG. 7 is in the same connection state as (B) in FIG. The shift register circuit shown in FIG. 6 operates in the same manner as the shift register circuit shown in FIG.

Next, as shown in FIG. 7C, after the output signal is output to the output terminal L (n) of the shift register circuit shown in FIG. 7, the signal line RB is output between time T1 and time T2. The potential may be lowered. This period is referred to as a reverse bias application period. Thus, the transistor 39b in FIG. 7B is turned off and the transistor 39a is turned on. That is, the terminal R and the terminal S are turned off, the terminal N and the terminal S are turned on, and the potential of the terminal S drops. After that, when the potential of the terminal S becomes higher than the potential of the electrode N by the threshold voltage of the transistor 39a, the transistor 39a is turned off and the drop in the potential of the terminal S stops. At this time, the potential of the signal line RB may be lower than that of the power supply line Vss. If the potential on the lower side of the signal line RB is lower than the power supply line Vss, the terminal S can be set to a lower potential during the reverse bias application period. In this way, the transistors 33 and 37 can be applied with a potential having a polarity opposite to that of the ON state to the gate electrode, so that there is an advantage that the threshold shift of the transistor can be reduced.

Here, the transistor 39b is a transistor having a role of making the terminal R and the terminal S conductive during a normal operation period and making the terminal R and the terminal S non-conductive during a reverse bias application period. When the transistor 39b is not provided and the terminal R and the terminal S are always in a conductive state, the circuit scale is reduced, and the parasitic capacitance value connected to the signal line RB is reduced, so that power consumption is reduced. There are advantages.

If the transistor 39b is arranged as shown in FIG. 7B, when the potential of the terminal S is lowered by lowering the potential of the terminal N by the signal line RB, the potential of the terminal R is also lowered at the same time. Can be prevented. Here, a case is considered in which the terminal R and the terminal S are in conduction during the reverse bias application period, and the potential of the terminal R decreases as the potential of the terminal S decreases. Since the terminal R is connected to the terminal F of the circuit 30 in the previous stage through the electrode SR, when the potential of the terminal R drops below the voltage lower than the threshold voltage of the transistor 36 in the previous stage from the power line Vss. The one-stage previous transistor 36 is turned on, and a steady current flows between the signal line RB and the power supply line Vss. Further, since the terminal R is also connected to the transistor 35 of the circuit 30 after the first stage through the electrode SR, when the potential of the terminal R decreases, the transistors 35 and 32 after the first stage are turned on. It is conceivable that a steady current flows through the clock signal line after one stage, the transistor 32, the transistor 35, the transistor 39a at the stage, and the signal line RB. Therefore, the terminal R and the terminal S are made non-conductive during the reverse bias application period, so that it is possible to prevent a current path including the terminal R from being generated due to a decrease in the potential of the terminal R. Sufficient reverse bias can be applied to transistors 33 and 37 while reducing power.

In the present embodiment, an example in which a reverse bias is applied to the gate electrodes of the transistors 33 and 37 during the reverse bias application period has been described. However, the present invention is not limited to this, and to which transistor the reverse bias is applied. Also good. However, the transistors 33 and 37 are in the on state during most of the period during which the output terminal L should output the L level. Thus, a transistor having a large ratio of the on state is a threshold value. The degree of shift is large. Therefore, as shown in FIG. 7B, it is effective to reduce the threshold shift by connecting the transistors 39a and 39b to the gate electrodes of the transistors 33 and 37 and providing a reverse bias application period. preferable.

Next, FIG. 8 shows a circuit obtained by adding a function of applying a reverse bias to the shift register circuit shown in FIG. 8A is an overall view of the shift register circuit according to the present invention, FIG. 8B is a circuit 40 for one stage of the shift register circuit according to the present invention, and FIG. It is another whole figure of the shift register circuit concerning invention.

FIG. 8B is obtained by adding transistors 49a, 49b, 49c, and 49d, a terminal N, a terminal S, and a terminal U to the circuit shown in FIG. The transistors 41, 42, 45, 46, 47b, 47c and the capacitor 44 correspond to the transistors 21, 22, 25, 26, 27b, 27c and the capacitor 24 in FIG. This is the same as (B) of FIG. 8B is connected to the terminal S, one of the source electrode and the drain electrode of the transistor 43 is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 43 is connected. Is connected to the terminal P.

Further, the gate electrode of the transistor 47a is connected to the terminal U, one of the source electrode and the drain electrode of the transistor 47a is connected to the terminal G, and the other of the source electrode and the drain electrode of the transistor 47a is connected to the terminal OUT. ing. The gate electrode of the transistor 49a is connected to the terminal S, one of the source electrode and the drain electrode of the transistor 49a is connected to the terminal S, and the other of the source electrode and the drain electrode of the transistor 49a is connected to the terminal N. ing. Further, the gate electrode of the transistor 49b is connected to the terminal N, one of the source electrode and the drain electrode of the transistor 49b is connected to the terminal R, and the other of the source electrode and the drain electrode of the transistor 49b is connected to the terminal S. ing. Further, the gate electrode of the transistor 49c is connected to the terminal U, one of the source electrode and the drain electrode of the transistor 49c is connected to the terminal U, and the other of the source electrode and the drain electrode of the transistor 49c is connected to the terminal N. ing. The gate electrode of the transistor 49d is connected to the terminal N, one of the source electrode and the drain electrode of the transistor 49d is connected to the terminal Q, and the other of the source electrode and the drain electrode of the transistor 49d is connected to the terminal U. ing.

Here, FIG. 8A is obtained by adding the signal line RB connected to the terminals N of the circuits 40 in all stages to the circuit shown in FIG. The transistor 48 corresponds to the transistor 28 in FIG. 2A and has the same connection. 8C shows a circuit in which the power supply line Vdd is added to the circuit shown in FIG. 8A. The power supply line Vdd is connected to the terminals V of the circuits 40 in all stages. ing.

Here, the circuits shown in FIGS. 8A, 8B, and 8C may be operated in accordance with the time chart shown in FIG. When the circuits shown in FIGS. 8A, 8B, and 8C are operated according to the time chart shown in FIG. 7C, an H level potential is applied to the signal line RB in the normal operation period. You may enter. At this time, the transistors 49b and 49d are on, and the transistors 49a and 49c are off. That is, since the terminal R and the terminal S, and the terminal Q and the terminal U are in a conductive state, and the terminal N and the terminal S, and the terminal N and the terminal U are in a nonconductive state, FIG. Thus, the shift register circuit shown in FIG. 8 operates in the same manner as the shift register circuit shown in FIG.

Next, in the reverse bias application period, the transistors 49b and 49d in FIG. 8B are turned off, and the transistors 49a and 49c are turned on. That is, the terminal R and the terminal S, the terminal Q and the terminal U are in a non-conductive state, the terminal N and the terminal S, and the terminal N and the terminal U are in a conductive state, and the potentials of the terminals S and U drop. After that, when the potential of the terminal S and the terminal U becomes higher than the potential of the electrode N by the threshold voltage of the transistors 49a and 49c, the transistors 49a and 49c are turned off, and the drop in the potentials of the terminals S and U stops. . At this time, the potential of the signal line RB may be lower than that of the power supply line Vss. If the potential on the lower side of the signal line RB is lower than the power supply line Vss, the terminal S and the terminal U can be set to a lower potential during the reverse bias application period. By doing so, the transistor 43 and 47a can be applied with a potential having a polarity opposite to that of the ON state to the gate electrode, so that there is an advantage that threshold shift of the transistor can be reduced.

Here, the transistors 49b and 49d are electrically connected between the terminal R and the terminal S and the terminal Q and the terminal U during the normal operation period, and are disconnected between the terminal R and the terminal S and between the terminal Q and the terminal U during the reverse bias application period. The transistor has the role of When the transistors 49b and 49d are not disposed and the terminals R and S and the terminals Q and U are always in a conductive state, the circuit scale is reduced and the parasitic capacitance value connected to the signal line RB is reduced. Therefore, there is an advantage that power consumption is reduced.

If the transistors 49b and 49d are arranged as shown in FIG. 8B, when the potential of the terminal S and the terminal U is lowered by lowering the potential of the terminal N by the signal line RB, the terminals R and Q Can be prevented from decreasing at the same time.

Here, a case is considered in which the terminal R and the terminal S are in conduction during the reverse bias application period, and the potential of the terminal R decreases as the potential of the terminal S decreases. Since the terminal R is connected to the terminal F of the circuit 40 in the previous stage through the electrode SR, when the potential of the terminal R drops below the voltage lower than the threshold voltage of the transistor 46 in the previous stage from the power line Vss. The transistor 46 in the previous stage is turned on, and a steady current flows between the signal line RB and the power supply line Vss. Further, since the terminal R is also connected to the transistor 45 of the circuit 40 after the first stage through the electrode SR, when the potential of the terminal R decreases, the transistors 45 and 42 after the first stage are turned on. It is conceivable that a steady current flows through the clock signal line after one stage, the transistor 42, the transistor 45, the transistor 49a at the stage concerned, and the signal line RB.

Further, consider a case where the terminal Q and the terminal U are in conduction during the reverse bias application period, and the potential of the terminal Q decreases as the potential of the terminal U decreases. Since the terminal Q is connected to the source electrode or the drain electrode of the transistors 47b and 47c, when the potential of the terminal Q decreases, the transistors 47b and 47c are turned on, and the terminal Q and the transistor 49d, A steady current flows through the terminal U, the transistor 49c, and the terminal N.

Therefore, in the reverse bias application period, the terminal R and the terminal S, and the terminal Q and the terminal U are made non-conductive by the transistors 49b and 49d, so that the potential of the terminal R and the terminal Q is lowered, so that the terminal R and the terminal Q Since a current path including Q can be prevented from being formed, a sufficient reverse bias can be applied to the transistors 43 and 47a while reducing power consumption. Note that both the transistors 49b and 49d may be arranged, or only one of them may be arranged, or both may not be arranged.

In this embodiment, an example is shown in which a reverse bias is applied to the gate electrodes of the transistors 43 and 47a during the reverse bias application period. However, the present invention is not limited to this, and the reverse bias is applied to any transistor. Also good. However, the transistors 43 and 47a are in the on state in most of the period during which the output terminal L should output the L level. Thus, a transistor having a large ratio of the on state is a threshold value. The degree of shift is large. Therefore, as shown in FIG. 8B, the threshold shift is reduced by connecting the transistors 49a and 49b and 49c and 49d to the gate electrodes of the transistors 43 and 47a and providing a reverse bias application period. It is effective and preferable.

As described above, in the present embodiment, transistors 39a, 39b and 49a, 49b, 49c, 49d for applying a reverse bias are connected to the gate electrodes of the transistors 33, 37, 43, and 47a, thereby The threshold shift of 33, 37 and 43, 47a can be reduced. In addition to the circuit described in this embodiment, a reverse bias may be applied to a transistor by connecting the circuit illustrated in FIG. 9 to the gate electrode of any transistor in any circuit. The circuit shown in FIG. 9 does not change the potential of the electrodes in the circuit other than the gate electrode of the transistor, so that a steady-state current does not flow and malfunction does not occur, and the threshold shift of the transistor can be reduced. .

The circuit shown in FIG. 9 includes a signal terminal SIG, a bias terminal BIAS, a target terminal GATE, a cutoff transistor SIG-Tr, and a bias transistor BIAS-Tr. Here, in the circuits shown in FIGS. 9 and 10, the bias transistor BIAS-Tr is used as a rectifying element.

In the circuits shown in FIGS. 9A, 9B, 9C, and 9D, the gate electrode of the cutoff transistor SIG-Tr is connected to the bias terminal BIAS, and the source electrode or drain of the cutoff transistor SIG-Tr. One of the electrodes is connected to the signal terminal SIG, and the other of the source electrode or the drain electrode of the cutoff transistor SIG-Tr is connected to the target terminal GATE.

In the circuits shown in FIGS. 9A and 9D, the gate electrode of the bias transistor BIAS-Tr is connected to the target terminal GATE, and one of the source electrode or the drain electrode of the bias transistor BIAS-Tr is the target terminal GATE. The other of the source electrode and the drain electrode of the bias transistor BIAS-Tr is connected to the bias terminal BIAS.

In the circuits shown in FIGS. 9B and 9C, the gate electrode of the bias transistor BIAS-Tr is connected to the bias terminal BIAS, and one of the source electrode or the drain electrode of the bias transistor BIAS-Tr is the target terminal GATE. The other of the source electrode and the drain electrode of the bias transistor BIAS-Tr is connected to the bias terminal BIAS.

The target terminal GATE is connected to a transistor that applies a reverse bias. Since it is appropriate to apply the reverse bias between the gate electrode and the source electrode of the transistor and between the gate electrode and the drain electrode, the target terminal GATE is the gate of the transistor to which the reverse bias is applied. It is preferable to be connected to an electrode. However, the present invention is not limited to this, and the target terminal GATE may be connected to a source electrode or a drain electrode of a transistor to which reverse bias is applied. In that case, the polarity when the reverse bias is applied may be opposite to that when it is connected to the gate electrode. Any number of transistors may be connected to the target terminal GATE.

The signal terminal SIG is connected to a signal line or a power supply line that is input to the transistor when the transistor is normally operated. The bias terminal BIAS is a signal line for selecting whether to apply a reverse bias to the transistor or to transmit the potential of the electrode connected to the signal terminal SIG to the target terminal GATE.

Here, the circuits shown in (A), (B), (C), and (D) of FIG. 9 are classified according to the polarity of the cutoff transistor SIG-Tr and the polarity of the bias transistor BIAS-Tr, respectively. It is.

9A and 9B are circuits in the case where an H level potential is applied to the bias terminal BIAS during normal operation and an L level potential is applied to the bias terminal BIAS during reverse bias application. For example, it can be used when the electrode to which the reverse bias is applied is the gate electrode of an N-channel transistor.

9C and 9D are circuits in the case where an L level potential is applied to the bias terminal BIAS during normal operation and an H level potential is applied to the bias terminal BIAS during reverse bias application. For example, it can be used when the electrode to which the reverse bias is applied is the gate electrode of a P-channel transistor.
In this manner, with the circuit shown in FIG. 9 in this embodiment, a reverse bias is applied to the gate electrode of an arbitrary transistor in an arbitrary circuit without changing the potential of the other electrode in the circuit. can do.

Next, a circuit in the case where a transistor to which a reverse bias is applied is included in the circuit illustrated in FIG. 9 will be described with reference to FIG.

FIG. 10A shows a circuit including the transistor AC-Tr to which a reverse bias is applied in the circuit shown in FIG. As shown in FIG. 10A, the gate electrode of the transistor AC-Tr may be connected to the target terminal GATE in the circuit shown in FIG. 10B is a circuit including the transistors AC-Tr1 and AC-Tr2 to which a reverse bias is applied in the circuit shown in FIG. 9A. As shown in FIG. 10B, the gate electrodes of the transistors AC-Tr1 and AC-Tr2 may be connected to the target terminal GATE in the circuit shown in FIG.

Here, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are part of a circuit having a function as a whole, such as the transistors 33 and 37 in FIG. 7 or the transistors 43 and 47a in FIG. The circuit for applying the reverse bias according to the present invention does not depend on the connection destination of the source electrode or the drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2. The transistors AC-Tr, AC-Tr1, and AC-Tr2 may be N-channel transistors. Thus, during the period when the H level is input to the bias terminal BIAS, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2, and the bias terminal BIAS is set to the L level. In the input period, a potential depending on the L-level potential is applied to the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2, and a reverse bias can be applied.

10C is a circuit including the transistor AC-Tr to which a reverse bias is applied in addition to the circuit shown in FIG. 9B. As shown in FIG. 10C, the gate electrode of the transistor AC-Tr may be connected to the target terminal GATE in the circuit shown in FIG. 10D is a circuit including the transistors AC-Tr1 and AC-Tr2 to which a reverse bias is applied in the circuit shown in FIG. 9B. As shown in FIG. 10D, the gate electrodes of the transistors AC-Tr1 and AC-Tr2 may be connected to the target terminal GATE in the circuit shown in FIG. Here, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are part of a circuit having a function as a whole, such as the transistors 33 and 37 in FIG. 7 or the transistors 43 and 47a in FIG. The circuit for applying the reverse bias according to the present invention does not depend on the connection destination of the source electrode or the drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2.

The transistors AC-Tr, AC-Tr1, and AC-Tr2 may be N-channel transistors. Thus, during the period when the H level is input to the bias terminal BIAS, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2, and the bias terminal BIAS is set to the L level. In the input period, a potential depending on the L-level potential is applied to the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2, and a reverse bias can be applied.

10E is a circuit including the transistor AC-Tr to which a reverse bias is applied in addition to the circuit shown in FIG. As shown in FIG. 10E, the gate electrode of the transistor AC-Tr may be connected to the target terminal GATE in the circuit shown in FIG. FIG. 10F is a circuit including the transistors AC-Tr1 and AC-Tr2 to which reverse bias is applied in the circuit shown in FIG. 9C. As shown in FIG. 10F, the gate electrodes of the transistors AC-Tr1 and AC-Tr2 may be connected to the target terminal GATE in the circuit shown in FIG.

Here, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are part of a circuit having a function as a whole, such as the transistors 33 and 37 in FIG. 7 or the transistors 43 and 47a in FIG. The circuit for applying the reverse bias according to the present invention does not depend on the connection destination of the source electrode or the drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2.

The transistors AC-Tr, AC-Tr1, and AC-Tr2 may be P-channel transistors. Thus, during the period when the L level is input to the bias terminal BIAS, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2, and the bias terminal BIAS is set to the H level. In the input period, a potential depending on the H level potential is applied to the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2, and a reverse bias can be applied.

FIG. 10G illustrates a circuit in which the transistor AC-Tr to which a reverse bias is applied is included in the circuit illustrated in FIG. As shown in FIG. 10G, the gate electrode of the transistor AC-Tr may be connected to the target terminal GATE in the circuit shown in FIG.

FIG. 10H is a circuit including the transistors AC-Tr1 and AC-Tr2 to which a reverse bias is applied in the circuit shown in FIG. 9D. As shown in FIG. 10H, the gate electrodes of the transistors AC-Tr1 and AC-Tr2 may be connected to the target terminal GATE in the circuit shown in FIG.
Here, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are part of a circuit having a function as a whole, such as the transistors 33 and 37 in FIG. 7 or the transistors 43 and 47a in FIG. The circuit for applying the reverse bias according to the present invention does not depend on the connection destination of the source electrode or the drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2.

The transistors AC-Tr, AC-Tr1, and AC-Tr2 may be P-channel transistors. Thus, during the period when the L level is input to the bias terminal BIAS, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2, and the bias terminal BIAS is set to the H level. In the input period, a potential depending on the H level potential is applied to the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2, and a reverse bias can be applied.

Next, referring to FIG. 11 and FIG. 12, the reset operation is performed on the circuits to which the reverse bias shown in FIG. 7A, FIG. 8A, and FIG. 8C can be applied. A shift register circuit according to the present invention, in which a dedicated signal line is added to achieve the above, will be described.

(A), (B), and (C) in FIG. 11 are dedicated to resetting the configuration shown in (A), FIG. 8 (A), and FIG. 8 (C), respectively. The signal line RES and a transistor RE (k) connected to the signal line RES (k is an integer of 1 to n) are added. The gate electrode of the transistor RE (k) is connected to the signal line RES, and one of the source electrode or drain electrode of the transistor RE (k) is connected to the signal line RES, and the source electrode or drain electrode of the transistor RE (k). Is connected to the electrode SR (k).

In FIG. 11, by adding and connecting the transistors RE (k) to all the stages, all the stages are reset at an arbitrary timing and immediately returned to the initial state without operating to the final stage. However, the present invention is not limited to this, and the number of transistors RE (k) may be any number. For example, the transistor RE may be provided only in the final stage, the transistor RE may be provided only in the odd or even stages, or the transistor RE may be provided only in the first half or the second half. If the number of transistors RE is reduced, there is an advantage that the circuit scale is reduced accordingly and the proportion of the circuit on the substrate is reduced. Further, if the number of transistors RE is reduced, there is an advantage that the load for driving the signal line RES is reduced and the power consumption can be reduced.

Here, the operation of the shift register circuit according to the present invention, in which a dedicated signal line is added to perform the reset operation, will be described with reference to FIG. FIG. 12 shows an input signal when a pulse is input to the signal line RES at time T1 to reset all the stages, and the potential of the signal line RB is lowered at time T2 to perform reverse bias application operation. 4 is a time chart showing changes in potentials of SP, terminal P (not shown), and output terminal L. When a start pulse is input at time T0, the same operation as in FIG. 1C is performed until a pulse is input to the signal line RES. However, when a pulse is input to the signal line RES at time T1, the potential of the electrode SR becomes H level in all stages, so that the terminal P and the output terminal L are fixed to L level. Here, the transistor 36 or 46 that sets the potential of the electrode SR to the L level is turned off because the potential of the terminal P becomes the L level. Therefore, when a pulse is input to the signal line RES, there is no path through which a current flows from the signal line RES to the power supply line Vss.

Thereafter, during the period from time T2 to T3, the reverse bias can be applied by lowering the potential of the signal line RB. At this time, the potential of the signal line RB is preferably lower than the potential of the power supply line Vss. Thereafter, the potentials of the signal line RB and the signal line RES may be set to the H level in order to perform the reset operation again during the period from the time T3 to the time T4. By performing the reset operation again after applying the reverse bias, the potential of the terminal S, the terminal R, and the electrode SR is set to the H level, so that the potential of the output terminal L is fixed to the L level, and the output potential fluctuation is changed. The period to suppress can be extended.

As described above, the shift register circuit according to the present invention, in which a dedicated signal line is added to perform the reset operation illustrated in FIG. 11, resets all the stages at an arbitrary timing and operates to the final stage. Thus, it is possible to immediately return to the initial state and apply a reverse bias at an arbitrary timing. When this shift register circuit is used as a drive circuit for a display device, for example, when only a part of the pixels arranged in the display area is used, the operation of the shift register circuit is stopped halfway, There is an advantage that a pixel in an unused region is not driven, power consumption can be reduced, and a threshold shift of the transistor can be reduced. In addition, when a pulse is input to the signal line RES, charges are injected into the electrode SR that is in a floating state, so that a decrease in the potential of the electrode SR due to a leakage current can be prevented. That is, there is an effect that it becomes easy for the transistor in which the gate electrode is connected to the electrode SR to keep the on state.

Next, by using FIG. 13, not only the reverse bias application operation but also the reset operation can be performed by adding one signal line to the shift register circuit shown in FIG. 7 that can apply the reverse bias. The circuit will be described.

13A is an overall view of the shift register circuit according to the present invention, FIG. 13B is a circuit 50 for one stage of the shift register circuit according to the present invention, and FIG. It is a time chart of the input signal and output signal of the shift register circuit concerning invention.

13B is obtained by changing the connection of the transistor 59a and adding a terminal M to the circuit shown in FIG. 7B. Here, the transistors 51, 52, 53, 55, 56, 57, 59b and the capacitor 54 are respectively connected to the transistors 31, 32, 33, 35, 36, 37, 39b and the capacitor 34 in FIG. Correspondingly, the connection is the same as in FIG. 13B, the gate electrode of the transistor 59a in FIG. 13B is connected to the terminal M, and one of the source electrode or the drain electrode of the transistor 59a is connected to the terminal S, and the source electrode or the transistor 59a The other of the drain electrodes is connected to the terminal N.

In FIG. 13A, the signal line RB in the circuit shown in FIG. 7A is used as a signal line BL, and the signal line BE connected to the terminals M of the circuits 50 in all stages is added. It is. The transistor 58 corresponds to the transistor 38 in FIG. 7A and has the same connection.

Here, the operation of the circuits shown in FIGS. 13A and 13B will be described with reference to FIG. During a normal operation period, an H level potential may be input to the signal line BL, and an L level potential may be input to the signal line BE. At this time, the transistor 59b is on, and the transistor 59a is off. That is, since the terminal R and the terminal S are in a conducting state and the terminal N and the terminal S are in a non-conducting state, FIG. 13B is in the same connection state as FIG. The shift register circuit shown in FIG. 6 operates in the same manner as the shift register circuit shown in FIG.

Next, as illustrated in FIG. 13C, the potential of the signal line BE may be increased between time T1 and time T4 after the normal operation period of the shift register circuit illustrated in FIG. 13 ends. This period is called a bias enable period. In the bias enable period, the transistor 59a is on. A period (time T1 to T2, T3 to T4) in which the potential of the signal line BL is at the H level during the bias enable period is referred to as a reset period. In the reset period, the transistors 59a and 59b are in the on state and the potential of the terminal N is at the H level. Therefore, the potentials of the terminals S and R and the electrode SR connected to the terminal R are Becomes H level. That is, a reset operation can be performed. Further, during the bias enable period, a period (time T2 to T3) in which the potential of the signal line BL is at the L level is a reverse bias application period. In the reverse bias application period, the transistor 59b in FIG. 13B is turned off and the transistor 59a is turned on. That is, the terminal R and the terminal S are in a non-conductive state, the terminal N and the terminal S are in a conductive state, and the potential of the terminal S becomes L level according to the potential of the electrode N. At this time, since the transistor 59b is in a non-conductive state, the potential of the terminal N is not transmitted to the terminal R. Here, the potential of the signal line BL may be lower than that of the power supply line Vss. If the lower potential of the signal line BL is lower than the power supply line Vss, the terminal S can be set to a lower potential during the reverse bias application period. By doing so, a potential having an opposite polarity to the on state can be applied to the transistors 53 and 57 to the gate electrode, so that the threshold shift of the transistor can be reduced.

As described above, the shift register circuit according to the present invention shown in FIG. 13 can arbitrarily set the normal operation period and the bias enable period by the signal line BE. In the bias enable period, if the potential of the signal line BL is at the H level, the circuit 50 can be reset, and if the potential of the signal line BL is at the L level, a reverse bias is applied to the transistors 53 and 57. In addition, even if the potential of the signal line BL is lowered, the potentials of the electrodes other than the terminal S are not changed, so that there are few problems such as a steady current flowing or malfunction. Note that the potential applied to the terminal S can be freely set in the bias enable period.

Next, referring to FIG. 14, not only the reverse bias application operation but also the reset operation can be performed by adding one signal line to the shift register circuit shown in FIG. 8 to which the reverse bias can be applied. The circuit will be described.

14A is an overall view of the shift register circuit according to the present invention, FIG. 14B is a circuit 60 for one stage of the shift register circuit according to the present invention, and FIG. It is another whole figure of the shift register circuit concerning invention. 14B is obtained by changing the connections of the transistors 69a and 69c and adding a terminal M to the circuit shown in FIG. 8B. In addition, the transistors 61, 62, 63, 65, 66, 67a, 67b, 67c, 69b, 69d, and the capacitor 64 are the transistors 41, 42, 43, 45, 46, 47a, FIG. Corresponding to 47b, 47c, 49b, 49d and the capacitor 44, the connection is the same as in FIG.

14B is connected to the terminal M, one of the source electrode and the drain electrode of the transistor 69a is connected to the terminal S, and the other of the source electrode and the drain electrode of the transistor 69a. Is connected to a terminal N. The gate electrode of the transistor 69c is connected to the terminal M, one of the source electrode and the drain electrode of the transistor 69c is connected to the terminal U, and the other of the source electrode and the drain electrode of the transistor 69c is connected to the terminal N. ing.

Here, FIG. 14A is obtained by adding signal lines RB connected to the terminals N of the circuits 40 in all stages to the circuit shown in FIG. The transistor 68 corresponds to the transistor 48 in FIG. 8A and has the same connection. 14C shows a circuit in which the power supply line Vdd is added to the circuit shown in FIG. 14A, and the power supply line Vdd is connected to the terminals V of the circuits 60 in all stages. ing.

Here, the circuits shown in FIGS. 14A, 14B, and 14C may be operated in accordance with the time chart shown in FIG. In the case where the circuit shown in FIGS. 14A, 14B, and 14C is operated in accordance with the time chart shown in FIG. 13C, in the normal operation period, the H level potential and the signal are applied to the signal line BL. An L level potential may be input to the line BE. At this time, the transistors 69b and 69d are on, and the transistors 69a and 69c are off. That is, since the terminal R and the terminal S, and the terminal Q and the terminal U are in a conductive state, and the terminal N and the terminal S, and the terminal N and the terminal U are in a nonconductive state, FIG. 14B, the shift register circuit shown in FIG. 14 operates in the same manner as the shift register circuit shown in FIG.

Next, in the bias enable period, the potential of the signal line BL is raised to H level to be a reset period, and the potential of the signal line BL is lowered to L level to apply reverse bias. It can be a period. In the reset period, the transistors 69a, 69b, 69c, and 69d are all turned on, and the terminal N is at the H level. Therefore, the circuit 60 performs a reset operation. On the other hand, in the reverse bias application period, the transistors 69b and 69d in FIG. 14B are turned off, and the transistors 69a and 69c are turned on. That is, the terminal R and the terminal S, and the terminal Q and the terminal U are in a non-conductive state, the terminal N and the terminal S, and the terminal N and the terminal U are in a conductive state, and the potential of the terminal N is low. And the electric potential of the terminal U becomes low. At this time, the potential of the signal line BL may be lower than that of the power supply line Vss. If the potential on the lower side of the signal line BL is lower than the power supply line Vss, the terminal S and the terminal U can be set to a lower potential during the reverse bias application period. Thus, a potential having a polarity opposite to that of the on state can be applied to the transistors 63 and 67a to the gate electrode, so that the threshold shift of the transistor can be reduced.

As described above, the shift register circuit according to the present invention shown in FIG. 14 can arbitrarily set the normal operation period and the bias enable period by the signal line BE. In the bias enable period, if the potential of the signal line BL is H level, the circuit 60 can be reset, and if the potential of the signal line BL is L level, a reverse bias is applied to the transistors 63 and 67a. In addition, even if the potential of the signal line BL is lowered, the potentials of the electrodes other than the terminal S and the terminal U are not changed, so that there are few problems such as a steady current flowing or malfunction. Note that the potential applied to the terminal S and the terminal U can be freely set in the bias enable period.

Here, not only the circuit shown in FIG. 13 and FIG. 14 but also the circuit shown in FIG. 15 is connected to the gate electrode of an arbitrary transistor in an arbitrary circuit. A forward bias may be applied. With the circuit shown in FIG. 15, when a reverse bias is applied, the potentials of the electrodes in the circuit other than the gate electrode of the transistor are not changed, so that a steady current flows and no malfunction occurs. Can be reduced. When the forward bias is applied, the cutoff transistor SIG-Tr is turned on, whereby the potential of the signal terminal SIG and the electrode connected to the signal terminal SIG can be initialized or reset.

The circuit shown in FIG. 15 includes a signal terminal SIG, a bias terminal BIAS, a target terminal GATE, a cutoff transistor SIG-Tr, and a bias transistor BIAS-Tr. In the circuits shown in FIGS. 15A, 15B, 15C, and 15D, the gate electrode of the cutoff transistor SIG-Tr is connected to the bias terminal BIAS, and the source electrode or drain of the cutoff transistor SIG-Tr. One of the electrodes is connected to the signal terminal SIG, and the other of the source electrode or the drain electrode of the cutoff transistor SIG-Tr is connected to the target terminal GATE.

In the circuits shown in FIGS. 15A, 15B, 15C, and 15D, the gate electrode of the bias transistor BIAS-Tr is connected to the selection terminal BE-SW, and the source electrode of the bias transistor BIAS-Tr. Alternatively, one of the drain electrodes is connected to the target terminal GATE, and the other of the source electrode and the drain electrode of the bias transistor BIAS-Tr is connected to the bias terminal BIAS.

The target terminal GATE is connected to a transistor that applies a reverse bias. Since it is appropriate to apply the reverse bias between the gate electrode and the source electrode of the transistor and between the gate electrode and the drain electrode, the target terminal GATE is the gate of the transistor to which the reverse bias is applied. It is preferable to be connected to an electrode. However, the present invention is not limited to this, and the target terminal GATE may be connected to a source electrode or a drain electrode of a transistor to which reverse bias is applied. In that case, the polarity when the reverse bias is applied may be opposite to that when it is connected to the gate electrode. Any number of transistors may be connected to the target terminal GATE.

The signal terminal SIG is connected to a signal line or a power supply line that is input to the transistor when the transistor is normally operated. The selection terminal BE-SW is a signal line for selecting whether to transmit the potential of the bias terminal BIAS to the target terminal GATE. The bias terminal BIAS is a signal line that controls a potential applied to an electrode connected to the target terminal GATE when the bias transistor BIAS-Tr is in an on state. When the bias transistor BIAS-Tr is in the OFF state, the signal line controls whether or not the signal terminal SIG and the target terminal GATE are made conductive.

Here, the circuits shown in FIGS. 15A, 15B, 15C, and 15D are divided into cases with respect to the polarity of the cutoff transistor SIG-Tr and the polarity of the bias transistor BIAS-Tr, respectively. It is.

FIG. 15A shows an H level potential applied to the bias terminal BIAS and an L level potential applied to the selection terminal BE-SW during a normal operation, and an H level potential applied to the bias terminal BIAS and a selection terminal BE during a reset operation. In this circuit, an H level potential is applied to -SW, and an L level potential is applied to the bias terminal BIAS and an H level potential is applied to the selection terminal BE-SW when a reverse bias is applied. For example, it can be used when the electrode to which the reverse bias is applied is the gate electrode of an N-channel transistor.

FIG. 15B shows that during normal operation, an H level potential is applied to the bias terminal BIAS and an H level potential is applied to the selection terminal BE-SW, and during the reset operation, an H level potential is applied to the bias terminal BIAS and the selection terminal BE. In this circuit, an L level potential is applied to -SW, and an L level potential is applied to the bias terminal BIAS and an L level potential is applied to the selection terminal BE-SW when a reverse bias is applied. For example, it can be used when the electrode to which the reverse bias is applied is the gate electrode of an N-channel transistor.

FIG. 15C shows an L level potential applied to the bias terminal BIAS and an L level potential applied to the selection terminal BE-SW during normal operation, and an L level potential applied to the bias terminal BIAS and a selection terminal BE during reset operation. This is a circuit in which an H level potential is applied to -SW, an H level potential is applied to the bias terminal BIAS when a reverse bias is applied, and an H level potential is applied to the selection terminal BE-SW. For example, it can be used when the electrode to which the reverse bias is applied is the gate electrode of a P-channel transistor.

FIG. 15D shows an L level potential applied to the bias terminal BIAS and an H level potential to the selection terminal BE-SW during a normal operation, and an L level potential applied to the bias terminal BIAS and a selection terminal BE during a reset operation. In this circuit, an L level potential is applied to -SW, an H level potential is applied to the bias terminal BIAS when a reverse bias is applied, and an L level potential is applied to the selection terminal BE-SW. For example, it can be used when the electrode to which the reverse bias is applied is the gate electrode of a P-channel transistor.

In this manner, with the circuit shown in FIG. 15 in this embodiment, a reverse bias is applied to the gate electrode of an arbitrary transistor in an arbitrary circuit without changing the potential of the other electrode in the circuit. In addition, a forward bias can be applied to both the signal terminal SIG and the target terminal GATE.

Next, a circuit in the case where a transistor to which a reverse bias is applied is included in the circuit illustrated in FIG. 15 will be described with reference to FIG.

FIG. 16A shows a circuit in which the circuit shown in FIG. 15A includes a transistor AC-Tr to which a reverse bias is applied. As shown in FIG. 16A, the gate electrode of the transistor AC-Tr may be connected to the target terminal GATE in the circuit shown in FIG. FIG. 16B is a circuit including the transistors AC-Tr1 and AC-Tr2 to which a reverse bias is applied in the circuit shown in FIG. As shown in FIG. 16B, the gate electrodes of the transistors AC-Tr1 and AC-Tr2 may be connected to the target terminal GATE in the circuit shown in FIG.

Here, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are part of a circuit having a function as a whole, such as the transistors 53 and 57 in FIG. 13 or the transistors 63 and 67a in FIG. The circuit for applying the reverse bias according to the present invention does not depend on the connection destination of the source electrode or the drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2.

The transistors AC-Tr, AC-Tr1, and AC-Tr2 may be N-channel transistors. In this way, during the period when the H level is input to the bias terminal BIAS and the L level is input to the selection terminal BE-SW, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2. In the period when the L level is input to the bias terminal BIAS and the H level is input to the selection terminal BE-SW, the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2 depend on the L level potential of the bias terminal BIAS. The reverse bias can be applied by applying the potential to be applied, and during the period when the H level is input to the bias terminal BIAS and the H level is input to the selection terminal BE-SW, the transistors AC-Tr, AC-Tr1, and AC-Tr2 Applying a potential depending on the H level potential of the bias terminal BIAS to the gate electrode It can be.

FIG. 16C is a circuit including the transistor AC-Tr to which a reverse bias is applied in addition to the circuit shown in FIG. As shown in FIG. 16C, the gate electrode of the transistor AC-Tr may be connected to the target terminal GATE in the circuit shown in FIG.

FIG. 16D is a circuit including the transistors AC-Tr1 and AC-Tr2 to which a reverse bias is applied in the circuit shown in FIG. As shown in FIG. 16D, the gate electrodes of the transistors AC-Tr1 and AC-Tr2 may be connected to the target terminal GATE in the circuit shown in FIG.
Here, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are part of a circuit having a function as a whole, such as the transistors 53 and 57 in FIG. 13 or the transistors 63 and 67a in FIG. The circuit for applying the reverse bias according to the present invention does not depend on the connection destination of the source electrode or the drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2.

The transistors AC-Tr, AC-Tr1, and AC-Tr2 may be N-channel transistors. Thus, during the period when the H level is input to the bias terminal BIAS and the H level is input to the selection terminal BE-SW, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2. During the period when the L level is input to the bias terminal BIAS and the L level is input to the selection terminal BE-SW, the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2 depend on the L level potential of the bias terminal BIAS. The reverse bias can be applied by applying the potential to be applied, and during the period when the H level is input to the bias terminal BIAS and the L level is input to the selection terminal BE-SW, the transistors AC-Tr, AC-Tr1, and AC-Tr2 Applying a potential depending on the H level potential of the bias terminal BIAS to the gate electrode It can be.

FIG. 16E illustrates a circuit including the transistor AC-Tr to which a reverse bias is applied in addition to the circuit illustrated in FIG. As shown in FIG. 16E, the gate electrode of the transistor AC-Tr may be connected to the target terminal GATE in the circuit shown in FIG.

FIG. 16F is a circuit including the transistors AC-Tr1 and AC-Tr2 to which a reverse bias is applied in the circuit shown in FIG. As shown in FIG. 16F, the gate electrodes of the transistors AC-Tr1 and AC-Tr2 may be connected to the target terminal GATE in the circuit shown in FIG.

Here, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are part of a circuit having a function as a whole, such as the transistors 53 and 57 in FIG. 13 or the transistors 63 and 67a in FIG. The circuit for applying the reverse bias according to the present invention does not depend on the connection destination of the source electrode or the drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2.

The transistors AC-Tr, AC-Tr1, and AC-Tr2 may be P-channel transistors. In this way, during the period when the L level is input to the bias terminal BIAS and the L level is input to the selection terminal BE-SW, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2. In the period in which the H level is input to the bias terminal BIAS and the H level is input to the selection terminal BE-SW, the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2 depend on the H level potential of the bias terminal BIAS. The reverse bias can be applied by applying the potential to be applied, and during the period when the L level is input to the bias terminal BIAS and the H level is input to the selection terminal BE-SW, the transistors AC-Tr, AC-Tr1, and AC-Tr2 Applying a potential depending on the L level potential of the bias terminal BIAS to the gate electrode It can be.

FIG. 16G illustrates a circuit in which the transistor AC-Tr to which a reverse bias is applied is included in the circuit illustrated in FIG. As shown in FIG. 16G, the gate electrode of the transistor AC-Tr may be connected to the target terminal GATE in the circuit shown in FIG.

FIG. 16H is a circuit including the transistors AC-Tr1 and AC-Tr2 to which a reverse bias is applied in the circuit shown in FIG. As shown in FIG. 16H, the gate electrodes of the transistors AC-Tr1 and AC-Tr2 may be connected to the target terminal GATE in the circuit shown in FIG. Here, the transistors AC-Tr, AC-Tr1, and AC-Tr2 are part of a circuit having a function as a whole, such as the transistors 53 and 57 in FIG. 13 or the transistors 63 and 67a in FIG. The circuit for applying the reverse bias according to the present invention does not depend on the connection destination of the source electrode or the drain electrode of the transistors AC-Tr, AC-Tr1, and AC-Tr2.

The transistors AC-Tr, AC-Tr1, and AC-Tr2 may be P-channel transistors. In this way, during the period when the L level is input to the bias terminal BIAS and the H level is input to the selection terminal BE-SW, the signal input to the signal terminal SIG is input to the transistors AC-Tr, AC-Tr1, and AC-Tr2. In the period in which the H level is input to the bias terminal BIAS and the L level is input to the selection terminal BE-SW, the gate electrodes of the transistors AC-Tr, AC-Tr1, and AC-Tr2 depend on the H level potential of the bias terminal BIAS. The reverse bias can be applied by applying the potential to be applied. During the period when the L level is input to the bias terminal BIAS and the L level is input to the selection terminal BE-SW, the transistors AC-Tr, AC-Tr1, and AC-Tr2 Applying a potential depending on the L level potential of the bias terminal BIAS to the gate electrode It can be.

Note that this embodiment can be freely combined with any of the other embodiments.

(Embodiment 4)
In this embodiment mode, a top view and a cross-sectional view when an element is formed over a substrate and a shift register circuit according to the present invention is formed will be described with reference to the drawings. FIG. 17 is an example of a top view when a circuit 10 is configured as a shift register circuit according to the present invention when a top gate transistor is used as a transistor. In FIG. 17, only the k-th stage circuit 10 and the (k + 1) -th stage circuit 10 are shown for the sake of explanation, but the present invention is not limited to this, and the circuit 10 may be composed of any number of stages. good. In addition, the transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 17 are the transistors 11, 12, 13, 15, 16, 17, and the capacitor element in FIG. 14 and terminal P, respectively. Further, in FIG. 1, the electrode SR and the output terminal L arranged outside the circuit 10 are arranged inside the circuit 10 in FIG. 17 in order to reduce the layout area. Note that in the top view referred to in this embodiment, a region represented by a broken line represents a region in which another layer is present above the region.

In FIG. 17, the power supply line Vss, the first clock signal line CLK <b> 1, and the second clock signal line CLK <b> 2 are configured by a wiring layer, and may be provided substantially in parallel with the extending direction of the circuit 10. In this way, when a plurality of the circuits 10 are extended, the wiring resistance increases due to an increase in the wiring routing distance, and it is possible to suppress an increase in malfunction and power consumption due to a voltage drop in the power supply line. In addition, it is possible to suppress the occurrence of malfunction due to the rounding of the signal waveform in the signal line and the reduction of the voltage range in which the signal operates normally.

Further, the power supply line Vss, the first clock signal line CLK1 and the second clock signal line CLK2 may be provided outside the elements constituting the circuit 10. The power supply line Vss may be provided on the side opposite to the first clock signal line CLK1 and the second clock signal line CLK2. By doing so, it is possible to avoid the occurrence of a region where the power supply line Vss intersects the first clock signal line CLK1 and the second clock signal line CLK2, and thus noise from the clock signal line is applied to the power supply line. Can be prevented, and malfunction becomes difficult.

Here, in this embodiment, a region where the active layer region of the transistor overlaps with the gate electrode region is also referred to as a channel region. Of the active layers of the transistor, one of the regions divided by the channel region is referred to as one of the source electrode or the drain electrode, and the other of the regions divided by the channel region is the source electrode or the drain electrode. Of the other. A tangential direction of a boundary line between one or the other of the source electrode or the drain electrode of the transistor and the channel region of the transistor is referred to as a channel width direction. A direction perpendicular to the channel width direction is referred to as a channel length direction. For example, in one transistor in this embodiment, when the boundary line between one or the other of the source electrode or the drain electrode of the transistor and the channel region of the transistor is a curve, at each point on the boundary line The channel width direction and the channel length direction may be different.

In FIG. 17, the channel length direction of the transistor 11 and the channel length direction of the transistor 12 may be substantially perpendicular. Thus, the area occupied by the transistors 11 and 12 on the substrate can be reduced, and the circuit scale can be reduced.

Further, the channel length directions of the transistors 13 and 16 may be substantially parallel, and one of the source electrode and the drain electrode may be common. Thus, the area occupied by the transistors 13 and 16 on the substrate can be reduced, and the circuit scale can be reduced. The channel length directions of the transistors 15 and 17 may be substantially parallel, and one of the source electrode and the drain electrode may be common. Thus, the area occupied by the transistors 15 and 17 on the substrate can be reduced, and the circuit scale can be reduced.

Further, in the capacitor element 14, the terminal P that is one electrode may be formed by a gate electrode, and the electrode connected to the output terminal L that is the other electrode may be formed by a wiring layer. Further, when the polarity of the transistor is an N-channel type, the wiring layer connected to the output terminal L and the active layer are connected, and the gate electrode in which the terminal P is formed by the active layer and the wiring layer is sandwiched. The capacitor element 14 may be formed by the following. If the terminal P is formed of a gate electrode, carriers are generated in the active layer connected to the output terminal L when the terminal P is at a high potential. Therefore, the capacitance of the capacitor 14 formed of the active layer and the gate electrode The value can be increased.

Next, the case where a thin film transistor is used as a transistor in a cross section taken along a line connecting points A and A ′ in FIG. 17 will be described with reference to FIGS. The structure shown in FIG. 18 includes a substrate 100, a base film 101, an active layer 102, an insulating film 103, gate electrodes 104 and 105, an interlayer film 106, and a wiring layer 108. 18 includes contacts 107 a and 107 b that connect the wiring layer 108 and the active layer 102 and contacts 107 c that connect the wiring layer 108 and the gate electrode 104. The structure shown in FIG. 18 will be described in order.

First, the substrate 100 may be a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate. Further, the substrate 100 may be polished by a CMP method or the like so that the surface of the substrate 100 is planarized.

Next, the base film 101 may be formed over the substrate 100. The base film 101 is formed of a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiOxNy) by a known method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. It may be formed by stacking. Note that the formation of the base film 101 has an effect of blocking contaminants and the like from the substrate 100. When the base film 101 is not formed, the manufacturing process is simplified, so that the cost can be reduced.

Next, the active layer 102 may be formed on the substrate 100 or the base film 101. Here, the active layer 102 may be polysilicon (p-Si). The active layer 102 may be selectively formed in a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

Next, the insulating film 103 may be formed over the substrate 100, the base film 101, or the active layer 102. Here, the insulating film 103 may be formed of silicon oxide (SiO ₂ ) or silicon oxynitride (SiOxNy).

Next, gate electrodes 104 and 105 may be formed on the substrate 100, the base film 101, the active layer 102, or the insulating film 103. Here, the gate electrodes 104 and 105 are formed in a desired shape by photolithography, a droplet discharge method, a printing method, or the like, and may be formed of different types of metals. Thus, when processing is performed by etching the gate electrodes 104 and 105 by photolithography or the like, etching is performed so that the gate electrodes 104 and 105 can have an etching selectivity without adding a photomask. The gate electrode 104 and the gate electrode 105 can be formed to have different areas. In this way, when the active layer 102 is doped with charged particles to control the conductivity of the active layer 102, an LDD region can be formed in the active layer 102 without adding a photomask. A transistor in which an electric field is hardly applied and hot carrier deterioration is small can be manufactured.

Next, an interlayer film 106 may be formed on the substrate 100, the base film 101, the active layer 102, the insulating film 103, or the gate electrodes 104 and 105. Here, the interlayer film 106 is formed of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or other inorganic insulating materials, or acrylic acid, methacrylic acid and derivatives thereof, or polyimide. , An aromatic polyamide, a heat-resistant polymer such as polybenzimidazole, or an insulating material such as a siloxane resin. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. When a photosensitive or non-photosensitive material such as acrylic or polyimide is used, the side surface has a shape in which the curvature radius changes continuously, and the upper thin film is formed without being cut off. The interlayer film 106 may be formed in a desired shape by photolithography, a droplet discharge method, a printing method, or the like. Here, when etching the interlayer film 106, on the one hand, the etching stops at the gate electrodes 104 and 105 as in the contact 107c, and on the other hand, the insulating film 103 is also processed as in the contacts 107a and 107b. May be. Thus, the wiring layer 108 can be formed and the active layer 102 and the gate electrodes 104 and 105 can be connected.

A wiring layer 108 may be formed on the substrate 100, the base film 101, the active layer 102, the insulating film 103, the gate electrodes 104 and 105, or the interlayer film 106. Here, as a conductive material for forming the wiring layer 108, a composition mainly composed of metal particles such as Ag (silver), Au (gold), Cu (copper), W (tungsten), and Al (aluminum). Can be used. Further, light-transmitting indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like may be combined. The wiring layer 108 may be formed in a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

Next, FIG. 19 is a top view of the circuit 10 when the shapes of the transistors 13 and 17 are devised to hold the potential of the electrode SR at the H level in order to fix the potential of the terminal P and the output terminal L. The description will be given with reference. The top view of the circuit 10 shown in FIG. 19 includes transistors 11, 12, 13, 15, 16, and 17 and a capacitor element 14 as well as FIG. The areas of are different. Thus, by making the average area of the gate electrodes of the transistors 13 and 17 larger than the area of the gate electrode of the transistor 12 of the circuit 10, the value of the parasitic capacitance associated with the electrode SR can be increased. This is preferable because the potential of the electrode SR can be held at the H level even after the reset operation.
In addition, as shown in FIG. 19, the electrode SR may be bent in the circuit 10 while avoiding the shape of the electrode SR to be a straight line. In this way, the length of routing the electrode SR can be made longer than the pitch between the k-th stage circuit 10 and the (k + 1) -th stage circuit 10, and the parasitic capacitance associated with the electrode SR can be increased. This is preferable because the potential of the electrode SR can be held at the H level even after the reset operation.

Next, with reference to FIG. 20, a top view when the cross capacitance between the clock signal line and the output terminal L is eliminated so that the output terminal L is not affected by the potential change of the clock signal line as much as possible. explain. The top view of the circuit 10 shown in FIG. 20 includes transistors 11, 12, 13, 15, 16, 17, a capacitor element 14, a terminal P, an electrode SR, and an output terminal L, as in FIGS. 17 and 19. However, the arrangement of the first clock signal line CLK1, the second clock signal line CLK2, and the transistors 11 and 12 is different from that in FIGS.

In FIG. 20, the power supply line Vss, the first clock signal line CLK <b> 1, and the second clock signal line CLK <b> 2 are configured by a wiring layer, and may be provided substantially parallel to the extending direction of the circuit 10. In this way, even when a plurality of circuits 10 are extended, the wiring resistance increases as the wiring routing distance increases, and malfunctions due to voltage drop in the power supply line and an increase in power consumption can be suppressed. In addition, it is possible to suppress the occurrence of malfunction due to the rounding of the signal waveform in the signal line and the reduction of the voltage range in which the signal operates normally.

Further, the power supply line Vss, the first clock signal line CLK1 and the second clock signal line CLK2 may be provided outside the elements constituting the circuit 10. The power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are provided on the same side, and the first transistor, the third transistor, the second transistor, and the fourth transistor The transistor may be provided on the opposite side of the output terminal L side. By doing so, it is possible to avoid the occurrence of a region where the output terminal L intersects with the first clock signal line CLK1 and the second clock signal line CLK2, so that the noise of the clock signal line gets on the power supply line. Can be prevented, and malfunction becomes difficult.

Further, the channel length direction of the transistor 11 and the channel length direction of the transistor 12 may be substantially parallel. By doing so, the area occupied by the transistors 11 and 12 on the substrate can be reduced while avoiding a region where the output terminal L intersects with the first clock signal line CLK1 and the second clock signal line CLK2. And the circuit scale can be reduced.

Next, a top view of the shift register circuit according to the present invention in the case where a bottom gate type transistor is used as a transistor and the active layer is processed into a desired shape using the wiring layer as a mask will be described with reference to FIG. explain. In FIG. 21, only the k-th stage circuit 10 and the (k + 1) -th stage circuit 10 are shown for explanation, but the present invention is not limited to this, and the circuit 10 may have any number of stages. good. Further, the transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 21 are the transistors 11, 12, 13, 15, 16, 17, and the capacitor element in FIG. 14 and terminal P, respectively. Further, in FIG. 1, the electrode SR and the output terminal L arranged outside the circuit 10 are arranged inside the circuit 10 in FIG. 21 in order to reduce the layout area. Note that in the top view referred to in this embodiment, a region represented by a broken line represents a region in which another layer is present above the region.

Next, with reference to FIGS. 22A and 22B, a thin film transistor is used for the cross section taken along the line connecting points a and a ′ and b and b ′ in FIG. I will explain. The structure shown in FIGS. 22A and 22B includes a substrate 110, a base film 111, a first wiring layer 112, an insulating film 113, active layers 114 and 115, a second wiring layer 116, An interlayer film 117 and a third wiring layer 119 are provided. 22A and 22B, the contact 118a connecting the third wiring layer 119 and the second wiring layer 116 and the contact 118b connecting the third wiring layer 119 and the first wiring layer 112 are used. Is provided.
The structures shown in FIGS. 22A and 22B will be described in order.

First, the substrate 110 may be a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate. Further, the substrate 110 may be polished by a CMP method or the like so that the surface of the substrate 110 is planarized.

Next, a base film 111 may be formed on the substrate 110. The base film 111 is formed of a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiOxNy), or the like by a known method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. It may be formed by stacking. Note that the formation of the base film 111 has an effect of blocking contaminants and the like from the substrate 110. When the base film 111 is not formed, the manufacturing process is simplified, so that the cost can be reduced.

Next, the first wiring layer 112 may be formed on the substrate 110 or the base film 111. Here, the first wiring layer 112 may be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

Next, an insulating film 113 may be formed on the substrate 110, the base film 111, or the first wiring layer 112. Here, the insulating film 113 may be formed of silicon oxide (SiO ₂ ) or silicon oxynitride (SiOxNy).

Next, active layers 114 and 115 may be formed on the substrate 110, the base film 111, the first wiring layer 112, or the insulating film 113. Here, the active layers 114 and 115 may be amorphous silicon (a-Si), and the active layers 114 and 115 may be continuously formed in the same film forming apparatus. 115 may have a higher conductivity than 114. Note that the channel region, that is, the region in the vicinity of the surface where the active layer 114 is in contact with the insulating film 113 may be formed more densely than the regions of the other active layers 114. Thus, the film formation rate of the active layer 114 can be increased while suppressing deterioration of the transistor, and the throughput is improved.

Next, the second wiring layer 116 may be formed on the substrate 110, the base film 111, the first wiring layer 112, the insulating film 113, or the active layers 114 and 115. Here, as a conductive material for forming the second wiring layer 116, particles of metal such as Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum) are mainly used. The composition can be used. Further, light-transmitting indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like may be combined. The second wiring layer 116 may be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

Next, an interlayer film 117 may be formed on the substrate 110, the base film 111, the first wiring layer 112, the insulating film 113, the active layers 114 and 115, or the second wiring layer 116. Here, the interlayer film 117 is formed of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or other inorganic insulating materials, or acrylic acid, methacrylic acid and derivatives thereof, or polyimide. , An aromatic polyamide, a heat-resistant polymer such as polybenzimidazole, or an insulating material such as a siloxane resin. When a photosensitive or non-photosensitive material such as acrylic or polyimide is used, the side surface has a shape in which the curvature radius changes continuously, and the upper thin film is formed without being cut off. The interlayer film 117 may be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like. Here, when the interlayer film 117 is processed, on the one hand, the etching stops at the second wiring layer 116 as in the contact 118a, and on the other hand, the insulating film 113 is also processed as in the contact 118b. Good. By doing so, the third wiring layer 119 can be formed, and the second wiring layer 116 and the first wiring layer 112 can be connected.

Next, a third wiring layer 119 is formed on the substrate 110, the base film 111, the first wiring layer 112, the insulating film 113, the active layers 114 and 115, the second wiring layer 116, or the interlayer film 117. Also good. Here, the conductive material forming the third wiring layer 119 is mainly composed of particles of metal such as Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum). The composition can be used. Further, light-transmitting indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like may be combined. The third wiring layer 119 may be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

In FIG. 22, Ctft17 is a parasitic capacitance element of the transistor 17, Cclk1 is a parasitic capacitance element between the output terminal L and the first clock signal line CLK1, and Cclk2 is an output terminal L and the second clock signal line CLK2. Each parasitic capacitance element is shown. In FIG. 22, x represents the width of the first wiring layer in which the active layer is present above in the parasitic capacitance element Ctft17. Further, y represents the distance between the upper end of the first wiring layer and the lower end of the second wiring layer in the parasitic capacitance elements Cclk1 and Cclk2.

Here, in FIG. 21, since the active layer is formed using the second wiring layer as a mask, it is formed in a shape according to the second wiring layer. At this time, the active layer may be formed in a shape surrounding the periphery of the second wiring layer. By doing so, the coverage of the third wiring layer overcoming the second wiring layer can be improved, and disconnection of the third wiring layer can be prevented. This is because, for example, when the shape around the active layer and the shape around the second wiring layer are the same or substantially the same, or when the shape surrounding the active layer is surrounded by the second wiring layer, This is because the taper angle of the interlayer film on the two wiring layers becomes steep compared to the case where the active layer is formed in a shape surrounding the periphery of the second wiring layer.

In FIG. 21, the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are configured by a wiring layer and an active layer, and are provided substantially in parallel with the extending direction of the circuit 10. It may be. In this way, when a plurality of the circuits 10 are extended, the wiring resistance increases due to an increase in the wiring routing distance, and it is possible to suppress an increase in malfunction and power consumption due to a voltage drop in the power supply line. In addition, it is possible to suppress the occurrence of malfunction due to the rounding of the signal waveform in the signal line and the reduction of the voltage range in which the signal operates normally.

Further, the power supply line Vss, the first clock signal line CLK1 and the second clock signal line CLK2 may be provided outside the elements constituting the circuit 10. The power supply line Vss may be provided on the side opposite to the first clock signal line CLK1 and the second clock signal line CLK2. By doing so, it is possible to avoid the occurrence of a region where the power supply line Vss intersects the first clock signal line CLK1 and the second clock signal line CLK2, and thus noise from the clock signal line is applied to the power supply line. Can be prevented, and malfunction becomes difficult.

In FIG. 21, the channel length direction of the transistor 11 and the channel length direction of the transistor 12 may be substantially perpendicular. Thus, the area occupied by the transistors 11 and 12 on the substrate can be reduced, and the circuit scale can be reduced. Further, the channel length directions of the transistors 13 and 16 may be substantially parallel, and one of the source electrode and the drain electrode may be common. Thus, the area occupied by the transistors 13 and 16 on the substrate can be reduced, and the circuit scale can be reduced.

The channel length directions of the transistors 15 and 17 may be substantially parallel, and one of the source electrode and the drain electrode may be common. Thus, the area occupied by the transistors 15 and 17 on the substrate can be reduced, and the circuit scale can be reduced. Further, in the capacitor element 14, the terminal P that is one electrode may be formed by a gate electrode, and the electrode connected to the output terminal L that is the other electrode may be formed by a wiring layer.

Next, FIG. 23 is a top view of the circuit 10 when the shapes of the transistors 13 and 17 are devised to hold the potential of the electrode SR at an H level in order to fix the potential of the terminal P and the output terminal L. The description will be given with reference. The top view of the circuit 10 shown in FIG. 23 includes transistors 11, 12, 13, 15, 16, 17, a capacitor element 14, a terminal P, an electrode SR, and an output terminal L, as in FIG. However, the shapes of the first wiring layers of the transistors 13 and 17 are different. As described above, the average of the areas of the first wiring layers of the transistors 13 and 17 is made larger than the area of the first wiring layer of the transistor 12 of the circuit 10, thereby increasing the value of the parasitic capacitance associated with the electrode SR. This is preferable because the potential of the electrode SR can be held at the H level even after the reset operation.

Further, as shown in FIG. 23, the electrode SR may be formed by being bent in the circuit 10 while avoiding the shape of the electrode SR to be linear. In this way, the length of routing the electrode SR can be made longer than the pitch between the k-th stage circuit 10 and the (k + 1) -th stage circuit 10, and the parasitic capacitance associated with the electrode SR can be increased. This is preferable because the potential of the electrode SR can be held at the H level even after the reset operation. Further, the top view of the circuit 10 shown in FIG. 23 is different from FIG. 21 in the structure of the region where the output terminal L and the clock signal line intersect. In the circuit 10 shown in FIG. 23, in the region where the output terminal L and the clock signal line intersect, the output terminal L is formed by the third wiring layer, and the clock signal line is formed by the second wiring layer and the active layer.

Next, with reference to FIGS. 24A and 24B, the thin film transistor is used as the cross section taken along the line connecting points a and a ′ and b and b ′ in FIG. I will explain. The structures shown in FIGS. 24A and 24B are similar to the structures shown in FIGS. 22A and 22B in that the substrate 110, the base film 111, the first wiring layer 112, and the insulating film are formed. 113, active layers 114 and 115, a second wiring layer 116, an interlayer film 117, and a third wiring layer 119. 24A and 24B, the contact 118a connecting the third wiring layer 119 and the second wiring layer 116 and the contact 118b connecting the third wiring layer 119 and the first wiring layer 112 are used. Is provided.

In FIG. 24, Ctft17 is a parasitic capacitance element of the transistor 17, Cclk1 is a parasitic capacitance element between the output terminal L and the first clock signal line CLK1, and Cclk2 is an output terminal L and the second clock signal line CLK2. Each parasitic capacitance element is shown. In FIG. 24, x represents the width of the first wiring layer in which the active layer is present above in the parasitic capacitance element Ctft17. Further, y represents the distance between the upper end of the first wiring layer and the lower end of the second wiring layer in the parasitic capacitance elements Cclk1 and Cclk2.

Here, the capacitance value of the parasitic capacitance element Ctft17 increases as x increases. Further, the capacitance values of the parasitic capacitance elements Cclk1 and Cclk2 become smaller as y becomes larger. As shown in FIG. 24A, if the capacitance value of the parasitic capacitance element Ctft17 is increased by increasing x, the parasitic capacitance value associated with the electrode SR can be increased. Can be retained sufficiently. Further, as shown in FIG. 24B, if the capacitance values of the parasitic capacitance elements Cclk1 and Cclk2 are reduced by increasing y, the potential fluctuations of the first clock signal line CLK1 and the second clock signal line CLK2 are changed. It is possible to reduce the fluctuation of the potential of the output terminal L via the parasitic capacitance elements Cclk1 and Cclk2. At this time, the first clock signal line CLK1 and the second clock signal line CLK2 may be formed of the first wiring layer.

Next, with reference to FIG. 25, a top view when the cross capacitance between the clock signal line and the output terminal L is eliminated so that the output terminal L is not affected by the potential change of the clock signal line as much as possible. explain. The top view of the circuit 10 shown in FIG. 25 includes transistors 11, 12, 13, 15, 16, 17, a capacitor element 14, a terminal P, an electrode SR, and an output terminal L, as in FIGS. Similarly, the arrangement of the first clock signal line CLK1, the second clock signal line CLK2, and the transistors 11 and 12 is different from that in FIGS.

In FIG. 25, the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are configured by the second wiring layer and the active layer, and are provided substantially parallel to the extending direction of the circuit 10. It may be. In this way, even when a plurality of circuits 10 are extended, the wiring resistance increases as the wiring routing distance increases, and malfunctions due to voltage drop in the power supply line and an increase in power consumption can be suppressed. In addition, it is possible to suppress the occurrence of malfunction due to the rounding of the signal waveform in the signal line and the reduction of the voltage range in which the signal operates normally.

Further, the power supply line Vss, the first clock signal line CLK1 and the second clock signal line CLK2 may be provided outside the elements constituting the circuit 10. The power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are provided on the same side, and the first transistor, the third transistor, the second transistor, and the fourth transistor The transistor may be provided on the opposite side of the output terminal L side. By doing so, it is possible to avoid the occurrence of a region where the output terminal L intersects with the first clock signal line CLK1 and the second clock signal line CLK2, so that the noise of the clock signal line gets on the power supply line. Can be prevented, and malfunction becomes difficult.

Further, the channel length direction of the transistor 11 and the channel length direction of the transistor 12 may be substantially parallel. By doing so, the area occupied by the transistors 11 and 12 on the substrate can be reduced while avoiding a region where the output terminal L intersects with the first clock signal line CLK1 and the second clock signal line CLK2. And the circuit scale can be reduced.

Next, a top view of the shift register circuit according to the present invention when a bottom gate type transistor is used as a transistor and the active layer and the wiring layer are individually processed into desired shapes will be described with reference to FIG. explain. In FIG. 26, only the k-th stage circuit 10 and the (k + 1) -th stage circuit 10 are shown for explanation. However, the present invention is not limited to this, and the circuit 10 may be configured in any number of stages. good. In addition, the transistors 11, 12, 13, 15, 16, and 17, the capacitor element 14, and the terminal P in FIG. 26 are the transistors 11, 12, 13, 15, 16, 17, and the capacitor element in FIG. 14 and terminal P, respectively. In FIG. 1, the electrode SR and the output terminal L that are arranged outside the circuit 10 are arranged inside the circuit 10 in FIG. 26 in order to reduce the layout area. Note that in the top view referred to in this embodiment, a region represented by a broken line represents a region in which another layer is present above the region.

Next, with reference to FIGS. 27A and 27B, a thin film transistor is used for the cross section taken along the line connecting points a and a ′ and b and b ′ in FIG. I will explain. 27A and 27B includes a substrate 120, a base film 121, a first wiring layer 122, an insulating film 123, active layers 124 and 125, a second wiring layer 126, An interlayer film 127 and a third wiring layer 129 are provided. 27A and 27B, the contact 128a connecting the third wiring layer 129 and the second wiring layer 126 and the contact 128b connecting the third wiring layer 129 and the first wiring layer 122 are used. Is provided. The structures shown in FIGS. 27A and 27B will be described in order.

First, the substrate 120 may be a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate. Further, the surface of the substrate 120 may be polished by a CMP method or the like so as to be planarized.

Next, a base film 121 may be formed on the substrate 120. The base film 121 is formed of a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiOxNy) by a known method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. It may be formed by stacking. Note that the formation of the base film 121 has an effect of blocking contaminants from the substrate 120. When the base film 121 is not formed, the manufacturing process is simplified, so that the cost can be reduced.

Next, the first wiring layer 122 may be formed on the substrate 120 or the base film 121. Here, the first wiring layer 122 may be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

Next, an insulating film 123 may be formed on the substrate 120, the base film 121, or the first wiring layer 122. Here, the insulating film 123 may be formed of silicon oxide (SiO ₂ ) or silicon oxynitride (SiOxNy).

Next, active layers 124 and 125 may be formed on the substrate 120, the base film 121, the first wiring layer 122, or the insulating film 123. Here, the active layers 124 and 125 may be amorphous silicon (a-Si), and the active layers 124 and 125 may be continuously formed in the same film forming apparatus. 125 may have a higher conductivity than 124. Note that the channel region, that is, the region in the vicinity of the surface where the active layer 124 is in contact with the insulating film 123 may be formed denser than the regions of the other active layers 124. Thus, the film formation rate of the active layer 124 can be increased while suppressing deterioration of the transistor, and the throughput is improved.

Next, the second wiring layer 126 may be formed on the substrate 120, the base film 121, the first wiring layer 122, the insulating film 123, or the active layers 124 and 125. Here, as a conductive material for forming the second wiring layer 126, metal particles such as Ag (silver), Au (gold), Cu (copper), W (tungsten), and Al (aluminum) are mainly used. The composition can be used. Further, light-transmitting indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like may be combined. The second wiring layer 126 may be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

Next, an interlayer film 127 may be formed on the substrate 120, the base film 121, the first wiring layer 122, the insulating film 123, the active layers 124 and 125, or the second wiring layer 126. Here, the interlayer film 127 is formed of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or other inorganic insulating materials, or acrylic acid, methacrylic acid, and derivatives thereof, or polyimide. , An aromatic polyamide, a heat-resistant polymer such as polybenzimidazole, or an insulating material such as a siloxane resin. When a photosensitive or non-photosensitive material such as acrylic or polyimide is used, the side surface has a shape in which the curvature radius changes continuously, and the upper thin film is formed without being cut off. The interlayer film 127 may be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like. Here, when the interlayer film 127 is processed, the etching is stopped at the second wiring layer 126 on the one hand like the contact 128a, and the insulating film 123 is also processed on the other hand like the contact 128b. Good. In this way, the third wiring layer 129 can be formed and the second wiring layer 126 and the first wiring layer 122 can be connected.

Next, a third wiring layer 129 is formed on the substrate 120, the base film 121, the first wiring layer 122, the insulating film 123, the active layers 124 and 125, the second wiring layer 126, or the interlayer film 127. Also good. Here, as a conductive material for forming the third wiring layer 129, particles of metal such as Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum) are mainly used. The composition can be used. Further, light-transmitting indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like may be combined. The third wiring layer 129 may be processed into a desired shape by photolithography, a droplet discharge method, a printing method, or the like.

In FIG. 27, Ctft17 is a parasitic capacitance element of the transistor 17, Cclk1 is a parasitic capacitance element between the output terminal L and the first clock signal line CLK1, and Cclk2 is an output terminal L and the second clock signal line CLK2. Each parasitic capacitance element is shown. In FIG. 27, x represents the width of the first wiring layer in which the active layer is present above in the parasitic capacitance element Ctft17. Further, y represents the distance between the upper end of the first wiring layer and the lower end of the second wiring layer in the parasitic capacitance elements Cclk1 and Cclk2. Here, in order to increase y, an active layer is formed in a region where the output terminal L intersects the first clock signal line CLK1 and the second clock signal line CLK2 on the line connecting the point b and the point b ′. 124 and 125 may be formed.

In FIG. 26, since the active layer and the second wiring layer are formed by separate masks, there may be no region where the active layer is formed in the second wiring layer other than the transistor portion. Further, an active layer is formed in the second wiring layer other than the transistor portion, such as a region where the output terminal L of FIG. 26 intersects the first clock signal line CLK1 and the second clock signal line CLK2. Also good.

In FIG. 26, the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are each composed of a wiring layer and an active layer, and are provided substantially parallel to the extending direction of the circuit 10. It may be. In this way, when a plurality of the circuits 10 are extended, the wiring resistance increases due to an increase in the wiring routing distance, and it is possible to suppress an increase in malfunction and power consumption due to a voltage drop in the power supply line. In addition, it is possible to suppress the occurrence of malfunction due to the rounding of the signal waveform in the signal line and the reduction of the voltage range in which the signal operates normally.

Further, the power supply line Vss, the first clock signal line CLK1 and the second clock signal line CLK2 may be provided outside the elements constituting the circuit 10. The power supply line Vss may be provided on the side opposite to the first clock signal line CLK1 and the second clock signal line CLK2. By doing so, it is possible to avoid the occurrence of a region where the power supply line Vss intersects the first clock signal line CLK1 and the second clock signal line CLK2, and thus noise from the clock signal line is applied to the power supply line. Can be prevented, and malfunction becomes difficult.

In FIG. 26, the channel length direction of the transistor 11 and the channel length direction of the transistor 12 may be substantially perpendicular. Thus, the area occupied by the transistors 11 and 12 on the substrate can be reduced, and the circuit scale can be reduced.

Further, the channel length directions of the transistors 13 and 16 may be substantially parallel, and one of the source electrode and the drain electrode may be common. Thus, the area occupied by the transistors 13 and 16 on the substrate can be reduced, and the circuit scale can be reduced. The channel length directions of the transistors 15 and 17 may be substantially parallel, and one of the source electrode and the drain electrode may be common. Thus, the area occupied by the transistors 15 and 17 on the substrate can be reduced, and the circuit scale can be reduced. Further, in the capacitor element 14, the terminal P that is one electrode may be formed by a gate electrode, and the electrode connected to the output terminal L that is the other electrode may be formed by a wiring layer.

Next, FIG. 28 is a top view of the circuit 10 when the shapes of the transistors 13 and 17 are devised to hold the potential of the electrode SR at the H level in order to fix the potential of the terminal P and the output terminal L. The description will be given with reference. The top view of the circuit 10 shown in FIG. 28 includes transistors 11, 12, 13, 15, 16, 17, a capacitor element 14, a terminal P, an electrode SR, and an output terminal L, as in FIG. However, the shapes of the first wiring layers of the transistors 13 and 17 are different. As described above, the average of the areas of the first wiring layers of the transistors 13 and 17 is made larger than the area of the first wiring layer of the transistor 12 of the circuit 10, thereby increasing the value of the parasitic capacitance associated with the electrode SR. This is preferable because the potential of the electrode SR can be held at the H level even after the reset operation.

Further, as shown in FIG. 28, the electrode SR may be bent in the circuit 10 while avoiding a straight shape. In this way, the length of routing the electrode SR can be made longer than the pitch between the k-th stage circuit 10 and the (k + 1) -th stage circuit 10, and the parasitic capacitance associated with the electrode SR can be increased. This is preferable because the potential of the electrode SR can be held at the H level even after the reset operation.

In addition, the top view of the circuit 10 shown in FIG. 28 differs from the structure in FIG. 26 in the structure of the region where the output terminal L and the clock signal line intersect. In the circuit 10 shown in FIG. 28, in the region where the output terminal L and the clock signal line intersect, the output terminal L is formed by the third wiring layer, and the clock signal line is formed by the second wiring layer.

Next, with reference to FIGS. 29A and 29B, a thin film transistor is used as a cross section taken along the line connecting points a and a ′ and b and b ′ in FIG. I will explain. 29A and 29B is similar to the structure shown in FIGS. 27A and 27B in the substrate 120, the base film 121, the first wiring layer 122, and the insulating film. 123, active layers 124 and 125, a second wiring layer 126, an interlayer film 127, and a third wiring layer 129. 29A and 29B, the contact 128a that connects the third wiring layer 129 and the second wiring layer 126 and the contact 128b that connects the third wiring layer 129 and the first wiring layer 122 are the structures shown in FIGS. Is provided.

In FIG. 29, Ctft17 is a parasitic capacitance element of the transistor 17, Cclk1 is a parasitic capacitance element of the output terminal L and the first clock signal line CLK1, and Cclk2 is an output terminal L of the second clock signal line CLK2. Each parasitic capacitance element is shown. In FIG. 29, x represents the width of the first wiring layer in which the active layer or the second wiring layer is present above in the parasitic capacitance element Ctft17. Further, y represents the distance between the upper end of the first wiring layer and the lower end of the second wiring layer in the parasitic capacitance elements Cclk1 and Cclk2.

Here, the capacitance value of the parasitic capacitance element Ctft17 increases as x increases. Further, the capacitance values of the parasitic capacitance elements Cclk1 and Cclk2 become smaller as y becomes larger. As shown in FIG. 29A, if the capacitance value of the parasitic capacitance element Ctft17 is increased by increasing x, the parasitic capacitance value associated with the electrode SR can be increased. Can be retained sufficiently. Further, as shown in FIG. 29B, if the capacitance values of the parasitic capacitance elements Cclk1 and Cclk2 are reduced by increasing y, the potential fluctuations of the first clock signal line CLK1 and the second clock signal line CLK2 are changed. It is possible to reduce the fluctuation of the potential of the output terminal L via the parasitic capacitance elements Cclk1 and Cclk2. At this time, the active layer and the first wiring layer may not be formed below the first clock signal line CLK1 and the second clock signal line CLK2. Further, the first clock signal line CLK1 and the second clock signal line CLK2 may be formed of the first wiring layer.

Next, with reference to FIG. 30, a top view when the cross capacitance between the clock signal line and the output terminal L is eliminated so that the output terminal L is not affected by the potential change of the clock signal line as much as possible. explain. The top view of the circuit 10 shown in FIG. 30 includes transistors 11, 12, 13, 15, 16, 17, a capacitor element 14, a terminal P, an electrode SR, and an output terminal L, as in FIGS. Similarly, the arrangement of the first clock signal line CLK1, the second clock signal line CLK2, and the transistors 11 and 12 is different from that in FIGS.

In FIG. 30, the power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are configured by the second wiring layer, and may be provided substantially in parallel with the extending direction of the circuit 10. Good. In this way, even when a plurality of circuits 10 are extended, the wiring resistance increases as the wiring routing distance increases, and malfunctions due to voltage drop in the power supply line and an increase in power consumption can be suppressed. In addition, it is possible to suppress the occurrence of malfunction due to the rounding of the signal waveform in the signal line and the reduction of the voltage range in which the signal operates normally.

Further, the power supply line Vss, the first clock signal line CLK1 and the second clock signal line CLK2 may be provided outside the elements constituting the circuit 10. The power supply line Vss, the first clock signal line CLK1, and the second clock signal line CLK2 are provided on the same side, and the first transistor, the third transistor, the second transistor, and the fourth transistor The transistor may be provided on the opposite side of the output terminal L side. By doing so, it is possible to avoid the occurrence of a region where the output terminal L intersects with the first clock signal line CLK1 and the second clock signal line CLK2, so that the noise of the clock signal line gets on the power supply line. Can be prevented, and malfunction becomes difficult.

Further, the channel length direction of the transistor 11 and the channel length direction of the transistor 12 may be substantially parallel. By doing so, the area occupied by the transistors 11 and 12 on the substrate can be reduced while avoiding a region where the output terminal L intersects with the first clock signal line CLK1 and the second clock signal line CLK2. And the circuit scale can be reduced.

(Embodiment 5)
In the present embodiment, the entire display panel using the shift register circuit according to the present invention and the display device using the display panel using the shift register circuit according to the present invention described in the first to fourth embodiments. An example of the configuration will be described. Note that in this specification, a display panel includes pixels formed in an array on a substrate such as a glass substrate, a plastic substrate, a quartz substrate, or a silicon substrate in order to display a still image or a moving image. This means a device having a region (also referred to as a pixel region). The display device is a circuit that converts an electrical signal input from the outside into a data signal that individually controls the optical state of the pixel, and a drive for time-division writing of the data signal to the pixel. It represents a systemized device for displaying an image on the display panel, including a circuit and the like. The display device may include a circuit for processing the data signal and optimizing an image displayed on the display panel.

The shift register circuit according to the present invention may be used as part of a drive circuit that constitutes a display device. In addition, as a method for mounting the shift register circuit according to the present invention on a display device, various methods can be used in consideration of productivity, manufacturing cost, reliability, and the like. Here, an example of a method of mounting the shift register circuit according to the present invention on a display device will be described with reference to FIG.

FIG. 31A shows a display panel in the case where a data line driver which is a peripheral driver circuit and a scanning line driver are integrally formed on the same substrate as the pixel region. A display panel 200a illustrated in FIG. 31A includes a pixel region 201a, a data line driver 202a, a scanning line driver 203a, and a connection wiring substrate 204a.
The pixel area 201a is an area where pixels are arranged in an array, and the state of the pixel array may be a stripe type or a delta type. Further, a data signal line which is a wiring for writing a data signal for individually controlling the optical state of the pixel to the pixel may be provided. In addition, a scanning line which is a wiring for selecting a pixel column into which a data signal for individually controlling the optical state of the pixel is written may be provided.

The data line driver 202a is a circuit that controls the electrical state of the data signal line in accordance with an image displayed in the pixel region 201a. The data line driver 202a may include a shift register circuit according to the present invention in order to control a plurality of data signal lines by dividing them in time.

The scanning line driver 203a is a circuit that controls the electrical state of the scanning line, which is a wiring for selecting a pixel column to which a data signal for individually controlling the optical state of the pixel is written. The scanning line driver 203a sequentially scans a plurality of scanning lines, sequentially selects a pixel column to which a data signal for individually controlling the optical state of the pixel is written, and writes the data signal to the pixel to write the data signal to the pixel region 201a. In order to display an image, the shift register circuit according to the present invention may be included.

The connection wiring substrate 204a is a substrate on which wiring for connecting the display panel 200a and an external circuit that drives the display panel 200a is formed, and the connection wiring substrate 204a is formed of a flexible substrate such as polyimide. Thus, it becomes easy to mount the display panel 200a in a housing having a movable part. Further, when the housing having the display panel 200a receives a strong impact, if the connection wiring board 204a has flexibility, the impact applied to the connection wiring board 204a is absorbed, so that the connection portion 205a is peeled off. The risk of disconnection can be reduced.

In the display panel 200a shown in FIG. 31A, the manufacturing cost can be reduced and the number of connection points can be reduced by integrally forming the data line driver 202a and the scanning line driver 203a on the same substrate as the pixel region 201a. The impact resistance can be increased.

In FIG. 31B, a scanning line driver, which is a peripheral driver circuit, is integrally formed on the same substrate as the pixel region, and the data line driver is connected by placing an IC manufactured on a single crystal substrate on the substrate ( A display panel in the case of COG) is also shown. A display panel 200b illustrated in FIG. 31B includes a pixel region 201b, a data line driver 202b, a scanning line driver 203b, and a connection wiring substrate 204b.

The pixel region 201b is a region in which pixels are arranged in an array, and the state of the pixel array may be a stripe type or a delta type. Further, a data signal line which is a wiring for writing a data signal for individually controlling the optical state of the pixel to the pixel may be provided. In addition, a scanning line which is a wiring for selecting a pixel column into which a data signal for individually controlling the optical state of the pixel is written may be provided.
The data line driver 202b is a circuit that controls the electrical state of the data signal line in accordance with an image displayed in the pixel region 201b. The data line driver 202b may include a shift register circuit according to the present invention in order to control a plurality of data signal lines by dividing them in time.

The scanning line driver 203b is a circuit that controls the electrical state of the scanning line, which is a wiring for selecting a pixel column to which a data signal for individually controlling the optical state of the pixel is written. The scanning line driver 203b sequentially scans a plurality of scanning lines, sequentially selects a pixel row to which a data signal for individually controlling the optical state of the pixel is written, and writes the data signal to the pixel to write the pixel signal to the pixel region 201b. In order to display an image, the shift register circuit according to the present invention may be included.

The connection wiring substrate 204b is a substrate on which wiring for connecting the display panel 200b and an external circuit that drives the display panel 200b is formed, and the connection wiring substrate 204b is formed of a flexible substrate such as polyimide. Thus, it becomes easy to mount the display panel 200b in a housing having a movable part. Further, when the housing having the display panel 200b receives a strong impact, if the connection wiring board 204b has flexibility, the impact applied to the connection wiring board 204b is absorbed, so that the connection portion 205b is peeled off. The risk of disconnection can be reduced.

In the display panel 200b shown in FIG. 31B, the manufacturing cost can be reduced by integrally forming the scanning line driver 203b on the same substrate as the pixel region 201b, and the impact resistance can be reduced by reducing the number of connection points. Can be increased. In addition, since the data line driver 202b is mounted using an IC manufactured using a single crystal substrate, variation in electrical characteristics of the transistor can be manufactured extremely small, and the yield of the display device can be improved. In addition, since the operating voltage can be reduced, power consumption can be reduced.

FIG. 31C shows a display panel in the case where a data line driver and a scanning line driver, which are peripheral drive circuits, are manufactured as ICs on a single crystal substrate on the same substrate as the pixel region and used as a COG. . A display panel 200c shown in FIG. 31C includes a pixel region 201c, a data line driver 202c, a scanning line driver 203c, and a connection wiring substrate 204c.

The pixel region 201c is a region in which pixels are arranged in an array, and the state of the pixel array may be a stripe type or a delta type. Further, a data signal line which is a wiring for writing a data signal for individually controlling the optical state of the pixel to the pixel may be provided. In addition, a scanning line which is a wiring for selecting a pixel column into which a data signal for individually controlling the optical state of the pixel is written may be provided.

The data line driver 202c is a circuit that controls the electrical state of the data signal line in accordance with an image displayed in the pixel region 201c. The data line driver 202c may include a shift register circuit according to the present invention in order to control a plurality of data signal lines by dividing them in time.

The scanning line driver 203c is a circuit that controls the electrical state of the scanning line, which is a wiring for selecting a pixel column to which a data signal for individually controlling the optical state of the pixel is written. The scanning line driver 203c sequentially scans a plurality of scanning lines, sequentially selects a pixel column to which a data signal for individually controlling the optical state of the pixel is written, and writes the data signal to the pixel to write the pixel signal into the pixel region 201c. In order to display an image, the shift register circuit according to the present invention may be included.

The connection wiring substrate 204c is a substrate on which wiring for connecting the display panel 200c and an external circuit that drives the display panel 200c is formed, and the connection wiring substrate 204c is formed of a flexible substrate such as polyimide. Thus, it becomes easy to mount the display panel 200c in a housing having a movable part. Further, when the housing having the display panel 200c receives a strong impact, if the connection wiring board 204c has flexibility, the impact applied to the connection wiring board 204c is absorbed, so that the connection portion 205c is peeled off. The risk of disconnection can be reduced.

In the display panel 200c shown in FIG. 31C, the data line driver 202c and the scan line driver 203c are mounted using an IC manufactured using a single crystal substrate, so that variation in electrical characteristics of transistors is extremely small. And the yield of the display device can be improved. In addition, since the operating voltage can be reduced, power consumption can be reduced.

In FIG. 31D, a scanning line driver, which is a peripheral driver circuit, is integrally formed on the same flexible substrate as the pixel region, and an IC manufactured on a single crystal substrate is arranged on the flexible substrate as the data line driver. A display panel when connected (also referred to as TAB) is shown. A display panel 200d illustrated in FIG. 31D includes a pixel region 201d, a data line driver 202d, a scanning line driver 203d, and a connection wiring substrate 204d.

The pixel area 201d is an area in which pixels are arranged in an array, and the state of the pixel array may be a stripe type or a delta type. Further, a data signal line which is a wiring for writing a data signal for individually controlling the optical state of the pixel to the pixel may be provided. In addition, a scanning line which is a wiring for selecting a pixel column into which a data signal for individually controlling the optical state of the pixel is written may be provided.

The data line driver 202d is a circuit that controls the electrical state of the data signal line in accordance with the image displayed in the pixel area 201d. The data line driver 202d may include a shift register circuit according to the present invention in order to control a plurality of data signal lines by dividing them in time.

The scanning line driver 203d is a circuit that controls the electrical state of the scanning line, which is a wiring for selecting a pixel column to which a data signal for individually controlling the optical state of the pixel is written. The scanning line driver 203d sequentially scans a plurality of scanning lines, sequentially selects a pixel column to which a data signal for individually controlling the optical state of the pixel is written, and writes the data signal to the pixel to write the pixel signal into the pixel region 201d. In order to display an image, the shift register circuit according to the present invention may be included.

The connection wiring substrate 204d is a substrate on which wiring for connecting the display panel 200d and an external circuit that drives the display panel 200d is formed, and the connection wiring substrate 204d is formed of a flexible substrate such as polyimide. Thus, it becomes easy to mount the display panel 200d in a housing having a movable part. Further, when the housing having the display panel 200d receives a strong impact, if the connection wiring board 204d has flexibility, the impact applied to the connection wiring board 204d is absorbed, and thus the connection portion 205d is peeled off. The risk of disconnection can be reduced.

In the display panel 200d shown in FIG. 31D, the manufacturing cost can be reduced by integrally forming the scanning line driver 203d on the same substrate as the pixel region 201d, and the impact resistance can be reduced by reducing the number of connection points. Can be increased. In addition, since the data line driver 202d is mounted using an IC manufactured using a single crystal substrate, variation in electric characteristics of the transistor can be manufactured extremely small, and the yield of the display device can be improved. In addition, since the operating voltage can be reduced, power consumption can be reduced. In addition, since the data line driver 202d is connected to the connection wiring board 204d, an area other than the pixel area 201d of the display panel 200d (also referred to as a frame) can be reduced, and the added value of the display device can be increased. Can do. Further, if the connection wiring board 204d has flexibility, when the casing having the display panel 200d receives a strong shock, the shock applied to the connection wiring board 204d is absorbed. The risk of peeling from the connection wiring substrate 204d and disconnection can be reduced.

FIG. 31E shows a display panel in which a data line driver and a scanning line driver, which are peripheral driver circuits, are manufactured as ICs on a single crystal substrate over the same substrate as the pixel region to form a TAB. . A display panel 200e illustrated in FIG. 31E includes a pixel region 201e, a data line driver 202e, a scanning line driver 203e, and a connection wiring substrate 204e.

The pixel area 201e is an area in which pixels are arranged in an array, and the state of the pixel array may be a stripe type or a delta type. Further, a data signal line which is a wiring for writing a data signal for individually controlling the optical state of the pixel to the pixel may be provided. In addition, a scanning line which is a wiring for selecting a pixel column into which a data signal for individually controlling the optical state of the pixel is written may be provided.

The data line driver 202e is a circuit that controls the electrical state of the data signal line in accordance with an image displayed in the pixel region 201e. The data line driver 202e may have a shift register circuit according to the present invention in order to control a plurality of data signal lines by dividing them in time.

The scanning line driver 203e is a circuit that controls the electrical state of the scanning line, which is a wiring for selecting a pixel column to which a data signal for individually controlling the optical state of the pixel is written. The scanning line driver 203e sequentially scans a plurality of scanning lines, sequentially selects a pixel column to which a data signal for individually controlling the optical state of the pixel is written, and writes the data signal to the pixel to write the pixel signal to the pixel region 201e. In order to display an image, the shift register circuit according to the present invention may be included.

The connection wiring substrate 204e is a substrate on which wiring for connecting the display panel 200e and an external circuit that drives the display panel 200e is formed, and the connection wiring substrate 204e is formed of a flexible substrate such as polyimide. Thus, it becomes easy to mount the display panel 200e in a housing having a movable part. Further, when the housing having the display panel 200e receives a strong impact, if the connection wiring board 204e has flexibility, the impact applied to the connection wiring board 204e is absorbed, and thus the connection portion 205e is peeled off. The risk of disconnection can be reduced.

A display panel 200e shown in FIG. 31E is manufactured with a very small variation in electrical characteristics of transistors because the data line driver 202e and the scanning line driver 203e are mounted using an IC manufactured using a single crystal substrate. And the yield of the display device can be improved. In addition, since the operating voltage can be reduced, power consumption can be reduced. In addition, since the data line driver 202e is connected to the connection wiring board 204e, the frame of the display panel 200e can be reduced, and the added value of the display device can be increased. Further, if the connection wiring board 204e has flexibility, when the casing having the display panel 200e receives a strong shock, the shock applied to the connection wiring board 204e is absorbed, so that the data line driver 202e and The risk that the scanning line driver 203e is peeled off from the connection wiring board 204e and disconnected is reduced.

Thus, the transistor in the present invention may be any type of transistor and may be formed on any substrate. Accordingly, the shift register circuit according to the present invention may be formed entirely on a glass substrate, may be formed on a plastic substrate, may be formed on a single crystal substrate, or may be formed on an SOI substrate. Or may be formed on any substrate. Alternatively, a part of the shift register circuit according to the present invention may be formed on a certain substrate, and another part of the shift register circuit according to the present invention may be formed on another substrate. That is, all the shift register circuits according to the present invention may not be formed on the same substrate.

Next, with reference to FIG. 32, a configuration example of a display device including a shift register circuit according to the present invention is shown. A display device 220 illustrated in FIG. 32 includes the display panel 200 illustrated in FIG. 31, an external drive circuit 221, and a connection wiring substrate 204.

The display panel 200 includes a pixel area 201, a data line driver 202, and a scanning line driver 203. Since the display panel 200 has been described above, it will not be described in detail here. Of course, various methods for mounting the data line driver 202 and the scanning line driver 203 can be applied to the display device 220 shown in FIG. .

The external drive circuit 221 includes a control circuit 210, a video data conversion circuit 211, and a power supply circuit 212. The power supply circuit 212 may include a control / video data conversion circuit power supply CV, a driver power supply DV, and a pixel circuit power supply PV. Note that the pixel circuit power source PV may not be provided in the power source circuit 212 depending on the configuration of the pixel region 201.

The connection wiring board 204 may be electrically connected to the display panel 200 through the connection unit 205 and may be electrically connected to the external drive circuit 221 through the connector 213.

Further, in order to cope with a display panel having a large pixel area 201, a plurality of data line drivers 202 (202-1, 202-2, 202-) are provided for one display panel 200 and one pixel area 201 as shown in FIG. 3, 202-4), a plurality of scanning line drivers 203 (203-1, 203-2, 203-3, 203-4), a plurality of connection wiring boards 204 (204-1, 204-2, 204-3, 204-4, 204-5, 204-6, 204-7, 204-8) may be used. Here, FIG. 33 shows the case where the number of the data line drivers 202 and the scanning line drivers 203 is four as an example, but the number of the data line drivers 202 and the scanning line drivers 203 is not limited to this. But you can. If the number of data line drivers 202 and scanning line drivers 203 is small, the number of ICs and the number of connection points are reduced, so that reliability is improved and manufacturing costs can be reduced. Also, if the number of data line drivers 202 and scanning line drivers 203 is large, the performance required for each driver is lowered, so that the yield can be improved.

Note that the number of the connection wiring boards 204 is preferably two or more and not more than the number of divisions of the data line driver 202 and the scanning line driver 203. If the number of connection wiring boards 204 is made larger than the number of divided drivers, an increase in the number of contacts causes a failure due to contact peeling.

In FIG. 32, the control circuit 210 is connected to a video data conversion circuit 211 and a power supply circuit 212. The control circuit 210 is connected to the data line driver 202 and the scanning line driver 203 via the connector 213, the connection wiring board 204, and the connection unit 205. The video data conversion circuit 211 is connected to an input terminal for inputting video data. The video data conversion circuit 211 is connected to the data line driver 202 via the connector 213, the connection wiring board 204, and the connection unit 205.

The power supply circuit 212 supplies power to each circuit. The control / video data conversion circuit power supply CV in the power supply circuit 212 is connected to the control circuit 210 and the video data conversion circuit 211. The driver power supply DV is The pixel circuit power source PV is connected to the data line driver 202 and the scanning line driver 203 through the connector 213, the connection wiring board 204, and the connection unit 205. 201 is connected.

Since the control circuit 210 and the video data conversion circuit 211 mainly perform a logic operation, the voltage supplied from the control / video data conversion circuit power source CV is preferably as low as possible, and is preferably about 3V. In order to reduce power consumption, it is preferable that the voltage supplied by the driver power supply DV be as low as possible. When a single crystal substrate IC is used for the data line driver 202 and the scanning line driver 203, about 3V is required. desirable. In the case where the data line driver 202 and the scanning line driver 203 are formed integrally with the display panel 200, it is desirable to supply a voltage having an amplitude of about 2 to 3 times the threshold voltage of the transistor. In this way, the circuit can be reliably operated while suppressing an increase in power consumption.

The control circuit 210 may be configured to perform an operation of generating and supplying a clock, an operation of generating and supplying a timing pulse, and the like to the data line driver 202 and the scanning line driver 203. The video data conversion circuit 211 may be configured to perform operations such as generating and supplying a clock, generating and supplying timing pulses for outputting the converted video data to the data line driver 202, and the like. Good. For example, when the video data conversion circuit 211, the data line driver 202, and the scanning line driver 203 do not need to operate, the power supply circuit 212 is stopped by supplying voltage to each circuit. It is good also as a structure which performs the operation | movement which reduces electric power.

When the video data is input to the video data conversion circuit 211, the video data conversion circuit 211 converts the video data into data that can be input to the data line driver 202 according to the timing supplied from the control circuit 210 and outputs the data to the data line driver 202. To do. Specifically, the video data input as an analog signal may be A / D converted by the video data conversion circuit 211, and the digital signal video data may be output to the data line driver 202.

The data line driver 202 operates the shift register circuit according to the present invention in accordance with the clock signal and timing pulse supplied from the control circuit 210, and captures and captures video data input to the data line driver 202 in a time-sharing manner. According to the data, an analog value data voltage or data current may be output to a plurality of data lines. The data voltage or data current output to the data line may be updated by a latch pulse supplied from the control circuit 210. In addition, in order to cause the shift register circuit according to the present invention to perform a reset operation, a signal for a reset operation may be input. In addition, in order to apply a reverse bias to the transistor included in the shift register circuit according to the present invention, a signal for applying the reverse bias may be input.

In synchronization with the update of the data voltage or data current output to the data line, the scanning line driver 203 operates the shift register circuit according to the present invention in accordance with the clock signal and the timing pulse supplied from the control circuit 210, and sets the scanning line. Scan sequentially. At this time, in order to cause the shift register circuit according to the present invention to perform a reset operation, a signal for a reset operation may be input. In addition, in order to apply a reverse bias to the transistor included in the shift register circuit according to the present invention, a signal for applying the reverse bias may be input.

32 and 33 show an example in which the scanning line driver 203 is arranged on one side, the scanning line driver may be arranged on both sides instead of one side. If they are arranged on both sides, there is an advantage that when the display device is mounted on an electronic device, the right and left balance is improved and the degree of freedom of arrangement is increased.

(Embodiment 6)
In this embodiment, electronic devices that can be realized using the shift register circuit according to the present invention will be described with reference to FIGS.

The present invention can be applied to various electronic devices. Specifically, it can be applied to a display device of an electronic device. As such electronic devices, cameras such as video cameras and digital cameras, goggle-type displays, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game devices, personal digital assistants (mobile computers, mobile phones) , Portable game machine, electronic book, etc.), image playback device provided with a recording medium (specifically, a device equipped with a display device capable of playing back a recording medium such as Digital Versatile Disc (DVD) and displaying the image) ) And the like.

FIG. 34A illustrates a television receiver, which includes a housing 3001, a support base 3002, a display portion 3003, speaker portions 3004, a video input terminal 3005, and the like. The display device of the present invention can be used for the display portion 3003. For example, since a large display unit for a television receiver is required, a display device as shown in FIG. 33 is preferable. The display device includes all information display light emitting devices for personal computers, television broadcast reception, advertisement display, and the like. By using the display device using the shift register circuit according to the present invention for the display portion 3003, it is difficult to malfunction even when exposed to noise such as electromagnetic waves from the outside, and an operation of applying a reverse bias is possible. Thus, a highly reliable electronic device can be obtained.

FIG. 34B shows a digital camera, which includes a main body 3101, a display portion 3102, an image receiving portion 3103, operation keys 3104, an external connection port 3105, a shutter 3106, and the like.
By using the display device using the shift register circuit according to the present invention for the display portion 3102, it is difficult to malfunction even when exposed to noise such as electromagnetic waves from the outside, and an operation of applying a reverse bias is possible. With this, a highly reliable digital camera can be obtained.

FIG. 34C illustrates a computer, which includes a main body 3201, a housing 3202, a display portion 3203, a keyboard 3204, an external connection port 3205, a pointing mouse 3206, and the like. By using the display device using the shift register circuit according to the present invention for the display portion 3203, it is difficult to malfunction even when exposed to noise such as electromagnetic waves from the outside, and an operation of applying a reverse bias is possible. By this, a highly reliable computer can be obtained.

FIG. 34D illustrates a mobile computer, which includes a main body 3301, a display portion 3302, a switch 3303, operation keys 3304, an infrared port 3305, and the like. By using the display device using the shift register circuit according to the present invention for the display portion 3302, it is difficult to malfunction even when exposed to noise such as electromagnetic waves from the outside, and an operation of applying a reverse bias is possible. A highly reliable mobile computer can be obtained.

FIG. 34E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 3401, a housing 3402, a display portion A3403, a display portion B3404, and a recording medium (DVD or the like). A reading unit 3405, an operation key 3406, a speaker unit 3407, and the like are included. The display portion A 3403 can mainly display image information, and the display portion B 3404 can mainly display character information. By using the display device using the shift register circuit according to the present invention for the display portion A3403 and the display portion B3404, it is difficult to malfunction even when exposed to noise such as electromagnetic waves from the outside, and an operation of applying a reverse bias is performed. Therefore, it is possible to obtain a highly reliable image reproducing apparatus.

FIG. 34F illustrates a goggle type display including a main body 3501, a display portion 3502, and an arm portion 3503. By using the display device using the shift register circuit according to the present invention for the display portion 3502, it is difficult to malfunction even when exposed to noise such as electromagnetic waves from the outside, and an operation of applying a reverse bias is possible. Thus, a highly reliable goggle type display can be obtained.

FIG. 34G shows a video camera, which includes a main body 3601, a display portion 3602, a housing 3603, an external connection port 3604, a remote control receiving portion 3605, an image receiving portion 3606, a battery 3607, an audio input portion 3608, operation keys 3609, and the like. . By using the display device including the shift register circuit according to the present invention for the display portion 3602, it is difficult to malfunction even when exposed to noise such as electromagnetic waves from the outside, and an operation of applying a reverse bias is possible. By this, a highly reliable video camera can be obtained.

FIG. 34H shows a cellular phone, which includes a main body 3701, a housing 3702, a display portion 3703, an audio input portion 3704, an audio output portion 3705, operation keys 3706, an external connection port 3707, an antenna 3708, and the like. By using the display device using the shift register circuit according to the present invention for the display portion 3703, it is difficult to malfunction even when exposed to noise such as electromagnetic waves from the outside, and an operation of applying a reverse bias is possible. Thus, a highly reliable mobile phone can be obtained.

Thus, the present invention can be applied to all electronic devices.

4A and 4B illustrate a shift register circuit and a time chart according to the invention. FIG. 6 illustrates a shift register circuit according to the present invention. FIG. 6 illustrates a shift register circuit according to the present invention. FIG. 9 is a diagram illustrating a time chart of a shift register circuit according to the present invention. FIG. 6 illustrates a shift register circuit according to the present invention. FIG. 9 is a diagram illustrating a time chart of a shift register circuit according to the present invention. 4A and 4B illustrate a shift register circuit and a time chart according to the invention. FIG. 6 illustrates a shift register circuit according to the present invention. The figure explaining the reverse bias circuit concerning this invention. The figure explaining the reverse bias circuit concerning this invention. FIG. 6 illustrates a shift register circuit according to the present invention. FIG. 9 is a diagram illustrating a time chart of a shift register circuit according to the present invention. 4A and 4B illustrate a shift register circuit and a time chart according to the invention. FIG. 6 illustrates a shift register circuit according to the present invention. The figure explaining the reverse bias reset circuit concerning this invention. The figure explaining the reverse bias reset circuit concerning this invention. The top view of the shift register circuit concerning this invention. Sectional drawing of the shift register circuit concerning this invention. The top view of the shift register circuit concerning this invention. The top view of the shift register circuit concerning this invention. The top view of the shift register circuit concerning this invention. Sectional drawing of the shift register circuit concerning this invention. The top view of the shift register circuit concerning this invention. Sectional drawing of the shift register circuit concerning this invention. The top view of the shift register circuit concerning this invention. The top view of the shift register circuit concerning this invention. Sectional drawing of the shift register circuit concerning this invention. The top view of the shift register circuit concerning this invention. Sectional drawing of the shift register circuit concerning this invention. The top view of the shift register circuit concerning this invention. 4A and 4B illustrate a display panel using a shift register circuit according to the invention. 8A and 8B illustrate a display device using a shift register circuit according to the present invention. 8A and 8B illustrate a display device using a shift register circuit according to the present invention. 8A and 8B each illustrate an electronic device using a shift register circuit according to the invention. FIG. 6 illustrates an operation of a shift register circuit according to the present invention. 4A and 4B illustrate a shift register circuit and a time chart according to the present invention. FIG. 10 illustrates a conventional shift register circuit. FIG. 10 illustrates a conventional shift register circuit.

Claims (22)

An input terminal, an output terminal, a first terminal, a second terminal, a third terminal, and a fourth terminal;
A first transistor for transmitting the potential of the first terminal to the output terminal;
A rectifying element that turns on the first transistor in accordance with the potential of the input terminal;
A second transistor for conducting the output terminal and the second terminal according to the potential of the fourth terminal and fixing the potential of the output terminal;
A third transistor for conducting the third terminal and the second terminal in accordance with the potential of the fourth terminal and fixing the potential of the third terminal;
A semiconductor device comprising: An input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal;
A first transistor for transmitting the potential of the first terminal to the output terminal;
A rectifying element that turns on the first transistor in accordance with the potential of the input terminal;
A second transistor for conducting the output terminal and the second terminal in accordance with the potential of the fifth terminal and fixing the potential of the output terminal;
A third transistor for conducting the third terminal and the second terminal in accordance with the potential of the fourth terminal and fixing the potential of the third terminal;
A circuit that inverts the potential of the third terminal and outputs the inverted potential to the fifth terminal;
A semiconductor device comprising: An input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal;
A first transistor for transmitting the potential of the first terminal to the output terminal;
A first rectifying element that turns on the first transistor in accordance with the potential of the input terminal;
A second transistor for conducting the output terminal and the second terminal according to the potential of the fourth terminal and fixing the potential of the output terminal;
A third transistor for conducting the third terminal and the second terminal in accordance with the potential of the fourth terminal and fixing the potential of the third terminal;
A second rectifying element that raises the potential of the fifth terminal according to the potential of the output terminal;
A fourth transistor for conducting the sixth terminal and the second terminal according to the potential of the third terminal and lowering the sixth potential;
A semiconductor device comprising: An input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal; With
A first transistor for transmitting the potential of the first terminal to the output terminal;
A first rectifying element that turns on the first transistor in accordance with the potential of the input terminal;
A second transistor for electrically connecting the output terminal and the second terminal and fixing the potential of the output terminal according to the potential of the seventh terminal;
A third transistor for conducting the third terminal and the second terminal in accordance with the potential of the fourth terminal and fixing the potential of the third terminal;
A second rectifying element that raises the potential of the fifth terminal according to the potential of the output terminal;
A fourth transistor for conducting the sixth terminal and the second terminal according to the potential of the third terminal and lowering the sixth potential;
A circuit that inverts the potential of the third terminal and outputs the inverted potential to the seventh terminal;
A semiconductor device comprising: An input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a rectifying element, a first transistor, a second transistor, 3 transistors,
One electrode of the rectifying element is electrically connected to the input terminal, and the other electrode of the rectifying element is electrically connected to the third terminal,
A gate electrode of the first transistor is electrically connected to the third terminal; one of a source electrode or a drain electrode of the first transistor is electrically connected to the first terminal; The other of the source electrode and the drain electrode of the first transistor is electrically connected to the output terminal;
A gate electrode of the second transistor is electrically connected to the fourth terminal; one of a source electrode or a drain electrode of the second transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the second transistor is electrically connected to the output terminal;
A gate electrode of the third transistor is electrically connected to the fourth terminal; one of a source electrode or a drain electrode of the third transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the third transistor is electrically connected to the third terminal. An input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a rectifying element, a first transistor, 2 transistors, a third transistor, and a potential inversion circuit,
One electrode of the rectifying element is electrically connected to the input terminal, and the other electrode of the rectifying element is electrically connected to the third terminal,
A gate electrode of the first transistor is electrically connected to the third terminal; one of a source electrode or a drain electrode of the first transistor is electrically connected to the first terminal; The other of the source electrode and the drain electrode of the first transistor is electrically connected to the output terminal;
A gate electrode of the second transistor is electrically connected to the fifth terminal; one of a source electrode or a drain electrode of the second transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the second transistor is electrically connected to the output terminal;
A gate electrode of the third transistor is electrically connected to the fourth terminal; one of a source electrode or a drain electrode of the third transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the third transistor is electrically connected to the third terminal;
One electrode of the potential inverting circuit is electrically connected to the third terminal, and the other electrode of the potential inverting circuit is electrically connected to the fifth terminal. apparatus. An input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a first rectifying element A second rectifying element, a first transistor, a second transistor, a third transistor, and a fourth transistor,
One electrode of the first rectifying element is electrically connected to the input terminal, and the other electrode of the first rectifying element is electrically connected to the third terminal;
A gate electrode of the first transistor is electrically connected to the third terminal; one of a source electrode or a drain electrode of the first transistor is electrically connected to the first terminal; The other of the source electrode and the drain electrode of the first transistor is electrically connected to the output terminal;
A gate electrode of the second transistor is electrically connected to the fourth terminal; one of a source electrode or a drain electrode of the second transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the second transistor is electrically connected to the output terminal;
A gate electrode of the third transistor is electrically connected to the fourth terminal; one of a source electrode or a drain electrode of the third transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the third transistor is electrically connected to the third terminal;
One electrode of the second rectifying element is electrically connected to the output terminal, and the other electrode of the second rectifying element is electrically connected to the fifth terminal;
A gate electrode of the fourth transistor is electrically connected to the third terminal; one of a source electrode or a drain electrode of the fourth transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the sixth terminal. An input terminal, an output terminal, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a seventh terminal; A first rectifying element, a second rectifying element, a first transistor, a second transistor, a third transistor, a fourth transistor, and a potential inversion circuit;
One electrode of the first rectifying element is electrically connected to the input terminal, and the other electrode of the first rectifying element is electrically connected to the third terminal;
A gate electrode of the first transistor is electrically connected to the third terminal; one of a source electrode or a drain electrode of the first transistor is electrically connected to the first terminal; The other of the source electrode and the drain electrode of the first transistor is electrically connected to the output terminal;
A gate electrode of the second transistor is electrically connected to the seventh terminal; one of a source electrode or a drain electrode of the second transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the second transistor is electrically connected to the output terminal;
A gate electrode of the third transistor is electrically connected to the fourth terminal; one of a source electrode or a drain electrode of the third transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the third transistor is electrically connected to the third terminal;
One electrode of the second rectifying element is electrically connected to the output terminal, and the other electrode of the second rectifying element is electrically connected to the fifth terminal;
A gate electrode of the fourth transistor is electrically connected to the third terminal; one of a source electrode or a drain electrode of the fourth transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the sixth terminal,
One electrode of the potential inverting circuit is electrically connected to the third terminal, and the other electrode of the potential inverting circuit is electrically connected to the seventh terminal. apparatus. 9. The semiconductor device according to claim 1, wherein the rectifying element is a diode-connected transistor. 10. The semiconductor device according to claim 1, further comprising: a signal line that can turn on the second transistor and the third transistor. 11. 11. The semiconductor device according to claim 1, further comprising a signal line that can apply a reverse bias to the second transistor and the third transistor. 12. The semiconductor device according to claim 1, wherein a signal input to the first terminal has a duty ratio smaller than 50%. 13. The area of the gate electrode of the second transistor and the area of the gate electrode of the third transistor according to any one of claims 1 to 12 is greater than the area of the gate electrode of the first transistor. A large semiconductor device. The wiring according to any one of claims 1 to 13, wherein the wiring electrically connected to the second terminal and the wiring electrically connected to the first terminal are the first transistor, A semiconductor device, wherein the second transistor and the third transistor are arranged on a side opposite to the output terminal. In any one of Claims 1 thru | or 14,
A first wiring layer, a second wiring layer, a third wiring layer,
Having an insulating film and an interlayer film;
The insulating film is formed between the first wiring layer and the second wiring layer;
The interlayer film is formed between the second wiring layer and the third wiring layer,
The interlayer film is formed thicker than the insulating film,
The electrode electrically connected to the first terminal is formed of at least the second wiring layer,
The electrode electrically connected to the output terminal is formed of at least the first wiring layer and the third wiring layer,
In the region where the electrode electrically connected to the output terminal and the electrode electrically connected to the first terminal intersect, the electrode electrically connected to the output terminal is connected to the third wiring. A semiconductor device comprising a layer. The semiconductor device according to any one of claims 1 to 15,
A semiconductor device formed on the same substrate as a substrate on which a pixel region is formed. The semiconductor device according to any one of claims 1 to 16,
A semiconductor device, wherein the semiconductor device is disposed as an IC on the same substrate as a substrate in which a pixel region is formed, and is connected to wiring on the substrate by a COG method. The semiconductor device according to any one of claims 1 to 17,
A semiconductor device, wherein the semiconductor device is disposed as an IC on a connection wiring substrate connected to a substrate forming a pixel region, and is connected to the wiring on the substrate by a TAB method. A first terminal, a second terminal, a third terminal, a transistor, and a rectifying element;
A gate electrode of the transistor is electrically connected to the second terminal, and one of a source electrode or a drain electrode of the transistor is electrically connected to the first terminal, and a source electrode or a drain of the transistor The other electrode is electrically connected to the third terminal;
One of the electrodes of the rectifying element is electrically connected to the third terminal, and the other of the electrodes of the rectifying element is electrically connected to the second terminal. apparatus. A first terminal, a second terminal, a third terminal, a fourth terminal, a first transistor, and a second transistor;
A gate electrode of the first transistor is electrically connected to the second terminal; one of a source electrode or a drain electrode of the first transistor is electrically connected to the first terminal; The other of the source electrode and the drain electrode of the first transistor is connected to the third terminal;
A gate electrode of the second transistor is electrically connected to the fourth terminal; one of a source electrode or a drain electrode of the second transistor is electrically connected to the second terminal; The other of the source electrode and the drain electrode of the second transistor is electrically connected to the third terminal. A semiconductor device according to any one of claims 1 to 20, an external drive circuit, and a connection wiring board,
The display device, wherein the semiconductor device and the external drive circuit are connected by a single connection wiring board. An electronic apparatus using the display device according to claim 21.

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