CN114120884A - Display panel light-emitting drive circuit and display panel - Google Patents
Display panel light-emitting drive circuit and display panel Download PDFInfo
- Publication number
- CN114120884A CN114120884A CN202010901933.3A CN202010901933A CN114120884A CN 114120884 A CN114120884 A CN 114120884A CN 202010901933 A CN202010901933 A CN 202010901933A CN 114120884 A CN114120884 A CN 114120884A
- Authority
- CN
- China
- Prior art keywords
- transistor
- gate
- source
- drain
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 16
- 230000000694 effects Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 238000007599 discharging Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
Abstract
The application provides a display panel light-emitting drive circuit and a display panel, and relates to the technical field of display. The display panel light-emitting drive circuit comprises a first output control module, a first output module, a second output control module and a second output module, wherein the first output module comprises a first transistor, the second output module comprises a second transistor, the second output control module comprises a third transistor, and a first source drain electrode of the third transistor is connected with a grid electrode of the second transistor; the gate of the third transistor is periodically inputted with a high level, and the second source-drain of the third transistor is inputted with a low level signal when the first transistor is in an on state, and transmits the low level signal to the gate of the second transistor when the gate signal of the third transistor is at the high level. The display panel light-emitting drive circuit and the display panel have the effect that high level voltage is higher.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel light-emitting driving circuit and a display panel.
Background
With the development of optical technology and semiconductor technology, flat panel displays represented by liquid crystal displays and organic light emitting diode displays have the characteristics of lightness, thinness, low energy consumption, high reaction speed, good color purity, high contrast ratio and the like, and occupy a leading position in the display field.
In the current panel driving design, different scan signals in the pixel driving circuit need to be routed separately, so two architectures of Gate D-IC On Array (GOA) and EOA (Emission D-IC On Array (EOA) are required to provide different scan signals.
In the light-emitting driving circuit of the EOA display panel, at present, when a high-potential driving signal is output, the voltage of the high-potential driving signal is not high enough, and thus the charging and discharging of pixels in a display area are influenced.
Disclosure of Invention
An object of the present application is to provide a light-emitting driving circuit of a display panel and a display panel, so as to solve the problem in the prior art that the voltage of a high-potential driving signal is not high enough.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in one aspect, an embodiment of the present application provides a light-emitting driving circuit for a display panel, where the light-emitting driving circuit for the display panel includes a first output control module, a first output module, a second output control module, and a second output module, where the first output module includes a first transistor, and a gate of the first transistor is connected to an output end of the first output control module; the second output module comprises a second transistor, and the grid electrode of the second transistor is connected with the output end of the second output control module; the first source drain electrode of the first transistor and the first source drain electrode of the second transistor are respectively connected to an output port; the first output control module transmits a high potential to the gate of the first transistor, and when the gate of the first transistor is at the high potential, the first transistor is turned on, and a signal of a second source drain of the first transistor is transmitted to the output port; the second output control module transmits a high potential to the grid electrode of the second transistor, and when the grid electrode of the second transistor is at the high potential, the second transistor is conducted, and a signal of a second source drain electrode of the second transistor is transmitted to the output port; the second output control module comprises a third transistor, and a first source drain electrode of the third transistor is connected with a grid electrode of the second transistor; the gate of the third transistor is periodically input with a high level, and the second source-drain of the third transistor inputs a low level signal when the first transistor is in a conducting state, and transmits the low level signal to the gate of the second transistor when the gate signal of the third transistor is at the high level.
Optionally, first source-drain electrodes of the first transistor, the second transistor, and the third transistor are a source electrode or a drain electrode, and second source-drain electrodes of the first transistor, the second transistor, and the third transistor are a drain electrode or a source electrode.
Optionally, the second output control module further includes a fourth transistor, a first source drain of the fourth transistor is connected to the gate of the second transistor, and a second source drain of the fourth transistor transmits a low-level signal to the second transistor when a high-level signal input to the gate of the fourth transistor is turned on.
Optionally, when a high-level signal is input to the second source-drain of the third transistor, and when a gate signal of the third transistor is at a high level, the third transistor transmits the high-level signal to the gate of the second transistor, and the first transistor is in an off state.
Optionally, the second output control module further includes a fifth transistor, a gate of the fifth transistor is connected to the gate of the second transistor, a first source drain of the fifth transistor is connected to the gate of the first transistor, and the third transistor is further configured to transmit the high-level signal to the gate of the fifth transistor while transmitting the high-level signal to the gate of the second transistor; and a second source drain of the fifth transistor is used for inputting a low level signal and transmitting the low level signal to the gate of the first transistor when the gate signal of the fifth transistor is at a high level.
Optionally, a second source-drain of the third transistor inputs a low-level signal when the first transistor is in an on state, and transmits the low-level signal to a gate of the fifth transistor when a gate signal of the third transistor is at a high level, so that the fifth transistor is in an off state.
Optionally, the first output module further includes a sixth transistor, a gate of the sixth transistor is connected to the first source-drain of the first transistor, the first source-drain of the sixth transistor is connected to the gate of the first transistor, and the second source-drain of the sixth transistor inputs a high level signal when the first transistor is in a conducting state, and transmits the high level signal to the gate of the first transistor when the gate signal of the sixth transistor is at a high level.
Optionally, the first output module further includes a storage capacitor, and two ends of the storage capacitor are respectively connected to the gate and the first source/drain of the first transistor.
Optionally, the first output control module includes a seventh transistor, a first source drain of the seventh transistor is connected to the gate of the first transistor, and a second source drain of the seventh transistor transmits a high potential to the gate of the first transistor when the seventh transistor is turned on.
On the other hand, the embodiment of the application also provides a display panel, and the display panel comprises the display panel light-emitting driving circuit.
Compared with the prior art, the embodiment of the application has the following beneficial effects:
the application provides a display panel light-emitting drive circuit and a display panel, wherein the display panel light-emitting drive circuit comprises a first output control module, a first output module, a second output control module and a second output module, the first output module comprises a first transistor, and the grid electrode of the first transistor is connected with the output end of the first output control module; the second output module comprises a second transistor, and the grid electrode of the second transistor is connected with the output end of the second output control module; a first source drain electrode of the first transistor and a first source drain electrode of the second transistor are respectively connected to an output port; the first output control module transmits a high potential to the grid electrode of the first transistor, when the grid electrode of the first transistor is at the high potential, the first transistor is conducted, and a signal of a second source drain electrode of the first transistor is transmitted to the output port; the second output control module transmits a high potential to the grid electrode of the second transistor, when the grid electrode of the second transistor is the high potential, the second transistor is conducted, and a signal of a second source drain electrode of the second transistor is transmitted to the output port; the second output control module comprises a third transistor, and a first source drain electrode of the third transistor is connected with a grid electrode of the second transistor; the gate of the third transistor is periodically inputted with a high level, and the second source-drain of the third transistor is inputted with a low level signal when the first transistor is in an on state, and transmits the low level signal to the gate of the second transistor when the gate signal of the third transistor is at the high level. Because the second source drain of the third transistor inputs the low level signal when the first transistor is turned on and transmits the low level signal to the gate of the second transistor, the second transistor can be ensured to be in a stable cut-off state when the first transistor outputs the high level, the high level output by the first transistor cannot be influenced, and the effect that the high-point level voltage is higher is realized.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a block diagram of a display panel light-emitting driving circuit according to an embodiment of the present disclosure.
Fig. 2 is a circuit diagram of a display panel light-emitting driving circuit according to an embodiment of the present disclosure.
Fig. 3 is an equivalent circuit diagram of an NMOS transistor according to an embodiment of the present application.
In the figure: 100-display panel light emitting driving circuit; 110-a first output control module; 120-a first output module; 130-a second output control module; 140-a second output module; 150-output port; m1 — first transistor; m2 — second transistor; m3 — third transistor; m4 — fourth transistor; m5 — fifth transistor; m6 — sixth transistor; m7-seventh transistor; c2-storage capacitor.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
As described in the background art, the conventional EOA display panel light-emitting driving circuit has a problem that the voltage of a high-potential driving signal is not high enough to affect the charging and discharging of pixels in a display area.
In view of the above, the present application provides a scan driving method to solve the problem that the voltage of the high-potential driving signal is not high enough. The following provides an exemplary description of a display panel light emission driving circuit provided in an embodiment of the present application:
as an optional implementation manner, please refer to fig. 1, the display panel light-emitting driving circuit 100 includes a first output control module 110, a first output module 120, a second output control module 130, and a second output module 140, wherein the first output control module 110 is electrically connected to the first output module 120, the second output control module 130 is electrically connected to the second output module 140, the first output control module 110, and the first output module 120 and the second output module 140 are electrically connected to an output port 150, respectively.
Referring to fig. 2, the first output module 120 includes a first transistor M1, a gate of the first transistor M1 is connected to the output terminal of the first output control module 110; the second output module 140 includes a second transistor M2, a gate of the second transistor M2 is connected to the output terminal of the second output control module 130; a first source drain of the first transistor M1 and a first source drain of the second transistor M2 are respectively connected to an output port 150.
In this application, the first output control module 110 transmits a high voltage to the gate of the first transistor M1, and when the gate of the first transistor M1 is at the high voltage, the first transistor M1 is turned on, and a signal of the second source/drain of the first transistor M1 is transmitted to the output port 150. The second output control module 130 transmits a high voltage to the gate of the second transistor M2, and when the gate of the second transistor M2 is at the high voltage, the second transistor M2 is turned on, and a signal of the second source/drain of the second transistor M2 is transmitted to the output port 150.
The second output control module 130 includes a third transistor M3, and a first source-drain of the third transistor M3 is connected to the gate of the second transistor M2; the gate of the third transistor M3 is periodically inputted with a high level, the second source-drain of the third transistor M3 is inputted with a low level signal in a state where the first transistor M1 is turned on, and the low level signal is transmitted to the gate of the second transistor M2 when the gate signal of the third transistor M3 is at a high level.
By setting the manner that the gate of the third transistor M3 periodically inputs a high level and the second source-drain of the third transistor M3 inputs a low level signal when the first transistor M1 is in an on state, the second transistor M2 can always input a low level when the first transistor M1 is in an on state, so that the second transistor M2 is in a stable off state when the first transistor M1 is in an on state, the high level output by the first transistor M1 cannot be interfered, and the voltage of the high level driving signal output by the first transistor M1 is ensured to be sufficiently high.
In the present application, when the first transistor M1 is turned on, a high level is output to the output port 150; when the second transistor M2 is turned on, a low level is output to the output port 150. In addition, the high level and the low level are only a relative concept, and in practical applications, the high level signal and the low level signal may be defined according to actual requirements, for example, in one possible embodiment, the high level signal refers to a signal with a voltage greater than or equal to 3V, and the low level signal refers to a signal with a voltage less than 3V. In another possible embodiment, the high voltage signal refers to a signal with a voltage value of about 15V, and the low voltage signal refers to a signal with a voltage value of about-15V, which is not limited in this application.
It should be further noted that the EOA circuit further includes a pixel circuit, and the output port 150 described herein is electrically connected to the pixel circuit, so that the first output module 120 and the second output module 140 can select a high level or a low level to output to the pixel circuit, and further drive the pixel circuit to operate.
In one driving cycle, the first output control module 110 and the second output control module 130 respectively control the first output module 120 and the second output module 140 in different time periods, so that the display panel light-emitting driving circuit 100 outputs a high level in a part of the time period of the one driving cycle and outputs a low level in another part of the time period.
In addition, the transistors may be transistors such as a transistor or a MOS transistor, and when the transistors are MOS transistors, the first source/drain electrodes of the first transistor M1, the second transistor M2, and the third transistor M3 are source electrodes or drain electrodes, and the second source/drain electrodes of the first transistor M1, the second transistor M2, and the third transistor M3 are drain electrodes or source electrodes. For example, for the first transistor M1, when the first source/drain is the source, the second source/drain is the drain; when the first source/drain is a drain, the second source/drain is a source, as follows.
The MOS transistor is taken as an example for explanation in the present application, and on this basis, the types of the switching transistor in the present application can be divided into three cases:
first, all transistors are NMOS transistors.
In the second type, part of the transistors are NMOS transistors, and part of the transistors are PMOS transistors.
Thirdly, all transistors are PMOS tubes. And are not limited herein.
For convenience of description, all transistors are referred to as NMOS transistors in this application.
Among them, the present application achieves an effect that the voltage of the high potential driving signal is sufficiently high by using the third transistor M3. The specific working principle is as follows:
when all the transistors are NMOS transistors, the equivalent circuit diagram of the third transistor M3 is shown in fig. 3, and it can be seen from the diagram that the capacitors are respectively connected to the first source drain and the second source drain of the third transistor M3. Further, when the gate input high level of the third transistor M3 is turned on, the third transistor M3 transmits a high potential to the gate of the second transistor M2, so that the second transistor M2 is turned on, and the capacitor in the third transistor M3 is actually charged. When the gate input high level of the third transistor M3 is in a conducting state and the second source-drain input low level, the electric quantity stored in the capacitor can be discharged.
In other words, upon turning on the third transistor M3, the capacitor in the third transistor M3 stores energy. When the gate of the third transistor M3 is inputted with a high level and the second source-drain is inputted with a low level, the capacitor is discharged.
It should be noted that, when the amount of energy stored in the capacitor cannot be discharged, the gate voltage of the second transistor M2 is affected, so that Vgs between the gate and the source of the second transistor M2 is greater than 0. Also, it can be understood that when the output port 150 of the display panel light emission driving circuit 100 outputs a high potential signal, the second source-drain of the first transistor M1 outputs a high level to the output port 150. On the basis, if Vgs of the second transistor M2 is greater than 0, a part of current output from the first transistor M1 to the output port 150 leaks, and a high-level voltage output from the first transistor to the output port 150 is reduced, so that the voltage of the high-potential driving signal is not high enough, which affects charging and discharging of pixels in the display area.
And through the connection mode that this application set up, can be when first transistor M1 is in the on-state, the gate input high level of third transistor M3, and the low level signal of second source drain input, and then can bleed the electric quantity in the electric capacity, and then the circumstances that Vgs of second transistor M2 > 0 can not appear, still can pull down the gate voltage of second transistor M2 simultaneously for second transistor M2 is in stable off-state, can not cause the influence to the high level of first transistor M1 output, and then can not influence the voltage of high potential drive signal and the regional pixel of display and charge-discharge.
Similarly, when some transistors in the display panel light-emitting driving circuit 100 are NMOS transistors and some transistors are PMOS transistors, for example, when the third transistor M3 is a PMOS transistor, the PMOS transistor also includes a capacitor, and when a low-potential signal is input to the gate and a high-potential signal is input to the second source/drain, the third transistor M3 is turned on and the internal capacitor stores energy. Further, when the display panel light-emitting driving circuit 100 outputs a high-potential driving signal, the voltage of the high-potential driving signal is not high enough due to the influence of the capacitor energy storage.
In order to further ensure that the first transistor M1 is not affected by the second transistor M2 when outputting a high-level signal to the output port 150, as an implementation manner, the second output control module 130 further includes a fourth transistor M4, a first source-drain of the fourth transistor M4 is connected to the gate of the second transistor M2, and a second source-drain of the fourth transistor M4 transmits a low-level signal to the second transistor M2 when the gate of the fourth transistor M4 inputs a high-level signal and is turned on. Meanwhile, the fourth transistor M4 is turned on when the first transistor M1 is turned on, thereby playing a role of pulling the gate voltage of the second transistor M2 low. In other words, the fourth transistor M4 and the third transistor M3 can cooperate to ensure that the second transistor M2 does not affect the high level signal output by the first transistor M1.
Also, it can be understood that when the second transistor M2 is turned on to output a low level to the output port 150, the first transistor M1 is also in a stable off state. At this time, a high level signal is input to the second source/drain of the third transistor M3, and when the gate signal of the third transistor M3 is at a high level, the high level signal is transmitted to the gate of the second transistor M2, so that the second source/drain of the second transistor M2 outputs a low level to the output port 150, and the first transistor is turned off.
On this basis, as an optional implementation manner, the second output control module 130 further includes a fifth transistor M5, a gate of the fifth transistor M5 is connected to the gate of the second transistor M2, a first source-drain of the fifth transistor M5 is connected to the gate of the first transistor M1, and the third transistor M3 is further configured to transmit a high-level signal to the gate of the fifth transistor M5 at the same time when the high-level signal is transmitted to the gate of the second transistor; the second source-drain of the fifth transistor M5 is used for inputting a low-level signal, and transmits the low-level signal to the gate of the first transistor M1 when the gate signal of the fifth transistor M5 is at a high level.
That is, by providing the fifth transistor M5, the third transistor M3 can transmit a high-level signal to the gate of the second transistor M2 to turn on the second transistor M2, and at the same time, can transmit a high-level signal to the gate of the fifth transistor M5 to turn on the fifth transistor M5, and transmit a low-level signal to the gate of the first transistor M1 to pull down the gate voltage of the first transistor M1, and further to turn off the first transistor M1 stably, so that the low-level signal output by the first transistor M1 is not affected.
In addition to the fifth transistor M5, when the first transistor M1 is turned on, if the third transistor M3 is affected by capacitance, the gate voltage of the fifth transistor M5 may be pulled low, so that the high level output by the first output control module 110 is pulled low by the fifth transistor M5. Therefore, the second source-drain of the third transistor M3 receives a low-level signal when the first transistor M1 is turned on, and when the gate signal of the third transistor M3 is at a high level, the low-level signal is transmitted to the second transistor M2, and at the same time, the low-level signal is transmitted to the gate of the fifth transistor M5, so that the gate voltage of the fifth transistor M5 is pulled low, and the fifth transistor M5 is turned off.
As an implementation manner, in order to enable the first transistor M1 to operate stably when outputting a high-level signal to the output port 150, the first output module 120 provided in the present application further includes a sixth transistor M6, a gate of the sixth transistor M6 is connected to a first source-drain of the first transistor M1, a first source-drain of the sixth transistor M6 is connected to a gate of the first transistor M1, and a second source-drain of the sixth transistor M6 is configured to input a high-level signal when the first transistor M1 is turned on, and to transmit the high-level signal to the gate of the first transistor M1 when the gate signal of the sixth transistor M6 is at a high level.
It can be understood that, through the connection relationship, when the first transistor M1 is turned on under the control of the first output control module 110 and outputs a high level signal, the high level signal is simultaneously transmitted to the gate of the sixth transistor M6, so that the sixth transistor M6 is turned on, and after being turned on, the second source-drain of the sixth transistor M6 transmits the high level signal to the gate of the first transistor M1. In this scenario, even if the high level voltage supplied to the first transistor M1 by the first output control module 110 fluctuates, the high level signal is input to the gate of the first transistor M1 due to the high level signal output by the sixth transistor M6, so that the high level signal at the gate of the first transistor M1 can be stabilized, and the operation of the entire display panel light-emitting driving circuit 100 is more stable.
Optionally, in order to protect the first transistor M1, the first output module 120 further includes a storage capacitor C2, and two ends of the storage capacitor C2 are respectively connected to the gate and the first source/drain of the first transistor M1.
Optionally, the first output control module 110 includes a seventh transistor M7, a first source-drain of the seventh transistor M7 is connected to the gate of the first transistor M1, and a second source-drain of the seventh transistor M7 transmits a high potential to the gate of the first transistor M1 when the seventh transistor M7 is turned on.
Based on the foregoing embodiments, the present application further provides a display panel, which includes the foregoing display panel light-emitting driving circuit 100.
In summary, the present application provides a display panel light-emitting driving circuit and a display panel, where the display panel light-emitting driving circuit includes a first output control module, a first output module, a second output control module, and a second output module, the first output module includes a first transistor, and a gate of the first transistor is connected to an output end of the first output control module; the second output module comprises a second transistor, and the grid electrode of the second transistor is connected with the output end of the second output control module; a first source drain electrode of the first transistor and a first source drain electrode of the second transistor are respectively connected to an output port; the first output control module transmits a high potential to the grid electrode of the first transistor, when the grid electrode of the first transistor is at the high potential, the first transistor is conducted, and a signal of a second source drain electrode of the first transistor is transmitted to the output port; the second output control module transmits a high potential to the grid electrode of the second transistor, when the grid electrode of the second transistor is the high potential, the second transistor is conducted, and a signal of a second source drain electrode of the second transistor is transmitted to the output port; the second output control module comprises a third transistor, and a first source drain electrode of the third transistor is connected with a grid electrode of the second transistor; the gate of the third transistor is periodically inputted with a high level, and the second source-drain of the third transistor is inputted with a low level signal when the first transistor is in an on state, and transmits the low level signal to the gate of the second transistor when the gate signal of the third transistor is at the high level. Because the second source drain of the third transistor inputs the low level signal when the first transistor is turned on and transmits the low level signal to the gate of the second transistor, the second transistor can be ensured to be in a stable cut-off state when the first transistor outputs the high level, the high level output by the first transistor cannot be influenced, and the effect that the high-point level voltage is higher is realized.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. The display panel light-emitting driving circuit is characterized by comprising a first output control module, a first output module, a second output control module and a second output module, wherein the first output module comprises a first transistor, and the grid electrode of the first transistor is connected with the output end of the first output control module; the second output module comprises a second transistor, and the grid electrode of the second transistor is connected with the output end of the second output control module; the first source drain electrode of the first transistor and the first source drain electrode of the second transistor are respectively connected to an output port;
the first output control module transmits a high potential to the gate of the first transistor, and when the gate of the first transistor is at the high potential, the first transistor is turned on, and a signal of a second source drain of the first transistor is transmitted to the output port;
the second output control module transmits a high potential to the grid electrode of the second transistor, and when the grid electrode of the second transistor is at the high potential, the second transistor is conducted, and a signal of a second source drain electrode of the second transistor is transmitted to the output port;
the second output control module comprises a third transistor, and a first source drain electrode of the third transistor is connected with a grid electrode of the second transistor; the gate of the third transistor is periodically input with a high level, and the second source-drain of the third transistor inputs a low level signal when the first transistor is in a conducting state, and transmits the low level signal to the gate of the second transistor when the gate signal of the third transistor is at the high level.
2. The display panel light-emitting driving circuit according to claim 1, wherein first source-drain electrodes of the first transistor, the second transistor, and the third transistor are a source electrode or a drain electrode, and second source-drain electrodes of the first transistor, the second transistor, and the third transistor are a drain electrode or a source electrode.
3. The light-emitting driving circuit of a display panel according to claim 1, wherein the second output control module further comprises a fourth transistor, a first source drain of the fourth transistor is connected to the gate of the second transistor, and a second source drain of the fourth transistor transmits a low-level signal to the second transistor when a high-level signal is input to the gate of the fourth transistor and turned on.
4. The light-emitting driving circuit of a display panel according to claim 1, wherein when a high-level signal is input to the second source drain of the third transistor and when a gate signal of the third transistor is at a high level, the third transistor transmits the high-level signal to the gate of the second transistor, and the first transistor is in an off state.
5. The display panel light-emitting driving circuit according to claim 4, wherein the second output control module further comprises a fifth transistor, a gate of the fifth transistor is connected to the gate of the second transistor, a first source drain of the fifth transistor is connected to the gate of the first transistor, and the third transistor is further configured to simultaneously transmit the high-level signal to the gate of the fifth transistor when transmitting the high-level signal to the gate of the second transistor; and a second source drain of the fifth transistor is used for inputting a low level signal and transmitting the low level signal to the gate of the first transistor when the gate signal of the fifth transistor is at a high level.
6. The light-emission driving circuit of a display panel according to claim 5, wherein a low-level signal is input to the second source-drain of the third transistor in an on state of the first transistor, and when a gate signal of the third transistor is at a high level, the low-level signal is transmitted to the gate of the fifth transistor so that the fifth transistor is in an off state.
7. The light-emitting driving circuit of a display panel according to claim 1, wherein the first output module further includes a sixth transistor, a gate of the sixth transistor is connected to the first source/drain of the first transistor, the first source/drain of the sixth transistor is connected to the gate of the first transistor, and the second source/drain of the sixth transistor inputs a high-level signal when the first transistor is in an on state, and transmits the high-level signal to the gate of the first transistor when the gate signal of the sixth transistor is at a high level.
8. The light-emitting driving circuit of a display panel according to claim 1, wherein the first output module further comprises a storage capacitor, and two ends of the storage capacitor are respectively connected to the gate and the first source/drain of the first transistor.
9. The light-emitting driving circuit of the display panel according to claim 1, wherein the first output control module comprises a seventh transistor, a first source drain of the seventh transistor is connected to a gate of the first transistor, and a second source drain of the seventh transistor transmits a high potential to the gate of the first transistor when the seventh transistor is turned on.
10. A display panel comprising the display panel light emission driving circuit according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010901933.3A CN114120884A (en) | 2020-09-01 | 2020-09-01 | Display panel light-emitting drive circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010901933.3A CN114120884A (en) | 2020-09-01 | 2020-09-01 | Display panel light-emitting drive circuit and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114120884A true CN114120884A (en) | 2022-03-01 |
Family
ID=80360213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010901933.3A Pending CN114120884A (en) | 2020-09-01 | 2020-09-01 | Display panel light-emitting drive circuit and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114120884A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001101889A (en) * | 1999-09-27 | 2001-04-13 | Casio Comput Co Ltd | Shift register and electronic equipment |
| JP2002057562A (en) * | 2000-08-07 | 2002-02-22 | Mitsubishi Electric Corp | High speed pulse output device for output transistor for high breakdown voltage |
| CN102113216A (en) * | 2008-08-11 | 2011-06-29 | 夏普株式会社 | Capacitance load drive circuit and display device using the same |
| CN104318883A (en) * | 2014-10-10 | 2015-01-28 | 北京大学深圳研究生院 | Shift register and unit thereof, display and threshold voltage compensation circuit |
| US20150248940A1 (en) * | 2013-04-24 | 2015-09-03 | Boe Technology Group Co., Ltd. | Shift register unit and display device |
| CN105096833A (en) * | 2015-08-26 | 2015-11-25 | 京东方科技集团股份有限公司 | Circuit and method for generating luminous control signals and driving method for pixel circuit |
| CN105632563A (en) * | 2016-01-05 | 2016-06-01 | 京东方科技集团股份有限公司 | Shifting register, grid-driven circuit and display device |
| CN106023946A (en) * | 2016-08-04 | 2016-10-12 | 京东方科技集团股份有限公司 | Shifting register and drive method thereof, grid drive device and display device |
| CN108615498A (en) * | 2018-05-14 | 2018-10-02 | 昆山龙腾光电有限公司 | Gate driving circuit, display panel and display device |
| CN111373469A (en) * | 2017-12-01 | 2020-07-03 | 深圳市柔宇科技有限公司 | Liquid crystal display panel and EOA module thereof |
-
2020
- 2020-09-01 CN CN202010901933.3A patent/CN114120884A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001101889A (en) * | 1999-09-27 | 2001-04-13 | Casio Comput Co Ltd | Shift register and electronic equipment |
| JP2002057562A (en) * | 2000-08-07 | 2002-02-22 | Mitsubishi Electric Corp | High speed pulse output device for output transistor for high breakdown voltage |
| CN102113216A (en) * | 2008-08-11 | 2011-06-29 | 夏普株式会社 | Capacitance load drive circuit and display device using the same |
| US20150248940A1 (en) * | 2013-04-24 | 2015-09-03 | Boe Technology Group Co., Ltd. | Shift register unit and display device |
| CN104318883A (en) * | 2014-10-10 | 2015-01-28 | 北京大学深圳研究生院 | Shift register and unit thereof, display and threshold voltage compensation circuit |
| CN105096833A (en) * | 2015-08-26 | 2015-11-25 | 京东方科技集团股份有限公司 | Circuit and method for generating luminous control signals and driving method for pixel circuit |
| CN105632563A (en) * | 2016-01-05 | 2016-06-01 | 京东方科技集团股份有限公司 | Shifting register, grid-driven circuit and display device |
| CN106023946A (en) * | 2016-08-04 | 2016-10-12 | 京东方科技集团股份有限公司 | Shifting register and drive method thereof, grid drive device and display device |
| CN111373469A (en) * | 2017-12-01 | 2020-07-03 | 深圳市柔宇科技有限公司 | Liquid crystal display panel and EOA module thereof |
| KR20200089328A (en) * | 2017-12-01 | 2020-07-24 | 선전 로욜 테크놀로지스 컴퍼니 리미티드 | Liquid crystal display panel and its EOA module |
| CN108615498A (en) * | 2018-05-14 | 2018-10-02 | 昆山龙腾光电有限公司 | Gate driving circuit, display panel and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10714005B2 (en) | Pixel compensation circuit and method of driving the same, display panel, and display device | |
| US8963907B2 (en) | Pixel circuit and driving method thereof | |
| CN109509433B (en) | Pixel circuit, display device and pixel driving method | |
| CN103778889B (en) | Organic light emitting diode circuit and driving method thereof | |
| US10290260B2 (en) | Pixel circuit having third drive circuit connected to first drive circuit and second drive circuit respectively, display panel and driving method | |
| KR101581147B1 (en) | Sensing circuit for external compensation, sensing method thereof and display apparatus | |
| CN100590691C (en) | Display and its pixel circuit | |
| US8605077B2 (en) | Display device | |
| US9489894B2 (en) | Pixel circuit and driving method thereof, and thin film transistor backboard | |
| CN109285504B (en) | Shifting register unit, driving method thereof and grid driving circuit | |
| CN104700783B (en) | The driving method of pixel-driving circuit | |
| US20140132642A1 (en) | Pixel circuit, display device and driving method of pixel circuit | |
| CN101859542B (en) | Organic light emitting diode display device and organic light emitting diode pixel circuit thereof | |
| US10235941B2 (en) | Pixel circuit | |
| US10600366B2 (en) | OLED driving circuit and AMOLED display panel | |
| US10991289B2 (en) | Memory-in-pixel circuit, driving method thereof, array substrate, and display apparatus | |
| CN103198793A (en) | Pixel circuit, drive method and display device thereof | |
| CN103035202A (en) | Pixel compensating circuit | |
| CN106067291A (en) | A kind of pixel-driving circuit and driving method, display device | |
| US20140368487A1 (en) | Pixel driver | |
| CN104036725A (en) | Pixel circuit and driving method, organic light emitting display panel and display device thereof | |
| CN111354308A (en) | Pixel driving circuit, organic light-emitting display panel and display device | |
| US20190164500A1 (en) | Oled pixel circuit and method for driving the same, display apparatus | |
| CN1996446A (en) | Pixel unit and related display panel, and display and electronic device utilizing the same | |
| CN103198788A (en) | Pixel circuit, organic electroluminescence display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20220301 |