JPH06104292A - Shift resistor - Google Patents

Abstract

PURPOSE:To start shift operation from midway and to magnify the image of a specified area to a one-scope size and display it by installing an input circuit constituted of a plurality of circuits which transmit an input signal on the input side of a midway circuit of a midway shift resistor including an initial- stage circuit. CONSTITUTION:A MOSFET Q12 performs storing and outputting operations. The MOSFET Q12 uses its gate capacitor as a storing device. At a gate of an initial-state MOSFET Q12, a first input circuit constituted of a diode-type MOSFET Q1 is installed. A MOSFET Q11 works as a one-way element which transmits a high-level signal V2 of a source side of the MOSFET Q12. A circuit constituted of the MOSFET Q11 or Q15 is a half-bit unit circuit which constitutes a shift resistor. A pair of the half-half unit circuits constitutes a one-bit unit circuit. A plurality of one-bit circuits are installed to build a shift resistor of a plurality of bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register, and is used, for example, in a solid-state image pickup device used in a camera-integrated color VTR (video tape recorder) equipped with a zoom mode or a surveillance camera. It is related to effective technology.

[0002]

2. Description of the Related Art Regarding an image pickup apparatus using a solid-state image pickup element, there is, for example, "CCD Camera Technology" by Hiroo Takemura, published by Radio Technology Co., Ltd., November 3, 1986.

[0003]

Zooming in a VTR camera is performed using a zoom lens. It is desired to increase the magnification of this zoom function. However, in order to increase the zoom magnification, a large number of lenses are required, and the lens part becomes large, which is a major cause of hindering the miniaturization and weight reduction and the cost reduction of the camera part for VTR and surveillance. is there. An object of the present invention is to provide a shift register that enables a shift operation from the middle according to a zoom mode or the like. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a first MOSFET is used in which a first timing signal is input to the drain and an output signal is sent from the source, using the gate capacitance as a storage means,
A dynamic shift register is configured by using a circuit including a bootstrap capacitance between the gate and the source and a unidirectional element for transmitting the signal of the source of the first MOSFET as a half bit, and a circuit through the unidirectional element. An input circuit including a plurality of input signals is provided to each input of the intermediate circuit of the shift register including the initial stage circuit.

[0005]

According to the above-mentioned means, the shift operation for forming the scanning signal can start the shift operation from the middle, so that the image of the fixed area on the image pickup surface can be of the size of one screen by a simple circuit operation. It enables electronic zooming by enlarging and displaying.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a screen configuration diagram for explaining the reading function of a solid-state image pickup device using a shift register according to the present invention. In the same figure, in the following description, up, down, left and right are defined corresponding to the orientation of the character. The screen configuration of the solid-state image sensor consists of an optical black section (a light-shielding section that serves as a reference for optical black) on the left and upper sides as shown by the diagonal lines in the figure, and an effective light-receiving section (vertical) that converts incident light into a video signal. Is V and the horizontal is H). A photoelectric conversion element such as a photodiode is two-dimensionally arranged corresponding to the light receiving section, and a horizontal switch MOSF for selecting it is provided.
An ET and a vertical switch MOSFET are provided.

Although not particularly limited, the matrix structure of photoelectric conversion elements and switch MOSFETs (insulated gate type field effect transistors) forming these light receiving portions is a known TSL (Transversal Signal Line) system. That is, one pixel cell is composed of a photodiode and a series circuit of a MOSFET whose gate is coupled to a vertical scanning line and a MOSFET whose gate is coupled to a horizontal scanning line. Similar pixel cells arranged in the same row (horizontal direction) are coupled to horizontal signal lines extending in the horizontal direction. The horizontal signal line is coupled to a vertical output line extending in the vertical direction through a switch MOSFET having a gate coupled to the vertical scanning line, and a read amplifier is provided.

The vertical shift register VSR and the horizontal shift register HSR form a scanning signal for reading out the above-mentioned two-dimensionally arranged photoelectric conversion elements in a fixed order. That is, the vertical shift register VSR forms the scanning signal selected by the vertical scanning line from the bottom to the top in FIG. The horizontal shift register HSR forms a scanning signal for selecting a horizontal scanning line from left to right in the figure.

In this embodiment, in order to add an electronic zoom function, the horizontal shift register HSR skips the portion corresponding to H / 4 of the screen after forming the scanning signal of the optical black portion. ), The scanning signal is formed in the area of H / 2 minutes at half the normal frequency. In other words, the horizontal shift register HSR is
The scanning signals from H / 4 to 3H / 4 are shifted from the left side of the light receiving unit by skipping the shaded portions in the figure at half the normal frequency, and the horizontal scanning line selection signal corresponding to each is shifted. To form.

Similarly, the vertical shift register VSR is added with a function of scanning by skipping over a hatched portion in FIG. That is, the vertical shift register VS
R jumps V / 4 from below the light receiving portion, starts the scanning operation from V / 4, and in other words, V / 2, in other words,
A scanning signal for scanning the area from V / 4 to 3V / 4 at a frequency half the normal frequency is formed, and V on the upper side of the screen is formed.
/ 4 jumps again to form an optical black scanning signal. In vertical scanning, non-interlaced scanning is performed during the V / 2 period in order to match the number of scanning lines. That is, as will be described later,
For vertical scanning, in the normal mode, an interlace gate circuit is provided from the viewpoint of preventing afterimages, and two lines are simultaneously read out by dividing one line into an odd field and an even field, and the spatial center of gravity corresponding to interlace is read. Move up and down. 1 in the zoom mode as described above
The number of scanning lines is adjusted by reading out non-interlaced line by line.

By the interlaced scanning operation of the horizontal shift register HSR and the vertical shift register VSR as described above, the video signal of the whole B of the light receiving portion is obtained in the normal operation, and as described above in the zoom mode. By the skip scanning, it is possible to obtain a video signal in which the portion of the screen A in the central portion of the light receiving portion is zoomed up by 2 times.

FIG. 1 shows the vertical shift register VSR.
A specific circuit diagram of one embodiment is shown. Each of the circuit elements shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a well-known semiconductor integrated circuit manufacturing technique together with circuit elements that form other circuits of other solid-state image pickup elements (not shown). It is formed.

The MOSFET Q12 performs a storage operation and an output operation. That is, the MOSFET Q12 uses its gate capacitance as a storage means. When the high level is held in the gate capacitance, the MOSFET Q12 is turned on and the shift clock pulse C supplied to its drain is supplied.
Transmit the high level of LK1 to the source side. This first stage M
The gate of the OSFET Q12 has a diode type MO
A first input circuit composed of SFETQ1 is provided. When the scanning operation is started from the first-stage circuit, the start signal S1 is set to logic "1" which means a high selection level at the start of scanning. The signal B1 on the source side is an output signal. At this time, a bootstrap capacitance C1 is provided between the gate and the source of the MOSFET Q12 in order to prevent the level of the output signal B1 from decreasing due to the threshold voltage of the MOSFET Q12.

The source of the MOSFET Q12 is a diode type MOS for performing a signal transmission operation.
An FET Q11 is provided. This MOSFET Q11
Operates as a unidirectional element that transmits a high level signal V2 on the source side of the MOSFET Q12. Although not particularly limited, a reset MOSFET Q13 for resetting the output signal B1 at high speed is provided between the source of the MOSFET Q12 and the ground potential point of the circuit.
Is provided. The gate of the reset MOSFET Q13 is supplied with a shift clock pulse CLK2 having a different phase so that the high levels of the shift clock pulse CLK1 do not overlap.

Output signal B1 of the MOSFET Q12
Are transmitted to the gate of a MOSFET Q22 as a similar storage means in the next stage through the diode type MOSFET Q11. The diode type MOSFET Q1
Reset MOSFETs Q14 and Q15 are provided in parallel at the source of 1 (cathode side as a diode) and the ground potential point of the circuit. A reset signal R is supplied to the gate of the MOSFET Q14, and when the reset signal R inputs an initial value, the previous state is once reset. The output signal from the similar diode MOSFET Q31 one bit before is fed back to the gate of the MOSFET Q15 as a reset signal. That is, the above M
A circuit composed of the OSFETs Q11 to Q15 shows a half-bit unit circuit which constitutes a shift register. A pair of similar circuits constitutes a one-bit unit circuit, and a plurality of these one-bit unit circuits are provided. As a result, a multi-bit shift register is configured.

A half-bit unit circuit (second circuit) forming a pair of the above circuits is composed of MOSFETs Q21 to Q25. However, a MOS that performs storage and output operations
A shift clock pulse C is applied to the drain of the FET Q22.
LK2 is supplied. The shift clock pulse CLK1 is supplied to the gate of the reset MOSFET Q23 provided on the output side.

FIG. 2 shows a timing chart for explaining an example of the operation. When performing the cyst operation from the first-stage circuit, the start signal S1 is set to the high level in synchronization with the shift clock pulse CLK2. Accordingly, the high level of the start signal S1 is transmitted to the gate capacitance of the MOSFET Q12 through the diode type MOSFET Q1. This allows the MOSFET
The gate voltage V1 of Q12 becomes high level and is turned on.

When the shift clock pulse CLK1 is set to the high level after the shift clock pulse CLK2 is set to the low level, the high level is output as the output signal B1 through the MOSFET Q12 which is already turned on. At this time, since the high level is also written in the bootstrap capacitor C1, the gate voltage V1 of the MOSFET Q12 is boosted according to the high level of the output signal. As a result, the high level of the shift clock pulse CLK1 does not lose the level of the output signal B.
It is output as 1. In accordance with the high level of the output signal B1, the source side node V3 passing through the diode type MOSFET Q11 is also set to the high level. However, the level V3 of the source side node of this MOSFET Q11
Is assumed to have its level lowered by the threshold voltage of MOSFET Q11. The high level V3 of the source side node of the MOSFET Q11 is the MOSFET of the next stage circuit.
It is transmitted to the gate electrode of TQ22, and its gate capacitance and bootstrap capacitance C2 are set to high level. As a result, the MOSFET Q22 is turned on.

After the shift clock pulse CLK1 changes from the high level to the low level, the shift clock pulse C
LK2 is set to high level. Shift clock pulse C
When LK2 is set to the high level, the MOSFET Q13 is turned on, so that the output signal B1 is rapidly extracted from the high level to the low level. Further, the high level of the shift clock pulse CLK2 is output as the output signal of the next stage through the MOSFET Q22 which is already turned on. At this time, since the high level is also written in the bootstrap capacitor C2, the gate voltage of the MOSFET Q22 is boosted according to the high level of the output signal. As a result, the high level of the shift clock pulse CLK2 is output as the next stage output signal B2 without level loss. According to the high level of the output signal, the node on the source side through the diode type MOSFET Q21 is also set to the high level. However, MO
The level of the source side node of SFETQ21 is MOSF.
It is assumed that the level is lowered by the threshold voltage of ETQ21. The high level of the source side node of the MOSFET Q21 is transmitted to the gate electrode of the similar MOSFET Q32 of the next stage circuit, and sets the gate capacitance and the bootstrap capacitance C3 to the high level. This allows the MOS
The FET Q32 is turned on.

Hereinafter, similarly, the shift clock pulse CLK
The shift operation for half a bit is performed in synchronization with 1 and CLK2. Therefore, the vertical shift register V as described above
When used as SR, odd-numbered output signals B1, B3, etc. are used as scanning signals.

In this embodiment, in order to enable the scanning operation from the middle in the zoom mode like the vertical shift register VSR in FIG. 3, diode type MOSFETs Q2 and Q3 are provided in the input stage of the unit circuit in the middle. An input circuit to which the start signals S1 and S2 are supplied.

For example, in the above operation, the start signal S
If the start signal S2 is changed to 1 and the start signal S2 is set to the high level, the output from the output B3 is enabled, and if the start signal S3 is set to the high level, the output from the output B5 is enabled. In the same figure, in order to facilitate understanding of the invention, a circuit for five half-bit stages shown as an example is shown as an example, and the odd-numbered stages B1, B3, and B5 thereof are provided with input circuits. In the vertical shift register VSR of the solid-state image pickup device having the above-mentioned zoom mode, the input for supplying the start signal S1 corresponding to the normal operation and the start signal S2 to the V / 4 unit circuit. A circuit is provided. Further, the start signal S3 may be supplied by providing an input circuit corresponding to the 8 × zoom or the like. This makes it possible to easily perform scanning operations from a plurality of types of scanning start points.

For the skip operation in the vertical shift register VSR and the skip operation in the horizontal shift register HSR, a circuit for bypassing the output signal in the middle of the shift register and inputting it to the unit circuit at the jump destination is provided. In this circuit, a switch circuit may switch a signal path for either a normal shift operation or a skipped shift operation.

In the horizontal shift register HSR, it is necessary to perform the shift operation for the read operation of the optical black even in the above zoom mode, so that the start is always started from the first stage circuit.

In the vertical scanning, in the normal mode, two rows are simultaneously read out from the viewpoint of preventing afterimage. On the other hand, in the zoom mode, the lines are read line by line in the non-interlaced mode. That is, reading is performed row by row in both the odd field and the even field.

FIG. 4 shows a circuit diagram of an embodiment of the output circuit provided in the vertical shift register VSR.
With such an output circuit, the vertical shift register VSR
The scanning signal V1 formed by
It is supplied to the gates of TQ2 and Q3, and outputs the timing pulses CLK3 and CLK4 corresponding to the rows L1 and L2. Hereinafter, similarly, the scanning signal V2 is similar to the above-described switch MOSFET and timing pulse CL.
Rows L3 and L4 are associated with K3 and CLK4.

In the zoom mode involving the interlaced shift operation as described above, the shift clock pulse CLK1
The frequency of CLK2 and CLK2 is half the normal frequency. Therefore, the output pulse V from the vertical shift register VSR
1, V2 and the like are output once for two horizontal scanning feedback, and switch MOSFETs Q2, Q3, etc. are turned on in this order. Therefore, the timing pulses CLK3 and CLK4 are
The non-interlaced operation is performed by setting the high level in the order of 1 and L2.

FIG. 5 shows a color filter arrangement diagram of an embodiment when applied to a color solid-state image pickup device.
The color filter uses four colors of white (W), yellow (Ye), cyan (Cy), and green (G). That is, they are arranged by repeating yellow (Ye) and cyan (Cy) in the horizontal direction. In the row below that, green (G) and white (W) are repeated.
Hereinafter, color filters are arranged by repeating similar patterns.

FIG. 6 shows a block diagram of an embodiment of an image pickup apparatus using the solid-state image pickup element having the above zoom mode function. The solid-state image sensor MID is a MOS-type solid-state image sensor having the interlace scanning function and the color filter as described above. The drive circuit DRV forms the clock pulse necessary for the read operation. In this embodiment, the drive signal DRV switches the scanning frequency of the vertical and horizontal shift registers to half the frequency of the normal mode by the control signal ZS for the electronic zoom function as described above.

In the normal operation mode, four colors of white (W), yellow (Ye), cyan (Cy), and green (G) are output from the solid-state image pickup device MID by the two-row simultaneous reading as described above. . This color signal is input to the matrix circuit MTX, where the following calculation is performed to form a luminance signal Y, a red signal R, and a blue signal B.

Y = W + Cy + G + Ye (1) R = (W-Cy) + (Ye-G)・ ・ ・ ・ ・ ・ ・ ・ (2) B = (W-Ye) + (Cy-G) ・ ・ ・ ・ ・ (3)

On the other hand, in the zoom mode,
As described above, only one line is read by interlacing. Therefore, as a color signal, yellow Ye, cyan (Cy), and white (W) and green (G) are alternately obtained every horizontal period. Therefore, each signal uses a signal delayed by one horizontal period, and the signals are added by an adder circuit, and the second matrix circuit MTX is used to perform the operations of the above formulas (2) and (3) to obtain a red signal. R and the blue signal B are obtained. The luminance signal Y is Y = Ye from the viewpoint of resolution by the addition circuit.
+ CY and Y = W + G are formed and alternately switched via the switch SW1 which is switch-controlled by the horizontal scanning pulse HP.

Luminance signal Y obtained in these zoom modes
And the red signal R, the blue signal B, and each signal output from the matrix circuit MTX1 in the normal mode,
The output is switched by the switch circuits SW2 to SW4 which are switch-controlled by the control signal ZS.

In the above-mentioned image pickup device, a video signal obtained by enlarging (zooming up) the image at the center of the screen twice in the vertical and horizontal directions can be displayed as a color signal. In this embodiment, the magnification is fixed at 2 times from the viewpoint of enlarging the height and width at the same size and displaying it on the television screen to the full, in other words, from the viewpoint of applying it to the camera integrated VTR. It is also possible to magnify the width only twice or four times. In the case of a surveillance camera or the like, there is a case where it may be enlarged vertically or horizontally as described above.

For example, by using a solid-state image pickup device having a 2 × electronic zoom function as described above and combining a 6 × lens type zoom mechanism, a high magnification zoom function of up to 12 × is equivalently realized. it can.

The functions and effects obtained from the above-mentioned embodiment are as follows. That is, (1) a first MOSFET is used that uses a gate capacitance as a storage means to send a first timing signal to a drain to output an output signal from a source, and a bootstrap capacitance between the gate and the source; A dynamic shift register is configured by using a circuit including a unidirectional element that transmits a signal of the source of the MOSFET as a half bit,
Since a shift operation can be started from the middle by providing a plurality of input circuits that respectively transmit an input signal to the input of the middle circuit of the shift register including the first stage circuit via the unidirectional element, a simple circuit There is an effect that electronic zooming is possible in which an image of a certain area on the image pickup surface is enlarged and displayed in the size of one screen by the operation.

(2) The solid-state image pickup device has a normal mode in which two rows are simultaneously read out and a zoom mode in which the vertical shift register is skipped and half of the rows are read out non-interlaced one row at a time with a half frequency. As a result, it is possible to obtain the effect that it is possible to obtain an image signal that has been magnified at an equal magnification of twice the height and width.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
The reading method of the solid-state image sensor may be any method other than the TSL. As the solid-state image sensor, a vertical shift register for sensitivity setting may be provided. A sensitivity variable function or an electronic shutter function can be added to the vertical shift register for sensitivity setting by adding the midway start function.

The solid-state image sensor may be a line sensor in addition to the area sensor. By providing the function of starting the read shift register in the middle of the line sensor, it is possible to add a trimming function of obtaining a video signal only at a necessary portion. The present invention can be widely utilized as a dynamic shift register in addition to the scanning shift register in the solid-state image sensor as described above.

[0040]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, using the gate capacitance as a storage means, a first MOSFET that sends a first timing signal to the drain and outputs an output signal from the source is used, and a bootstrap capacitance is provided between the gate and the source, and
The circuit including the unidirectional element that transmits the signal of the source of the MOSFET is configured as a half bit to configure a dynamic shift register, and is input to the intermediate circuit of the shift register in the middle including the initial stage circuit via the unidirectional element. Since the shift operation can be started from the middle by providing a plurality of input circuits for transmitting the input signals respectively, the image of a certain area on the imaging surface can be enlarged to the size of one screen by a simple circuit operation. It enables electronic zooming for display.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a shift register according to the present invention.

FIG. 2 is a waveform diagram for explaining an example of the operation of the shift register in FIG.

FIG. 3 is a screen configuration diagram for explaining a reading function of a solid-state imaging device using a shift register according to the present invention.

FIG. 4 is a circuit diagram showing an example of an output circuit of the vertical shift register.

FIG. 5 is a layout view showing an embodiment of a color filter used in the solid-state image sensor.

FIG. 6 is a block diagram showing an embodiment of an image pickup apparatus using the solid-state image pickup element.

[Explanation of symbols]

Q1 to Q55 ... MOSFET, C1 to C5 ... Bootstrap capacitance, VSR ... Vertical shift register, HSR ... Horizontal shift register, MID ... Solid-state imaging device, DRV ... Drive circuit, MTX1, MTX2 ... Matrix circuit, SW
1-SW4 ... switch circuit, IHDL ... 1H delay circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Ogura 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (4)

[Claims] 1. A first MOSFET, which is supplied with a first timing signal at its drain, uses its gate capacitance as a storage means, and sends out an output signal from its source, and said first M-channel.
A first circuit including a first capacitance means provided between the gate and the source of the OSFET and a unidirectional element for transmitting the signal of the source of the first MOSFET, and the first timing signal. Is a second MOS in which the second timing signals having mutually different phases are supplied to the drain, the gate capacitance thereof is used as the storage means, and the output signal is transmitted from the source.
An FET, a second capacitance means provided between the gate and the source of the second MOSFET, and the second MOS
A plurality of unit circuits each including a second circuit including a unidirectional element that transmits a signal from the source of the FET, and a signal that has passed through the unidirectional element in the second circuit or a unit of the next stage. The first circuit of the circuit is provided with a plurality of input circuits which are connected in a cascade form so as to be transmitted to the gates of the MOSFETs of the first circuit and which are each configured to transmit an input signal to the input of a unit circuit in the middle including the first stage circuit via a unidirectional element. A shift register characterized by the following. 2. The shift register according to claim 1, wherein the shift register forms a scanning signal of a solid-state image pickup device that outputs a signal formed by a photoelectric conversion element via a switch element. 3. The shift register also performs a zoom mode operation which starts halfway and reads out half a row in the vertical direction one row at a time with a half frequency in a non-interlaced manner. Shift register. 4. The shift register according to claim 2, wherein the shift register performs an operation of starting from the middle and enabling reading from an arbitrary position in a vertical direction or a horizontal direction.