JP3514000B2 - Display drive - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driving device, and more particularly to a display driving device using a transistor having a channel length longer than that of a normal transistor.

[0002]

2. Description of the Related Art A display driving device includes, for example, a liquid crystal driving device that drives a liquid crystal to control display. In the case of this liquid crystal driving device, it can be divided into a segment system and a matrix system depending on the display form. The matrix type is used in display devices such as liquid crystal televisions, personal computers, and word processors for displaying images. The matrix method includes a simple matrix method and an active matrix method, but an active matrix method that has high image quality and does not have a crosstalk phenomenon is receiving attention.

A liquid crystal drive device of the active matrix system displays an image by applying a voltage to the liquid crystal portion of the pixel by a liquid crystal drive element provided for each pixel. As the liquid crystal driving element, a thin film transistor (TFT) is rapidly becoming popular in recent years. This thin film transistor was developed as a liquid crystal driving element that overcomes the drawbacks of the MOS transistor formed on the previous silicon single crystal substrate, that is, that the size of the display screen is limited and that it cannot be made transmissive. Is. This thin film transistor is one in which impurities are injected into a predetermined region of a semiconductor thin film formed on a substrate such as glass to form a transistor. In particular, cadmium selenide, polycrystalline silicon, amorphous silicon or the like is used as a material of a semiconductor thin film for a liquid crystal display device.

Conventionally, when a driver circuit of a liquid crystal display device or the like is integrally formed on a glass substrate by using thin film transistors (TFTs), it is usually CMOS (Compleme).
nta-ry Metal Oxide Semiconductor) circuit is used. This CMOS circuit consists of an nMOS transistor that carries current by electrons and a pM transistor that carries current by holes.
It is a complementary transistor circuit in which an OS transistor is paired.

For example, FIG. 8 is a diagram showing a configuration of a conventional CMOS inverter circuit 1. As shown in FIG.
The MOS inverter circuit 1 is configured by connecting the sources or drains of two types of transistors, pMOS2 and nMOS3, in series between a power supply (Vdd) and a ground (GND).

The CMOS inverter circuit 1 shown in FIG.
When the IN (input) is "0", the nMOS transistor 3 is turned off, the pMOS transistor 2 is turned on, and "1" is output (output) from the power supply Vdd. When the input is "1", the pMOS transistor 2 turns off,
When the nMOS transistor 3 is turned on, "0" is output from the ground. In this way, the CMOS inverter circuit can output the logic opposite to the input logic. For example, FIG. 9 is a cross-sectional configuration diagram of the nMOS transistor 3 that constitutes the CMOS inverter circuit 1 of FIG. 8, and FIG. 9A is a diagram of an nMOS transistor having a normal channel length. b) is
It is a figure of the nMOS transistor whose channel length is longer than (a).

When forming the nMOS transistor 3 of FIG. 9A, a base insulating film 5 having a predetermined thickness is formed on a glass substrate 4, and a width (W) of 60 μm is formed at a predetermined position on the base insulating film 5.
A gate electrode 6 made of metallic chromium or the like having a length (L) of 6 μm is formed. Then, a gate insulating film 7 is formed so as to cover the base insulating film 5 and the gate electrode 6, and the semiconductor layer 8 is centered on the gate electrode 6 on the gate insulating film 7.
Are formed to extend in the left-right direction.

The semiconductor layer 8 is self-aligned with the gate electrode as an ion implantation mask.
By doping n-type impurity ions by a technique and performing heat treatment, a channel region in which 81 and 83 are n-type impurity implantation regions and 82 is an intrinsic semiconductor region can be formed.

Then, the semiconductor layer 8 and the gate insulating film 7 are formed.
An interlayer insulating film 9 is formed so as to cover and planarize. Then, in order to form the source / drain electrodes of the nMOS transistor 3, contact holes penetrating the interlayer insulating film 9 and reaching both ends of the semiconductor layer 8 are formed by anisotropic etching, and aluminum ( Source / drain electrode 1 made of Al) or the like
The nMOS transistor 3 is formed by embedding 0 and wiring.

Further, as shown in FIG. 9B, when the nMOS transistor 3'having a longer channel length than that of FIG. 9A is formed, the manufacturing process itself is the same as the above, but on the base insulating film 5. The length of the gate electrode 6 to be formed was 6 μm, but was set to 10 μm, and the gate electrode 6 ′ was used as a mask to perform ion doping by the self-alignment technique to form a channel region 82 ′ having a long channel length of 10 μm. Can be formed.

FIG. 10 is a diagram showing a connection example for detecting the off-current of the nMOS transistor 3, and FIG.
FIG. 9 is a diagram showing a relationship between drain voltage and drain current of an nMOS transistor having a channel width (W) of 60 μm and a channel length (L) of 6 μm shown in FIG. 9A.

As shown in FIG. 10, the nMOS transistor 3 has its source and gate grounded to the ground, the transistor is in an off state, and a predetermined drain voltage (Vd) is applied to its drain. A drain current (Id) corresponding to the above, so-called off current flows. The relationship diagram is shown in FIG. 11. When a drain voltage of 4 V is applied, a drain current of about 0.1 μA flows, and when a drain voltage of 6 V is applied, about 0.2 μA.
It can be seen that the drain current of flows. In addition, FIG.
FIG. 9 is a diagram showing the relationship between the drain voltage and the drain current of an nMOS transistor having a channel width (W) of 60 μm and a channel length (L) of 10 μm shown in FIG. 9B.

As shown in FIG. 10, when the nMOS transistor 3 is off and a predetermined drain voltage (Vd) is applied to the drain, a drain current (Id = off current) corresponding to the voltage flows. For example, as shown in FIG. 12, when a drain voltage of 4 V is applied, it is about 0.0
When a drain current of 2 μA flows and a drain voltage of 6 V is applied, a drain current of about 0.04 μA flows,
It takes about 8.5 for the drain current of 0.1 μA to flow.
It can be seen that it is necessary to apply a drain voltage of V.

Further, the other conductivity type pMOS transistor 2 constituting the CMOS transistor 1 of FIG. 8 can be similarly formed by doping a p-type impurity ion instead of the n-type impurity ion. ,
The relationship between the channel length and the off-current (source current in the pMOS transistor, drain current in the nMOS transistor) is similar to that of the nMOS transistor described above.

Thus, as can be seen by comparing FIGS. 11 and 12, when the channel width is the same and the channel length is changed from 6 μm to 10 μm, the off current is significantly reduced, and the static power consumption of the transistor is reduced. Can be reduced. This is because when the channel length of the transistor is shortened, the electric field strength of the PN junction portion is increased and a sufficient on-current can be obtained, while the off-current (leakage current) is increased, but when the channel length is lengthened, the PN junction is increased. This is because the electric field strength of the portion is reduced and the on-current is reduced, but the off-current (leakage current) is reduced. In addition to the inverter circuit, the CMOS transistor described above can form a latch circuit, an AND circuit, a NAND circuit, a tri-state circuit, or the like, which is necessary to form a display drive device.

[0016]

However, in such a conventional display driving device, the operating frequency of the CMOS transistor composed of TFT is "f", the load capacitance is "C", and the power supply voltage is Where “Vdd” and leakage current are “IL”, the power consumption of the CMOS transistor can be expressed by the following equation.

W (power consumption) = fCVdd (dynamic power consumption) + ILVdd (static power consumption) A CMOS transistor composed of conventional TFTs has a leak current "IL" of the above formula. Since the value of is large, for example,
There has been a problem that the leakage current (static power consumption) occupies a large proportion of the total power consumption of the display driving device including a large number of TFTs.

Further, the performance required for the TFT used in the display driving device is that an on-current sufficient to drive the liquid crystal can be obtained, and an off-current (leakage) in order to improve the retention characteristic in the off-state. Current) is as small as possible. However, in order to obtain a sufficient on-current, it is sufficient to shorten the channel length, but since the electric field strength at the PN junction portion is increased, an off-current (leakage current) increases, which is a trade-off phenomenon. Therefore, when it is desired to reduce the power consumption of the display drive device, the TF to be used
If the channel length of T is made longer than the conventional one, the static power consumption becomes small, and the power consumption of the entire display drive device can be reduced.

However, all TFs of the display drive device
When the channel length of T is increased, not only a sufficient on-current cannot be obtained, but the channel length is increased, which causes a problem that the mounting area of the transistor is increased.

The present invention has been made in view of the above-mentioned problems, and it is possible to obtain a sufficient on-current while suppressing an increase in circuit area to a minimum, and to provide a leak current which is static power consumption of a transistor. It is an object of the present invention to provide a display drive device that can reduce the power consumption and reduce the power consumption.

[0021]

A display driving device according to claim 1, wherein the display driving device comprises a display driving circuit for applying a predetermined driving voltage to a display section to control display. In the output circuit block that has a plurality of stages of inverter circuits in the circuit and outputs the drive voltage, the channel length of the transistor used in the final stage inverter circuit is made longer than the channel length of the other transistors. It is characterized by doing. That is, in the final stage inverter circuit in the output circuit block of the display drive circuit, a large current is required in order to increase the driving capability and obtain a sufficient on-current. The off-state current can be effectively reduced by making the channel length longer than that of the transistor.

Therefore, by configuring the channel length of the transistor of the final stage inverter circuit in the output circuit block of the display drive circuit to be long, the PN of the transistor is formed.
Since the electric field strength at the junction is small, off current (leakage current) can be reduced. In particular, since the transistor in the final stage of the display driver circuit has a large current, by increasing the channel length of the transistor in this portion, the off current can be effectively reduced and power consumption can be reduced. .

The display driving device according to claim 1 is, for example, a display driving device for driving a liquid crystal display panel in which pixels are formed in a matrix in a liquid crystal cell. Then, in the signal side drive circuit that supplies a display signal to each pixel, the channel length of the transistor of the final stage inverter circuit of the tri-state circuit that has a plurality of stages of inverter circuits and outputs the display signal, It is characterized in that it is configured to be longer than the channel length of the transistors in the other circuits. Therefore, the channel length of the transistor of the final stage inverter circuit of the tri-state circuit that outputs the display signal of the signal side drive circuit that is the display drive circuit is configured to be longer than the channel length of the transistor used in other circuits. Thus, the off current can be effectively reduced, and since the transistor having a long channel length is limited to the tristate circuit, the increase in the circuit area can be suppressed to the minimum.

The display driving device according to claim 1 is, for example, a display driving device for driving a liquid crystal display panel in which pixels are formed in a matrix in a liquid crystal cell. The channel length of the transistor of the final stage inverter circuit of the buffer circuit that has a plurality of stages of inverter circuits in the scanning side drive circuit that supplies a scanning signal to each pixel and that outputs the scanning signal. It is characterized in that it is configured to be longer than the channel length of the transistors of circuits other than.

Therefore, the channel length of the transistor of the inverter circuit at the final stage of the buffer circuit for outputting the scanning signal of the scanning side driving circuit which is the display driving circuit is longer than the channel length of the transistor used in other circuits. By doing so, the off current can be effectively reduced, and since the transistor having a long channel length is limited to the buffer circuit and used, an increase in the circuit area can be suppressed to the minimum.

According to a fourth aspect of the present invention, the display drive device is characterized in that the inverter circuit is an inverter circuit formed of complementary CMOS transistors formed by pairing an nMOS transistor and a pMOS transistor. Therefore, the CMOS transistor is composed of a pair of an nMOS transistor and a pMOS transistor. Therefore, when one of the nMOS transistor and the pMOS transistor turns on with respect to the input gate voltage,
Since the other structure is always turned off, power consumption can be reduced and an appropriate output level can be obtained.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 to 7 are diagrams showing an embodiment of a display driving device of the present invention, in which a liquid crystal driving circuit on a glass substrate and a switching device including a thin film transistor (TFT) for each pixel of a pixel portion are shown. This is implemented as a drive circuit integrated type liquid crystal display device by integrally forming elements. The feature of the present embodiment is that the channel length of the CMOS transistor at the final stage of the liquid crystal drive circuit described above is set longer than the channel lengths of the other transistors.

First, the structure will be described. FIG. 1 is a cross-sectional configuration diagram of an inverter circuit 21 that is a final stage of a liquid crystal drive circuit and that includes CMOS transistors using nMOS and pMOS having a long channel length. Inverter circuit 2
1, the circuit diagram is the same as FIG. 8 of the conventional inverter circuit, but the channel length of the transistor of the inverter circuit used in the final stage of the liquid crystal drive circuit is longer than the channel length of the transistor used in other parts. It is configured.

The inverter circuit 21 of FIG. 1 is the same as the inverter circuit 1 of the conventional CMOS transistor shown in FIG.
MOS transistor 2 and pMOS transistor 3 are
pMOS transistor 22 and nMOS transistor 23
The channel length is usually about 6 μm, but each channel length is about 10 μm.

As in the present embodiment, by making the channel length of the transistor longer than usual, the electric field strength of the PN junction portion of each transistor becomes small, so that the off current of the transistor can be reduced. it can. In particular, the transistor having the long channel length is used only for the final stage transistor of the liquid crystal drive circuit, and the transistors having the normal channel length are used for the other circuits. As described above, in the transistor at the final stage of the display drive circuit, a large current is supplied in order to increase the driving capability. Therefore, by increasing the channel length of the transistor in this portion, the off current is effectively reduced and consumed. The power can be reduced, a sufficient on-current can be obtained, and further, since the transistor having a long channel length is limitedly used, the increase in the circuit area can be minimized.

As shown in FIG. 1, C according to the present embodiment.
In the MOS inverter circuit 21, a base insulating film 25 having a predetermined thickness is formed on the entire surface of the glass substrate 24. Then, at predetermined positions on the surface of the base insulating film 25, gate electrodes 26 and 27 made of metallic chromium having a width (W) of 60 μm and a length (L) of 10 μm are formed. further,
A gate insulating film 28 is formed so as to cover the base insulating film 25 and the gate electrodes 26 and 27, and semiconductor layers 29 and 30 are formed on the gate insulating film 28 with the gate electrodes 26 and 27 as the center. It is formed so as to extend in the left-right direction.

The semiconductor layers 29 and 30 are doped with n-type and p-type impurity ions by the self-alignment technique using the gate electrodes 26 and 27 as ion implantation masks, respectively, and then heat-treated. Done. Thereby, in the semiconductor layer 29, 291, 293 are formed.
Serves as a p-type impurity implantation region, and 292 serves as a channel region which is an intrinsic semiconductor region.

Further, in the semiconductor layer 30, 301, 303
Serves as an n-type impurity implantation region, and 302 serves as a channel region which is an intrinsic semiconductor region. Then, the semiconductor layer 2
An interlayer insulating film 31 is formed so as to cover the gate insulating film 28 and the gate insulating film 28 and planarize them. Then, the sources of the pMOS transistor 22 and the nMOS transistor 23
In order to form the drain electrodes respectively, contact holes penetrating the interlayer insulating film 31 and reaching both ends of the semiconductor layers 29, 30 are formed by anisotropic etching, and the contact holes are made of aluminum (Al) or the like. After embedding the source / drain electrodes 32, wiring for forming the inverter circuit shown in FIG.
The OS inverter circuit 21 is formed.

As described above, in the liquid crystal drive circuit,
Except for the transistor having a channel length of 10 μm which constitutes the circuit at the final stage, the conventional 6-channel transistor as shown in FIG.
It is composed of a transistor having a channel length of μm.

When the transistor having the channel length of 6 μm is formed, the manufacturing process itself is the same as the above, but the gate electrodes 26, 2 formed on the base insulating film 25 are formed.
The length of 7 is set to 10 μm and is set to 6 μm.
Using the gate electrodes 26 and 27 made of
By ion-doping with the self-alignment technique, the channel regions 292 and 302 of a normal transistor having a channel length of 6 μm can be formed.

FIG. 2 is a diagram showing a connection example for detecting the on-current of the nMOS transistor 23, and FIG.
Vg- for detecting the on-current of the transistor of FIG.
It is a diagram which shows Id characteristics. In the nMOS transistor 23 shown in FIG. 2, the source is grounded, the gate voltage (Vg) is applied to the gate, and the drain voltage of +1 V is applied to the drain. FIG. 3 shows the relationship in which the drain current (Id) flowing through the drain changes in accordance with the above-mentioned change in the gate voltage (Vg) in the connected state as shown in FIG.

In FIG. 3, the case where the channel length (L) of the transistor is 6 μm is shown by a solid line, and the channel length (L) is shown.
Is 10 μm, it is indicated by a broken line. As shown in FIG. 3, when the channel length of the transistor is increased from 6 μm to 10 μm, the reduction of the on-current of the transistor is 40%.
It can be seen that the degree is sufficient (proportional to 1 / L). On the other hand, as described with reference to FIGS. 11 and 12 of the conventional example described above, when the channel length is changed from 6 μm to 10 μm, the off current (leakage current) is reduced by almost one digit, and the source・ Drain breakdown voltage is improved.

As described above, by using a transistor having a long channel length (L), it is possible to effectively reduce the static power consumption of the circuit. In particular, in the present embodiment, since the transistor having a long channel length is limited to the final-stage transistor of the liquid crystal drive circuit in which a large current flows, the power consumption can be effectively reduced and the increase of the circuit area can be suppressed. There is an advantage that you can. In this case, as described above, the decrease in the on-current of the transistor is sufficiently smaller than the decrease tendency of the leakage current.

Of course, in FIGS. 2 and 3 above,
Although the nMOS transistor 23 having a different channel length has been described as an example, the CMOS inverter circuit 2 shown in FIG.
The same applies to the case of the pMOS transistor 22 of 1.
When the channel length is increased, power consumption can be effectively reduced, and an increase in circuit area can be suppressed by limiting the place where the channel is used.

In the CMOS inverter circuit 21 of FIG. 1 described above, when the input is "0", the nMOS transistor 23 is turned off, the pMOS transistor 22 is turned on, and "1" is output from the power supply Vdd. When the input is "1", the pMOS transistor 22 is turned off and the nMOS transistor 23 is turned on.
"0" is output from the ground. In this way, CM
The OS inverter circuit 21 outputs the logic opposite to the input logic.

As described above, in the present embodiment, by using the transistor having the long channel length (L), the electric field strength of the PN junction portion of the transistor is reduced, and the off current (leakage current) of the transistor is reduced. It is possible to reduce the ON current significantly compared to the rate of decrease. In particular, since a transistor with a long channel length is used only in the final stage transistor of a liquid crystal drive circuit in which a large current flows, power consumption can be effectively reduced and an increase in circuit area can be suppressed. It became so.

Next, FIG. 4 is a schematic configuration diagram of the drive circuit integrated TFT-LCD 41 according to the present embodiment. The drive circuit integrated type TFT-LCD 41 includes a glass substrate 45.
Liquid crystal display panel (TFT-LCD: Thin Film Tran)
sistor-Liquid Crystal Display 42, a gate driver 43 for driving switching elements of each pixel arranged in a matrix on the liquid crystal display panel 42, and a drain driver 44 are integrally formed by COG (Chip On Glass) technology. is doing.

FIG. 5 is a diagram showing a part of a concrete example of the liquid crystal drive circuit and the liquid crystal display panel of FIG. In the liquid crystal display panel 42 shown in FIG. 5, the TF connected to each pixel is
T and the TFT form a liquid crystal capacitor LC between the pixel electrode and the common electrode. Then, from the gate driver 43, the gate lines G1, G2, G3, ...
Scan signals are sequentially applied to the T connected to each scan line.
The gate of the FT is driven to create a selected state and a non-selected state. Here, the TFT on the scanning line selected by the gate driver 43 is the drain driver 44.
When a display signal is applied to each of the drain lines D1, D2, ... From the liquid crystal display device, a drive voltage is applied to the pixel electrode in the selected state, the liquid crystal is driven by the potential difference between the pixel electrode and the common electrode, and display control is performed. Is done.

Since the present embodiment is characterized by the configurations of the drain driver 44 and the gate driver 43 which are liquid crystal drive circuits, the configuration and operation will be described separately for the drain driver and the gate driver.

(Drain driver) As shown in FIG.
The drain driver 44 includes a data shift register 52.
And latch circuits LA101 and LA102, and tristate circuits TS101 and TS102.
The horizontal shift signal φH and the horizontal clock signal CPH are input from the external circuit 51 to the data shift register 52. The horizontal shift signal φH is sequentially shifted by the horizontal clock signal CPH while the output terminals DSR1 and DSR are shifted.
2 outputs a latch signal for latching the video signal to the control terminals L of the latch circuits LA101 and LA102, respectively.

Latch circuits LA101, LA102 are provided by the number corresponding to the drain lines D1, D2, ..., The input terminals I are connected to the video signal line L100, and the video signal line L100 is connected to an external circuit. 5
The 1- to 2-valued video signal DATA is applied and the latch signal is input to the control terminal L from the data shift register 52 described above. The serial binary video signal DATA input from the video signal line L100 latches data at the timing of the latch signal input to each latch circuit LA101, LA102, and the latched data is output from the output terminal O to the next stage. It is output to the state circuit.

Tristate circuits TS101, TS10
2 is arranged in the final stage of the drain driver 44 in a number corresponding to each of the drain lines D1, D2, ... And, based on the latch data latched by the above-mentioned latch circuit, a liquid crystal drive voltage for alternating-current driving the liquid crystal. It is a circuit that generates a waveform. The control terminals of the tri-state circuits TS101 and TS102 are latch circuits LA101 and LA10, respectively.
The output positive power supply VOH and the output negative power supply VOL are connected to the positive power supply terminal and the negative power supply terminal of each tri-state circuit while being connected to the second output terminal O. Then, each tri-state circuit TS101, TS102, ...
The drain terminals D1 and D are connected to the output terminals of ...
.. are connected, and a liquid crystal drive voltage is supplied to the pixel electrode via each TFT.

FIG. 6 is a diagram showing a specific configuration example of the latch circuit LA101 and the tri-state circuit TS101 of FIG. The latch circuit LA101 shown in FIG. 6 includes transfer gates TG1 and TG2 and inverters IN1 and IN.
2 and IN3 are provided.

The output terminal DSR1 of the data shift register 52 is connected to the transfer gate TG.
1 is connected to the P-side control terminal and the transfer gate TG2 of the N-side control terminal, and the inverter IN1
Through the N-side control terminal of the transfer gate TG1 and the P-side control terminal of the transfer gate TG2. The first non-control terminal of the transfer gate TG1 is connected to the video signal line L100,
The second non-control terminal of the transfer gate TG1 is connected to the first non-control terminal of the transfer gate TG2 via the inverters IN2 and IN3 in series, and the second non-control terminal of the transfer gate TG2 is the transfer gate TG1. Connected to the second non-control terminal of the.

Next, the tri-state circuit TS shown in FIG.
101 includes inverters IN4, IN5, IN6, and transistors TR1 to TR8. Here, in the above transistor, TR1, TR2, TR4 and TR7 are pMOS transistors, and TR3, TR5 and TR are
6 and TR8 are composed of nMOS transistors.

Therefore, from the connection portion of the inverters IN2 and IN3 of the latch circuit LA101 described above, the inverters IN4, IN5, IN of the tri-state circuit TS101 are connected.
6 in series with pMOS transistors TR1 and n
It is connected to each gate of the MOS transistor TR5. The connection between the inverters IN5 and IN6 is connected to the gates of the pMOS transistor TR2 and the nMOS transistor TR3.

Further, the gates of the pMOS transistor TR4 and the nMOS transistor TR6 are
Frame signal line 55 to which the frame signal φf is input
Connected to.

Then, the pMOS transistor TR1
Source is connected to the positive power supply Vcc and the drain is pMO
It is connected to the source of the S transistor TR2. further,
The drain of the pMOS transistor TR2 is nMO
This nM is connected to the drain of the S transistor TR3.
The source of the OS transistor TR3 is grounded.

Further, the pMOS transistor TR4
Has a source connected to the positive power source Vcc and a drain connected to nMO
It is connected to the drain of the S transistor TR5. This n
The source of the MOS transistor TR5 is further nMO.
This nM is connected to the drain of the S transistor TR6.
The source of the OS transistor TR6 is grounded. Then, the pMOS transistors TR1 and T
The drains of R4 are connected to each other and to the gate electrode of the pMOS transistor TR7 of the CMOS inverter circuit 56 having the same configuration as that of FIG. 1 in which the channel length is longer than that of a normal transistor.

The source of the nMOS transistor TR5 is connected to the drain of the pMOS transistor TR2, and the channel length of the nMOS transistor TR5 is longer than that of an ordinary transistor. It is connected to the gate electrode of TR8.

Then, the CMOS inverter circuit 56
The source of the pMOS transistor TR7 is connected to the output positive power supply VOH, the drain of the pMOS transistor TR7 is connected to the data line D1, and the nMO
NMOS connected to the drain of the S transistor TR8
The source of the transistor TR8 is connected to the output negative power supply VOL.

The drain driver 44 according to the present embodiment
Is characterized in that the tri-state circuit TS1 arranged at the final stage of the drain driver 44 which is a liquid crystal drive circuit.
PM having a channel length longer than that of other transistors (usually about 6 μm is 10 μm)
OS transistor TR7 and nMOS transistor TR8
Is used to form the CMOS inverter circuit 56. As a result, a CM having a normal channel length
Since the channel length is longer than that in the case where the OS inverter circuit is used, the electric field strength of the PN junction portion in each transistor is reduced, so that the off-state current of the transistor can be reduced. In particular, in the present embodiment, the above-mentioned transistor having a long channel length is used only in the final stage of the drain driver 44 that flows a large current in order to sufficiently enhance the driving capability and obtain a sufficient on-current, so that the circuit area is large. The off-current is effectively reduced while the increase in the current is suppressed to the minimum.

Next, the operation will be described. The data shift register 52 shown in FIG. 5 receives the horizontal synchronizing signal φH and the horizontal clock signal CPH from the external circuit 51, outputs a latch signal from the output terminal DSR1, and outputs the latch circuit L.
It is supplied to the control terminal L of A101. Also, the latch circuit L
The video signal DATA is supplied to the input terminal I of A101.

In FIG. 6, when the latch signal from the output terminal DSR1 of the data shift register 52 becomes low level, the output of the inverter IN1 becomes high (Hi).
gh) level, transfer gate TG1
Is turned on, the video signal DATA is taken in, and when the latch signal from the output terminal DSR1 of the data shift register 52 becomes high level, the output of the inverter IN1 becomes low level, so the transfer gate TG1
Is turned off, the transfer gate TG2 is turned on, and the video signal DATA is stored.

Therefore, the case where the video signal DATA is at the low level will be described. Low level video signal DA
TA becomes high level via the inverters IN2, IN4, IN5, and the pMOS transistors TR2 and n
Since it is supplied to each gate of the MOS transistor TR3, the pMOS transistor TR2 is turned off, and nMO
The S transistor TR3 is turned on. The low-level video signal DATA is supplied to the inverters IN2, IN4, I
Since it becomes a low level via N5 and IN6 and is supplied to the gates of the pMOS transistor TR1 and the nMOS transistor TR5, the pMOS transistor TR1 is turned on and the nMOS transistor TR5 is turned off. When the nMOS transistor TR3 is turned on, the gate of the nMOS transistor TR8 is grounded and turned off. Further, when the pMOS transistor TR1 is turned on, the pMOS transistor TR7 is turned off by supplying the positive power supply Vcc to the gate. Therefore,
The output positive power supply VOH and the output negative power supply VOL are not supplied to the data line D1.

Next, the case where the video signal DATA is at the high level and the frame signal φf is at the high level will be described. The high-level video signal DATA is supplied to the inverter I
Low level via N2, IN4, IN5, pM
OS transistor TR2 and nMOS transistor T
Since it is supplied to each gate of R3, the pMOS transistor TR2 is turned on and the nMOS transistor TR3 is turned on.
Turns off. In addition, high level video signal DATA
Becomes high level via the inverters IN2, IN4, IN5, IN6, and is supplied to the gates of the pMOS transistor TR1 and the nMOS transistor TR5.
The MOS transistor TR5 is turned on. Further, the high-level frame signal φf changes to the pMOS transistor TR4.
And the gates of the nMOS transistor TR6, the pMOS transistor TR4 is turned off and the nMOS transistor TR6 is turned on. nMO
S transistor TR5 and nMOS transistor TR
By turning on 6, the pMOS transistor TR7
Is turned on with its gate grounded, and the nMOS transistor TR8 is turned off with its gate grounded. Therefore, when the pMOS transistor TR7 is turned on, the output positive power supply VOH is supplied to the data line D1.

Next, the case where the video signal DATA is at a high level and the frame signal φf is at a low level will be described. The high level video signal DATA is supplied to the inverter IN
Low level via 2, IN4, IN5, pMO
S transistor TR2 and nMOS transistor TR
Since they are supplied to the respective gates of 3, the pMOS transistor TR2 is turned on and the nMOS transistor TR3 is turned off. In addition, the high level video signal DATA is
It goes high through the inverters IN2, IN4, IN5, IN6, and the pMOS transistors TR1 and n
Since it is supplied to each gate of the MOS transistor TR5, the pMOS transistor TR1 is turned off,
The S transistor TR5 is turned on. Further, since the low-level frame signal φf is supplied to the gates of the pMOS transistor TR4 and the nMOS transistor TR6, the pMOS transistor TR4 turns on and n
The MOS transistor TR6 is turned off. When the pMOS transistor TR4 and the nMOS transistor TR5 are turned on, the pMOS transistor TR7 is turned off by supplying the positive power supply Vcc to the gate, and is turned off.
The MOS transistor TR8 is turned on when the positive power supply Vcc is supplied to its gate. Therefore, when the nMOS transistor TR8 is turned on, the output negative power supply VOL is supplied to the data line D1.

As described above, in the above-described embodiment, the CMOS using the transistors TR7 and TR8 whose channel length is longer than the other transistors in the tri-state circuit TS101 arranged at the final stage of the drain driver 44.
Since the inverter circuit 56 is provided, the power consumption of the drain driver 44 is reduced by reducing the electric field strength of the PN junction portion of each transistor and effectively reducing the off current while suppressing the increase of the circuit area to the minimum. Can be reduced.

(Gate Driver) As shown in FIG. 5, the gate driver 43 is composed of a scanning shift register 53 and a buffer circuit 54. The vertical shift signal φV and the vertical clock signal CPV are input from the external circuit 51 to the scan shift register 53. The scanning shift register 53 generates a horizontal scanning signal to be applied to a plurality of gate lines based on the input vertical synchronizing signal φV and vertical clock signal CPV, and each buffer circuit 54.
Gate lines G1, G2, G3,
Are sequentially applied to the thin film transistor (TFT) of each pixel of the liquid crystal display panel 42 to turn on / off to perform horizontal scanning.

FIG. 7 shows the scanning shift register 53 of FIG.
FIG. 3 is a diagram showing a specific configuration example of a buffer circuit 54. As shown in FIG. 7, the scanning shift register 53 includes latch circuits 61, 62, 63, 64, ... And a NAND circuit 7.
It consists of 1, 72, 73, 74, ....

In the latch circuits 61, 62, 63 and 64, the vertical synchronizing signal φV and the inverted vertical synchronizing signal ΦφV input from the external circuit 51 are supplied to the control signal input end L and the inverted control signal input end L. Every other signal is input in the opposite phase. When "1" is input to the control signal input end L, the input signal is output through, and when "0" is input, the previous input signal is latched.

As for the input signal to the latch circuit 61, when the vertical clock signal CPV is input to the input end I from the external circuit 51, an output signal corresponding to the through state and the latched state is output to the output end O and the inverted output. It is output from the end portion O and is input to the NAND circuit 71 and the input end portion I of the latch circuit 62 at the next stage. Similarly, the output signal of the latch circuit 62 is input to the NAND circuits 71 and 72 and the input terminal I of the latch circuit 63 at the next stage. Then, the NAND circuit 71 includes the latch circuit 6
1 and the inverting output from each inverting output end -0 of the latch circuit 62 are input and the negative logical product is output.

Similarly to the above, the latch circuits 63, 64, ...
, And the NAND circuits 73, 74, ... Are continuously connected to form a shift register, and the NAND circuits 71 to 7 are connected.
Negative logical ANDs output from the output signals 4 ... At predetermined timings are sequentially output to the buffer circuit 54 at the next stage.

The buffer circuit 54 is composed of three inverter circuits (for example, 81, 91, 101) connected in cascade, and each of the NAND circuits 71 to 74, ... The negative logical product that is input is amplified by sequentially inverting the logic through each inverter circuit and output to each gate line G1, G2, G3, G4, ....

FIG. 7 merely illustrates a part of the structure of the gate driver 43 which supplies the four gate lines G1 to G4, and the above circuits are arranged in the vertical direction according to the number of gate lines. . As a result, each gate line is line-scanned by a predetermined scanning method to bring each gate line into a selected state or a non-selected state.

As described above, the characteristic configuration of the gate driver 43 according to the present embodiment is that the buffer circuit 54 arranged at the final stage of the gate driver 43 which is a liquid crystal drive circuit.
Of some of the inverter circuits 101 to 104 having a channel length longer than that of other transistors, similar to that of FIG.
C using transistor 7 and nMOS transistor 8
Since the MOS inverter circuit 56 is provided, the increase of the circuit area is suppressed to the minimum, and the P of each transistor is reduced.
It has become possible to reduce the power consumption of the gate driver 43 by reducing the electric field strength at the N-junction portion and effectively reducing the off current. In particular, in the present embodiment, the transistor having a long channel length described above is used in the final stage of the gate driver 43 that flows a large current in order to sufficiently enhance the driving capability and obtain a sufficient on-current, so that the circuit area is increased. It is possible to effectively reduce the off-current while keeping it to a minimum, and to reduce the power consumption of the gate driver 43.

Then, the drain driver 44 and the gate driver 43 described above are operated by the gate driver 43 so that the gate lines G1, G2, G3 of the liquid crystal display panel 42,
... are sequentially applied with a horizontal scanning signal to bring them into a selected state, and a video signal corresponding to each pixel on the horizontal scanning line in the selected state is supplied from the drain driver 44 to each data line D.
, D2, ..., Signal charges are transmitted to the thin film transistor of a predetermined pixel to drive the liquid crystal, so that display is performed. Although the invention made by the present inventors has been specifically described based on the preferred embodiments, the present invention is not limited to the above-described embodiments and various modifications are possible without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-described embodiment, the CMOS inverter circuit 56 consisting of a transistor having a long channel length is arranged at the output stage of each of the tristate circuits TS101, TS102, ... Provided in the final stage of the drain driver 44. However, the transistors in each of the tristate circuits other than this may also be configured by using those having a long channel length.

Further, in the above-described embodiment, the inverter circuits 101, 102, 103, 10 at the output stage of the buffer circuit 54 provided at the final stage of the gate driver 43.
Although each of the CMOS inverter circuits is composed of a transistor having a long channel length in 4, ..., It is also possible to use transistors having a long channel length for the transistors of all the inverter circuits in the buffer circuit 54.

Further, in the above-described embodiment, a transistor having a channel length longer than that of other transistors is used. However, the present invention is not limited to this configuration, and in addition to the above-mentioned configuration, a plurality of transistors are used. A multi-gate structure in which the gate electrode of the divided transistor is shared is adopted, and further, impurity regions having different concentrations are formed in the semiconductor layer of the transistor. (LD
D) A structure may be adopted. Since such a multi-gate structure or LDD structure can further reduce the electric field strength of the PN junction portion of the transistor, off current (leakage current) can be reduced and power consumption can be significantly reduced. .

Further, in the above-mentioned embodiment, the TFT adopting the transistor having the long channel length is the TFT of the liquid crystal drive circuit, but of course, the TFT is not limited to this, and the TFT forming the pixel portion is also applicable. The above-mentioned transistor having a long channel length may be adopted.

Further, in the above embodiment, the channel length of a normal transistor is 6 μm and the long channel length is 10 μm.
However, the actual channel length is determined by the relative relationship such as the channel width and the characteristics of the transistor. However, it is not limited to these channel lengths. When the channel lengths of the transistors are compared, the channel length of the final-stage transistor is made longer. Furthermore, although the channel length of the transistor at the final stage of the display drive circuit is set to be long in the above-described embodiments, the gate length of the transistor having a large off current (leakage current) may be set to be long.

Further, in the above embodiment, as shown in FIG. 1, the structure of the transistor is a bottom gate inverted stagger type transistor, but the invention is not limited to this, and a top gate coplanar type transistor or another type. A transistor structure can also be adopted.

[0079]

According to the display driving device of the first aspect,
The channel length of the transistor used in the final stage inverter circuit in the output circuit block having a plurality of stages of inverter circuits and outputting the drive voltage in the display drive circuit is longer than the channel length of the other transistors. With this structure, the electric field strength at the PN junction portion of the transistor is reduced, so that the off current (leakage current)
Can be reduced. In particular, the inverter circuit at the final stage in the output circuit block of the display drive circuit has a large current in order to increase the drive capability and obtain a sufficient on-current. The power consumption of the drive device can be effectively reduced.

According to the display driving device of the second aspect, the final stage of the tri-state circuit which has a plurality of stages of inverter circuits and outputs the display signal in the signal side driving circuit which is the display driving circuit. Since the channel length of the transistor of the inverter circuit is configured to be longer than the channel length of other transistors, the off current can be effectively reduced, and the transistor with the long channel length can be connected to the final stage of the tri-state circuit. Since it is used only for the inverter circuit, the increase in the circuit area can be suppressed to the minimum.

According to the display drive device of the third aspect, the final stage inverter of the buffer circuit which has a plurality of stages of inverter circuits in the scanning side drive circuit which is a display drive circuit and outputs the scanning signal. Since the channel length of the transistor in the circuit is configured to be longer than the channel length of other transistors, the off current can be effectively reduced, and the transistor with the long channel length can be used as the inverter circuit at the final stage of the buffer circuit. Since it is limited to the above, the increase in the circuit area can be suppressed to the minimum.

According to the display driving device of the fourth aspect, since the inverter circuit is composed of complementary CMOS transistors each composed of an nMOS transistor and a pMOS transistor, an input gate voltage is input. For nMOS transistor or pM
Since one of the OS transistors is turned on when the other is turned on, the current consumption is reduced and an appropriate output level can be obtained.

[Brief description of drawings]

FIG. 1 is a CMOS with a long channel length according to the present embodiment.
FIG. 3 is a cross-sectional configuration diagram of an inverter circuit including transistors.

FIG. 2 is a diagram showing a connection example for detecting an on-current of an nMOS transistor 23.

3 is a diagram showing a Vg-Id characteristic for detecting an on-current of the transistor of FIG.

FIG. 4 is a drive circuit integrated type TFT-L according to the present embodiment.
The schematic block diagram of CD.

5 is a diagram showing a part of a specific example of the liquid crystal drive circuit and the liquid crystal display panel of FIG.

FIG. 6 is a diagram showing a specific configuration example of a latch circuit and a tri-state circuit of FIG.

7 is a diagram showing a specific configuration example of a scanning shift register and a buffer circuit in FIG.

FIG. 8 is a diagram showing a configuration of a conventional CMOS inverter circuit.

9 is an nM configuring the CMOS inverter circuit of FIG.
FIG. 6 is a cross-sectional configuration diagram of an OS transistor.

FIG. 10 is a diagram showing a connection example for detecting an off current of an nMOS transistor.

FIG. 11 is a diagram showing a relationship between drain voltage and drain current of an nMOS transistor having a channel width (W) of 60 μm and a channel length (L) of 6 μm in FIG.

FIG. 12 is a diagram showing a relationship between drain voltage and drain current of an nMOS transistor having a channel width (W) of 60 μm and a channel length (L) of 10 μm in FIG. 9B.

[Explanation of symbols]

21 inverter circuit 22 pMOS transistor 23 nMOS transistor 24 glass substrate 25 base insulating films 26, 27 gate electrode 28 gate insulating films 29, 30 semiconductor layers 291, 293 p-type impurity implantation region 292 channel regions 301, 303 n-type impurity implantation region 302 Channel region 31 Interlayer insulating film 32 Source / drain electrode 41 Drive circuit integrated TFT-L
CD 42 Liquid crystal display panel 43 Gate driver 44 Drain driver 45 Glass substrate 51 External circuit 52 Data shift register 53 Scanning shift register 54 Buffer circuit 55 Frame signal line 56 CMOS inverter circuit LA101, LA102 Latch circuit TS101, TS102 Tristate circuit TR7 pMOS transistor TR8 nMOS transistors 81 to 104 Inverter circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1/1368 G09G 3/36

Claims (4)

(57) [Claims] 1. A display drive device comprising a display drive circuit for performing display control by applying a predetermined drive voltage to a display section, the display drive device comprising a plurality of stages of inverter circuits. A display driver, wherein a channel length of a transistor used in an inverter circuit at a final stage in an output circuit block that outputs a drive voltage is configured to be longer than a channel length of other transistors. 2. A display drive device for driving a liquid crystal display panel in which pixels are formed in a matrix in a liquid crystal cell, wherein a plurality of inverters are provided in a signal side drive circuit for supplying a display signal to each pixel. 2. A tri-state circuit having a circuit for outputting the display signal is configured so that a channel length of a transistor of an inverter circuit at a final stage is longer than a channel length of a transistor of other circuits. The display driving device described. 3. A display drive device for driving a liquid crystal display panel in which pixels are formed in a matrix in a liquid crystal cell, wherein a plurality of inverters are provided in a scan side drive circuit for supplying a scan signal to each pixel. The channel length of a transistor of a final stage inverter circuit of a buffer circuit having a circuit and outputting the scan signal is configured to be longer than the channel length of transistors of other circuits. Display drive device. 4. The inverter circuit according to claim 1, wherein the inverter circuit is an inverter circuit formed of complementary CMOS transistors each including an nMOS transistor and a pMOS transistor. Display drive device.