JP3514002B2 - Display drive - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display driving device, and more particularly to a display driving device using a multi-gate structure transistor in which a plurality of transistors are connected in series and driven by a common gate electrode.

[0002]

2. Description of the Related Art A display driving device includes, for example, a liquid crystal driving device that drives a liquid crystal to control display. In the case of this liquid crystal driving device, it can be divided into a segment system and a matrix system depending on the display form. The matrix type is used in display devices such as liquid crystal televisions, personal computers, and word processors for displaying images. The matrix method includes a simple matrix method and an active matrix method, but an active matrix method that has high image quality and does not have a crosstalk phenomenon is receiving attention.

An active matrix type liquid crystal drive device displays an image by applying a voltage to the liquid crystal portion of each pixel by a liquid crystal drive element provided for each pixel.
A thin film transistor (TF) is used as the liquid crystal driving element.
T: Thin Film Transistor) has become rapidly popular in recent years. This thin film transistor was developed as a liquid crystal driving element that overcomes the drawbacks of the MOS transistor formed on the previous silicon single crystal substrate, that is, that the size of the display screen is limited and that it cannot be made transmissive. Is. This thin film transistor is one in which impurities are injected into a predetermined region of a semiconductor thin film formed on a substrate such as glass to form a transistor. In particular, as materials for semiconductor thin films for liquid crystal display devices, cadmium selenide,
Polycrystalline silicon, amorphous silicon or the like is used.

Conventionally, when a driver circuit of a liquid crystal display device or the like is integrally formed on a glass substrate by using thin film transistors (TFTs), it is usually CMOS (Compleme).
nta-ry Metal Oxide Semiconductor) circuit is used. This CMOS circuit consists of an nMOS transistor that carries current by electrons and a pM transistor that carries current by holes.
It is a complementary transistor circuit in which an OS transistor is paired.

For example, FIG. 7 is a diagram showing a configuration of a conventional CMOS inverter circuit 1. As shown in FIG.
The MOS inverter circuit 1 is configured by connecting sources or drains of two types of transistors, pMOS2 and nMOS3, in series between a power supply (Vdd) and a ground (GND).

FIG. 8 is a cross-sectional view of the CMOS inverter circuit 1 shown in FIG. As shown in FIG. 8, a base insulating film 5 having a predetermined thickness is formed on a glass substrate 4, and semiconductor layers 6 and 7 are selectively formed on the nMOS transistor forming region and the pMOS transistor forming region, respectively. ing.

Ion implantation masks are sequentially formed on the semiconductor layers 6 and 7, and n-type or p-type impurity ions are doped so that regions having different impurities or impurity concentrations are formed. Specifically, 61 and 65 are n-type high-concentration impurity implantation regions, 62 and 64 are n-type low-concentration impurity implantation regions, and 63 is an intrinsic semiconductor region, which are channel regions. Further, 71 and 75 are p-type high concentration impurity implantation regions, 72 and 74 are p-type low concentration impurity implantation regions, and 73.
Is an intrinsic semiconductor region and serves as a channel region. As described above, in FIG. 8, a so-called low-concentration ion implantation drain (LDD) structure in which impurity regions having different concentrations are formed in the semiconductor layers 6 and 7 is adopted. However, in the structure of FIG. 8, since the resist pattern is easily formed, the source region also has the LDD structure.
Since the LDD structure is adopted, the PN junction portion of the thin film transistor, that is, the low concentration impurity region is formed between the high concentration impurity region to which the electrode is connected and the channel region. As a result, the off current (leakage current) can be reduced.

Further, on the surfaces of the base insulating film 5 and the semiconductor layers 6 and 7, the gate insulating film 8 is formed on the entire surface so as to cover them, and the gate electrode 9 is formed at a predetermined position on the gate insulating film 8. An interlayer insulating film 10 is formed selectively on each gate electrode 9 so as to cover the gate electrode 9 and flatten the surface.

Next, in order to form source / drain electrodes, contact holes penetrating the interlayer insulating film 10 and the gate insulating film 8 to reach predetermined positions of the semiconductor layers 6 and 7 are formed by anisotropic etching. It And
Aluminum (A
The source / drain electrode 11 made of 1) or the like is embedded and wired to form the CMOS inverter circuit 1 shown in FIG. 7.

The CMOS inverter circuit 1 shown in FIG. 7 and FIG. 8 has an nMOS when the IN (input) is "0".
The transistor 3 is turned off, the pMOS transistor 2 is turned on, and "1" is output (output) from the power supply Vdd. When the input is "1", the pMOS transistor 2 is turned off and the nMOS transistor 3 is turned on, so that "0" is output from the ground. In this way, CMOS
The inverter circuit can output the logic opposite to the input logic.

In addition to the above-mentioned inverter circuit, the conventional CMOS transistor is used in combination with a CMOS transistor, so that a latch circuit, an AND circuit, a NAND circuit, and
Alternatively, a tristate circuit or the like can be configured.

[0012]

However, in such a conventional display driving device, the operating frequency of the CMOS transistor composed of TFT is "f", the load capacitance is "C", and the power supply voltage is Where “Vdd” and leakage current are “IL”, the power consumption of the CMOS transistor can be expressed by the following equation.

W (power consumption) = f.C.Vdd (dynamic power consumption) + IL.Vdd (static power consumption) As shown in FIG. Although the leakage current is reduced by adopting the LDD structure for the layers 6 and 7, the value of the leakage current “IL” is still small and the consumption of the entire display driver including a large number of CMOS transistors is reduced. There has been a problem that the leak current (static power consumption) accounts for a large proportion of the electric power.

Further, the performance required for a thin film transistor used in a liquid crystal display device is that an on-current (sufficient on-current for driving liquid crystal) and an off-current ( The leak current is as small as possible. However, if the channel length is made short and the channel width is made large in order to obtain a sufficient on-current, the electric field strength at the PN junction portion becomes large, and thus the off-current increases, which is a trade-off phenomenon.

Therefore, conventionally, a multi-gate thin film transistor in which a plurality of thin film transistors connected in series to a semiconductor thin film are formed to divide a channel length and a gate electrode is provided for each channel is used.

However, in the thin film transistor having the multi-gate structure, the number of gates has to be increased in order to reduce the off current, and there is a problem that the mounting area of the transistor also increases as the number of gates increases.

In particular, if all the CMOSs, which are made up of a large number of thin film transistors that constitute the liquid crystal drive circuit, have a multi-gate structure, there is a problem that the circuit area increases further.

Therefore, the present invention has been made in view of the above problems, and minimizes the increase in circuit area while reducing the leak current, which is the static power consumption of a transistor, to reduce the overall consumption. It is an object of the present invention to provide a display drive device capable of reducing power consumption.

[0019]

A display driving device according to claim 1, wherein the display driving device comprises a display driving circuit for applying a predetermined driving voltage to a display section to control display. In the output circuit block that has a plurality of stages of inverter circuits in the circuit and outputs the drive voltage, only each transistor used in the final stage inverter circuit is divided into a plurality of transistors. The source and drain of the transistors are connected in series, and the gate electrodes of the plurality of divided transistors are commonly used for simultaneous driving.

Here, as described above, a structure in which the sources or drains of a plurality of transistors are connected in series and the gate electrodes of the plurality of transistors are shared and simultaneously driven is called a multi-gate structure. In the present invention, this multi-gate transistor is used in the final stage inverter circuit in the output circuit block of the display drive circuit.

Therefore, when a transistor having a multi-gate structure is adopted, the electric field strength of the PN junction portion in each transistor is dispersed by dividing the channel length into shorter parts, and as a result, the off current is reduced. You can In particular, in the final stage of the output circuit block of the display drive circuit, a large current is required in order to increase the driving capability and obtain a sufficient on-current. Therefore, it is effective to use a multi-gate structure for the transistor in this part. The off current can be reduced.

Further, in the display driving device according to claim 1, for example, as described in claim 2, the display part is a liquid crystal display panel in which pixels are formed in a matrix in a liquid crystal cell. The display drive circuit has a signal side drive circuit for supplying a display signal to each of the pixels, and has a plurality of stages of inverter circuits included in the signal side drive circuit to output the display signal. Only each transistor constituting the final stage inverter circuit of the circuit is divided into a plurality of transistors, the sources or drains of the plurality of transistors are connected in series, and the gate electrodes of the divided transistors are connected to each other. You may make it common and drive simultaneously.

Therefore, since only the transistor of the inverter circuit at the final stage of the tri-state circuit of the signal side driving circuit which is the display driving circuit has the multi-gate structure, the off current can be effectively reduced and the multi-gate structure can be achieved. Since it is used only in the tri-state circuit, the increase in the circuit area can be minimized.

Further, in the display driving device according to claim 1, for example, as described in claim 3, the display portion is a liquid crystal display panel in which pixels are formed in a matrix in a liquid crystal cell, The display drive circuit has a scan side drive circuit that supplies a scan signal to each of the pixels, and a buffer circuit that includes a plurality of stages of inverter circuits included in the scan side drive circuit and outputs the display signal. , Only each transistor that constitutes the final stage inverter circuit is divided into a plurality of transistors, the sources or drains of the plurality of transistors are connected in series, and the gate electrodes of the plurality of divided transistors are shared. You may make it drive simultaneously.

Therefore, since only the transistor of the inverter circuit at the final stage of the buffer circuit of the scanning side drive circuit which is the display drive circuit has the multi-gate structure, the off current can be effectively reduced and the multi-gate structure can be realized. Since it is used only for the buffer circuit, the increase in the circuit area can be suppressed to the minimum.

Further, the inverter circuit of the display drive device according to any one of claims 1 to 3 is, for example, as described in claim 4.
NMOS transistor and pMOS, as described in
It may be an inverter circuit formed of complementary CMOS transistors formed by pairing transistors.

Therefore, the CMOS transistor has an nMO
Since the S-transistor and the pMOS transistor are paired, nM is applied to the input gate voltage.
Since one of the OS transistor and the pMOS transistor is turned on when the other is turned on, the current consumption is small and an appropriate output level can be obtained.

Further, the semiconductor region of the transistor of the display driving device according to any one of claims 1 to 4 is, for example, as described in claim 5, at least two high-concentration impurity regions and this high-concentration impurity region. A plurality of channel regions existing between the high-concentration impurity regions, and a low-concentration impurity region between the high-concentration impurity region and the channel region, with an insulating layer interposed at a position corresponding to each of the channel regions. A common gate electrode may be formed.

Therefore, since the transistor of the display driving device adopts the low concentration ion implantation drain (LDD) structure in addition to the adoption of the multi-gate structure, the PN junction part of the transistor, that is, the source / drain electrodes. A low-concentration impurity region is provided between a high-concentration impurity region connected to the channel region and a plurality of channel regions, and the electric field strength at the PN junction portion is reduced, so that the off-state current can be further increased without increasing the area of the transistor. It is possible to reduce the power consumption. Note that the multi-gate structure of a transistor has a dual gate in the case of two gate electrodes, a triple gate in the case of three gate electrodes, and a four gate structure.
This case is called a quad gate, and the number of gate electrodes may be 5 or more. And the effect of reducing the off current is
The number of triple gates, which has a larger number of gates, is significantly lower than the number of dual gates described above. However, increasing the number of gates leads to an increase in circuit area.
By combining with the D structure, off-state current can be reduced without increasing the area of the transistor.

Further, between the respective channel regions of the display driver according to the fifth aspect, for example, as described in the sixth aspect, low-concentration impurity regions may be formed.

Therefore, even if the channel regions of the multi-gate structure transistor are formed only by the low-concentration impurity regions, the effect of reducing the off-current due to the LDD structure can be obtained, and the power consumption can be reduced.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

1 to 6 are views showing an embodiment of a display driving device of the present invention. Here, a liquid crystal driving circuit and a thin film transistor (TFT) for each pixel of a pixel portion are arranged on a glass substrate. A switching element composed of the above is integrally formed and implemented as a drive circuit integrated liquid crystal display device. In the present embodiment, the final stage transistor of the liquid crystal drive circuit described above is composed of a CMOS transistor having a dual gate structure.

First, the structure will be described.

FIG. 1 is a diagram showing an inverter circuit 21 composed of CMOS transistors having a dual gate structure which constitutes the final stage of the liquid crystal drive circuit. The inverter circuit 21 shown in FIG. 1 is composed of the nMOS transistor 2 and pM of the inverter circuit 1 shown in FIG.
Each of the OS transistors 3 is divided into two and the gate electrodes are made common. That is, the inverter circuit 21 of FIG. 1 has pMOS transistors 22, 23 and nM.
It is composed of OS transistors 24 and 25, and pMOS transistors 22 and 23 and nMOS transistors 24 and 25 are provided between the power supply (Vdd) and the ground (GND).
Of the transistors 22 to 25 are connected in series, and the gate electrodes 31 of these transistors 22 to 25,
32 are connected to each other for common use. The common gate electrode described above is connected to the input terminal (I
N) and the pMOS transistor 23 and nMO described above.
A connection portion with the S transistor 24 is used as an output terminal (OUT).

When a transistor having a dual gate structure is adopted as in this embodiment, the electric field strength of the PN junction portion of each transistor is dispersed due to the short channel length of the transistor, The off-state current of the transistor can be reduced.

Next, FIG. 2 is a sectional configuration diagram of the CMOS inverter circuit 21 of FIG. As shown in FIG. 2, a base insulating film 27 having a predetermined thickness is formed on the entire surface of the glass substrate 26. On the surface of the base insulating film 27, thin film semiconductor layers 28 and 29, which are composed of a plurality of different regions, an nMOS transistor forming region and a pMOS transistor forming region, are selectively formed.

In the thin film semiconductor layers 28 and 29, a plurality of masks for ion implantation (not shown) are formed, and n-type or p-type is formed so as to partially form impurities and a plurality of regions having different impurity concentrations. The impurity ions forming the semiconductor of the type are doped.

Specifically, 281, 287 are n-type high-concentration impurity implantation regions, and 282, 284, 286 are:
The n-type low-concentration impurity implantation regions 283 and 285 are intrinsic semiconductor regions into which impurities are not implanted and serve as channel regions.

Further, 291, 297 are p-type high-concentration impurity implantation regions, 292, 294, 296 are p-type low-concentration impurity implantation regions, and 293, 295 are intrinsic semiconductor regions into which impurities are not implanted and are channel regions. Becomes

As described above, in the CMOS inverter circuit 21 shown in FIG. 2, in addition to the above-described dual gate structure, impurity regions having different concentrations are formed in the thin film semiconductor layers 28 and 29, so-called low concentration. An ion implantation drain (LDD) structure is adopted. However, Figure 2
In the LDD structure shown in (1), not only the drain region but also the source region has the LDD structure. Since the LDD structure is adopted, the PN junction portion of the thin film transistor, that is, the low concentration impurity region is formed between the high concentration impurity region to which the electrode is connected and the channel region. As a result, the off current (leakage current) can be reduced.

As described above, in the present embodiment, by combining the dual gate structure and the LDD structure,
Static power consumption (off-current) of the thin film transistors that make up the LCD drive circuit while minimizing the increase in circuit area
To reduce the power consumption of the liquid crystal drive circuit as a whole.

Returning to FIG. 2 again, the thin film semiconductor layer 28,
The entire surface of 29 is covered with a gate insulating film 30, and each channel region 28 on the surface of the gate insulating film 30 is covered.
Gate electrodes 31 and 32 are formed at positions corresponding to 3, 285, 293, and 295. The gate insulating film 30 and the gate electrodes 31 and 32 are covered with the interlayer insulating film 33.

Next, the above-mentioned thin film semiconductor regions 28, 2
High-concentration impurity regions 281, 287, 291,
A gate insulating film 30 and an interlayer insulating film 33 above 297
In order to form source / drain electrodes, contact holes are formed by anisotropic etching, and aluminum (Al) is formed in each contact hole.
The source / drain electrodes 34 made of
The CMOS inverter circuit 21 is formed by wiring as shown in FIG.

The CMOS inverter circuit 21 shown in FIGS. 1 and 2 described above has an nMO level when IN (input) is "0".
S24 and 25 are turned off, pMOSs 22 and 23 are turned on, and "1" is output (output) from the power supply Vdd. When the input is "1", the pMOSs 22 and 23 are turned off and n
When the MOSs 24 and 25 are turned on, "0" is output from the ground. In this way, the CMOS inverter circuit 21 outputs the logic opposite to the input logic.

As described above, in the present embodiment, the final stage thin film transistor of the liquid crystal drive circuit is configured by using the CMOS inverter circuit 21 in which the LDD structure is added to the multi-gate structure. This is because the final stage of the liquid crystal drive circuit has a large current in order to increase the driving capability and obtain a sufficient on-current, so at least the transistor in this part has a multi-gate structure, so that the transistor is effectively turned off. This is because the current can be reduced.

In the present embodiment, the final stage thin film transistor of the liquid crystal drive circuit has a dual gate structure as shown in FIGS. 1 and 2, but the invention is not limited to this, and a multi-gate structure having a plurality of gate electrodes. If For example, if there are three gate electrodes, a triple gate structure,
The case of four is called a quad gate structure. The effect of reducing the number of gate electrodes and the off-current of the thin film transistor is significantly reduced as the number of gate electrodes is increased, but blindly increasing the number of gates leads to an increase in circuit area.

Therefore, in the present embodiment, the above-mentioned multi-gate structure is limited to the thin film transistor at the final stage of the liquid crystal drive circuit, and the LDD structure described later is combined to minimize the increase in the area of the transistor. , To reduce the off current.

Next, FIG. 3 is a schematic configuration diagram of the drive circuit integrated TFT-LCD 41 according to the present embodiment. The drive circuit integrated type TFT-LCD 41 includes a glass substrate 45.
Liquid crystal display panel (TFT-LCD: Thin Film Tran)
sistor-Liquid Crystal Display) 42, a gate driver 43 for driving switching elements of each pixel arranged in a matrix on the liquid crystal display panel 42, and a drain driver 44 are integrally formed by COG (Chip On Glass) technology. There is.

FIG. 4 is a diagram showing a part of a concrete example of the liquid crystal drive circuit and the liquid crystal display panel of FIG.

In the liquid crystal display panel 42 shown in FIG. 4, a TFT connected to each pixel and the TFT form a liquid crystal capacitor LC between the pixel electrode and the common electrode.
Then, from the gate driver 43, each gate line G
Scan signals are sequentially applied to 1, G2, G3, ... To drive the gates of the TFTs connected to the respective scan lines to create a selected state and a non-selected state. Here, the TFT on the scanning line selected by the gate driver 43 is
From the drain driver 44 to each drain line D1, D
When a display signal is applied to 2, ..., A drive voltage is applied to the pixel electrode in the selected state, the liquid crystal is driven by the potential difference between the pixel electrode and the common electrode, and display control is performed.

Since the present embodiment is characterized by the configuration of the drain driver 44 and the gate driver 43 which are liquid crystal drive circuits, the configuration and operation will be described separately for the drain driver and the gate driver.

(Drain driver) As shown in FIG.
The drain driver 44 includes a data shift register 52.
And latch circuits LA101 and LA102, and tristate circuits TS101 and TS102.

The data shift register 52 receives the horizontal synchronizing signal φH and the horizontal clock signal C from the external circuit 51.
PH is input and the horizontal synchronizing signal φH is sequentially shifted by the horizontal clock signal CPH while the output terminals DS
From R1 and DSR2 to latch circuits LA101 and L, respectively
A latch signal for latching the video signal is output to the control terminal L of A102.

Latch circuits LA101, LA102 are provided by the number corresponding to the drain lines D1, D2, ..., The input terminals I are connected to the video signal line L100, and the video signal line L100 is provided with an external circuit. 5
The 1- to 2-valued video signal DATA is applied and the latch signal is input to the control terminal L from the data shift register 52 described above. The serial binary video signal DATA input from the video signal line L100 latches data at the timing of the latch signal input to each latch circuit LA101, LA102, and the latched data is output from the output terminal O to the next stage. It is output to the state circuit.

Tristate circuits TS101, TS10
2 are arranged in the final stage of the drain driver 44 by the number corresponding to each drain line D1, D2, ... And generate a liquid crystal drive voltage for AC driving the liquid crystal based on the latch data of the above-mentioned latch circuit. It is a circuit to do. The control terminals of the tri-state circuits TS101 and TS102 are
The output terminals O of the latch circuits LA101 and LA102 are respectively connected, and the positive power supply terminal and the negative power supply terminal of each tri-state circuit are connected to the output positive power supply VOH and the output negative power supply VOL. The drain terminals D1, D2, ... Are connected to the output terminals of the tri-state circuits TS101, TS102, ..., respectively, and the liquid crystal drive voltage is supplied to the pixel electrodes via the TFTs.

FIG. 5 is a diagram showing a specific configuration example of the latch circuit LA101 and the tri-state circuit TS101 of FIG. The latch circuit LA101 shown in FIG. 5 includes transfer gates TG1 and TG2 and inverters IN1 and IN.
2 and IN3 are provided.

The output terminal DSR1 of the data shift register 52 is connected to the transfer gate TG1.
P-side control terminal and transfer gate TG2 N
It is connected to the side control terminal and is also connected to the N side control terminal of the transfer gate TG1 and the P side control terminal of the transfer gate TG2 via the inverter IN1. Then, the first of the transfer gate TG1
Of the transfer gate TG1 is connected to the video signal line L100, and the second non-control terminal of the transfer gate TG1 is connected to the first non-control terminal of the transfer gate TG2 via the inverters IN2 and IN3 in series. The second non-control terminal of the gate TG2 is connected to the second non-control terminal of the transfer gate TG1.

Next, the tri-state circuit TS shown in FIG.
101 includes inverters IN4, IN5, IN6 and transistors TR1 to TR10. here,
The transistors are TR1, TR2, TR4, TR
7, TR8 is a pMOS transistor, TR3,
TR5, TR6, TR9 and TR10 are composed of nMOS transistors.

Therefore, from the connecting portion of the inverters IN2 and IN3 of the latch circuit LA101 described above, the inverters IN4, IN5, IN of the tri-state circuit TS101 are connected.
6 in series with pMOS transistors TR1 and n
It is connected to each gate of the MOS transistor TR5.

The connection between the inverters IN5 and IN6 is connected to the gates of the pMOS transistor TR2 and the nMOS transistor TR3.

Further, the gates of the pMOS transistor TR4 and the nMOS transistor TR6 are
Frame signal line 55 to which the frame signal φf is input
Connected to.

Then, the pMOS transistor TR1
Source is connected to the positive power supply Vcc and the drain is pMO
It is connected to the source of the S transistor TR2. further,
The drain of the pMOS transistor TR2 is nMO
This nM is connected to the drain of the S transistor TR3.
The source of the OS transistor TR3 is grounded.

Further, the pMOS transistor TR4
Has a source connected to the positive power source Vcc and a drain connected to nMO
It is connected to the drain of the S transistor TR5. This n
The source of the MOS transistor TR5 is further nMO.
This nM is connected to the drain of the S transistor TR6.
The source of the OS transistor TR6 is grounded.

Then, the pMOS transistor TR1
And the drains of TR4 are connected to each other, and the pMOS of the CMOS inverter circuit 56 having the dual gate structure is connected.
It is connected to a common gate electrode of transistors TR7 and TR8.

The drain of the pMOS transistor TR2 is connected to the source of the nMOS transistor TR5, and the nMOS transistors TR9 and T of the dual gate structure CMOS inverter circuit 56 are connected.
It is connected to the common gate electrode of R10.

Then, the CMOS inverter circuit 56
The source of the pMOS transistor TR7 is connected to the output positive power source VOH, the drain of the pMOS transistor TR8 is connected to the data line D1, and the nMO
NMOS connected to the drain of S transistor TR9
The source of the transistor TR10 is connected to the output negative power supply VOL.

The drain driver 44 according to the present embodiment
Is characterized in that the tri-state circuit TS1 arranged at the final stage of the drain driver 44 which is a liquid crystal drive circuit.
In 01, the transistors TR7 to TR10 are used to form the CMOS inverter circuit 56 having a dual gate structure (so-called multi-gate structure).
As a result, the channel length is divided shorter than in the case of using a normal CMOS inverter circuit, the electric field strength of the PN junction portion of each transistor is dispersed, and the off current of the transistor can be reduced. In particular, in the present embodiment, the drain driver 4 that flows a large current in order to sufficiently enhance the driving capability and obtain a sufficient on-current.
Because the dual gate structure was adopted only in the last stage of 4,
The off-current is effectively reduced while the increase in the circuit area is minimized.

Next, the operation will be described.

The data shift register 52 shown in FIG.
Receives the horizontal synchronizing signal φH and the horizontal clock signal CPH from the external circuit 51 and outputs the signal DSR1.
It is supplied to the control terminal L of the latch circuit LA101. Also,
The video signal DA is input to the input terminal I of the latch circuit LA101.
TA is supplied.

In FIG. 5, when the output signal DSR1 from the data shift register 52 goes to the low level, the output of the inverter IN1 goes to the high level, so the transfer gate TG1 turns on, When the video signal DATA is taken in and the output signal DSR1 of the data shift register 52 becomes high level, the output of the inverter IN1 becomes low level.
The transfer gate TG1 is turned off, the transfer gate TG2 is turned on, and the video signal DAT
A is stored.

Therefore, the case where the video signal DATA is at the low level will be described.

The low-level video signal DATA becomes high level via the inverters IN2, IN4, IN5, and is supplied to the gates of the pMOS transistor TR2 and the nMOS transistor TR3.
The MOS transistor TR2 is turned off and the nMOS transistor TR3 is turned on. In addition, the low level video signal D
ATA is an inverter IN2, IN4, IN5, IN6
To the low level via the pMOS transistor TR
1 and nMOS transistor TR5 are supplied to their respective gates, so that pMOS transistor TR1 is turned on and nMOS transistor TR5 is turned off. nMO
When the S transistor TR3 is turned on, the nMOS
The gates of the transistors TR9 and TR10 are grounded and turned off. Further, when the pMOS transistor TR1 is turned on, the pMOS transistors TR7 and TR8 are turned off by the positive power supply Vcc being supplied to their gates. Therefore, the output positive power supply VOH and the output negative power supply VOL are not supplied to the data line D1.

Next, the case where the video signal DATA is at the high level and the frame signal φf is at the high level will be described.

The high-level video signal DATA becomes low level via the inverters IN2, IN4, IN5, and is supplied to the gates of the pMOS transistor TR2 and the nMOS transistor TR3.
The MOS transistor TR2 is turned on and the nMOS transistor TR3 is turned off. In addition, the high level video signal D
ATA is an inverter IN2, IN4, IN5, IN6
To the high level via the pMOS transistor TR
1 and nMOS transistor TR5 are supplied to the respective gates, so that pMOS transistor TR1 is turned off and nMOS transistor TR5 is turned on. Also,
Since the high-level frame signal φf is supplied to the gates of the pMOS transistor TR4 and the nMOS transistor TR6, the pMOS transistor TR4
Is turned off and the nMOS transistor TR6 is turned on. n
When the MOS transistor TR5 and the nMOS transistor TR6 are turned on, the pMOS transistor T5
The gates of R7 and TR8 are turned on with their gates grounded, and the nMOS transistors TR9 and TR10 are turned off with their gates grounded. Therefore, by turning on the pMOS transistors TR7 and TR8,
The output positive power supply VOH is supplied to the data line D1.

Next, the case where the video signal DATA is at the high level and the frame signal φf is at the low level will be described.

The high-level video signal DATA becomes low level via the inverters IN2, IN4, IN5, and is supplied to the gates of the pMOS transistor TR2 and the nMOS transistor TR3.
The MOS transistor TR2 is turned on and the nMOS transistor TR3 is turned off. In addition, the high level video signal D
ATA is an inverter IN2, IN4, IN5, IN6
To the high level via the pMOS transistor TR
1 and nMOS transistor TR5 are supplied to the respective gates, so that pMOS transistor TR1 is turned off and nMOS transistor TR5 is turned on. Also,
Since the low-level frame signal φf is supplied to the gates of the pMOS transistor TR4 and the nMOS transistor TR6, the pMOS transistor TR4
Is turned on and the nMOS transistor TR6 is turned off. p
When the MOS transistor TR4 and the nMOS transistor TR5 are turned on, the pMOS transistor T4
The R7 and TR8 are turned off by the positive power supply Vcc being supplied to their gates, and the nMOS transistors TR9 and TR10 are turned on by the positive power supply Vcc being supplied to their gates. Therefore, the nMOS transistors TR9 and T
When R10 is turned on, the output negative power supply VOL is supplied to the data line D1.

As described above, in the above-described embodiment, since the tri-state circuit TS101 arranged at the final stage of the drain driver 44 is provided with the CMOS inverter circuit 56 having the dual gate structure using the transistors TR7 to TR10, Since the electric field strength of the PN junction portion of each transistor is dispersed while suppressing an increase in the circuit area to a minimum, the off current can be effectively reduced, and the power consumption of the drain driver 44 can be reduced. .

(Gate Driver) As shown in FIG. 4, the gate driver 43 is composed of a scanning shift register 53 and a buffer circuit 54.

The scanning shift register 53 is the external circuit 5
1 to vertical synchronization signal φV and vertical clock signal CP
V is input. By the vertical synchronizing signal φV and the vertical clock signal CPV, the scanning shift register 53
Generates a horizontal scanning signal to be applied to a plurality of gate lines and sequentially applies the signals to the gate lines G1, G2, G3, ... While amplifying the signals in each buffer circuit 54, thereby forming thin film transistors of each pixel of the liquid crystal display panel 42. Horizontal scanning is performed by driving (TFT) on / off.

FIG. 6 shows the scanning shift register 53 of FIG.
FIG. 3 is a diagram showing a specific configuration example of a buffer circuit 54.

As shown in FIG. 6, the scanning shift register 53 includes latch circuits 61, 62, 63, 64 ,.
The NAND circuits 71, 72, 73, 74 ,.

In the latch circuits 61, 62, 63 and 64, the vertical synchronizing signal φV and the inverted vertical synchronizing signal φV input from the external circuit 51 are supplied to the control signal input end L and the inverted control signal input end L. Every other signal is input in the opposite phase. When "1" is input to the control signal input end L, the input signal is output through, and when "0" is input, the previous input signal is latched.

As for the input signal to the latch circuit 61, when the vertical clock signal CPV is input to the input end I from the external circuit 51, an output signal corresponding to the through state and the latch state is output to the output end O and the inverted output. It is output from the end portion O and is input to the NAND circuit 71 and the input end portion I of the latch circuit 62 at the next stage.

Similarly, the output signal of the latch circuit 62 is input to the NAND circuits 71 and 72 and the input end I of the latch circuit 63 at the next stage.

The NAND circuit 71 includes the latch circuit 6
1 and the inverting output from each inverting output end -0 of the latch circuit 62 are input and the negative logical product is output.

Similarly to the above, the latch circuits 63, 64, ...
, And the NAND circuits 73, 74, ... Are continuously connected to form a shift register, and the NAND circuits 71 to 7 are connected.
Negative logical ANDs output from the output signals 4 ... At predetermined timings are sequentially output to the buffer circuit 54 at the next stage.

The buffer circuit 54 is composed of three inverter circuits (for example, 81, 91, 101) connected in cascade, and the negative logical product input from each NAND circuit is obtained. Each gate line G1 is amplified while sequentially inverting the logic through each inverter circuit.
It is output to G2, G3, G4, ...

FIG. 6 merely illustrates a part of the structure of the gate driver 43 which supplies the gate lines for four lines, and the above-mentioned circuits are arranged according to the number of lines arranged in the vertical direction. There is. As a result, each gate line is line-scanned by a predetermined scanning method to bring each gate line into a selected state or a non-selected state.

As described above, the characteristic configuration of the gate driver 43 according to the present embodiment is that the buffer circuit 54 arranged at the final stage of the gate driver 43 which is a liquid crystal drive circuit.
In the above, some of the inverter circuits 101 to 104 are CMOS inverter circuits having the dual gate structure shown in FIGS. 1 and 2. This allows the normal C
The channel length is divided shorter than that of the MOS inverter circuit, and the electric field strength of the PN junction portion of each transistor is dispersed, so that the off current of the transistor can be reduced. In particular, in the present embodiment, since the dual gate structure is adopted in the final stage of the gate driver 43 through which a large current is passed in order to sufficiently enhance the driving capability and obtain a sufficient on-current, the increase in the circuit area can be minimized. At the same time, the off current can be effectively reduced, and the gate driver 4
3 can be reduced.

The drain driver 44 and the gate driver 43 described above are arranged so that the gate driver 43 causes the gate lines G1, G2, G3 of the liquid crystal display panel 42,
... are sequentially applied with a horizontal scanning signal to bring them into a selected state, and a video signal corresponding to each pixel on the horizontal scanning line in the selected state is supplied from the drain driver 44 to each data line D.
, D2, ..., Signal charges are transmitted to the thin film transistor of a predetermined pixel to drive the liquid crystal, so that display is performed.

Although the invention made by the present inventors has been specifically described based on the preferred embodiments, the present invention is not limited to the above-mentioned embodiments and does not depart from the gist of the invention. It goes without saying that various changes can be made within the range.

For example, in the above embodiment, the transistor having a dual gate structure has been described, but if the number of gates is increased, such as a triple gate or a quad gate, the effect of reducing the off current can be increased. Therefore, the transistor may have a so-called multi-gate structure in which the transistor is divided into a plurality and the plurality of gate electrodes are shared.

Further, in the above embodiment, the multi-gate structure CMOS inverter circuit 56 is arranged at the output stage of each of the tri-state circuits TS101, TS102, ... Provided at the final stage of the drain driver 44.
Other transistors in each tristate circuit may have a multi-gate structure.

Further, in the above-described embodiment, the inverter circuits 101, 102, 103, 10 at the output stage of the buffer circuit 54 provided at the final stage of the gate driver 43.
Although 4 ... Are composed of CMOS transistors having a multi-gate structure, all the inverter circuits in the buffer circuit 54 may have a multi-gate structure.

Further, in the above embodiment, the transistor in which the LDD structure is added to the multi-gate structure has been described, but the transistor may have a multi-gate structure but not the LDD structure.

In the above embodiment, the TFT adopting the multi-gate structure or the LDD structure is the TFT of the liquid crystal driving circuit, but it is not limited to this, and the TFT forming the pixel portion is not limited to this. The above-mentioned multi-gate structure or LDD structure may be adopted.

[0098]

According to the display driving device of the first aspect,
Display transistor with multi-gate structure
It is used for the final stage inverter circuit in an output circuit block that has a plurality of stages of inverter circuits and outputs the drive voltage. In the final stage inverter circuit of the output circuit block of this display drive circuit, since it becomes a large current in order to increase the drive capability and obtain a sufficient on-current, by making the transistor in this part a multi-gate structure, The electric field strength of the PN junction portion of the transistor is dispersed, and as a result, the off current can be reduced, so that the power consumption of the display driver can be reduced.

According to the display drive device of the second aspect, the final stage inverter of the tri-state circuit which has a plurality of stages of inverter circuits of the signal side drive circuit which is the display drive circuit and outputs the display signal. Since only the transistors that make up the circuit have a multi-gate structure, it is possible to effectively reduce the off-current, and since the multi-gate structure is limited to a tri-state circuit, the increase in circuit area can be minimized. .

According to the display driving device of the third aspect, the final stage inverter circuit of the buffer circuit which has a plurality of stages of inverter circuits of the scanning side driving circuit which is a display driving circuit and outputs the display signal. Since only the transistor that constitutes the transistor has a multi-gate structure, the off-current can be effectively reduced, and since the multi-gate structure is limited to the buffer circuit, the increase in the circuit area can be minimized.

According to the display driving device of the fourth aspect, since the inverter circuit is an inverter circuit of complementary CMOS transistors in which an nMOS transistor and a pMOS transistor are paired, it is possible to reduce the power consumption and to make it appropriate. The output level can be obtained.

According to the display driving device of the fifth aspect, in addition to the multi-gate structure, a low-concentration ion implantation drain (LDD) structure is adopted in the semiconductor region of the transistor, and source / drain electrodes are connected. Further, since the low-concentration impurity region is provided between the high-concentration impurity region and the plurality of channel regions, the electric field strength at the PN junction portion is reduced and the off current can be further reduced. Therefore, if the number of gates in the multi-gate structure is increased, the circuit area is increased. However, by combining with the LDD structure, it is possible to reduce the off-current while minimizing the increase in the area of the transistor.

According to the display driving device of the sixth aspect, since the low-concentration impurity regions are formed between the channel regions of the divided transistors, the effect of reducing the off-current due to the LDD structure is obtained and the consumption is reduced. Electric power can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an inverter circuit composed of CMOS transistors having a dual gate structure, which constitutes a final stage of a liquid crystal drive circuit.

FIG. 2 is a cross-sectional configuration diagram of the CMOS inverter circuit of FIG.

FIG. 3 is a drive circuit integrated type TFT-L according to the present embodiment.
The schematic block diagram of CD.

FIG. 4 is a diagram showing a part of a specific example of the liquid crystal drive circuit and the liquid crystal display panel of FIG.

5 is a diagram showing a specific configuration example of the latch circuit and the tri-state circuit of FIG.

FIG. 6 is a diagram showing a specific configuration example of a scanning shift register and a buffer circuit in FIG.

FIG. 7 is a diagram showing a configuration of a conventional CMOS inverter circuit.

8 is a cross-sectional configuration diagram of the CMOS inverter circuit of FIG.

[Explanation of symbols]

21 Inverter circuit 22, 23 pMOS transistor 24, 25 nMOS transistor 26 glass substrates 27 Base insulating film 28, 29 thin film semiconductor layer 281, 287 n-type high concentration impurity implantation region 282, 284, 286 n-type low concentration impurity implantation region 283, 285 channel area 291, 297 p-type high concentration impurity implantation region 292, 294, 296 p-type low concentration impurity implantation region 293 and 295 are channel regions. 30 Gate insulating film 31, 32 Gate electrode 33 Interlayer insulation film 34 Source / drain electrodes 42 Liquid crystal display panel 43 Gate driver 44 drain driver 51 External circuit 52 Data shift register 53 Scanning shift register 54 buffer circuit LA101, LA102 latch circuit TS101, TS102 Tri-state circuit TR7, TR8 pMOS transistor TR9, TR10 nMOS transistor 81-104 Inverter circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 616A (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 G02F 1 / 1368 G09G 3/36

Claims (6)

(57) [Claims] 1. A display drive device comprising a display drive circuit for performing display control by applying a predetermined drive voltage to a display section, the display drive device comprising a plurality of stages of inverter circuits. In the output circuit block that outputs the driving voltage, only each transistor used in the final stage inverter circuit is divided into a plurality of transistors, and the sources or drains of the plurality of transistors are connected in series, and a plurality of transistors are connected. A display driving device characterized in that the gate electrodes of the transistors divided into are shared and driven simultaneously. 2. The display unit is a liquid crystal display panel in which pixels are formed in a matrix in a liquid crystal cell, and the display drive circuit has a signal side drive circuit for supplying a display signal to each pixel, In the tri-state circuit that includes a plurality of stages of inverter circuits included in the signal side drive circuit and outputs the display signal, only each transistor that constitutes the final stage inverter circuit is divided into a plurality of transistors, 2. The display drive device according to claim 1, wherein the sources or drains of the plurality of transistors are connected in series, and the gate electrodes of the plurality of divided transistors are commonly used for simultaneous driving. 3. The display unit is a liquid crystal display panel in which pixels are formed in a matrix in a liquid crystal cell, and the display drive circuit has a scan side drive circuit for supplying a scan signal to each pixel, In the buffer circuit having a plurality of stages of inverter circuits included in the scanning side drive circuit and outputting the display signal, only each transistor forming the final stage inverter circuit is divided into a plurality of transistors, 2. The display driving device according to claim 1, wherein the sources or drains of the plurality of transistors are connected in series, and the gate electrodes of the plurality of divided transistors are commonly used for simultaneous driving. 4. The inverter circuit according to claim 1, wherein the inverter circuit is an inverter circuit formed of complementary CMOS transistors each including an nMOS transistor and a pMOS transistor. Display drive device. 5. The semiconductor region of the transistor has at least two high-concentration impurity regions, a plurality of channel regions existing between the high-concentration impurity regions, and between the high-concentration impurity region and the channel region. 5. A low-concentration impurity region, and a common gate electrode is formed at a position corresponding to each of the channel regions with an insulating layer interposed therebetween. The display drive device according to claim 1. 6. The display drive device according to claim 5, wherein a low-concentration impurity region is formed between the respective channel regions.