JP5351868B2 - Differential amplifier circuit, semiconductor device and display device - Google Patents

Abstract

This invention provides a thin film semiconductor device and its manufacturing method which can form n-channel thin film transistors (TFTs) and p-channel TFTs suitable for circuit characteristics on a polycrystalline silicon film without complicating the manufacturing processes. When n-channel thin film transistors (TFTs) and p-channel TFTs are formed on a polycrystalline silicon film 3 formed on a glass substrate 1, a process is included in which p-dopant or n-dopant is introduced to the channel regions of some n-channel TFTs and those of some p-channel TFTs at the same time. In one channel doping operation, a set of low-VT and high-VT p-channel TFTs and a set of low-VT and high-VT n-channel TFTs can be formed. This method is used for forming high-VT TFTs which can reduce the off-current for logics and switch circuits, and for forming low-VT TFTs which can increase the dynamic range for analog circuits, thus improving the performance of a thin film semiconductor device.

Description

  The present invention relates to a thin film semiconductor device, and in particular, a thin film semiconductor device and a differential amplifier circuit including at least an analog circuit unit and a switch using thin film transistors (TFTs) having different threshold voltages (VT). And a display device.

  2. Description of the Related Art Image monitors such as liquid crystal display devices and organic EL display devices that are thinner and lighter than CRTs are used as monitors for mobile terminal devices such as mobile phones and mobile devices, and notebook personal computers. These liquid crystal display devices and organic EL display devices use a thin film formation technique to form a display portion having pixels arranged in a matrix on an insulating substrate such as a glass substrate, and externally attached gate drivers and data A signal corresponding to display is given to each pixel from a driver circuit such as a driver, thereby controlling the alignment direction of the liquid crystal and the light emission of the organic EL element to display an image. In recent years, with the improvement of thin film formation technology, it has become possible to form TFTs using polycrystalline silicon on the same substrate as the display portion, and a part of the drive circuit is formed with TFT circuits using polycrystalline silicon. Has come to be able to.

  In portable terminal devices, it is important to reduce size, reduce power consumption, and improve performance, and accordingly, image display devices are also required to be reduced in size and power consumption. As a method for realizing downsizing of the image display device, the number of external parts can be reduced by forming the display unit and the driving circuit integrally on a glass substrate or the like, and downsizing can be realized. In addition, since the display portion and the drive circuit are formed integrally, load capacity due to connection resistance when externally attached or wiring to an external connection terminal is reduced, and power consumption can be reduced. In recent years, an image display device has been required to display with high definition and clearness, and there is an increasing demand for an active matrix display device in which each pixel is independently formed. In the active matrix display device, a switching element is provided for each pixel. When the switching element is turned on by a signal corresponding to an image supplied from a driving circuit and a signal for controlling the switching element, an image is displayed on each pixel. A signal corresponding to is displayed. Note that in the case where the active matrix display portion and the drive circuit are formed integrally on a glass substrate or the like, the switching elements (TFTs) of each pixel are formed simultaneously with the TFTs of the drive circuit formed on the same substrate. Will be.

  The TFT is composed of two types of TFTs, n-channel type and p-channel type. In general, the polycrystalline silicon film serving as an active layer tends to be n-type, so that the n-channel type TFT is somewhat depleted. As a result, the driving power is relatively increased and the off-current is increased. An image display device, particularly an image display device used for a portable terminal device, requires a low off-current at least in a switch TFT in order to reduce power consumption. The region is doped and VT is controlled.

  Since this channel doping is normally performed collectively for the channel regions of a plurality of TFTs, the dose amount of the dopant implanted into the plurality of TFTs is substantially equal. However, the dose of each TFT is one time doping. The amount can also be changed. For example, in Japanese Patent Laid-Open No. 8-264798, the thickness of a control film (silicon oxide film) for controlling the amount of dopant implanted is changed for each region, and doping is performed on the control film to reduce the thickness of the control film. A method is disclosed in which the dose is increased at the portion and the dose is decreased at the thick portion of the control film.

JP-A-8-264798 (page 4-7, FIG. 5)

Edited by Hiroshi Hara, "Basics of MOS Integrated Circuits", VLSI Introduction Series 5, page 64, published by Modern Science Co., Ltd., May 30, 1992

  The analysis of related technology is given below.

  There are various types of circuits formed using TFTs. Some circuits, such as logic circuits, perform digital processing using a low level and a high level binary level, while others can handle continuous quantities such as amplifier circuits. Some circuits perform processing. A switch is an element that switches between conduction and non-conduction between two terminals. It can shut off the current between the two terminals, confine the charge in combination with the capacitance, etc. Used in a circuit or an analog circuit.

  However, the performance required for TFTs differs depending on the type of circuit. For example, a TFT used for a logic circuit or a switch needs to have sufficient current drive capability in an on state and no current flows in an off state. In particular, it is important that the off-leak current is sufficiently small when reduction of power consumption is strongly required. In this case, the threshold voltage is set higher. On the other hand, in the case of a TFT used in an analog circuit, the TFT in the circuit section where idling current flows is always in an on state, and the operation of the analog circuit accurately adjusts the drain current from a small value to a large value depending on the TFT control voltage. It is important to be able to control.

  When off-leakage current is large, power is consumed by leakage current even when the circuit is stopped, so it is a serious problem especially for the drive circuit of mobile devices where battery life is one of the important performances. In response to demands for energy savings, there is a growing need for reducing power consumption during operation and standby power during stoppages for devices other than mobile devices. In view of such a demand, conventionally, all TFTs used in a circuit are controlled to have a high threshold voltage VT so that an off-leakage current is sufficiently small (for example, 1 pA or less).

  However, since the conventional channel doping is to collectively perform doping on the channel region of all n-channel type (or p-channel type) TFTs, for example, when channel doping is performed on n-channel type TFTs, The VT of the n-channel TFT is controlled in the same manner. Therefore, when the threshold voltage of the TFT is set high in order to suppress the off-leakage current, the TFT ON region in the power supply voltage range is narrowed, and the upper limit of the TFT current driving capability is lowered. Another problem such as a narrow dynamic range (output voltage range with respect to the power supply voltage range) occurs.

  Further, in the method of doping one of the n-channel type and the p-channel type, since the amount of change in drain current with respect to the gate-source voltage changes only in one channel-type TFT, VT and p of the n-channel type TFT are changed. The symmetry of the VT of the channel TFT is broken, and for example, when a CMOS circuit is formed, the operation speed is determined by a TFT having inferior characteristics, and good circuit characteristics cannot be obtained. Occurs.

  In order to suppress the breakage of the symmetry of the VT, there is a method of performing channel doping separately for both the n-channel type and the p-channel type. However, even in this method, the same channel type TFT has the same VT. In addition, if the VT is increased, the operation speed and dynamic range of the analog circuit are deteriorated. On the other hand, if the VT is decreased, the off-current of the logic and the switch circuit is increased. Strictly speaking, the symmetry of VT cannot be maintained due to manufacturing errors, and a thin film semiconductor device with a good balance of VT cannot be manufactured. Furthermore, there is a problem that the process becomes complicated because the channel doping is performed in a plurality of times. Even if this channel doping is performed using the method described in Japanese Patent Laid-Open No. 8-264798, channel doping must be performed at least once for each of the n-channel TFT and the p-channel TFT. The problem that the process becomes complicated cannot be solved.

  Such a problem applies not only to circuits used in image display devices such as liquid crystal display devices and organic EL display devices, but also to all circuits including n-channel TFTs and p-channel TFTs having a polycrystalline silicon film as an active layer. It is a problem.

  The present invention has been made in view of the above problems, and its main object is to form an n-channel TFT and a p-channel TFT having a VT suitable for each circuit without complicating the process. Then, it is providing the thin film semiconductor device which can improve the performance of an analog circuit, without increasing power consumption. It is another object of the present invention to provide a differential amplifier circuit and a display device that improve characteristics such as a dynamic range while suppressing an increase in current consumption.

  To achieve the above object, according to the present invention, a differential pair that differentially receives a signal voltage applied to an input pair, and a load element connected between an output pair of the differential pair and a first power supply A differential stage having a pair and a current source connected between the differential pair and a second power supply and supplying a constant current to the differential pair, and the differential pair and / or the load The element pair is composed of a relatively low threshold transistor, and is inserted in the current path of the differential stage, and has a higher threshold than the low threshold transistor as a switch function for controlling conduction / cutoff of the current path. In addition, a differential amplifier circuit including at least one transistor that is on / off controlled by a control signal input to the control terminal is provided.

  A thin film semiconductor device according to another aspect of the present invention includes an n-channel thin film transistor (TFT) having a polycrystalline silicon film as an active layer and a p-channel TFT on an insulating substrate. The same channel type includes a plurality of types of TFTs having different threshold voltages, and the different channel types include TFTs in which the same dopant is introduced at a substantially equal concentration in the channel region.

  In the present invention, the plurality of types of TFTs having different threshold voltages are TFTs including one of P-type and N-type dopants in the channel region, TFTs not including the dopant in the channel region, or P-type in the channel region. Alternatively, the TFT may include a TFT including one N-type dopant and a TFT including both P-type and N-type dopants in the channel region.

  In the present invention, the circuit constituting the thin film semiconductor device includes at least an analog circuit that requires an idling current during circuit operation and a switch, and the analog circuit includes a plurality of types of TFTs having different threshold voltages. It is preferable that a TFT having a low threshold voltage is included on the current path of the idling current, and the switch is configured by a TFT having a high threshold voltage among a plurality of types of TFTs having different threshold voltages. .

  In the present invention, the analog circuit may include the switch on a current path of the idling current, and the idling current may be cut off by the switch. The analog circuit is configured by the switch. It is preferable that operation and stop of the circuit are controlled by conduction and interruption of the idling current.

  In the present invention, when the analog circuit section includes a TFT having a low threshold voltage in the current path path of the idling current between the input terminal, the output terminal, and the power supply terminal, the current path path It is preferable that the switch is included above.

  In the present invention, the analog circuit may be a differential amplifier circuit including at least a TFT having a low threshold voltage in a differential pair, and including the switch on a current path path of the differential pair.

  In the display device of the present invention, a display portion and a circuit portion for driving the display portion are integrally formed on an insulating substrate, and the circuit portion includes the analog circuit and a switch.

  In addition, the image display device of the present invention includes an analog circuit unit, a logic circuit unit, a circuit unit including a switch, and a display unit configured by using TFTs formed on a polycrystalline silicon film on an insulating substrate. The analog circuit portion includes a TFT having a threshold voltage lower than the threshold voltage of the TFT used in the logic circuit portion.

  In the present invention, the analog circuit unit is supplied with power via the switch, and the switch is composed of a TFT having the same threshold voltage as the TFT used in the logic circuit unit, or the pixel switch of the display unit Can be made of a TFT having the same threshold voltage as the TFT used in the logic circuit section.

  In the present invention, in a method of manufacturing a thin film semiconductor device in which an n-channel TFT and a p-channel TFT are formed on an insulating substrate using at least a polycrystalline silicon film, a part of the n-channel TFT and the p-channel TFT are formed. The method includes a step of simultaneously introducing a P-type or N-type dopant into a partial channel region of the channel TFT.

In the present invention, in a method for manufacturing a thin film semiconductor device, an n-channel TFT and a p-channel TFT are formed on an insulating substrate using at least a polycrystalline silicon film.
Introducing one of P-type and N-type dopants on the entire surface;
A step of simultaneously introducing the other dopant of the N type or the P type into a part of the channel region of the n channel type TFT and a part of the p channel type TFT.

  As described above, according to the present invention, VT is reduced in a polycrystalline silicon film formed on an insulating substrate such as glass without complicating the manufacturing process so that an off-current is reduced with respect to a logic circuit and a switch. TFTs with high control can be formed with TFTs with low VT controlled so as to increase the operating speed and the dynamic range for analog circuits, and n-channel and p-type TFTs for channel doping. Since the same dopant is introduced at substantially the same concentration in both channel types, the symmetry of VT can be maintained, and a TFT having characteristics suitable for each circuit can be formed.

  According to the present invention, in a thin film semiconductor device including an n-channel thin film transistor (TFT) and a p-channel TFT having at least a crystalline silicon film as an active layer on an insulating substrate, the n-channel and p-channel transistors are provided. At least one channel type TFT of the type includes a plurality of types of TFTs having different threshold voltages, and includes a TFT in which the same dopant is introduced into the channel region in substantially the same concentration in different channel types. Good.

  In the present invention, the TFT channel region may include two types of TFTs, one containing a dopant and one not containing a dopant.

  In the present invention, an n-channel type and p-channel type thin film transistor having a crystalline silicon film as an active layer is provided over an insulating substrate, and a plurality of thin film transistors of at least one of the n-channel type and the channel type are provided. Is a thin film semiconductor device that is divided into a plurality of different threshold voltages, and forms at least one TFT having a relatively low threshold voltage that forms part of the path of the power supply current and is connected in series. The TFT having at least one relatively high threshold voltage may be configured to be turned on / off by a control signal applied to a control terminal of the TFT.

The present invention has the following effects.

  The first effect of the present invention is that TFTs having different VTs can be formed for each of the n-channel type and the p-channel type without increasing the number of steps.

  The reason for this is that, according to the present invention, when channel doping is performed, doping is not performed on either the n-channel TFT or the p-channel TFT, but all or part of the n-channel TFT. This is because doping is performed on all or a part of the p-channel TFT at the same time, so that n and p can be doped at the same time, and the VT can be changed with / without doping even in the same channel type.

  The second effect of the present invention is that the VT symmetry of the n-channel TFT and the p-channel TFT can be prevented from being lost, and the circuit design can be optimized.

  The reason for this is that in the present invention, the doping of the n-channel TFT and the doping of the p-channel TFT are not performed separately, but the same dopant is introduced at the same concentration in the same process, so that the VT symmetry It is because it can maintain.

  The third effect of the present invention is that a circuit including logic and switches with good off characteristics and analog circuits with good operating speed and dynamic range can be easily formed.

  The reason is that in the present invention, the characteristics required for the circuit are set by appropriately selecting a TFT that requires off characteristics such as logic and a switch and a TFT for an analog circuit that does not require off characteristics, and setting a channel doping region. This is because N-type or P-type dopants are introduced according to the above to control VT.

It is sectional drawing which shows the structure of the thin film semiconductor device which concerns on one Embodiment of this invention. It is process sectional drawing which shows the manufacturing method (B doping) of the thin film semiconductor device which concerns on one Embodiment of this invention. It is process sectional drawing which shows the manufacturing method (B doping) of the thin film semiconductor device which concerns on one Embodiment of this invention. It is process sectional drawing which shows the other manufacturing method (P doping) of the thin film semiconductor device which concerns on one Embodiment of this invention. It is process sectional drawing which shows the other manufacturing method (B whole surface doping and P strike-back) of the thin film semiconductor device which concerns on one Embodiment of this invention. It is process sectional drawing which shows the other manufacturing method (P whole surface doping and B strike back) of the thin film semiconductor device which concerns on one Embodiment of this invention. It is a circuit diagram which shows the structure of the analog circuit which concerns on one Embodiment of this invention. 1 is a circuit diagram showing a configuration of a differential amplifier circuit according to a first example of the present invention. FIG. It is a circuit diagram which shows the other structure of the differential amplifier circuit based on the 2nd Example of this invention. It is a circuit diagram which shows the other structure of the differential amplifier circuit based on the 3rd Example of this invention. It is a circuit diagram which shows the structure of the drive circuit which concerns on the 4th Example of this invention. It is a figure which shows the structure of the drive circuit of the liquid crystal display device which concerns on the 5th Example of this invention. It is a figure which shows the structure of the drive circuit of the organic electroluminescence display which concerns on the 5th Example of this invention. It is a figure which shows the specific structure of the data driver which concerns on the 5th Example of this invention. It is a figure which shows the specific structure of the memory based on the 5th Example of this invention. It is a circuit diagram for demonstrating the effect of this invention. It is a figure which shows the circuit structure of the differential amplifier circuit based on the 6th Example of this invention. It is a figure which shows the circuit structure of the source follower amplifier circuit which concerns on the 7th Example of this invention. It is a figure which shows the circuit structure of the differential circuit based on the 8th Example of this invention. It is a figure which shows the circuit structure of the differential circuit based on the 9th Example of this invention.

  One mode for carrying out a thin film semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings. In the following description of an embodiment, an analog circuit is a circuit that handles a continuous amount, and means a circuit that requires an idling current at an operating point when the operation is stable. The logic circuit means a circuit that handles a high-level or low-level binary voltage. The switch means an element that switches between conduction and non-conduction between two points.

  As described in the related art, in a thin film semiconductor device in which an n-channel TFT and a p-channel TFT made of a polycrystalline silicon film are formed, an n-channel TFT (or a p-channel TFT) is used to reduce the off-current of the TFT. However, in this method, the same channel type TFT has the same VT. If the VT is set high in order to reduce the TFT's off-leakage current sufficiently to achieve low power consumption, it is better due to the problem of deterioration of the operation speed and dynamic range of the analog circuit and the collapse of the symmetry of the VT. There has been a problem that circuit characteristics cannot be obtained.

  On the other hand, in the case of a circuit (referred to as a silicon circuit) formed on a silicon substrate, for example, a sense amplifier of a memory circuit has an example using two types of VT for high-speed response and leakage current suppression. Accordingly, a method of controlling the VT by adjusting the well potential is used. However, since a back gate exists in a silicon circuit, a method such as well potential control can be used. However, such a method cannot be used in a TFT provided on an insulating substrate. Cannot be applied.

  In a thin film semiconductor device formed on an insulating substrate, in order to control VT separately in a logic circuit, a switch, and an analog circuit, if channel doping is performed individually even for the same channel type TFT, VT is individually controlled. However, in this method, channel doping must be performed at least once for each of the n-channel TFT and the p-channel TFT, which complicates the manufacturing process of the thin film semiconductor device. In a device that is required to reduce the price, such as an increase in price due to an increase in the process becomes a serious problem.

  Further, although different VTs can be provided in the same channel by the method described in Japanese Patent Application Laid-Open No. 8-264798, the above publication simultaneously performs doping on both the n-channel TFT and the p-channel TFT. In consideration of the voltage drop due to the wiring resistance of the gate line of the active matrix display device, a method for reducing the VT as the TFT farther from the gate line driving circuit is provided. Similarly to the channel doping method, the channel doping must be performed at least once for each of the n-channel TFT and the p-channel TFT.

  Further, in these methods, since channel doping is separately performed for the n-channel TFT and the p-channel TFT, the symmetry of each channel-type VT is lost, which is desirable when configuring a CMOS circuit or the like. The problem that circuit characteristics cannot be obtained cannot be solved.

  The inventor of the present application paid attention to the fact that the TFT off-current characteristics are not particularly required in the operation of the analog circuit when controlling the VT of each circuit. That is, except for analog circuits that must cut off current such as analog switches, the analog circuit generally has an idling current flowing during operation, so the TFT is on, and the amount of leakage current in the off state is analog. It has nothing to do with circuit performance or power consumption. On the other hand, the lower the VT of the TFT, the higher the operation speed of the analog circuit and the wider the dynamic range. Therefore, in the operation of the analog circuit, there is no problem even if the off current of the TFT is somewhat large, and the higher the VT, the higher the performance.

  In consideration of the characteristics of this analog circuit, the same dopant is controlled by an n-channel TFT in order to control the VT suitable for the circuit for each of the n-channel TFT and the p-channel TFT without complicating the doping process. A method was devised for simultaneous introduction into part of the TFT and part of the p-channel TFT. A method for introducing a different dopant into each of an n-channel TFT and a p-channel TFT has been conventionally performed. However, a method for controlling VT by introducing the same dopant into different channel-type TFTs is the present invention. This is a new method devised by the author.

  Hereinafter, a structure of a thin film semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. FIGS. 1 to 6 show the case where n-channel TFTs and p-channel TFTs (total of four TFTs) having different VTs are formed on an insulating substrate, but the present invention is limited to the structure shown in the figure. Instead, the present invention can be applied to a configuration in which n-channel TFTs and p-channel TFTs are mixed and a plurality of at least one channel type are provided.

  As shown in FIG. 1, a thin film semiconductor device according to an embodiment of the present invention includes a polycrystalline silicon film 3 formed on an insulating substrate 1 such as glass or plastic with an undercoat layer 2 interposed between B ( A low VT p-channel TFT (hereinafter referred to as a low VT-p TFT (1)) and a high VT n-channel TFT (hereinafter referred to as a high VT-n type) having a channel region in which boron is introduced at substantially the same concentration. TFT (4)), undoped p-channel TFT with high VT (hereinafter referred to as high VT-p TFT (2)) and n-channel TFT with low VT (hereinafter referred to as low VT-n TFT (3) )) Is formed. That is, it is characterized in that TFTs having different VTs are formed not only in different channel types but also in the same channel type. In the above, high VT or low VT indicates a magnitude relationship as an absolute value of the potential. A manufacturing method of the thin film semiconductor device having such a configuration will be described with reference to the process cross-sectional views of FIGS.

  First, as shown in FIG. 2 (a), a silicon oxide film (SiOx), a silicon nitride film (SiNx) or the like to be an undercoat layer 2 is formed on an insulating substrate 1 such as glass or plastic by LPCVD (low pressure CVD). It is formed with a film thickness of about 300 nm using a method, a PCVD (plasma CVD) method, a sputtering method or the like. This undercoat layer 2 is provided to prevent impurities from diffusing from the insulating substrate 1 to the active layer, and is not necessarily provided when the influence of the impurities does not matter. Thereafter, an amorphous silicon (hereinafter abbreviated as a-Si) film 3a to be an active layer is formed with a film thickness of about 20 nm to 100 nm by LPCVD, PCVD, sputtering, or the like. When the PCVD method is used, dehydrogenation treatment is performed after film formation.

  Next, as shown in FIG. 2B, a resist pattern 10a having an opening in a region to be doped using a photolithography process is formed on the a-Si film 3a, and an ion implantation method or an ion doping method is performed. Is used to perform channel doping. Here, in the conventional method of manufacturing a thin film semiconductor device, all the same channel type TFTs (for example, two n-channel type TFTs on the right side of FIG. 2A) are doped. In order to control both n-channel type and p-channel type VT by one doping, at least a part of the n-channel type TFT (the right-side n-channel type TFT in the figure) and at least a part of the p-channel type TFT (see FIG. Then, B (boron) is selectively doped only in the left p-channel TFT). The impurity concentration introduced by this ion implantation method or ion doping method varies depending on the VT to be set, but a range of 2E + 11 to 5E + 12 / cm 2 is usually preferable.

  Here, in order to describe the case where the above four types of TFTs are formed at the same time, for each of the n-channel TFT and the p-channel TFT, a TFT doped with B and a TFT undoped are provided. When a TFT having a different VT is formed in only one of the TFT and the p-channel TFT, only the channel type may be partially doped with B. In this embodiment, TFTs having different VTs are classified into two types of TFTs, a TFT having a high VT and a TFT having a low VT. However, VTs can be classified into three or more types. In that case, a doping process with different dopant types and doses may be added.

  Thereafter, as shown in FIG. 2C, the a-Si film 3a doped with part of the n-channel TFT and part of the p-channel TFT is annealed (ELA) using excimer laser light. Crystallization forms polycrystalline silicon film 3 having non-doped region 8 and B-doped region 9.

  Next, as shown in FIG. 2D, after the polycrystalline silicon film 3 is etched into an island pattern using a photolithography process, an LPCVD method, a PCVD method, a sputtering method is used as shown in FIG. Etc. is used to form a silicon oxide film as the gate insulating film 4. The thickness of the gate insulating film 4 varies depending on TFT characteristics such as power supply voltage and VT, and specifications, but a range of about 30 nm to 200 nm is usually preferable. Thereafter, a conductive material such as metal, silicon, or silicide is deposited using PCVD, sputtering, or the like, and the conductive material is patterned using a photolithography process to form the gate electrode 5.

  Next, as shown in FIG. 3A, the p-channel TFT formation region is covered using the resist pattern 10b, and the n-channel TFT is doped with P (phosphorus) using the gate electrode 5 as a mask. The n-channel TFT formation region is covered using the resist pattern 10c, and B is doped in the p-channel TFT using the gate electrode 5 as a mask to form source / drain regions. Note that the order of doping of the n-channel TFT and the doping of the p-channel TFT is arbitrary and may be reversed.

  Here, when an LDD (Lightly Doped Drain) structure is formed in order to prevent a reduction in device reliability in a high electric field region near the drain, an impurity is implanted by offsetting the gate using a resist pattern. P is implanted at a low concentration using the gate electrode 5 as a mask, and then activation is performed. The activation method includes orthodox thermal activation, laser activation using a laser, RTA (Rapid Thermal Anneal) using a lamp and high temperature N2, etc., and activation most suitable for the structure of gate metal etc. Select a process.

  Then, after performing a hydrogen plasma treatment, as shown in FIG. 3C, a silicon oxide film, a silicon nitride film, etc. are deposited as an interlayer insulating film 6, and contact holes are formed on the gate and source / drain, A metal is formed as the electrode 7 to perform electrode wiring. As this metal, Al is usually used. Thereafter, although not shown, a passivation such as a silicon nitride film is formed to form a pad contact hole to form a thin film semiconductor device.

  As described above, in the present invention, when doping a part of the n-channel type with B, a part of the p-channel TFT forming region is also doped with B at the same time, thereby increasing the number of steps without increasing the number of steps. Two types of TFTs having different VTs can be created. In addition, since the same dopant (B) is introduced into the channel regions of the low VT-n type TFT and the high VT-p type TFT at substantially the same concentration, VT symmetry can be ensured.

  In the above description, the method of controlling the VT of n and p by basically using the method of controlling the VT of the n-channel TFT by B in the p-channel TFT has been described. Also in the method of controlling the VT of p, a TFT having the same channel type and two types of VTs can be produced in the same way. For example, as shown in FIG. 4, instead of doping B in the process of FIG. 2B, the resist pattern 10a is exposed so that the center TFT (high VT-p TFT and low VT-n TFT) is exposed. In this way, the VT of a p-channel TFT doped with P is increased, the VT of an n-channel TFT is decreased, and a TFT having two types of VTs for both n and p is produced. Can do.

  Further, although the doping step is increased by one step as compared with these methods, a TFT having two types of VTs for both n and p can also be formed by a method of repelling the opposite conductivity type dopant. For example, as shown in FIG. 5, instead of doping B in the two TFTs at both ends in the step of FIG. 2B, after doping the entire surface (both n and p) with B (FIG. 5A), A resist pattern 10a is formed so that the central TFT (high VT-p type TFT (2) and low VT-n type TFT (3)) is exposed, and P is doped (FIG. 5B). You can also. In this case, the n-type impurity concentration is substantially reduced in the low VT-n type TFT (3), and the p-type impurity concentration is increased in the high VT-p type TFT (2). VT TFTs can be created. Further, as shown in FIG. 6, after doping the entire surface (both n and p) with P (FIG. 6A), the TFTs on both ends (low VT-p TFT and high VT-n TFT) are exposed. In this manner, a method of forming the resist pattern 10a and doping B (FIG. 6B) can also be used. In this case, the n-type impurity concentration is increased in the high VT-n type TFT (4), and the p-type impurity concentration is substantially reduced in the low VT-p type TFT (1). Two types of VT TFTs can be created.

  In this way, a configuration using B for VT control of an n-channel TFT for a p-channel TFT, a configuration using P for VT control of a p-channel TFT for an n-channel TFT, or a part of the configuration By combining an n-channel TFT or a p-channel TFT with a structure in which B or P is not doped, TFTs having a plurality of different VTs for the same channel type can be formed. Further, by configuring a switch / logic circuit that requires off-current characteristics and an analog circuit that requires low VT and does not require off-characteristics with TFTs having different VTs, both circuit characteristics can be improved. it can.

  A specific example of an analog circuit including a TFT formed using the above method will be described. By configuring an analog circuit with a low VT-TFT, the operating speed can be improved and the dynamic range can be widened. However, if the analog circuit is configured with only a low VT TFT, power is consumed by leakage current when the analog circuit is stopped. Problem arises. Therefore, a switch composed of a high VT TFT that cuts off the leakage current due to the low VT TFT when the circuit is stopped is provided, and the high VT TFT switch is turned off when the circuit is stopped to suppress power consumption due to the leakage current when the analog circuit is stopped. Thus, the above problem is solved.

  Specifically, as shown in FIG. 7, the circuit of one embodiment of the present invention includes an input terminal 11, an output terminal 12, a high potential side power supply terminal 13, a low potential side power supply terminal 14, and a low VT-TFT. The analog circuit 20 includes switches 21 and 22 composed of a high VT-TFT. The analog circuit 20 outputs an output voltage Vout from the output terminal 12 in accordance with the input voltage Vin input to the input terminal 11. The switches 21 and 22 are respectively provided between the high potential side power supply terminal 13 and the low potential side power supply terminal 14 and the analog circuit 20, and are controlled by the control signal S1 and its inverted signal S1B. The control signal S1 is at the high level, S1B. The analog circuit 20 is activated (operable) when is low, and the analog circuit 20 is deactivated (stopped) when the control signal S1 is low and S1B is high.

  In the above-described configuration, the switches 21 and 22 formed of high VT-TFTs have a low VT on the current path path between the input terminal 11, the output terminal 12, the high potential power supply terminal 13, and the low potential power supply terminal 14. When the TFT is included, the current path is interrupted to stop the circuit, and power consumption due to leakage current at the time of stop can be suppressed. In addition, it is possible to suppress the influence of potential fluctuations on the input terminal 11 and the output terminal 12 due to leakage current when the circuit is stopped.

  For example, even if a current path path including a low VT-TFT exists between the input terminal 11 and the low-potential side power supply terminal 14, the current path can be blocked by the switch 22, Even if a current path path including a low VT-TFT exists between the output terminal 12 and the output terminal 12, the switch 21 can block the current path. Further, even if a current path path exists between the high potential side power supply terminal 13 and the low potential side power supply terminal 14, the current path can be interrupted by either the switch 21 or the switch 22.

  As described above, by using the method of the present invention to form the analog circuit 20 including the low VT-TFT and the switches 21 and 22 composed of the high VT-TFT, the performance of the analog circuit is improved (the operation speed is improved, Expansion of the dynamic range) can be realized, and power consumption due to leakage current can be prevented. Even when the structure of the present invention is applied to a drive circuit of a mobile device that requires low power consumption, the leakage current is limited when the low VT-TFT used in the analog circuit is turned off. Can be relaxed. Specifically, the leakage current when the high VT-TFT is turned off is usually required to be 1 / 10,000 (about 10-11 A) or less of the current (about 10-7 A) at the threshold voltage, whereas the low VT-TFT The leakage current at the time of turning off may be less than or equal to the current at the threshold voltage (about 10 −7 A), and the degree of freedom in design can be increased. The current values shown above are approximate guidelines.

  The configuration of the analog circuit 20 can be applied to analog circuit portions of various circuits such as an amplifier circuit, a power supply circuit, a comparator, and a drive circuit. In addition, the low VT-TFT is desirably an enhancement type, but may be slightly a depletion type.

  A specific suitable configuration of the circuit according to the above embodiment will be described below. In the following circuit configuration, in order to simplify the description, two types of TFTs, a TFT having a high VT and a TFT having a low VT, are provided, but a third TFT having a different VT from the two types of TFTs. It is good also as a structure provided with. In general, a low VT has a larger off-leakage current than a high VT TFT.

[Example 1]
First, an analog circuit including two types of VT TFTs according to the first embodiment of the present invention will be described with reference to FIG. FIG. 8 is a circuit diagram showing an example in which the structure of the present invention is applied to a differential amplifier circuit. In the following description, the TFT is an insulated gate transistor for both high VT and low VT.

  As shown in FIG. 8, the circuit of this embodiment is the simplest differential amplifier circuit composed of a differential stage and an amplifier stage. A low VT-TFT is applied to the differential stage (23 in FIG. 8). This is a differential amplifier circuit in which the differential pair 101, 102 is formed of a low VT-TFT and the switch 501 that cuts off the current path of the differential pair 101, 102 is formed of a high VT-TFT. Except for the differential pair 101 and 102, all are formed by the same high VT-TFT as the switch 501. Although both the differential stage and the amplification stage are analog circuit portions through which idling currents flow, in this embodiment, an embodiment in which only the differential pair 101, 102 is formed of a low VT-TFT will be described. Hereinafter, FIG. 8 will be described in detail. The differential pair 101 and 102 whose differential stage is an n-channel transistor, the differential pair is driven, and a transistor switch is connected between the differential pair and the low-potential-side power supply terminal 14. A current source circuit 105 connected via the power source 501, current mirror circuits 103 and 104, which form a load circuit of a differential pair and are formed of p-channel transistors connected between the differential pair and the high-potential side power supply terminal 13; It consists of

  The input terminal (the connection point between the drain and gate of the transistor 104) of the current mirror circuit is connected to the drain of the transistor 102 of the differential pair, and the output terminal is connected to the drain of the transistor 101 of the differential pair. Is the output of the differential stage. In the amplification stage, the output of the differential stage is input to the gate, the p-channel transistor 106 having the source connected to the high potential side power supply terminal 13 and the drain connected to the output terminal 12, and the output terminal 12 and the low potential side power supply. The current source 107 and the transistor switch 502 are connected in series with the terminal 14, and the transistor switch 503 is connected between the gate of the p-channel transistor 106 and the high potential side power supply terminal 13. . A control signal S1 is input to each of the transistor switches 501, 502, and 503. In the present embodiment, since the two differential input terminals are gate terminals of an insulated gate transistor, a current path is not generated between the differential input terminal and the power supply terminal or output terminal.

  In operation, the differential amplifier circuit sets the control signal S1 to a high level, turns on the switches 501 and 502, and turns off the switch 503. As a result, the output of the differential stage changes according to the voltage difference between the two differential input voltages Vin (+) and Vin (−), and the drain current of the p-channel transistor 106 is controlled by the change of the gate of the p-channel transistor 106. The output voltage Vout is determined by the balance with the current of the current source 107. As an example, when the inverting input terminal of the differential pair (the gate of the transistor 102) is connected to the output terminal 12, a voltage follower circuit that outputs a voltage equal to the input voltage of the non-inverting input terminal (the gate of the transistor 101) can be formed. . In operation, an idling current controlled by the current source 105 flows through the differential pairs 101 and 102 and the current mirror circuits 103 and 104 in the differential stage. On the other hand, in the amplification stage, the idling current flowing through the p-channel transistor 106 differs depending on the circuit connected to the output terminal 12, and when there is a constant discharge current from the output terminal 12 to the external circuit, the idling current flowing through the p-channel transistor 106. The total current of the discharge current and the current controlled by the current source 107 flows. When a capacitive load is connected to the output terminal 12, the idling current controlled by the current source 107 flows through the p-channel transistor 106 as it is in a stable operation state in which charging / discharging of the capacitor is completed.

  On the other hand, when stopping, the control signal S1 is set to the low level, the switches 501, 502 are turned off, and the switch 503 is turned on. Since the switch 501 is turned off in the differential stage, the current flowing into the low potential side power supply terminal 14 is cut off, and the output of the differential stage changes to the high power supply voltage VDD side. In the amplification stage, since the switch 503 is turned on, the gate of the p-channel transistor 106 is pulled up to the high power supply voltage VDD, and the p-channel transistor 106 is turned off. In addition, since the switch 502 is turned off, the current path between the output terminal 12 and the low potential side power supply terminal 14 is also cut off. In this way, the operation and stop of the differential amplifier circuit are controlled by the control signal S1.

  The dynamic range (output voltage range with respect to the power supply voltage range) of this differential amplifier circuit is a range in which the upper limit is the high power supply voltage VDD and the lower limit is narrower than the low power supply voltage VSS by the threshold voltage of the n-channel transistors 101 and 102. For this reason, in the configuration of FIG. 8, the differential pair 101 and 102 are formed of low VT-TFTs, so that the operation range of the differential stage 23 is expanded and the dynamic range of the differential amplifier circuit can be expanded. In this differential amplifier circuit, when the operation is stopped, the current path of the differential pair 101, 102 constituted by the low VT-TFT is cut off by the switch 501 formed by the high VT-TFT, so that the power consumption due to the leakage current Will not increase.

[Example 2]
Next, an analog circuit including two types of VT TFTs according to the second embodiment of the present invention will be described with reference to FIG. In FIG. 9, the low VT-TFT is applied to the differential stage (23 in FIG. 9), the differential pairs 101 and 102 and the current mirror circuits 103 and 104 are formed by the low VT-TFT, and the differential pair and the current mirror circuit. This is a differential amplifier circuit in which a switch 501 that cuts off the current path is formed of a high VT-TFT. Except for the differential pair 101 and 102 and the current mirror circuits 103 and 104, all are formed by the same high VT-TFT as the switch 501.

  By forming the differential pair 101, 102 with a low VT-TFT, the operating range of the differential stage 23 can be expanded as in FIG. 8, and the dynamic range of the differential amplifier circuit can be expanded. Further, by forming the current mirror circuits 103 and 104 with low VT-TFTs, the load as a load circuit for the differential pair is reduced, so that the operation response of the current mirror circuit is accelerated and the operation of the differential amplifier circuit is improved. You can speed up. Note that a low VT-TFT may be applied only to the current mirror circuits 103 and 104, and the switch 501 that cuts off the current path of the differential pair may be a differential amplifier circuit formed of a high VT-TFT. In this case, similarly to the amplifier circuit of FIG. 8, the performance of the differential amplifier circuit can be improved by using the low VT-TFT, and the low VT-TFT can be provided by providing the switch 501 formed of the high VT-TFT. It is also possible to prevent an increase in power consumption due to the leakage current.

[Example 3]
Next, an analog circuit including two types of VT TFTs according to a third embodiment of the present invention will be described with reference to FIG. FIG. 10 is a circuit diagram showing another example in which the structure of the present invention is applied to a differential amplifier circuit.

  As shown in FIG. 10, the circuit of this embodiment is a differential amplifier circuit in which a low VT-TFT is applied to a differential stage (23 in FIG. 10) and an amplifier stage (24 in FIG. 10). , 102 and the current mirror circuits 103 and 104 are formed by low VT-TFTs, the switch 501 for cutting off the current path of the differential pair and the current mirror circuit is formed by high VT-TFTs, and the p-channel transistor 106 in the amplification stage Is a low VT-TFT, and a switch 504 that cuts off the current path between the high-potential-side power supply terminal 13 and the output terminal 12 provided with the p-channel transistor 106 is formed of a high VT-TFT. It is.

  The transistor switch 504 is connected between the high-potential-side power supply terminal 13 and the output terminal 12 in series with the p-channel transistor 106. This is because the transistor switch 504 is not connected with the p-channel transistor 106 in series. This is because when the differential amplifier circuit is stopped, the leakage current of the p-channel transistor 106 of the low VT-TFT may affect the voltage at the output terminal 12 or the like. The inverted signal S1B of the control signal S1 is input to the gate of the transistor switch 504, and is turned on together with the switches 501 and 502 when the differential amplifier circuit is operating, and turned off together with the switches 501 and 502 when stopped.

  Among the effects of the present embodiment, when the low VT-TFT is applied to the differential stage (23 in FIG. 10), the operating range of the differential stage 23 is expanded as in FIG. 9, and the dynamic range of the differential amplifier circuit is increased. Can be enlarged. Further, in this embodiment, by forming the p-channel transistor 106 of the amplification stage (24 in FIG. 10) with a low VT-TFT, the ON region of the p-channel transistor 106 in the power supply voltage range is expanded, and the differential stage output (transistor 106) Since the upper limit of the transistor current driving capability in the range of change in the gate voltage) increases, the operation speed of the differential amplifier circuit can be improved. Thus, also in this embodiment, the performance of the differential amplifier circuit can be improved without causing an increase in power consumption.

[Example 4]
Next, an analog circuit including two types of VT TFTs according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 11 is a circuit diagram showing an example in which the structure of the present invention is applied to a differential amplifier circuit.

  In this embodiment, the differential amplifier circuit shown in FIG. 10 is combined with two differential amplifier circuits (30 and 40 in FIG. 11), which are symmetrical with respect to the transistor polarity in FIG. This is a dynamic amplification circuit. The two differential amplifier circuits 30 and 40 in FIG. 11 each have a non-inverting input terminal Vin (+) connected to the input terminal 11, and each output terminal is commonly connected to the output terminal 12. Each amplifier circuit has a voltage follower configuration in which the inverting input terminal Vin (−) is commonly connected to the output terminal 12. The two differential amplifier circuits can be individually controlled to be operated and stopped by the control signals S1 and S2 and the inverted signals S1B and S2B.

  The differential amplifier circuit of FIG. 11 can perform a high-speed charging operation by the p-channel transistor 106 when the differential amplifier circuit 30 is activated by the control signals S1 and S1B. When activated by S2 and S2B, the n-channel transistor 206 can perform a fast discharge operation. By controlling the control signals S1, S1B, S2, and S2B (S1B and S2B are inverted signals of S1 and S2, respectively), the fast charge operation and the fast discharge operation can be switched as appropriate. Therefore, the differential amplifier circuit of FIG. 11 can operate at high speed even if the current flowing through the current sources 107 and 207 is suppressed to reduce the power.

  The output terminal 12 is connected to the power supply VCC via complementary switches 131 and 132 controlled by signals PC and PCB. Thereby, the voltage of the output terminal 12 can be precharged or predischarged to the power supply voltage VCC as required. The operation ranges of the two differential amplifier circuits 30 and 40 constituting FIG. 11 are narrowed by the threshold voltage of the transistors constituting the differential pair, respectively. The circuit can achieve an operating range equal to the power supply voltage range. The power supply VCC may be a variable power supply having a plurality of voltage levels.

[Example 5]
Next, an image display device circuit formed on an insulating substrate having two types of VT TFTs according to a fifth embodiment of the present invention will be described with reference to FIGS. FIG. 12 is a diagram illustrating an example in which the present invention is applied to a liquid crystal display device, and FIG. 13 is a diagram illustrating an example in which the present invention is applied to an organic EL display device. 14 and 15 are diagrams showing the specific circuit configuration.

  FIG. 12 shows an embodiment of a circuit block diagram on the TFT substrate side in which a drive circuit and peripheral circuits necessary for driving a display unit, a display controller, a driver and other display units are formed on the same insulating substrate. In FIG. 12, a system power supply, a digital video signal, and a control signal are input from the outside of the TFT substrate 31. These signals are sent to the display controller 36, and the digital video signal is sent to the memory 37. There are various ways to send digital video signals, such as sending in correspondence with the address signal, sending serially or in parallel, and providing necessary signals and necessary circuits according to the sending method. And The operation of each block is controlled based on a control signal sent from the display controller 36. The power supply circuit 35 generates a power supply voltage required for each block based on the system power supply. The digital video signal is stored in the memory 37, and the video signal read from the memory 37 according to the timing is sent to the data driver 34. The data driver 34 includes a gradation voltage generation circuit, a data latch, a decoder, an output amplifier, and the like. The data driver 34 amplifies the gradation voltage selected according to the digital video signal by the output amplifier and outputs the amplified voltage to the data line 43. The gate driver 33 outputs a scanning signal for sequentially selecting each gate line 42. The display unit 32 is arranged such that the gate line 42 and the data line 43 intersect each other. Note that the memory 37 is preferably capable of storing image data of one frame or a plurality of frames.

  In FIG. 12, the display unit 32 shows an active matrix type configuration. In the active matrix display portion, pixels are arranged in a matrix, and a TFT 41 is provided for each pixel. The TFT 41 has a control end connected to the gate line 42, a drain connected to the data line 43, and a source connected to the pixel electrode. . Although omitted in FIG. 12, there is a counter substrate provided with a transparent electrode so as to face the TFT substrate 31, and liquid crystal is sealed between the TFT substrate 31 and the counter substrate. The liquid crystal between the pixel and the electrode (common line 44) of the counter substrate forms a liquid crystal capacitor 45, and by controlling the liquid crystal transmittance by holding the voltage difference applied to both ends of the capacitor together with the storage capacitor 46, the gradation Display can be made. The common driver 38 generates a voltage signal to be applied to the electrode on the counter substrate, and sends the voltage signal to the electrode (common line 44) on the counter substrate from the TFT substrate side.

  Since the TFT substrate 31 shown in FIG. 12 is formed integrally with the display portion 32 and its drive circuit and peripheral circuit, TFTs and wirings can be formed in one step. In the present invention, an insulating substrate ( TFTs formed on the TFT substrate 31) can simultaneously form TFTs having different VT for each polarity (high VT-TFT and low VT-TFT). The low VT-TFT is applied to an analog circuit unit that requires an idling current during circuit operation, and the high VT-TFT is applied to a logic circuit and a switch, thereby increasing the operation speed of the analog circuit unit without increasing power consumption. Can be improved and the dynamic range can be expanded, thereby improving the performance of the display device.

  FIG. 13 is a circuit block diagram of a display device in which a display unit, its drive circuit, and peripheral circuits are integrally formed on an insulating substrate as in FIG. 12, and a circuit block on the TFT substrate side of a typical organic EL display device. The figure is shown. In FIG. 13, the same element numbers are used for the same functions as in FIG. FIG. 13 also shows a configuration in which the display unit 32 is an active matrix type. An active matrix display unit of an organic EL display device has pixels arranged in a matrix, and each pixel is provided with a switching TFT 51, a current control TFT 54, and a light emitting diode OLED55 (Organic Light Emitting Diode) formed of an organic thin film. The TFT 51 has a control end connected to the gate line 52, a drain connected to the data line 53, and a source connected to the control end of the TFT 54. The TFT 54 has a source connected to the high level power supply VDD and a drain connected to one end of the OLED, and the other end of the OLED is supplied with the low level power supply VSS. Although not shown in FIG. 13, the low-level power supply VSS is applied to an electrode formed on the cathode substrate side. When the TFT 51 is turned on and a voltage corresponding to the image signal is applied to the TFT 54, the TFT 54 passes a current corresponding to the voltage difference from the high-level power supply VDD to the OLED 55, and the OLED 55 emits light with a luminance corresponding to the magnitude of the current. To do. In this way, gradation display can be performed by controlling the current flowing through the OLED 55. Note that the common driver 38 in FIG. 13 is a circuit that generates the voltage VSS to be applied to the electrode on the cathode substrate side, but may not be provided when the voltage VSS is GND.

  Since the TFT substrate 31 shown in FIG. 13 is formed integrally with the display portion 32 and its driving circuit and peripheral circuit, TFTs and wirings can be formed in a single process. In the present invention, an insulating substrate ( TFTs formed on the TFT substrate 31) can simultaneously form TFTs having different VT for each polarity (high VT-TFT and low VT-TFT). The low VT-TFT is applied to an analog circuit portion that requires an idling current during circuit operation, and the high VT-TFT is applied to a logic circuit and a switch so that analog power consumption is not increased as in FIG. The operation speed of the circuit unit can be improved and the dynamic range can be expanded, thereby improving the performance of the display device.

  12 and FIG. 13 will be described in more detail. Specific examples of the analog circuits in FIG. 12 and FIG. 13 include an output amplifier of the data driver 34, a regulator of the power supply circuit 35, a sense amplifier of the memory 37, and the like. By forming some of these elements with low VT-TFTs, the dynamic range can be expanded and the performance of high-speed operation can be improved, and the performance of the display device can be improved. For example, if the operation speed of the output amplifier of the data driver 34 is improved according to the present invention, the grayscale voltage output to each data line 43 can be shortened, so a high-definition panel that requires data line driving in a short time can be obtained. It can also be realized.

  Specific examples of the logic circuit and the switch include a gate driver 33, a display controller 36, and a switch (TFT 41 in the drawing) of the pixel portion of the display portion 32. The TFTs constituting these circuits are consumed by leakage current. In order to prevent an increase in power and malfunction, the high VT-TFT is used. The data driver 34, the memory 37, and the like also include many logic circuits and switches. In other words, any circuit block may include a part of the analog circuit even if the logic circuit is the main component. Representative examples of such circuit blocks are shown in FIGS.

  FIG. 14 is a diagram illustrating a configuration example of the data driver 34. The data driver shown in FIG. 14 includes a gradation voltage generation circuit 200, a latch 400, a decoder 300, an amplifier circuit 100, and an output terminal group 500. The gradation voltage generation circuit 200 is a resistor having power supply voltages VH and VL applied to both ends. The gradation voltage (multilevel voltage) generated from each tap of the resistor string is output, and the latch 400 receives the video digital data input to the data driver 34, and the decoder 300 at a predetermined timing. The decoder 300 selects the gradation voltage corresponding to the digital data output from the latch 400 and outputs the selected gradation voltage to the amplifier circuit 100. The amplifier circuit 100 amplifies the input gradation voltage to the data line (see FIG. 12 to 43, and 53) in FIG. Note that the video digital data sent to the latch 400 from the outside of the data driver is preferably read from the memory 37 of FIGS. 12 and 13 and directly input to the latch 400 in parallel format. When the data is sent, a shift register may be provided so that it is sequentially fetched into the latch 400 in synchronization with the clock. In FIG. 14, the latch 400 corresponds to a logic circuit. The decoder 300 is a circuit that processes multi-levels but is configured by a switch, and is formed of a high VT-TFT together with the latch 400. On the other hand, the amplifier circuit 100 is an analog circuit, and a differential amplifier circuit as shown in FIGS. 8 to 11 can be applied. By applying the present invention to the amplifier circuit 100, the operating speed of the amplifier circuit 100 can be improved and the dynamic range can be expanded without increasing the power consumption. Note that the grayscale voltage generation circuit 200 of FIG.

  15 shows a configuration example of the memory 34 in which the static RAM of Non-Patent Document 1 (“Modern Sciences Publishing, VLSI Introduction Series 5“ Basics of MOS Integrated Circuit ”, p64”) is formed on an insulating substrate. The figure is composed of a memory cell array 600, a data input buffer 700, a data output buffer 800, a sense amplifier 900, and the like. In the memory of FIG. 15, a memory cell 600 is designated by a row address and a column address, and writing to and reading from the designated memory cell 600 are performed by the level of a write enable signal (low level, high level). The sense amplifier 900 amplifies the data read from the memory cell 600 and operates to quickly perform the read operation. In FIG. 15, a memory cell 600 has a flip-flop structure, and corresponds to a logic circuit together with a data input buffer 700 and a data output buffer 800, and each is formed of a high VT-TFT. On the other hand, the sense amplifier 900 has substantially the same configuration as the differential stage of FIG. 8 to FIG. 10 (21 in each figure). Like the differential stage of FIG. 8 to FIG. -By providing a switch formed of a TFT and formed of a high VT-TFT that cuts off these current paths, the operating speed of the sense amplifier 900 can be improved and the operating range can be expanded without increasing power consumption. be able to.

  Note that the analog circuit can be configured as an arbitrary circuit on an insulating substrate, and the present invention can be applied to the circuit. For example, in FIG. 12 and FIG. 13, only the switch TFT is used in the pixel portion, but it is possible to provide various functional circuits in the pixel portion. It can also be improved.

  Further, even when circuit blocks such as the data driver of FIG. 14 and the memory of FIG. 15 are independently formed on an insulating substrate and individually formed into chips, the power consumption of the chip can be achieved by applying the present invention to an analog circuit. Needless to say, higher performance than before can be realized without increasing.

  As shown in the above embodiments, the circuit is configured by arranging the low VT-TFT and the high VT-TFT formed by the method of the present invention, thereby improving the performance as an analog circuit by the low VT-TFT. In addition, current leakage can be prevented by the high VT-TFT. In order to clarify the effect of the present invention, problems in a configuration in which a low VT-TFT is applied to a logic circuit such as an inverter or a switch (case not included in the present invention) will be described.

  FIG. 16A is a diagram showing a circuit configuration of an inverter formed by a low VT-TFT. The inverter of FIG. 16A has a p-channel transistor 901 whose source is connected to the high-order power supply VDD, a drain connected to the output terminal 12 together with the drain of the p-channel transistor 901, and a gate together with the gate of the p-channel transistor 901. The n-channel transistor 902 is connected to the input terminal 11. When the input Vin is at a low level (VSS), the p-channel transistor 901 is turned on, the n-channel transistor 902 is turned off, the output Vout is at a high level (VDD), and the input Vin is at a high level (VDD). At this time, the p-channel transistor 901 is turned off, the n-channel transistor 902 is turned on, and the output Vout becomes low level (VSS).

  Thus, one of the p-channel transistor 901 and the n-channel transistor 902 is off. However, when the p-channel transistor 901 and the n-channel transistor 902 are formed of a low VT-TFT and the off-leakage current is relatively large, the operation as an inverter is speeded up, but consumed by the leakage current of the off transistor. The problem of increased power arises. On the other hand, in the present invention, a low VT-TFT is applied to an analog circuit and its operation is speeded up, but power consumption does not increase.

  FIG. 16B is a diagram showing a configuration in which a low VT-TFT is applied to a clocked inverter (case not included in the present invention). In FIG. 16B, a transistor switch 903 is connected between the inverter formed of the low VT-TFT of FIG. 16A and the high potential side power supply terminal 13, and the inverter of FIG. 16A and the low potential side are connected. A transistor switch 904 is connected between the power supply terminal 14 and control signals S3 and S4 are input to the gates of the transistors 903 and 904, respectively.

  In the configuration of FIG. 16B, since the current path is completely cut off when both the transistors 903 and 904 of the high VT-TFT are off, the leakage current of the transistors 901 and 902 formed of the low VT-TFT is high. However, the operation is not affected, but the operation may be affected when at least one of the transistors 903 and 904 of the high VT-TFT is on. For example, when the transistors 901, 902, 903, and 904 are off, on, on, and off, respectively, if the leakage current of the transistor 901 is high, the charge flows from the high potential side power supply terminal 13 to the output terminal 12 to cause malfunction. There is a case.

  FIG. 16C is a diagram showing a configuration in which a low VT-TFT is applied to a switch (case not included in the present invention). FIG. 16C shows a differential stage in which a low VT-TFT switch 951 is provided in place of the high VT transistor switch 501 with a configuration similar to the differential stage of FIG. In this configuration, a switch configured with a high VT-TFT is not provided on a current path including the differential pair 911 and 912 of the low VT-TFT. Accordingly, even when the operation of the differential stage is stopped by setting S1 to the low level, the current controlled by the current source 915 tends to flow through the differential stage, and thus the leakage current of the low VT-TFT switch 951 is high. This increases the power consumption when the differential stage is stopped. As described above, even in an analog circuit, when a low VT-TFT is applied to a switch, there is a problem that power consumption increases. On the other hand, in the present invention, the low VT-TFT is applied to a circuit portion through which a predetermined internal current of an analog circuit flows, and is not applied to a switch. In addition, since the current path path includes a switch composed of a high VT-TFT on the current path path including the low VT-TFT, power consumption does not increase.

[Example 6]
In addition, an analog circuit including two types of VT TFTs according to the sixth embodiment of the present invention will be described with reference to FIG. FIG. 17 is a diagram showing a circuit configuration of another embodiment in which the present invention is applied to a differential amplifier.

  As shown in FIG. 17, in the differential amplifier circuit of this embodiment, the differential stage 23 has a low VT-TFT, and the amplifier stage 24 has a low VT-TFT. That is, in the differential stage 23, the transistor pair 101, 102 constituting the differential pair, and the switch transistor 501 inserted between the current source 501 and the power source VSS are constituted by a high VT-TFT, and the active load of the differential pair A pair of transistors 103 and 104 constituting a current mirror circuit constituting the circuit is formed by a low VT-TFT. The p-channel transistor 106 of the amplification stage 24 is formed by a low VT-TFT, the transistor 504 inserted between the p-channel transistor 106 and the source and the high-potential side power supply terminal 13 is configured by a high VT-TFT, An n-channel transistor 502 connected in series with the current source 107 is formed of a high VT-TFT between the low potential side power supply terminals 13. In the case where the current sources 105 and 107 are formed of transistors, the current sources 105 and 107 are connected in series with the transistors 501 and 502, respectively. Therefore, the current sources 105 and 107 are formed of either a low VT-TFT or a high VT-TFT. Also good. A control signal S1 is input to the gates of the transistors 501 and 502 functioning as switching elements, and an inverted signal S1B of the control signal S1 is input to the gate of the transistor 504. When the differential amplifier circuit operates (when activated), the transistors 501, 502, and 504 are turned on, and when stopped (when deactivated), the transistors 501, 502, and 504 are turned off. .

  In the circuit shown in FIG. 17, when the signal S1 is at a high level and the differential stage 23 and the amplification stage (output amplification stage) 24 are in the active state, for example, the signal voltage Vin (+) at the non-inverting input terminal 11b is inverted. As the signal voltage Vin (−) at the terminal 11a changes in a larger direction, the gate-source voltage of the N-channel transistor 101 increases and the drain current increases. The output node voltage of the dynamic stage 23 decreases, and the gate-source potential of the P-channel transistor 106 becomes larger. As a result, the drain current (source current) of the P-channel transistor 106 increases and the current of the constant current source 107 (sink) Output terminal voltage Vout rises in phase with the signal voltage Vin (+) of the non-inverting input terminal 11b. (For example, in the case of such capacitive load, charge accumulated in the load capacitance connected to the output terminal 12 is increased). When the signal voltage Vin (+) of the non-inverting input terminal 11b changes in a smaller direction with respect to the signal voltage Vin (−) of the inverting input terminal 11a, the gate-source voltage of the N-channel transistor 101 becomes smaller and the drain current becomes smaller. The output node voltage of the differential stage 23 rises due to the voltage drop of the on-resistance of the transistor 103 and the gate-source potential of the P-channel transistor 106 becomes smaller, so that the drain current of the P-channel transistor 106 ( Source current) decreases and the output terminal voltage Vout drops in phase with the signal voltage Vin (+) of the non-inverting input terminal 11b due to the difference from the current (sink current) of the constant current source 107, and the P-channel transistor 106 Is cut off, the charge at the output terminal 12 is discharged, and the voltage Vout is reduced to the lower power supply voltage V Reach the lower limit of the S side.

  In this embodiment, in FIG. 10, the differential stages 101 and 102 are configured with high VT-TFTs instead of the low VT-TFTs. In this case, the operating range of the differential stage 23 does not widen, but by forming the current mirror circuits 103 and 104 and the transistor 106 of the output amplification stage 24 with a low VT-TFT, the differential stage 23 is similar to FIG. The operating speed of the amplifier circuit can be improved. The current mirror circuits 103 and 104 have a single-stage configuration, but it is a matter of course that the same effect can be realized even in a configuration in which all or part of a plurality of stages of cascode current mirror circuits are formed of low VT-TFTs. is there.

  Although FIGS. 8 to 10 and FIG. 17 show an example in which a high performance is realized by using a low VT-TFT in the differential amplifier circuit, a portion (element) to which the low VT-TFT is applied, The influence on the performance of the differential amplifier circuit will be described in more detail.

  As described in the above embodiments, when the differential pair of the differential amplifier circuit is formed with a low VT-TFT (otherwise, it is formed with a high VT-TFT), the input / output voltage range can be expanded. . Further, when the current mirror circuit or the transistor of the output amplification stage is formed with a low VT-TFT, the operation speed can be improved.

  However, when the differential pair is formed of a low VT-TFT, the operation speed of the differential amplifier circuit may decrease. This is a case where the threshold voltage of the low VT-TFT constituting the differential pair is sufficiently smaller than the threshold voltage of the high VT-TFT, and at this time, the difference from the input voltage near the high potential side power supply voltage VDD. The operation speed of the dynamic amplifier circuit is reduced.

  This will be described with reference to FIG. 8. When the input voltage Vin (+) of the differential pair 101, 102 is close to the high potential side power supply voltage VDD, the common source potential of the differential pair 101, 102 is also brought to the VDD side. To rise. At this time, the maximum amplitude of the output voltage of the differential pair (the drain voltage of the transistor 101) is a voltage range between the power supply voltage VDD and the common source potential of the differential pairs 101 and 102. Therefore, if the threshold voltage of the differential pair 101, 102 of the low VT-TFT is sufficiently small, the amplitude of the output voltage of the differential pair becomes small and the amplification action of the amplification transistor 106 becomes small. As a result, the differential amplification The operation speed of the circuit decreases. However, there is no problem when the upper limit of the input / output voltage range of the differential amplifier circuit is sufficiently lower than the high potential side power supply voltage VDD. Therefore, when a low VT-TFT is used for the differential pair in order to expand the input / output voltage range, the threshold voltage of the low VT-TFT is set in consideration of the upper limit of the input / output voltage range and the operation speed. There is a need. That is, the differential amplifier circuit shown in FIG. 8 can expand the input / output voltage range, but the operation speed may be reduced.

  The differential amplifier circuit shown in FIG. 10 can expand the input / output voltage range, and the operation speed can be improved as compared with the difference image amplifier circuit shown in FIG.

  In the differential amplifier circuit of FIG. 17, the input / output voltage range does not change, but the operation speed can be most improved.

  As described above, the required performance can be improved by selecting a portion (element) to which the low VT-TFT is applied.

[Example 7]
Next, an embodiment in which the configuration of the low VT-TFT and the high VT-TFT is applied to an amplifier circuit other than the differential amplifier circuit will be described. FIG. 18 is a diagram showing a circuit configuration of an embodiment of the source follower amplifier circuit according to the seventh embodiment of the present invention. Referring to FIG. 18, the source follower amplifier circuit of this embodiment includes an n-channel transistor 111 and a p-channel switch transistor 511 connected in series between a high-potential-side power supply terminal 13 and an output terminal 12, and a low potential. A current source 112 and an n-channel switch transistor 512 connected in series are provided between the side power supply terminal 14 and the output terminal 12. The input voltage Vin is applied to the gate of the n-channel transistor 111, and the control signal S1 and its inverted signal S1B are applied to the gates of the transistors 512 and 511, respectively. The source follower amplifier circuit is activated when the control signals S1 and S1B are at a high level and a low level, respectively, and is deactivated when the control signals S1 and S1B are at a low level and a high level, respectively. 18, when Vin increases, the n-channel transistor 111 operates as a source follower to raise the output voltage Vout, and is stabilized at a voltage shifted from the input voltage Vin by the gate-source voltage. When Vin decreases, the n-channel transistor 111 is temporarily turned off, and the output voltage Vout is lowered by the discharging action of the current source 112. When the potential difference between the voltages Vin and Vout exceeds the threshold voltage of the transistor 111, the transistor 111 is turned on again. The transistor is turned on and is stabilized at a voltage shifted from the input voltage Vin by the gate-source voltage of the transistor 111. In the amplifier circuit of FIG. 18, the transistor 111 is formed of a low VT-TFT, and the other transistors are formed of a high VT-TFT. As a result, the threshold voltage of the transistor 111 is lowered, so that the dynamic range of the amplifier circuit is expanded and the operation speed of the source follower is also improved. On the other hand, since the transistor switches 511 and 512 are formed of high VT-TFTs, power consumption does not increase due to leakage current even when the amplifier circuit is stopped.

[Example 8]
Next, an eighth embodiment of the present invention will be described with reference to FIG. In each embodiment of the differential amplifier circuit shown in FIGS. 8 to 11, 17 and 18 to which the low VT-TFT is applied, the current path from the high potential side power supply terminal 13 to the low potential side power supply terminal 14 is cut off. For this purpose, a dedicated switch transistor is separately provided. In contrast, in this embodiment, a high VT-TFT is provided with a switch function.

  FIG. 19 shows the transistor 105 constituting the current source 105 in the differential stage 23 shown in FIG. 8 having the function of the switch 501 in FIG. 8, and the switch transistor 501 in FIG. 8 is removed. Yes.

  FIG. 19 shows the differential stage 23 as a representative example, and the amplification stage 24 is not shown. The current source 105 is formed of a high VT-TFT, and a bias voltage VB1 is applied to its gate. When the differential amplifier circuit is activated, the bias voltage VB1 is set to a predetermined voltage, and when the differential amplifier circuit is deactivated, the bias voltage VB1 is set to the power supply voltage VSS. When the differential amplifier circuit is deactivated, the current source 105 formed of the high VT-TFT is turned off, so that the power consumption is not increased by the leakage current. As described above, in this embodiment, the same function and effect as that of the differential stage 23 shown in FIG. 8 can be realized by providing a switching function in the current source 105 formed of a transistor.

  FIG. 20 is a diagram showing a modification of the configuration shown in FIG. Referring to FIG. 20, the transistors 103 and 104 constituting the current mirror circuit forming the active load of the differential pair in the differential stage 23 shown in FIG. 8 also have a switch function. In the example shown in FIG. 20, the switching transistor 501 is removed from the differential stage 23 of FIG. 8, and p-channel transistors 108 and 109 of high VT-TFT are added. The p-channel transistor 108 is connected between the common gate of the transistors 103 and 104 constituting the current mirror circuit and the drain of the transistor 104, and a control signal S1B (an inverted signal of the control signal S1) is input to the gate. Is connected between the common gate of the transistors constituting the current mirror circuits 103 and 104 and the high potential side power supply terminal 13, and the control signal S1 is inputted to the gate. When the differential amplifier circuit is activated, the control signals S1 and S1B are set to a high level and a low level, respectively. At this time, the transistors 108 and 109 are turned on and off, respectively, and the transistors 103 and 104 constitute a cant mirror circuit. On the other hand, when the differential amplifier circuit is deactivated, the control signals S1 and S1B are set to low level and high level, respectively. At this time, the transistors 108 and 109 are turned off and on, respectively, the common gate of the transistors 103 and 104 is turned off with the high-potential power supply voltage VDD, and the transistor 108 between the drain and the gate of the transistor 104 is also turned off. Thus, a non-conduction state is established.

  Since the transistors 103, 104, and 108 formed of high VT-TFTs are all turned off, the idling current is completely cut off and the power consumption is not increased by the leakage current. As described above, in this embodiment, by adding a switching function to the current mirror circuit composed of the transistors 103 and 104, the same effect as that of the differential stage 23 of the embodiment shown in FIG. 8 can be realized. it can.

  As described above with reference to FIG. 8, as in the present embodiment, also in other embodiments of the present invention, the switch formed of a high VT-TFT that cuts off the idling current is not necessarily dedicated to current blocking. It is not necessary to have a switch, and an arbitrary configuration in which a switch function and other functions are simultaneously provided may be used.

  Further, as a modification of FIG. 8 and the like, the P-channel transistor 106 in the amplification stage may be configured with a source follower configuration (N-channel transistor). In this case, the switch 503 is configured such that the source is connected to the lower power supply terminal 13, the drain is connected to the gate of the source follower transistor, and the complementary signal S1B of the control signal S1 is input to the gate. Of course, the amplification stage 24 shown in FIG. 10 or the like may have the source follower configuration shown in FIG. When the amplification stage transistor has a follower configuration, the inverted input signal Vin (−) and the non-inverted input signal Vin (+) are interchanged with those shown in FIG. 10, and the input terminal 11a has the signal voltage Vin (+ ), And the input terminal 11b becomes the inverting input terminal Vin (−) receiving the signal voltage Vin (−).

  In the above embodiment, in the 5V system, the threshold value of the high VT-TFT is, for example, ± 1.0 to ± 1.2, and the threshold value of the low VT-TFT is, for example, about ± 0.0 to ± 0.2. . However, + is an n-channel TFT, and-is a threshold of a p-channel TFT (a gate-source voltage when the p-channel TFT is turned on). As for the threshold value of the p-channel TFT, the absolute value with the sign is compared, and the threshold value 0.2 (absolute value of −0.2) is the threshold value 1.2 (absolute value of −1.2). It is said that it is lower.

  The embodiments of the present invention have been described with reference to the drawings. However, the present invention is not limited to the above-described embodiments, and those skilled in the art will be within the scope of the claims. Of course, various modifications and corrections that may be possible are included.

  For example, in the above embodiment, a polycrystalline silicon thin film transistor (polycrystalline silicon TFT) has been described as an example. However, in the present invention, the channel region of the transistor is not limited to the polycrystalline silicon thin film. For example, the present invention includes the case where the channel region of the transistor is located in one grain due to the enlargement of the silicon crystal grain size.

  The formation of the polycrystalline silicon film by laser crystallization may be crystallization by solid phase growth.

  Note that the operational effects of the present invention are not limitedly realizable only by the method of manufacturing a thin film semiconductor device. In the above embodiment, the present invention has been described in conjunction with a manufacturing method realized with a small number of steps. However, it is also possible to divide channel dope into a plurality of times to form TFTs of the same channel type and different VTs. In this case, the number of processes is increased (the manufacturing cost is increased). For example, when the circuit performance is more important than the manufacturing cost, the embodiments of the present invention (FIGS. 7 to 11 and FIGS. With the configuration described in 20), the circuit performance can be improved. The same applies to the case of using other manufacturing methods.

  However, by using the manufacturing method described in the above embodiment, it is possible to improve circuit performance while suppressing an increase in manufacturing cost.

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Undercoat layer 3 Polycrystalline silicon film 3a Amorphous silicon film 4 Gate insulating film 5 Gate electrode 6 Interlayer insulating film 7 Electrode 8 Non-doped region 9a, 9dB B doped region 9b, 9c P doped region 10a, 10b, 10c Resist pattern 11, 11a, 11b Input terminal 12 Output terminal 13 High-potential side power terminal 14 Low-potential side power terminal 20 Analog circuit including low VT-TFT 21 Switch composed of low VT-TFT 22 Configured with high VT-TFT Switch 23 Differential stage 24 Differential stage 30 Differential amplifier circuit 31 Insulating substrate (TFT substrate)
32 Display 33 Gate Driver 34 Data Driver 35 Power Supply Circuit 36 Display Controller 37 Memory 38 Common Driver 40 Differential Amplifier 41 TFT
42 Gate line 43 Data line 44 Common line 45 Liquid crystal capacitance 46 Storage capacitance 51 Switching TFT
52 Gate line 53 Data line 54 Current control TFT
55 OLED
100 Amplifying circuit 101, 102, 201, 202 Differential pair 103, 104, 203, 204, 913, 914 Current mirror circuit 105, 107, 205, 207, 915 Current source 106, 901 P-channel transistor 131, 132 Complementary switch 200 gradation voltage generation circuit 206, 902 N channel transistor 300 decoder 400 latch 500 output terminal group 501-503, 601, 602, 903, 904 transistor switch 504, 604 transistor switch 511 P channel transistor 512 N channel transistor 600 memory cell array 700 Data input buffer 800 Data output buffer 900 Sense amplifier 951 Low VT-TFT switch

Claims (7)

A differential pair comprising a first conductive type (one of N-type and P-type) transistor pairs that differentially receives a signal voltage applied to an input pair at a control terminal ;
A load element pair comprising a transistor pair of the second conductivity type (the other of the N type and P type) opposite to the first conductivity type, connected between the output pair of the differential pair and a first power supply;
A current source connected between the differential pair and a second power source and supplying a constant current to the differential pair;
A differential stage having
The transistor pair of the differential pair and / or the transistor pair of the load element pair includes a relatively low threshold transistor,
As a switching function that is inserted into the current path of the differential stage and controls conduction / cutoff of the current path , the low current threshold is connected between the differential pair and the second power source in series with the current source. A transistor of a first conductivity type having a higher threshold than that of the first transistor and controlled to be turned on / off by a control signal input to a control terminal;
A second conductivity type output stage transistor connected between the first power source and an output terminal and receiving the output of the differential stage at a control terminal;
Connected between said first power source and the control terminal of the output stage transistor, the have a higher threshold than the transistors of low threshold, by the control signal inputted to the control terminal, contrary to the transistors of the switch function A second conductivity type transistor which is turned on and off in phase;
Connected to said serial output terminal and between the second power source, a second current source, is turned on and off by the control signal inputted to the control terminal of a transistor and phase of the switching function, the low threshold A first conductivity type transistor having a higher threshold than the first transistor;
With
Each of the transistors is a thin film transistor provided on an insulating substrate and having a crystalline silicon film as an active layer,
The transistor of at least one of the first and second conductivity types includes a plurality of types of transistors having different threshold values,
Transistors of different conductivity types include transistors in which the same dopant is introduced at approximately equal concentrations in the channel region;
The plurality of types of transistors having different threshold values include a transistor including one of P-type and N-type dopants in a channel region and a transistor including both P-type and N-type dopants in a channel region. A differential amplifier circuit. A first differential pair comprising a first conductive type (one of N-type and P-type) transistor pairs that differentially receives an input signal voltage from the first and second input terminals at the control terminal; A first load element connected between the output pair of the first differential pair and the first power supply, and comprising a second conductive type (the other of the N type and P type) transistor pairs opposite to the first conductive type. A first differential stage comprising: a pair; and a first current source connected between the first differential pair and a second power source and providing a constant current to the first differential pair;
Said first and second differential pair consisting of the input signal voltage control transistor pair of a second conductivity type Ru received differentially to the terminal from the second input terminal, said second differential pair of output pairs wherein a second second load element pair consisting of a first conductivity type transistor pair that will be connected between the power supply, the second differential pair and the first of the connected second difference between the power source and A second differential stage having a second current source for providing a constant current to the moving pair;
A first output amplification stage for receiving an output of the first differential pair and outputting an output signal from an output terminal;
A second output amplification stage for receiving an output of the second differential pair and outputting an output signal from the output terminal;
Have
The transistor pair of the first differential pair and / or the transistor pair of the first load element pair is a relatively low threshold transistor,
The transistor pair of the second differential pair and / or the transistor pair of the second load element pair is composed of a relatively low threshold transistor,
As a first switch function for controlling activation / deactivation of the first differential stage, the first differential pair and the second power source have a threshold higher than that of the low threshold transistor. A transistor of a first conductivity type connected in series with the first current source and controlled to be turned on and off by a first control signal input to a control terminal;
As a second switch function for controlling activation / deactivation of the second differential stage, the second differential pair and the first power source have a threshold higher than that of the low threshold transistor. A transistor of a second conductivity type connected in series with the second current source in between and controlled to be turned on / off by a second control signal input to the control terminal;
The first output amplification stage is connected between the first power supply and the output terminal, receives the output of the first differential pair at a control terminal, and has a second conductivity type second with a relatively low threshold. One output stage transistor,
The second output amplification stage is connected between the second power source and the output terminal, receives the output of the second differential pair at a control terminal, and has a first conductivity type first having a relatively low threshold value. Two output stage transistors,
As a third switch function for controlling activation / deactivation of the first output amplification stage, the first output stage transistor is connected in series between the output terminal and the first power supply, A second conductivity type transistor having a threshold higher than that of the low threshold transistor is turned on / off in phase with the first switch function transistor by a complementary signal of the first control signal input to the control terminal. Prepared,
The first output amplification stage further includes a third current source connected in series between the output terminal and the second power supply, and the first control signal input to a control terminal. A first-conductivity-type transistor having a threshold higher than that of the low-threshold transistor, which is turned on / off in the same phase as that of the first switch-function transistor,
As a fourth switch function for controlling activation / deactivation of the second output amplification stage, the second output stage transistor is connected in series between the output terminal and the second power supply, A transistor having a first conductivity type that is turned on / off in phase with the transistor having the second switch function by a complementary signal of the second control signal input to the control terminal, and has a threshold higher than that of the low threshold transistor. ,
The second output amplification stage further includes a fourth current source connected in series between the output terminal and the first power source, and the second control signal input to a control terminal. A second conductivity type transistor having a threshold higher than that of the low threshold transistor, which is turned on and off in phase with the transistor having the switch function of No. 2;
With
Each of the transistors is a thin film transistor provided on an insulating substrate and having a crystalline silicon film as an active layer,
The transistor of at least one of the first and second conductivity types includes a plurality of types of transistors having different threshold voltages,
Transistors of different conductivity types include transistors in which the same dopant is introduced at approximately equal concentrations in the channel region;
The plurality of types of transistors having different threshold values include a transistor including one of P-type and N-type dopants in a channel region and a transistor including both P-type and N-type dopants in a channel region. A differential amplifier circuit. The differential amplifier circuit according to claim 2 , further comprising a circuit that charges or discharges the output terminal before an output signal is output from the output terminal. 3. The difference according to claim 1, wherein the transistors having different threshold values include a transistor including one of a P-type dopant and an N-type dopant in a channel region and a transistor not including a dopant in the channel region. Dynamic amplification circuit. 3. The differential amplifier circuit according to claim 1, wherein when the threshold value of the transistor is a negative value, the level of the threshold corresponds to the magnitude of the absolute value of the threshold. In the display device having a data driver for driving data lines of the display panel to input data signals, a display apparatus having a differential amplifier circuit according to any one of claims 1 to 5. Semiconductor device including a differential amplifier circuit according to any one of claims 1 to 5.

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