JPH0256799A - Memory circuit - Google Patents

Abstract

PURPOSE:To reduce the energy consumption of a sense circuit by using a conductive MOS transistor for selecting a memory cell different from an MOS transistor for input and an MOS transistor for pullup or pulldown. CONSTITUTION:At a memory circuit for reading data, a gate input type MOS sense circuit SA, static memory cells #1-#N and a pulldown circuit PD of a bit line are provided. For MOS transistors QT1-QTN for selecting a memory cell in memory cells #1-#N, inverting QT1-QTN, and MOS transistors Q6 and Q7 for pulldown in the circuit PD, the conductive different from MOS transistors Q2 and Q3 for input in the circuit SA is used. Thus, at the action point having small energy consumption and having large output amplitude, the sensing circuit can be operated and a sense action time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a gate input type sense circuit used in a static MOS memory, etc., and particularly relates to a technique for reducing power consumption of the sense circuit.

[Conventional technology]

A semiconductor memory is composed of a memory cell array in which memory cells for storing data are arranged vertically and horizontally, and peripheral circuits for reading and writing data from and to the memory cell array. Since the area occupied by each cell has a great influence on the storage capacity of a semiconductor memory, memory cells are often designed using the minimum design rule. Therefore, the load driving ability of memory cells is generally low, and it takes a considerable amount of time for the output signal voltage to reach a certain logic amplitude.

Therefore, in order to read data stored in memory cells to the outside of the memory at high speed, peripheral circuits must have a function to amplify the output signal voltage of the memory cells to a certain logic amplitude. It is called. The operation of this sense circuit is faster as the load capacitance of the output node is smaller.

In static type memories and the like, a sense circuit of the type that applies a signal to the gate of an lMo5 transistor is used. - As an example, a gate input type sense circuit using a current mirror circuit as a load is shown in FIG.

In Figure 2, El is a DC constant voltage power supply with an output voltage of Vcc, C1 is a clock generation circuit that outputs a two-level signal φ, T1n and Ttn2 are a pair of input terminals, and Tout is an output terminal. be. Also, Q1 to Q3 are N-c
The hMOS transistors Q4 and Q5 are P-chMOS transistors. Note that the higher the gate voltage of the N-ch MOS transistor, the lower the conduction resistance;
OS transistors have low gate voltage and low conduction resistance. Q4 and Q5 constitute a current mirror circuit, and are used as loads for MOS transistors Q2 and Q3.

In the above circuit, by applying a differential signal, that is, a small signal voltage in which the - side is relatively HIGH or LOv compared to the other, to the input terminals Tsn□ and Tin2, the amplified single output A signal is available at the output terminal TOut. Further, the N-chMO5l-transistor Q1 is used as a switch, and when the sense circuit is not operated, the power consumption of the sense circuit can be reduced to zero by switching the transistor Q1 to a non-conductive state.

When operating the sense circuit shown in FIG.

The control signal φ is switched to HIGH level, and Ql is set to a conductive state. By applying a sufficiently high voltage to the gate of Ql, the potential at node N1 drops to near the ground potential, so the potential at node N2 is approximately determined by the ratio of the conduction resistances of Q4 and Q2. For the same reason, the potential of node N3 is also determined approximately by the ratio of conduction resistances of Q5 and Q3. and input terminal Tt
. , the applied voltage V l n 1 and the input terminal T,. If the applied voltage V ln 2 of 2 is set equal to VA, then 1
The potentials of nodes N2 and N3 become equal and take an intermediate value between power supply voltage Vcc and ground potential.

In the above circuit, the differential signal voltage, Vtn1”VA+
Vstg/2 and Vtn2= VA Vstg/2
and the input terminals T ln□ and T,. When both are applied, the operation is as follows.

That is, since V r n has increased by Vs□/2, the conduction resistance of Q2 decreases, and the potential of node N2 decreases. This reduces the conduction resistance of Q4 and Q5. On the other hand, ■. 2 has decreased by vslt/2, the conduction resistance of Q3 increases.

Since the potential of node N3 is approximately determined by the ratio of the conduction resistance of Q5 and Q3, the potential of N3 increases as a result, and the output terminal T o
The old GH level signal is output to ut.

On the other hand, the differential signal voltage, Vtn1 = VA Vsrt
/2 and Vtn2=V^+Vst*/2 are respectively applied to TIJ and T In 2, the operation is as follows.

That is, since vi□ has decreased by Vstg/2, the conduction resistance of Q2 increases and the potential of node N2 increases. This increases the oil guide resistance of Q4 and Q5. On the other hand, since Vtn2 has increased by Vszt/2, the conduction resistance of Q3 decreases.

Since the potential of node N3 is approximately determined by the ratio of the conduction resistances of Q5 and Q3, the potential of N3 falls as a result, and the output terminal T o
A LOW level signal is output to ut.

As mentioned above, if the input signal Vln of the input terminal T1o is IIIG)I, the output terminal T. The amplified old GH level signal is output to ut, and the input signal vin1 is L.
In the case of OFF, an amplified LOW level signal is output to the output terminal.

Note that when a differential signal is input, the rate of change in the potential of N2 is much smaller than the rate of change in the potential of N3. this is,
This is because the differential signal acts to increase the conduction resistance of one of Q5 and Q3 and decrease the other, whereas it acts to increase or decrease the conduction resistance of both Q4 and Q2. Therefore, along with the input voltage V In 1, Q4 and Q
Even if the value of the conduction resistance of N2 changes, the change of the conduction resistance ratio becomes small, and the rate of change in the potential of N2 becomes smaller than that of N3.

FIG. 3 is a diagram showing the operating characteristics of the circuit shown in FIG. 2, and shows the voltage levels of the input signals v1n1 and v02 and the output V o u
The relationship with t is the signal amount Vstg = l V + □x V
tn2l is shown under constant conditions.

Note that Voutl represents the output voltage when V*nz>V+nz, and Voutz represents the output voltage when vInl<v1□2. Also, Vt□1 and Vt. The voltage level is also listed.

In FIG. 3, when a constant signal amount V s Ig is applied between the input terminals T In 1 and 'ran2, the output amplitude of the sense circuit is represented by IVout knee Voutzl.

The larger the output amplitude of the sense circuit, the more desirable. but,
As shown in FIG. 3, the output amplitude decreases as the input signal level increases and approaches power supply voltage Vce. As described above, the output amplitude strongly depends on the change in the conduction resistance ratio of Q5 and Q3. Therefore, when the input signal level rises and the conduction resistance of Q3 becomes smaller than that of Q5, V 111
Even if the conduction resistance of Q3 is modulated by 2, the change in the conduction resistance ratio is reduced, so the output amplitude is reduced.

In addition, the power consumption of a single sense circuit is determined by the output terminal Tau
is determined by the sum of the currents flowing through Q4 and Q2 and the currents flowing through Q5 and Q3 with Q4 and Q2 open. Q4 and Q
2, and the current flowing from El to ground via Ql increases from Q4 and Q as the level of input signal V tn□ rises.
It increases because the conduction resistance of 2 decreases. The current flowing from El to ground via Q5, Q3 and Ql is almost zero when the levels of V1n and VInt are low, but increases as the input signal level rises. That is, when the levels of the input signals V In 1 and V in 2 rise, the current flowing from El to the ground increases, and power consumption increases.

FIG. 4 is an example of a conventional static memory circuit using the sense circuit shown in FIG. 2.

1 is a diagram showing the configuration of a read circuit system from a memory cell to an output buffer (for example, IEEE Journal of Solid State Circuits IEEE, Jou
rnal of 5olid 5tate C1rcu
itVo1.5C-22Na5. Oct 1987
(described on page 722).

In the 4th m, #1' to #N' are static memory cells, WL(n) (where n=1...N) is a word line, and BL and BL are paired bit lines.

PU is a bit line pull-up circuit, MPX is a multiplexer, SA is a sense circuit, and BUF is an output sofa. Note that the word line is a line for transmitting a memory cell selection signal, and the bit line is a line for transmitting a differential signal outputted from a memory cell corresponding to stored data to a sense circuit. In this example, the potential of the word line is HI when selecting a memory cell.
G11 level.

It is at LOW level when not selected. Further, the multiplexer MPX is a circuit that selects a pair of pins 1 to &@ from a plurality of bit line pairs and connects it to the sense circuit.

In FIG. 4, only a pair of bit lines in a selected state are shown. In addition, in each of the above circuit blocks, Ql, Q2,
Q3, Q6', Q7', Qt' (n) and Qding' (n) (where n=1.-, N) are N-chMOs
Transistors, Q4 and Q5 are P-ch MOS transistors, 1 to 4 are inverters, and El and E2 have output voltages of Vc.
C is a positive DC constant voltage power supply, and C1 and C2' are clock generation circuits.

The clock generation circuit C1 outputs a two-level signal φ2, and the clock generation circuit C2' outputs a two-level signal φ2'. Further, the N-ch MOs transistors Q6' and Q7' forming the bit line pull-up circuit PU supply the current 'rAE?' through these transistors. The size of the IMOS transistor and the gate voltage (HIGH level) during operation are set so that when a current is sucked from ' into the selected memory cell #n', a predetermined voltage drop occurs across the selected memory cell #n'. In addition, Q6' and Q during operation
, 7' are often set to Vcc, which is equal to the power supply E2'.

When operating the readout circuit system shown in FIG. 4, control signal φ2' is switched to HIGH level (VCC level) and Q6' and Q7' are set in a conductive state.

At this time, the bit lines BL and the parasitic capacitance of BL are charged with electric charge from the power source E2'. N-chMOS
Assuming that the threshold voltage of the transistor is V11N, when all the word lines WL(n) (where n=1°...,N) are in the non-selected state, the bit lines BL and BL are equal (V
cc -VTHN).

Also, static type memory cell #n' (where n=1
．． ..., N) are configured to output complementary signals, so when - word lines W L (n) are selected, the memory cell selection transistor Q on the LOIII level side
Current is sucked into memory cell #n from one bit line via t'(n) or Qt'(n). As a result, a voltage drop occurs in the pull-up transistor Q6' or Q7', and the potential of the bit line decreases to a certain level. )IIGH level side memory cell selection transistor Qr'(n) or Qr'(n) does not sink current, so the potential of the bit line is (Vcc
-VTHN).

The potential difference between the bit lines BL and BL is input as a differential signal to the sense circuit SA via the multiplexer MPX. This differential signal between the bit lines is detected and amplified by the sense circuit SA as explained in FIG. 2, and is outputted to the outside via the output buffer BUF as a single output signal.

[Problem to be solved by the invention]

As is clear from the above explanation of the operation, in conventional static memory, the bit line pull-up level (V c
The potential drop from c-V THN ) is input to the sense circuit SA as a differential signal. That is, the third
Since the sense circuit is operating at point B in the figure, the output amplitude of the sense circuit is small and the power consumption of the sense circuit alone is large.

In addition, for inverter 1 in the subsequent output cover sofa BUF, the smaller the output amplitude of the sense circuit that serves as the input, the less the output will not switch sufficiently to the old GH or LOV, and the inside of inverter 1 will be disconnected from the power supply. A through current is formed that flows to ground, increasing power consumption.

Since the sense circuit SA and output buffer BUF described above need to be installed in a number corresponding to the output bit width of the semiconductor memory, the power consumption of these circuits becomes a problem, especially in semiconductor memories with a large output bit width. Become.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an object of the present invention is to provide a memory circuit for reading data that enables a sense circuit to operate at an operating point with low power consumption and a large output amplitude. .

[Means to solve the problem]

In order to achieve the above object, the present invention provides a data reading memory circuit comprising a gate input type MOS sense circuit, a static type memory cell, and a bit line pull-up or pull-down circuit as components.
As a memory cell selection MoS transistor in the memory cell and a pull-up or pull-down MOS transistor in the pull-up or pull-down circuit,
For example, a memory cell selection MOS configured to use a MOS transistor of a different conductivity type from the input MOS transistor of the gate input type MOS sense circuit.
Mo for transistor and pull-up or pull-down
An N-ch MOS transistor is used as the S transistor, and a P-ch MOS transistor is used as the input MOS transistor of the sense circuit.
A configuration using chMOS transistors or the opposite configuration is used.

The conventional technology depends on the conductivity type of the bit line pull-down or pull-up MOS transistor.

The output voltage of the pull-down or pull-up power supply is set to Vs
The difference is that by setting it to s (ground potential) or Vcc (positive potential), the sense circuit can be operated at an operating point where power consumption is low and output amplitude is large.

〔Example〕

FIG. 1 is a diagram showing one embodiment of the present invention, and is a diagram showing the configuration of a read circuit system from a memory cell to an output buffer as an embodiment of a static type memory circuit.

In FIG. 1, #1 to #N are static type memory cells, WL(n) (where n = 1 g ・= v N
) is a word line, BL and BL are paired bit lines, PD is a bit line pull-down circuit, MPX is a multiplexer,
SA is a sense circuit, and BUF is an output sofa. The functions of each of the circuit blocks described above are similar to those of the conventional example shown in FIG. 4 above. Note that the pull-down circuit PD corresponds to the pull-up circuit PU in FIG. 4, and Q6 and Q7 are pull-down transistors.

Furthermore, in each of the above circuit blocks, Q6. Q7, Qt(n) 4Qt(n) (however, n = 1, -,
N), P-ch M whose conductivity type is different from that of the input MOS transistors Q2 and Q3 in the sense circuit SA.
A clock generation circuit whose output polarity (IIGH or LOW level) is opposite to that of C2' is used. C2 should be used, and the word line selection signal should be L when selected.
The difference from the conventional example shown in FIG. 4 is that a signal having an OW level is used. Note that the clock generation circuit C2 outputs a two-level signal φ2.

Next, the effect will be explained.

In order to shorten the cycle time and operate the semiconductor memory at high speed, it is more effective if the change in potential of the bit line between when a memory cell is selected and when it is not selected is as small as possible within a range that can be detected by a sense circuit. N-c as shown in FIG.
h In the case of a MOS gate input type sense circuit, the effective signal amount is the threshold voltage V TH of the N-ch MOS transistor.
N or more signal components. At the time of manufacturing, V TH
The value of N is the threshold voltage V T of the P-ch MOS transistor.
It is often set to the same level as HP. Therefore, Q6
, Q7, Qt(n) , P-chMO as Qt(n)
By using the s-transistor to prevent the bit line potential from dropping below Vrop, it is possible to suppress the reduction in effective signal components and set the bit line potential change to a small value. Note that Q6 and Q7 are connected to the MOS MOS transistors and the gate voltage during operation so that when a current is supplied from the selected memory cell #n to the power supply E2 through these MOS transistors, a predetermined voltage is generated across the MOS transistors. (LOV level). Here, the gate voltage is set to Vss, which is equal to the power supply E2.

Furthermore, the characteristics of MOS transistors often vary during manufacture. Characteristic variations tend to be large between MOS transistors of different conductivity types, and small between MoS transistors of the same conductivity type.

In the case of the embodiment shown in FIG. 1, in order to secure the signal amount necessary for the sense circuit operation, it is necessary to
It is necessary to guarantee the voltage level of the IG11 level signal. The HIGH level signal is determined by the conduction resistance ratio between the P-ch MOS transistor Q7 and Qr(n) that constitute the inverter 3 in the memory cell, and between the P-ch MOS transistor Q6 and the P-ch MOS transistor that constitutes the inverter 4 in the memory cell. It is determined by the conduction resistance ratio of QT(n). Therefore, by using MOS transistors having the same conductivity type as these MOS transistors, it is possible to suppress variations in the voltage level of the IIIGH level signal due to variations in characteristics during LD manufacturing.

When operating the readout circuit system shown in FIG.

Control signal φ2 is switched to LOW level (Vss level), and Q6 and Q7 are set to conductive state. At this time, bit! The charges stored in the parasitic capacitances of IjABL and BL are discharged to power supply E2. If the threshold voltage of a P-ch MOS transistor is VTHP, all word lines WL(n
) (where n=LH·=eN) is in a non-selected state, the bit lines BL and BL are equally at V THP.

Static memory cell #n (where n=1°...
, N) are configured to output complementary signals, so -
When the main word line WL(n) is selected, the memory cell selection transistor Qr(n) or Q on the HIGH level side
A current is supplied from memory cell #n to one bit line via r(n). As a result, a voltage is generated across the pull-down transistor Q6 or Q7, and the potential of the bit line rises to a certain level. LOW level side memory cell selection transistor QT(n) or Qt(n
), since no current is supplied, the potential of the bit line remains at VTHP. The potential difference between the bit lines BL and BL is input as a differential signal to the sense circuit SA via the multiplexer MPX. The differential signal between the bit lines is detected and amplified by the sense circuit SA as described in FIG. 2, and is outputted to the outside via the output buffer 7BUF as a single output signal.

As is clear from the above operation description, in the static memory of the present invention, the bit line pull-down level VTI
(The sense circuit SA uses the potential increase from P as a differential signal.
is being input. In other words, since the sense circuit is operating at point A in Figure 3, the output amplitude of the sense circuit is large, and the power consumption of the sense circuit alone is 1/3 to 1/4 compared to point B. It is possible to reduce it to a certain extent.

Furthermore, with respect to the inverter 1 in the buffer circuit BUF, the output amplitude of the sense circuit serving as the input is set to be large, so that the through current flowing through the inverter 1 from the power supply to the ground becomes almost zero. Therefore, compared to the conventional configuration shown in FIG. 4, power consumption can be reduced by the amount of power generated by the through current.

In the memory circuit of the present invention, since the sense circuit operates in a region where the conduction resistance of Q5 or Q3 is relatively high, the driving ability of the load capacitance is lower than that of the conventional example shown in FIG. However, by downsizing the inverter 1 that makes up the input stage of the output buffer BUF: to reduce its input capacitance, and by placing the layerer 1 close to the sense circuit to reduce parasitic capacitance, we can minimize the drop in speed performance. It is possible to reduce the power consumption of the sense circuit while keeping the power consumption to a minimum.

In addition, in the embodiment shown in FIG. 1, N-chMO is applied to Q1 to Q3.
Using 8l-transistors, P-chMOs are installed in Q4 to Q7.
Although a configuration using transistors has been shown, a configuration using opposite conductivity types for each MoS transistor, that is, Q1
~Using a P-ch MOS transistor in Q3,
Of course, a configuration in which N-ch MoS transistors are used for Q4 to Q7 is also possible. In this case, the output voltage of power supply E2 is set to Vcc, the output voltage of power supply E1 is set to Vss (ground potential), the source of Ql is connected to a positive constant voltage power supply (for example, output voltage Vcc) instead of being grounded, and the Output polarity of generation circuits C1 and C2 (HIGH and LOII
), the same effect as the embodiment shown in FIG. 1 can be obtained.

Note that a sense circuit using a load other than a current mirror circuit, such as a resistive load or a MoS transistor load, can also be applied to the sense circuit, and the same effect can be obtained.

〔Effect of the invention〕

As explained above, the memory circuit of the present invention uses MoS transistors having a different conductivity type from the input MOS transistor of the sense circuit as the memory cell selection MOS transistor and the pull-down or pull-up MoS transistor, thereby reducing power consumption. This has the advantage that the sense circuit can be operated at an operating point where the output amplitude is small and the output amplitude is large. Furthermore, since the precharge level on the bit line is set to the threshold level of the pull-down or pull-up MOS transistor, the sensing operation time can be shortened.

Since a semiconductor memory needs to be equipped with a number of sense circuits corresponding to the output bit width, if the memory circuit of the present invention is applied to a semiconductor memory with a particularly large output bit width, it is possible to reduce power consumption, which increases with the output bit width. Since it can be reduced, the effect is great.

[Brief explanation of the drawing]

1 is a diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of a gate input type sense circuit with a current mirror circuit as a load, and FIG. 3 is a diagram showing input/output characteristics of the sense circuit of FIG. 2. Fourth
The figure shows the configuration of a read circuit system in a conventional memory. <Explanation of symbols>#1 to #N...Memory cell SA...Sense circuit PU...Pull-up circuit PD...Pull-down circuit MPX...Multiplexer SA...Sense circuit BUF...Output Buffer WL(n) (n=1...,N)...Word lines BL, BL...Bit lines 1.2.3.4...Inverters Ql, Q2, Q3, Q6', Q7', QT' (n
), QT'(n) (where n=1.-, N)...N-
chMOs transistor Q6. QT, QT(n), QT(n) (where n=1°..., N)...P-ch MOs transistor E1,
E2, E2'... Constant voltage DC power supply C1, C2, C2'
...Clock generation circuit φ2. φ2...Control clock TInU, Ttn2,...Input terminal T
o u t...Output terminals N1, N2, N3...Node patent applicant Junnosuke Nakamura, patent attorney representing Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] A memory circuit for reading data comprising a gate input type MOS sense circuit, a static type memory cell, and a bit line pull-up or pull-down circuit as constituent elements; As a pull-up or pull-down MOS transistor in a pull-up or pull-down circuit, an input M of the gate input type MOS sense circuit is used.
A memory circuit characterized by using a MOS transistor having a conductivity type different from that of an OS transistor.