JP2004201297A - Analog circuit, and display device and electronic equipment using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog circuit for reducing influence caused by dispersion of a transistor. <P>SOLUTION: In correction operation, a voltage between a gate and a source of a transistor to be corrected is held in a capacitor after flowing a bias current. In normal operation, the voltage stored in the capacitor in the correction operation is overlapped on a signal voltage. As the voltage is held in the capacitor in response to characteristics of the target transistor to be corrected, the influence caused by the dispersion can be reduced. The analog circuit reduced the influence caused by the dispersion can be obtained by applying this method to a differential circuit and an operational amplifier. An input voltage is not applied as it is to a gate terminal of the transistor, but is applied after being added the voltage held in a capacitor element. Magnitude of the voltage held in the capacitor element is made in response to current characteristics of the transistor and a size of the transistor. Therefore, the influence caused by the dispersion of the transistor can be reduced as the magnitude of the voltage held in the capacitor element is changed in response to the characteristics of the transistor and the size of the transistor. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to analog circuit technology. More specifically, the present invention relates to a circuit technique for reducing the influence of variations in transistor current characteristics.

  In recent years, a display device in which a thin film transistor (TFT) is formed on glass has been widely used. For example, a liquid crystal display (LCD) in which a TFT using amorphous silicon is arranged in each pixel is widely used in a notebook personal computer, a portable device, and the like.

  However, since a TFT using amorphous silicon has low mobility, a large amount of current cannot flow. Therefore, a TFT using polycrystalline (polycrystalline) silicon is formed on a glass substrate. Polycrystalline silicon TFTs have high mobility. Therefore, a driver circuit can be integrated over glass. In many cases, a drive circuit mainly includes a digital circuit. However, recently, research is being conducted toward realizing a system-on-panel in which all circuits are mounted on glass. In other words, mounting an analog circuit as well as a digital circuit is being studied.

  Therefore, a configuration of a source follower circuit will be described as one of the analog circuits. FIG. 21 shows a circuit diagram of the source follower circuit. The input voltage Vi is input to the gate terminal 4308 of the transistor TR1. A bias voltage Vb is applied to the gate terminal 4309 of the transistor TR2. Then, the gate-source voltage of the transistor TR1 is set to Vgs1. For simplicity, it is assumed that the potential of the low potential side power supply (Vss) is 0V. Then, the voltage (output voltage Vo) of the source terminal 4310 of the transistor TR1 satisfies the following equation (1).

  Here, for simplicity, it is assumed that the transistor TR1 and the transistor TR2 have the same current characteristics, transistor size (gate length L, gate width W), and the like. Here, since the transistor TR1 and the transistor TR2 are connected in series, the same amount of current flows through each transistor. Therefore, when both the transistor TR1 and the transistor TR2 operate in the saturation region, the gate-source voltage Vgs1 of the transistor TR1 becomes equal to the gate-source voltage of the transistor TR2, that is, the bias voltage Vb. Therefore, the following expression (2) is satisfied.

  However, even if the transistor size (gate length L, gate width W) of the transistor TR1 and the transistor TR2 is designed to be the same, each size will vary when actually manufactured. In addition, variations in the thickness of the gate insulating film, variations in the crystal state of the channel formation region, and the like cause variations in current characteristics of the transistor, such as the threshold voltage and the mobility.

  Here, as an example, it is assumed that the threshold voltage of the transistor TR1 is 2V, and the threshold voltage of the transistor TR2 varies and is 3V. Note that the current flowing through the transistor changes according to a value obtained by subtracting a threshold voltage from a gate-source voltage. Therefore, in order to make the same amount of current flow in the transistor TR1 as the current flowing in the transistor TR2, the threshold voltage is smaller by 1V, so that the gate-source voltage of the transistor TR1 is also reduced by 1V. As a result, as compared with the case where the threshold voltages of the transistor TR1 and the transistor TR2 are the same, it can be seen from the equations (1) and (2) that the output voltage Vo increases by 1V.

  As described above, if the current characteristics and the transistor size of the transistors TR1 and TR2 vary, the output voltage Vo also varies.

  Therefore, a technique for performing correction so as to reduce the influence of variation has been studied. For example, a source follower circuit in which variation has been corrected has been reported (see Non-Patent Document 1).

FIG. 24 shows a circuit diagram thereof. Next, the operation of the circuit will be described. First, among the switches 4401 to 4406, the switches 4401, 4406, and 4404 are turned on. Note that the switch is turned on when turned on. Then, an input terminal 4407 input voltage Vi is applied. Next, the switches 4401 and 4406 are turned off, and the switch 4402 is turned on. Then, the first offset voltage is stored in the capacitor 4409. Next, the switches 4402 and 4404 are turned off, and the switch 4403 is turned on. Then, the second offset voltage is stored in the capacitor 4410. As a result of the above operation, variations in the output voltage Vo are corrected.
Euro Display 2002: p831: LN-4: A 3.8 inch Half-VGA Transflective Color TFT-LCD with Completely Integrated 6-bit RGB Parallel Interface Drivers

  In the source follower circuit of FIG. 24 described above, when performing correction, an extremely large number of steps are required. That is, the switches 4401 to 4406 are repeatedly turned on and off many times, and the correction is finally completed. Therefore, in order to start a normal operation, much time is required for performing the correction.

  Also, many switches and capacitors are required. For this reason, the layout area increases, which also causes a reduction in manufacturing yield.

  Also, in an analog circuit other than the source follower, if the current characteristics of the transistor vary, the circuit does not operate normally or the output result varies.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an electric circuit in which influence of variation in characteristics of transistors is suppressed. More specifically, an object of the present invention is to provide an electric circuit which can perform a desired operation by suppressing an influence of variation in characteristics of a transistor in an electric circuit which handles an analog signal.

  The present invention uses an analog circuit having the following configuration to solve the above problems.

  According to the above structure, the present invention provides a first transistor, a first capacitor, a first switch, a first terminal, a second terminal, a second transistor, a second capacitor, a second switch, and a second switch. An analog circuit having a third terminal and a fourth terminal, wherein a gate terminal of the first transistor and one terminal of the first capacitor are electrically connected to each other; A gate terminal electrically connected to one terminal of the second capacitor, a source terminal of the first transistor electrically connected to a source terminal of the second transistor, and the first terminal And one terminal of the first capacitive element are electrically connected via the first switch, and the third terminal and one terminal of the second capacitive element are Electrically connected via a second switch Means for electrically connecting the other terminal of the first capacitor element to one of the second terminal and the source terminal of the first transistor; An analog circuit is provided, comprising means electrically connected to the other terminal of the element and any one of the fourth terminal and the source terminal of the second transistor. You.

  In the analog circuit having the above configuration, the operation method is divided into two operation states. One is a correction operation, and the other is a normal operation. In the correction operation, information for correcting the influence of the variation is obtained. Then, in the normal operation, the information obtained by the correction operation is added to the input signal, and the operation of the original circuit is performed. As described above, since the information obtained by the correction operation is added to the input signal, the influence of the variation is reduced in the normal operation.

  Information obtained by the correction operation is stored. When performing a normal operation, the stored information is used. As a result, it is not necessary to perform the correction operation every time the normal operation is performed.

  Therefore, the connection state of the circuit in each operation state will be described next.

  First, FIG. 22 shows a connection state of the circuit when the correction operation is performed. The capacitor 104 is provided between the gate terminal and the source terminal of the transistor TR1. One terminal of the capacitor 104 and the gate terminal of the transistor TR1 are electrically connected, and the other terminal of the capacitor 104 and the source terminal of the transistor TR1 are electrically connected. Here, since the terminals are electrically connected, an on-state switch, a passive element, an active element, or the like may be arranged on the wiring between the terminals. Hereinafter, in this specification, being connected is the same as being electrically connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, another element (for example, another element or a switch) that enables electrical connection therebetween may be arranged. In addition, the gate terminal, the drain terminal, and the source terminal of the transistor TR1 are each electrically connected to another element (an active element such as a switch or a transistor, a passive element, or the like), a wiring, or the like.

  In this connection state, the gate terminal of the first transistor is connected to one terminal of the first capacitor, the first terminal is connected to one terminal of the first capacitor, The other terminal of the first capacitor is not connected to the second terminal, and the other terminal of the first capacitor is connected to the source terminal of the first transistor. Equivalent to.

  In such a connection state, a current of a certain value flows between the drain and the source of the transistor TR1. The value of the current includes zero and is arbitrary. Then, the gate-source voltage Vgs of the transistor TR1 when the current is flowing is stored in the capacitor 104. The magnitude of the gate-source voltage Vgs of the transistor TR1 depends on the magnitude of the current flowing between the drain and source of the transistor TR1. Therefore, if the current characteristics and the transistor size of the transistor TR1 vary, the magnitude of the gate-source voltage Vgs of the transistor TR1 also has a different value. However, even if the transistors vary, the magnitude of the gate-source voltage Vgs of the transistor TR1 remains the same according to the magnitude of the current flowing between the drain and source of the transistor TR1.

  In this way, in the correction operation, information for correcting the influence of the variation, that is, the gate-source voltage of the transistor TR1 is obtained.

  Next, FIG. 23 illustrates a connection state of a circuit in a case where normal operation is performed. The capacitor 104 is provided between the gate terminal of the transistor TR1 and the input terminal 108. One terminal of the capacitor 104 and the gate terminal of the transistor TR1 are electrically connected, and the other terminal of the capacitor 104 and the input terminal 108 are electrically connected. Then, an input voltage Vi is applied to the input terminal 108. Here, the charge obtained during the correction operation is stored in the capacitor 104. Therefore, a voltage obtained by adding the voltage stored in the capacitor 104 to the input voltage Vi is applied to the gate terminal of the transistor TR1.

  In this connection state, the gate terminal of the first transistor is connected to one terminal of the first capacitor, and the first terminal is disconnected from one terminal of the first capacitor. The other terminal of the first capacitor is connected to the second terminal, and the other terminal of the first capacitor is not connected to the source terminal of the first transistor. It corresponds to that.

  As described above, the input voltage Vi is not applied as it is to the gate terminal of the transistor TR1, but the voltage stored in the capacitor 104 is added and applied. The magnitude of the voltage stored in the capacitor 104 is a magnitude corresponding to the current characteristics of the transistor TR1, the size of the transistor, and the like. In other words, even if the current characteristics and the transistor size of the transistor TR1 vary, the magnitude of the voltage stored in the capacitor 104 changes accordingly.As a result, the influence of the variation of the transistor TR1 can be reduced. It becomes possible.

  By performing such correction for each transistor, it becomes possible to correct variations in the entire circuit. That is, by applying the present invention to the first transistor, the second transistor, and various transistors included in a circuit, variation can be corrected.

  In order to be electrically connected as shown in FIG. 22 during the correction operation and electrically as shown in FIG. 23 during the normal operation, it is necessary to arrange a switch between a certain terminal and a certain terminal. realizable. Only a few such switches are required.

  Note that in FIGS. 22 and 23, the transistor TR1 is an n-channel transistor; however, the present invention is not limited to this, and the transistor TR1 may be a p-channel transistor. Even in the case of the p-channel type, it can be easily deformed by taking care that the capacitor 104 is arranged between the gate and the source of the transistor TR1 when performing the correction operation.

  The correction operation may be performed at least once before performing the normal operation. That is, when an appropriate voltage is held in the capacitor 104, normal operation can be performed. Note that the charge stored in the capacitor 104 may gradually change due to noise, leakage current, or the like. At that time, the correction operation may be performed again before the charge stored in the capacitor 104 changes significantly.

  As described above, the effect of the variation in transistor characteristics can be reduced in the subsequent normal operation only by performing the correction operation at least once. Therefore, the operation is simplified without complicating the drive timing.

  In addition, the capacitance may be only the capacitance element 104 and may be several switches. Therefore, the layout area can be reduced. As a result, it is possible to prevent the production yield from lowering and to reduce the size.

  Note that the transistor in the present invention may be a transistor formed by any material, means, or manufacturing method, or may be any type of transistor. For example, a thin film transistor (TFT) may be used. Among the TFTs, the semiconductor layer may be amorphous, polycrystalline (polycrystal), or single crystal. As another transistor, a transistor formed on a single crystal substrate, a transistor formed on an SOI substrate, a transistor formed on a plastic substrate, a transistor formed on a glass substrate, or the like. Good. In addition, a transistor formed of an organic substance or a carbon nanotube may be used. Further, a MOS transistor or a bipolar transistor may be used.

  Further, according to the present invention, an analog circuit includes a means for supplying a current, and a source terminal of the first transistor and the means for supplying the current are electrically connected. Is provided.

  By providing the means for supplying a current in this way, it is possible to set the bias of the analog circuit.

  Further, according to the present invention, there is provided an analog circuit having the above structure, which includes means for interrupting a current flowing in a first transistor and means for interrupting a current flowing in a second transistor. .

  With this configuration, it is possible to separately correct the first transistor and the second transistor.

  Further, according to the present invention, the first terminal and the second terminal are electrically connected to each other, and the third terminal and the fourth terminal are electrically connected to each other. An analog circuit is provided.

  With this configuration, wiring for supplying a voltage to the first terminal and the third terminal can be omitted.

  In the present invention, the input voltage is not applied to the gate terminal of the transistor as it is, but is added with the voltage stored in the capacitor. The magnitude of the voltage stored in the capacitive element depends on the current characteristics of the transistor, the size of the transistor, and the like. Therefore, even if the current characteristics of the transistor, the transistor size, and the like vary, the magnitude of the voltage stored in the capacitor changes accordingly.As a result, it is possible to reduce the influence of the variation in the transistor. It becomes possible.

  In addition, the operation of storing the voltage in the capacitor, that is, the correction operation may be performed at least once. Then, in the subsequent normal operation, the influence of the variation in the characteristics of the transistor can be reduced. Therefore, the operation is simplified without complicating the drive timing.

  Further, since the number of capacitors and the number of switches are small, the layout area can be reduced. As a result, it is possible to prevent the production yield from lowering and to reduce the size.

(Embodiment 1)
The present invention can be applied to various circuits such as an analog circuit, for example, a differential circuit, an amplifier circuit, and an arithmetic circuit represented by an operational amplifier. Therefore, in this embodiment, a differential circuit to which the present invention is applied will be described as an example.

  First, FIG. 1 shows a circuit configuration of a differential circuit to which the present invention is applied. In the conventional differential circuit, a transistor TR21 that operates as a current source and sets a bias of the circuit is arranged. Connected to terminal. The drain terminal of the transistor TR11 is connected to a high potential power supply (Vdd) via a load 1812 and the like, and the drain terminal of the transistor TR12 is also connected to a high potential power supply (Vdd) via a load 1813 and the like.

  On the other hand, in the differential circuit to which the present invention is applied, switches 1801 to 1811 and capacitors 1812 and 1813 are added.

  Note that when a transistor is used as a switch, the polarity of the transistor is not particularly limited because the transistor operates as a simple switch. However, in the case where it is preferable that the off-state current be small, for example, in a switch or the like connected to the capacitors 1812 and 1813, it is preferable to use a transistor whose polarity is smaller in the off-state current. As a transistor with small off-state current, there is a transistor provided with an LDD region. In the case where the transistor operated as a switch operates in a state in which the source terminal potential is close to the low potential side power supply (Vss, Vgnd, 0 V, or the like), the n-channel type is used. When operating near a side power supply (such as Vdd), it is desirable to use a p-channel type. This is because the absolute value of the gate-source voltage can be increased, and the switch can easily operate. Note that a CMOS type may be used by using both the n-channel type and the p-channel type.

  The switch may be an electric switch or a mechanical switch. Anything can be used as long as it can control the current flow. It may be a transistor, a diode, or a logic circuit combining them.

  Thus, next, the operation of the differential circuit in FIG. 1 will be described with reference to FIGS.

  First, a correction operation is performed. At that time, the correction operation may be performed simultaneously on the transistors TR11 and TR12. However, there is only one transistor TR21 that operates as a current source, and it is considered that performing the correction operation using the same transistor has higher accuracy. Therefore, first, a correction operation is performed using the transistors TR11 and TR21, and then a correction operation is performed using the transistors TR12 and TR21. Note that this order may be reversed.

  First, as shown in FIG. 2, a correction operation is performed using the transistors TR11 and TR21. At this time, the current flowing through the transistor TR21 is made to flow toward the transistor TR11 but not to the transistor TR12. This is because if the current also flows toward the transistor TR12, an error is generated by that much. Therefore, in order to prevent the current flowing through the transistor TR21 from flowing toward the transistor TR12, the current is controlled using the switches 1801 to 1804.

  In FIG. 2, the switch 1801 is turned on, and the switches 1802 to 1804 are turned off. The switch 1801 is connected to the second high-potential-side power supply (Vdd2). However, the switch 1801 may be connected to a first high-potential-side power supply (Vdd1) to which a load 1812 and the like are connected. That is, it suffices that a current flows through the transistor TR11 and a current does not flow through the transistor TR12. Therefore, the arrangement of the switches 1802 and 1803 may be changed, for example, the switch 1802 may be arranged between the source terminal of the transistor TR11 and the drain terminal of the transistor TR21. Alternatively, a function for controlling the current may be provided in the loads 1812 and 1813. Alternatively, the switch 1801 and the second high potential side power supply (Vdd2) may be deleted, and the switch 1802 may be controlled. In that case, the load 1812 needs to be in a state where current can flow.

  Thus, the gate-source voltage Va1 of the transistor TR11 is stored in the capacitor 1812. As illustrated in FIG. 3, when the switches 1806 and 1808 and the like are turned off, the charge accumulated in the capacitor 1812 is held.

  Next, as shown in FIGS. 4 and 5, a correction operation is performed using the transistors TR12 and TR21. Each switch may be turned on and off in the same manner as in FIGS. The gate-source voltage Va2 of the transistor TR12 is stored in the capacitor 1813. Thus, the correction operation ends.

  The correction operation may be performed at least once before performing the normal operation. That is, the normal operation can be performed any number of times as long as an appropriate voltage is held in the capacitors 1812 and 1813. However, the charge stored in the capacitors 1812 and 1813 may gradually change due to noise, leakage current, or the like. At that time, the correction operation may be performed again before the electric charges stored in the capacitors 1812 and 1813 change significantly.

  Next, a normal operation is performed as shown in FIG. That is, the switches 1801, 1804, 1806, 1808, 1809, 1811 are turned off, and the switches 1802, 1803, 1805, 1807, 1810 are turned on. Then, even if the characteristics of the transistor TR11 and the transistor TR12 vary, the variation is reflected on the gate-source voltages Va1 and Va2, so that the influence of the variation can be reduced. Note that during normal operation, the gate-source voltage of each transistor may change depending on the amount of current flowing through the transistors TR11 and TR12. In that case, the gate-source voltage may not be equal to Va1 or Va2. However, since the value reflected in the characteristic variation is added to the gate terminal of the transistor, the influence of the variation in the transistor is reduced.

  Note that the switch 1805 may be omitted when the input impedance of the portion that outputs the output voltage Vo1 is high. Alternatively, depending on the configuration of the loads 1812 and 1813, the switch 1805 or the like may not be necessary.

  If such a differential circuit is used, various circuits can be configured. For example, when a resistance element or an active load circuit is used as the loads 1812 and 1813, a differential amplifier circuit can be configured. In addition, by arranging a diode-connected (gate terminal and drain terminal) transistor as the loads 1812 and 1813, a part of an OTA (Operational Transconductance Amplifier) circuit can be configured. Further, by combining these circuits, circuits such as an operational amplifier, a sense amplifier, and a comparator can be configured.

  Therefore, next, an example in which the configuration is devised for a differential amplifier circuit when an active load circuit is used as the loads 1812 and 1813 will be described.

  First, an example will be described in which the operating point is made closer between the correction operation and the normal operation to reduce the error.

  The most standard operating condition of the differential amplifier circuit is when the input voltages Vi1 and Vi2 are equal. In that case, the current flowing through the transistor TR21 flows through the transistor TR11 and the transistor TR12 in a half amount.

  On the other hand, when the correction operation is performed and when the normal operation is performed, it is desirable that the operation state such as the operation point is close. Therefore, in order to make the operating point closer, the amount of current when performing the correction operation may be set to half of the amount of current during normal operation. An example in that case is shown in FIGS. 25 and 26.

  In FIG. 25, a transistor TR22 is added as a transistor operated as a current source. It is desirable that the transistor sizes of the transistor TR21 and the transistor TR22 be the same. Then, the same bias voltage Vb is applied to each gate terminal. Then, a switch 2501 is arranged in series with the transistor TR22. By switching the switch 2501 on and off, the amount of current for performing the correction operation is reduced to half the amount of current for the normal operation. Note that the switch 2501 may be placed anywhere as long as the amount of current can be controlled.

  In FIG. 26, a transistor TR22 is added as a transistor operated as a current source. It is desirable that the transistor sizes of the transistor TR21 and the transistor TR22 be the same. Then, a bias voltage Vb is applied to the gate terminal of the transistor TR21. Then, the voltage applied to the gate terminal of the transistor TR22 is changed between the correction operation and the normal operation. Specifically, at the time of the correction operation, a low-potential-side power supply (Vss) is applied so that the transistor TR22 is turned off. During normal operation, a bias voltage Vb is applied. Thus, the amount of current when performing the correction operation is reduced to half of the amount of current during normal operation.

  As described above, by changing the magnitude of the current flowing through the bias transistor, the operating point can be made closer between the correction operation and the normal operation. The closer the operating point is, the smaller the error is.

  Next, an example in which the connection of the switch is changed will be described for a differential amplifier circuit using an active load circuit.

  In FIG. 2, it has already been described that the arrangement of the switches 1801 to 1804 can be changed. Therefore, an example in which the arrangement of the switches 1801 to 1804 is changed in a differential amplifier circuit using an active load circuit as the loads 1812 and 1813 will be described. FIG. 27 shows a case where the switch 1801 is omitted.

  The operation of each switch is as follows. First, when a current flows through the transistor TR11 and no current flows through the transistor TR12, the switch 1802 is turned on, the switch 1803 is turned on, and the switch 1804 is turned off. Then, the voltage between the gate and the source of the transistor 1813 becomes 0 V, so that the transistor 1813 is turned off. The transistor 1812 is also turned off, but current flows from the switch 1803 through the switch 1802. Next, in the case where a current is caused to flow through the transistor TR12 without flowing a current through the transistor TR11, the switch 1802 is turned off, and the switch 1803 may be turned on, and the switch 1804 is turned on. Then, a current flows only through the transistor TR12. Finally, when current flows through the transistors TR11 and TR12, that is, in the case of normal operation, the switch 1802 is turned on, the switch 1803 is turned off, and the switch 1804 is turned off.

  With this arrangement, the arrangement of the switches can be changed. Note that the connection example is not limited to this.

  As described above, various circuits can be configured by applying the present invention to a differential circuit.

  Note that the case where the transistors TR11 and TR12 are of the n-channel type has been mainly described. However, the present invention can be easily applied to a p-channel type. As an example, FIG. 28 shows a case where the circuit in FIG. 1 is a p-channel type.

  In addition, since the magnitude of the reference voltage is arbitrary, the terminal providing the reference voltage may be connected to another wiring, a contact, or a terminal. For example, in FIG. 1, the terminals supplying the reference voltages Vx1 and Vx2 may be connected to the terminals supplying the input voltages Vi1 and Vi2, or may be connected to the drain terminals of the transistors.

(Embodiment 2)
In this embodiment mode, a source follower circuit will be described as an example of the analog circuit of the present invention, and the configuration and operation will be described. First, the configuration of the source follower circuit of the present invention will be described with reference to FIG.

  In FIG. 18, a transistor TR1 is an n-channel transistor and has a function of amplifying current. The transistor TR2 is an n-channel transistor, and normally operates as a current source, and determines a bias for the source follower circuit. The capacitor 104 has a function of holding a gate-source voltage of the transistor TR1. Reference numerals 101 to 103 and 105 denote switches, and a semiconductor element such as a transistor is preferably used. By controlling the switches 101 to 103 and 105, the connection status of the source follower circuit is changed between the correction operation and the normal operation.

  In FIG. 18, the drain terminal of the transistor TR1 is connected to a high potential side power supply (Vdd). The source terminal of the transistor TR2 is connected to the lower potential power supply (Vss). For simplicity, it is assumed that the potential of the low potential side power supply (Vss) is 0V. The terminal 106 is the source terminal of the transistor TR1, is connected to the drain terminal of the transistor TR2, and is connected to the output terminal 110 via the switch 105.

  A reference voltage Vx is applied to the terminal 107, and the terminal 107 is connected to the gate terminal of the transistor TR1 and one terminal of the capacitor 104 through the switch 101. An input voltage Vi is applied to the input terminal 108 and is connected to the other terminal of the capacitor 104 via the switch 102. The other terminal of the capacitor 104 is connected to the source terminal 106 of the transistor TR1 via the switch 103. The bias voltage Vb is applied to the gate terminal 109 of the transistor TR2.

  Next, the operation of the source follower circuit shown in FIG. 18 will be described.

  First, a correction operation is performed. The switches 101 and 103 are turned on to turn on, and the switches 102 and 105 are turned off to turn off. Since the bias voltage Vb is applied to the gate terminal 109 of the transistor TR2, a current flows through the transistor TR2. At this time, the terminal 106 is connected to the terminal 107 via the capacitor 104, and the terminal 107 is supplied with the reference voltage Vx. Therefore, current flows between the terminal 107 and the terminal 106. When the voltage at both ends of the capacitor 104 becomes higher than the threshold voltage of the transistor TR1, the transistor TR1 turns on, and current flows between the source and the drain of the transistor TR1. When the value of the current flowing between the source and the drain of the transistor TR2 becomes equal to the value of the current flowing between the source and the drain of the transistor TR1, no current flows to the capacitor 104, and the capacitor 104 enters a steady state.

  At this time, the capacitor 104 holds the voltage required for the same amount of current as the current flowing through the transistor TR2 to flow through the transistor TR1, that is, the gate-source voltage of the transistor TR1. Therefore, if the current characteristics and the transistor size of the transistor TR1 vary, the magnitude of the gate-source voltage of the transistor TR1 also has a different value. The magnitude of the gate-source voltage of the transistor TR1 at this time is defined as Va. Then, the potential of the terminal 106 becomes a potential lower by Va than the reference voltage Vx.

  Note that since the current is already in a steady state and no current flows between the terminal 106 and the terminal 107, there is no problem even if the switches 101 and 103 are turned off. As a result, the charge of the capacitor 104 is held, and the voltage across the capacitor 104 does not change due to the law of conservation of charge.

  With the above operation, the correction operation ends. By this correction operation, an appropriate voltage is held in the capacitor 104.

  Note that if current does not continue to flow toward the output terminal 110 during the correction operation, that is, if the input impedance of the output terminal 110 is sufficiently high, the switch 105 is omitted and the terminal 106 and the output terminal 110 are directly connected. You may connect.

  The correction operation may be performed at least once before performing the normal operation. That is, the normal operation can be performed any number of times as long as an appropriate voltage is held in the capacitor 104. Note that the charge stored in the capacitor 104 may gradually change due to noise, leakage current, or the like. At that time, the correction operation may be performed again before the charge stored in the capacitor 104 changes significantly.

  Then, the normal operation is performed. The switches 102 and 105 are turned on, and the switches 101 and 103 are turned off. The input voltage Vi is applied to the terminal 108. Therefore, a voltage obtained by adding the voltage Va of the capacitor 104 to the input voltage Vi is applied to the gate terminal of the transistor TR1. Then, in a steady state, the value of the current flowing between the source and the drain of the transistor TR2 becomes equal to the value of the current flowing between the source and the drain of the transistor TR1. The gate-source voltage of the transistor TR1 at that time is Va.

  Therefore, the potential of the terminal 106 becomes lower than the potential of the gate terminal of the transistor TR1 by Va, which is the gate-source voltage of the transistor TR1. Then, the potential of the gate terminal of the transistor TR1 becomes higher by Va than the input voltage Vi. From the above, the potential of the terminal 106 becomes equal to the input voltage Vi. That is, the output voltage Vo becomes equal to the input voltage Vi.

  Therefore, the output voltage Vo does not depend on the value of the reference voltage Vx. This means that there is no problem regardless of the magnitude of the reference voltage Vx. That is, the magnitude of the reference voltage Vx is arbitrary as long as the correction operation can be performed normally. However, it is more desirable that the reference voltage Vx be large enough to allow the transistors TR1 and TR2 to operate in the saturation region. This is because the source follower circuit is usually operated in a saturation region in many cases.

  Further, since the magnitude of the reference voltage Vx is arbitrary, the terminal 107 may be connected to another wiring, a contact, or a terminal. For example, the terminal 107 may be connected to the input terminal 108. At this time, since the magnitude of the reference voltage Vx is arbitrary, the magnitude of the input voltage Vi during the correction operation is also arbitrary. Therefore, the magnitude of the input voltage Vi may be different between when the correction operation is being performed and when the normal operation is being performed.

  Similarly, the terminal 107 may be connected to a high potential side power supply (Vdd), may be connected to the drain terminal of the transistor TR1, may be connected to the output terminal 110, or may be connected to the terminal 109. May be. As described above, the terminal 107 can be connected to an arbitrary place.

  Further, the output voltage Vo does not depend on the voltage Va between the gate and the source of the transistor TR1, as does not depend on the value of the reference voltage Vx. This means that there is no problem irrespective of the magnitude of Va. That is, even if the current characteristics (such as mobility and threshold voltage) of the transistor TR1 and the transistor size (gate length L and gate width W) vary, the influence is not exerted.

Further, the output voltage Vo does not depend on the magnitude of the current flowing between the source and the drain of the transistor TR1 or the transistor TR2. That is, the output voltage Vo does not depend on the magnitude of the bias voltage Vb applied to the gate terminal 109 of the transistor TR2. Further, it does not depend on the current characteristics (such as mobility and threshold voltage) of the transistor TR2 or the transistor size (gate length L and gate width W).

  As described above, in the normal operation, the input voltage Vi is not applied to the gate terminal of the transistor TR1 as it is, but is added with the voltage stored in the capacitor 104. The magnitude of the voltage stored in the capacitor 104 becomes a magnitude according to the situation. That is, even if the current characteristics and the transistor size of the transistor TR1 and the transistor TR2 vary, the magnitude of the voltage stored in the capacitor 104 changes accordingly. Therefore, as a result, it is possible to reduce the influence of variations in the transistors TR1 and TR2.

  Note that FIG. 18 illustrates the case where the transistors TR1 and TR2 are n-channel transistors. However, the present invention can be easily applied to a p-channel type. FIG. 13 illustrates a source follower circuit in the case where the transistors TR1 and TR2 are p-channel transistors. The transistor TR1 has a function of amplifying the current. Transistor TR2 normally operates as a current source and determines the bias for the source follower circuit. Reference numeral 104 denotes a capacitor, which has a function of holding a gate-source voltage of the transistor TR1. The operation and configuration are the same as in the case of the n-channel type, and thus detailed description is omitted.

  In FIG. 18 and FIG. 13, the transistor TR2 that operates as a current source and determines the bias for the source follower circuit is provided. However, the transistor TR2 may not be provided. This corresponds to a case where the current value of the transistor TR2 is 0.

  FIG. 7 shows a circuit diagram in the case where the transistor TR2 is not provided for the source follower circuit of FIG. A switch 701 is connected between the terminal 106 and the low-potential-side power supply (Vss). With the switch 701, the transistor TR1 can be turned on during the correction operation. Therefore, if the transistor TR1 can be turned on at the time of the correction operation, the switch 701 may be connected to another place or the switch 701 itself may not be disposed.

  Next, an operation of the circuit in the case where the transistor TR2 illustrated in FIG. 7 is not provided will be described.

  First, a correction operation is performed. The correction operation is roughly divided into two stages. In the first stage, the transistor TR1 is turned on. Thereafter, in the second stage, the gate-source voltage of the transistor TR1 is set to a voltage substantially equal to the threshold voltage of the transistor TR1.

  In the case of the circuit of FIG. 18, it was not necessary to divide the correction operation into two stages. However, in the case of the circuit in FIG. 7, it is necessary to change the connection state of the circuit and the like depending on each stage in the correction operation.

  In the first stage of the correction operation, the switches TR101, TR103, and 701 are turned on and the switches 102 and 105 are turned off, so that the transistor TR1 is turned on. Therefore, the gate-source voltage of the transistor TR1 at this time is higher than the threshold voltage of the transistor TR1.

  Note that, at this stage, it is only necessary that the transistor TR1 be turned on, and therefore, the method is not limited to this method. For example, if the switch 701 is removed and the terminal 106 is not connected to the low potential side power supply (Vss), the switch 102 is also turned on, and the values of the reference voltage Vx and the input voltage Vi are adjusted. The transistor TR1 can be turned on.

  Next, in the second stage of the correction operation, the switches 101 and 103 are turned on and the switches 102, 105 and 701 are turned off. Thus, the source terminal of the transistor TR1 is connected only to the capacitor 104. Then, if the transistor TR1 is on, a current flows between the source and the drain of the transistor TR1. The current flows toward the capacitor 104. As a result, the charge stored in the capacitor 104 is discharged. This continues until the transistor TR1 turns off, that is, until the gate-source voltage of the transistor TR1 becomes equal to the threshold voltage of the transistor TR1. When the gate-source voltage of the transistor TR1 becomes equal to the threshold voltage of the transistor TR1, almost no current flows through the transistor TR1 and the capacitor 104.

  Note that since no current has already flowed and no current has flowed between the terminals 106 and 107, there is no problem even if the switches 101 and 103 are turned off. As a result, the charge of the capacitor 104 is held, and the voltage across the capacitor 104 does not change due to the law of conservation of charge.

  With the above operation, the correction operation ends. With this correction operation, the threshold voltage of the transistor TR1 is held in the capacitor 104.

  Note that the operation is continued until the voltage of the capacitor 104 becomes equal to the threshold voltage of the transistor TR1, but this is not necessarily required. What is necessary is that the voltage of the capacitor 104 is approximately equal to the threshold voltage of the transistor TR1.

  Then, the normal operation is performed. The switches 102 and 105 are turned on, and the switches 101, 103 and 701 are turned off. The input voltage Vi is applied to the terminal 108. Therefore, the voltage obtained by adding the voltage of the capacitor 104, that is, the threshold voltage of the transistor TR1 to the input voltage Vi is applied to the gate terminal of the transistor TR1. Then, in a steady state, current hardly flows between the source and the drain of the transistor TR1. The gate-source voltage of the transistor TR1 at that time is substantially equal to the threshold voltage of the transistor TR1.

  Therefore, the potential of the terminal 106 is lower than the potential of the gate terminal of the transistor TR1 by the threshold voltage of the transistor TR1. Then, the potential of the gate terminal of the transistor TR1 becomes higher than the input voltage Vi by the voltage of the capacitor 104, that is, the threshold voltage of the transistor TR1. From the above, the potential of the terminal 106 becomes equal to the input voltage Vi. That is, the output voltage Vo becomes equal to the input voltage Vi.

  In FIG. 7, the transistor TR2 that operates as a current source is not provided. However, the transistor TR2 may be provided in the circuit of FIG. The circuit diagram at that time is shown in FIG. The operation is the same as the correction operation, and the capacitor 104 holds the threshold voltage. However, when performing a normal operation, the switch 701 in FIG. 15 needs to be turned on because the transistor TR2 must operate as a current source.

  Note that a capacitance element may be arranged also in the transistor TR2, the threshold voltage of the transistor TR2 may be stored therein, and the variation of the transistor TR2 may be corrected.

  As described above, the present invention can be similarly applied to a circuit in which the transistor TR2 is not provided. Therefore, even if the reference voltage Vx is arbitrary and the current characteristics (such as mobility and threshold voltage) and the transistor size (gate length L and gate width W) of the transistor TR1 vary, the influence is not exerted. And so on. Although FIG. 7 shows the case where the transistor TR1 is an n-channel type, the present invention can be easily applied to a case where the transistor TR1 is a p-channel type.

  In addition, a case where the transistor TR1 is an n-channel type and a case where the transistor TR1 is a p-channel type may be combined, and both may be used as amplification transistors to form a push-pull type. FIG. 14 shows a circuit diagram in that case. The p-channel transistor TR1p is connected to the low-potential-side power supply (Vss), and the capacitor 104p is connected between the gate and the source. The n-channel transistor TR1n is connected to a high-potential-side power supply (Vdd), and a capacitor 104n is connected between the gate and the source. The operation and the like are the same as those in FIG.

  In addition, as shown in FIG. 15, making the capacitance element not hold the gate-source voltage of the transistor, but make the threshold voltage of the transistor not only the source follower circuit but also the differential circuit May be applied. For example, when applied to FIG. 1, it is necessary to switch on between the source terminal of the transistor TR11 and the drain terminal of the transistor TR21 and between the source terminal of the transistor TR12 and the drain terminal of the transistor TR21.

  In this embodiment, the case where the present invention is applied to a source follower circuit is described. However, a cascode circuit is a circuit having a configuration very similar to that of the source follower circuit, and the present invention can be applied to such a cascode circuit. The reason that the cascode circuit is different from the source follower circuit in FIG. 21 is that the gate terminal 4309 of the transistor TR2 is an input terminal, the gate terminal 4308 of the transistor TR1 is a terminal for applying a bias voltage, and the transistor TR1 A load such as a resistance element is disposed between the drain terminal of the transistor TR1 and the high-potential-side power supply (Vdd), and a contact between the load and the drain terminal of the transistor TR1 is an output terminal. .

  Thus, a circuit diagram in the case where the present invention is applied to a cascode circuit is shown in FIG. A load 1601 is arranged between the drain terminal of the transistor TR1 and the high potential power supply (Vdd). Note that in FIG. 16, the transistors TR1 and TR2 are of the n-channel type, but it is needless to say that the present invention can be applied to the case of the p-channel type. The operation and the like are the same as those of the source follower circuit, and the description is omitted.

  Finally, a method for reducing power consumption of a circuit will be described. In an analog circuit, a current often continues to flow even in a steady state. For example, in a source follower circuit, usually, even in a steady state, current continues to flow from the transistor TR1 to the transistor TR2. Therefore, power consumption is large. Therefore, if the current that continues to flow in the steady state is cut off, power consumption can be reduced. As an example, FIG. 17 shows a circuit obtained by devising the circuit of FIG. 18 to reduce power consumption. In FIG. 17, a switch 1701 is provided between the high potential side power supply (Vdd) and the drain terminal of the transistor TR1. By controlling this switch, it is possible to cut off the current that continuously flows from the transistor TR1 to the transistor TR2 even in a steady state. Note that the switch 1701 may be provided anywhere as long as it can interrupt a current that continues to flow. Further, the current that continues to flow may be cut off without disposing the switch 1701. For example, current may not flow through the transistor TR2 by adjusting the voltage Vb of the gate terminal 109 of the transistor TR2. Similarly, current may be prevented from flowing by adjusting the potential of the gate terminal of the transistor TR1.

  In order to reduce the power consumption, the interruption of the current flowing in the steady state may be applied not only to the source follower circuit but also to a differential circuit.

  The contents described in the first embodiment can be applied to the present embodiment, and the contents described in the present embodiment can also be applied to the first embodiment.

(Embodiment 3)
In the first and second embodiments described above, the source follower circuit and the differential circuit to which the present invention is applied have been described. If these circuits are further combined, it can be applied to various circuits. Therefore, in the present embodiment, an operational amplifier to which the present invention is applied will be described as an example.

  There are various operational amplifier circuit configurations. Therefore, the circuit configuration of the operational amplifier is not limited to this embodiment. The present invention can be applied to operational amplifiers having various configurations.

  First, as the simplest configuration, an operational amplifier having a configuration in which a source amplifier circuit is combined with a differential amplifier circuit will be described. As shown in FIG. 29, the circuit of FIG. 1 is used as a differential circuit, an active circuit is used as a load of the differential circuit, and the circuit of FIG. 18 is used as a source follower circuit. An area 2910 surrounded by a dotted line corresponds to a source follower circuit. A signal is input from a positive input terminal 2901 and a negative input terminal 2902, and a signal is extracted from an output terminal 2903. The voltage applied to the bias terminal 2904 is adjusted to control the amount of current flowing as a bias. By controlling the timing of signals input to the terminals 2905 to 2909, the correction operation of each part and the normal operation are switched. Note that, by changing the connection to the terminals 2905 to 2909, a correction operation can be performed in a plurality of circuit portions at the same time.

  Next, FIG. 30 shows an operational amplifier in the case of a push-pull format as a buffer in the output stage. The circuit in FIG. 14 is used as a push-pull source follower circuit. An area 3011 surrounded by a dotted line corresponds to a push-pull type source follower circuit. In FIG. 30, a signal is input from a positive input terminal 3001 and a negative input terminal 3002, and a signal is extracted from an output terminal 3003. By adjusting the voltage applied to the bias terminal 3004, the magnitude of the current flowing as a bias is controlled. By controlling the timing of signals input to the terminals 3005 to 3010, the correction operation and the normal operation of each part are switched. Note that by changing the connection to the terminals 3005 to 3010 and the like, a correction operation can be performed in a plurality of circuit portions at the same time.

  Next, FIG. 31 shows an operational amplifier in a case where the number of amplification stages is two. As the second amplification stage, a common-source amplification circuit is used. A region 3111 surrounded by a dotted line corresponds to a common-source amplifier circuit. In FIG. 31, a signal is input from a positive input terminal 3101 and a negative input terminal 3102, and a signal is extracted from an output terminal 3103. By adjusting the voltage applied to the bias terminal 3104, the magnitude of the current flowing as a bias is controlled. By controlling the timing of the signals input to the terminals 3105 to 3109, the correction operation and the normal operation of each part are switched. Note that, by changing the connection to the terminals 3105 to 3109 or the like, it is possible to simultaneously perform a correction operation in a plurality of circuit portions.

  The capacitor 3110 is provided for performing phase compensation, and may be provided in another place or a resistor may be provided in series with the capacitor 3110. Further, a source follower circuit may be further provided before the second amplification stage.

  Here, the common source amplifier circuit will be briefly described. FIG. 32 shows a common-source amplifier circuit to which the present invention is applied.

  In the conventional source-grounded amplifier circuit, the drain terminal of the transistor TR4 for supplying a bias current and the drain terminal of the transistor TR3 for amplification are connected to each other and serve as an output terminal. The source terminals of both the transistor TR3 and the transistor TR4 are grounded, and as a result, the transistor polarities are reversed. A bias voltage is applied to the gate terminal of the transistor TR4, and an input voltage is applied to the gate terminal of the transistor TR3.

  On the other hand, in the common-source amplifier circuit of FIG. 32, switches 3201 to 3203 and 3205 and a capacitor 3204 are added. Note that when the input impedance of the output terminal 3210 is high, the switch 3205 can be omitted, and the drain of the transistor TR3 and the output terminal 3210 can be directly connected.

  Next, the operation of the common-source amplifier circuit of FIG. 32 will be described with reference to FIGS. First, a correction operation is performed. As shown in FIG. 33, the switches 3203 and 3202 are turned on, and the switches 3201 and 3205 are turned off. Then, the gate-source voltage Va of the transistor TR3 is stored in the capacitor 3204.

  Thereafter, normal operation is performed. As shown in FIG. 34, the switches 3201 and 3205 are turned on, and the switches 3202 and 3203 are turned off. Then, an input voltage Vi is applied from the input terminal 3208. Then, the voltage Va stored in the capacitor 3204 is added to the input voltage Vi and applied to the gate terminal of the transistor TR3. The voltage Va stored in the capacitor 3204 has a magnitude corresponding to the current characteristics of the transistor TR3. Therefore, even if the transistor TR3 varies, the effect can be reduced.

  It should be noted that the correction operation only needs to be performed at least once, which is similar to the case of the source follower circuit or the like.

  Further, as illustrated in FIG. 7, the voltage stored in the capacitor 3204 may be set to the threshold voltage of the transistor.

  When the common-source amplifier circuit is configured as a part of the operational amplifier circuit, a capacitance and a resistor for performing the phase compensation of the operational amplifier may be arranged in the common-source amplifier circuit. As an example, FIG. 35 shows a circuit diagram in the case where a capacitor 3501 is provided between the input terminal 3208 and the drain terminal of the transistor TR3. Note that any element may be arranged anywhere as long as the phase compensation of the operational amplifier can be performed.

  The contents described in the first and second embodiments can be applied to the present embodiment.

  For example, when and how often the correction operation is performed is the same in the present embodiment.

  In addition, since the magnitude of the reference voltage is arbitrary, the terminal providing the reference voltage may be connected to another wiring, a contact, or a terminal.

  Further, instead of causing the capacitor to hold the gate-source voltage of the transistor, the threshold voltage of the transistor may be set.

  Further, in order to reduce power consumption, it is also possible to apply to the present embodiment to cut off a current that continuously flows in a steady state.

  In this embodiment, the case where the transistor is an n-channel transistor has been mainly described. However, the present invention can be easily applied to a p-channel type.

  In this embodiment, the case where the present invention is applied to an operational amplifier has been described. However, the present invention can be applied to circuits such as an OTA (Operational Transconductance Amplifier), a sense amplifier, and a comparator. Further, the present invention can be applied to a case where the transistors are connected in cascade.

  This embodiment can be arbitrarily combined with Embodiments 1 and 2.

(Embodiment 4)
In this embodiment mode, a method for saving time in an electric circuit to which the present invention is applied will be described.

  As described above, in the circuit of the present invention, the operation state includes the correction operation and the normal operation. The correction operation does not need to be performed frequently, but needs to be performed at least once before performing the normal operation.

  Therefore, when there is one circuit (for example, one source follower circuit) between one set of input terminal and output terminal, the timing for performing the correction operation is as follows.

  First, a correction operation is always performed before a normal operation is performed. For example, when a signal is input / output for a certain period, the period is divided into two, a correction operation is performed in a first half period, and a normal operation is performed in a second half period.

  Second, a correction operation is performed during a period when no signal is input / output, and then a normal operation is performed many times.

  As another timing example, it is conceivable that the normal operation is performed at the same time as the correction operation is performed. In that case, in a configuration in which only one circuit is arranged between one set (one pair) of input terminals and output terminals, the correction operation and the normal operation cannot be performed simultaneously. . Therefore, for example, two or more circuits are arranged in parallel between a pair of input terminals and output terminals. Then, by controlling the operation of each circuit, the normal operation can be performed simultaneously while performing the correction operation.

  FIG. 8 shows an example in which two source follower circuits are arranged in parallel between a pair of input terminals and output terminals. A circuit 3603 is provided between the input terminal 3601 and the output terminal 3602. In the circuit 3603, source follower circuits 3604 and 3605 are arranged. Then, the normal operation is performed in one source follower circuit to output a signal to the output terminal 3602, and at the same time, the correction operation is performed in the other source follower circuit. Which of the source follower circuits performs which operation is switched by using a signal input from the terminal 3606. In FIG. 8, when the terminal 3606 is an H signal, the correction operation is performed in the source follower circuit 3604, and when the terminal 3606 is an L signal, the correction operation is performed in the source follower circuit 3605.

  This makes it possible to perform the normal operation while performing the correction operation. As a result, two operations can be performed at the same time, there is no waste in the operation, no wasted time is required, and the time for performing each operation can be increased. Therefore, in the correction operation, the operation can be performed until the steady state is reached, so that the correction can be performed accurately.

  Note that the timing for performing the correction operation is not limited to the above.

  FIG. 8 shows an example in which a source follower circuit is used. However, arranging two or more circuits between a pair of input terminals and an output terminal can be applied to another circuit such as a differential circuit or an operational amplifier. Can also be applied.

  Note that this embodiment can be arbitrarily combined with Embodiments 1 to 3.

(Embodiment 5)
In this embodiment, a structure and operation of a display device, a signal line driver circuit, and the like are described. The circuit of the present invention can be applied to part of a signal line driver circuit.

  As illustrated in FIG. 9, the display device includes a pixel 3701, a gate line driver circuit 3702, and a signal line driver circuit 3710. The gate line driver circuit 3702 sequentially outputs a selection signal to the pixel 3701. The signal line driver circuit 3710 sequentially outputs video signals to the pixels 3701. The pixel 3701 displays an image by controlling the state of light in accordance with a video signal. A video signal input to the pixel 3701 from the signal line driver circuit 3710 is often a voltage. That is, a display element provided in a pixel and an element for controlling the display element often change states in accordance with a video signal (voltage) input from the signal line driver circuit 3710. Examples of a display element arranged in a pixel include a liquid crystal (LCD), an organic EL, an FED (field emission display), and the like.

  Note that a plurality of gate line driver circuits 3702 and signal line driver circuits 3710 may be provided.

  The structure of the signal line driver circuit 3710 is divided into a plurality of parts. For example, the circuit is roughly divided into a shift register 3703, a first latch circuit 3704, a second latch circuit 3705, a digital / analog conversion circuit 3706, and a buffer circuit (amplification circuit) 3707, for example.

  Therefore, the operation of the signal line driver circuit 3710 will be briefly described. The shift register 3703 includes a plurality of rows of flip-flop circuits (FF) and the like, and receives a clock signal (S-CLK), a start pulse (SP), and a clock inversion signal (S-CLKb). Sampling pulses are sequentially output in accordance with the timing of (1).

  The sampling pulse output from the shift register 3703 is input to the first latch circuit 3704. The first latch circuit 3704 receives a video signal from the video signal line 3708, and holds the video signal in each column according to the timing at which the sampling pulse is input. When the digital / analog conversion circuit 3706 is provided, the video signal is a digital value.

  In the first latch circuit 3704, when the holding of the video signal up to the last column is completed, a latch pulse (Latch Pulse) is input from the latch control line 3709 during the horizontal retrace period, and is held in the first latch circuit 3704. The video signal is simultaneously transferred to the second latch circuit 3705. After that, one row of the video signal held in the second latch circuit 3705 is simultaneously input to the digital / analog conversion circuit 3706. Then, a signal output from the digital-analog conversion circuit 3706 is input to a buffer circuit (amplification circuit) 3707. Then, a signal is input from the buffer circuit (amplifier circuit) 3707 to the pixel 3701.

  While the video signal held in the second latch circuit 3705 is input to the digital-to-analog conversion circuit 3706 and is input to the pixel 3701, the shift register 3703 outputs a sampling pulse again. That is, two operations are performed simultaneously. This enables line-sequential driving. Thereafter, this operation is repeated.

  In the signal line driver circuit 3710 performing the above operation, the present invention can be applied to the buffer circuit (amplifier circuit) 3707. The buffer circuit (amplifier circuit) 3707 has a capability of supplying a large amount of current to the pixel 3701. That is, the buffer circuit (amplifier circuit) 3707 has a function of converting impedance. As the buffer circuit (amplifier circuit) 3707, a source follower circuit, a differential amplifier circuit, an operational amplifier, or the like can be used. When a differential amplifier circuit or an operational amplifier is used, an output terminal can be connected to a negative input terminal and a signal can be fed back to function as a voltage follower circuit or the like.

  Further, as shown in FIG. 8, a plurality of source follower circuits, differential amplifier circuits, operational amplifiers, and the like may be arranged so that the correction operation and the normal operation can be performed simultaneously.

  When the first latch circuit 3704 and the second latch circuit 3705 are circuits that can store analog values, the digital-analog conversion circuit 3706 can be omitted in many cases. When data output to the pixel 3701 is binary, that is, a digital value, the digital-to-analog conversion circuit 3706 can be omitted in many cases. Further, the digital-analog conversion circuit 3706 may include a gamma correction circuit in some cases. As described above, the configuration of the signal line driver circuit 3710 is not limited to FIG. 9 and there are various configurations.

  Therefore, FIG. 10 illustrates a signal line driver circuit 3710 in which the first latch circuit 3704 and the second latch circuit 3705 are circuits that can store analog values. A video signal having an analog value is input from the video signal line 3708. FIG. 11 shows an example of one column 3801 of the first latch circuit 3704 and the second latch circuit 3705. The one column 3801 includes one column of the first latch circuit 3704 and one column of the second latch circuit 3705. The first latch circuit 3704 for one column includes a capacitor 3901 and a buffer circuit (amplifier circuit) 3902. The second latch circuit 3705 for one column includes a capacitor 3903 and a buffer circuit (amplifier circuit) 3904.

  One column 3801 of the first latch circuit 3704 and the second latch circuit 3705 operates as follows. First, an analog video signal is input from the video signal line 3708 to the capacitor 3901 and stored therein. Then, data stored in the capacitor 3901 is transferred to the capacitor 3903 in accordance with a signal of the latch control line 3709. At this time, the buffer circuit (amplifier circuit) 3902 converts the impedance. Therefore, by adjusting the size of the capacitors 3901 and 3902, the buffer circuit (amplifier circuit) 3902 can be omitted. Then, the signal stored in the capacitor 3903 is output to the pixel through a buffer circuit (amplifier circuit) 3904.

  As the buffer circuits (amplifier circuits) 3902 and 3904, a source follower circuit, a differential amplifier circuit, an operational amplifier, or the like can be used. As an example, FIG. 12 shows a circuit diagram in the case where a source follower circuit is used as a buffer circuit (amplifier circuit). Further, as shown in FIG. 8, a plurality of buffer circuits (amplifier circuits) may be arranged so that the correction operation and the normal operation can be performed simultaneously.

  This embodiment can be arbitrarily combined with Embodiments 1 to 4.

(Embodiment 6)
In this embodiment mode, a layout diagram of an electric circuit using the present invention will be described.

  In this embodiment, a layout diagram of a source follower circuit to which the present invention is applied will be described as an example. FIG. 19 shows a circuit diagram when the circuit diagram of the source follower circuit of FIG. 18 is described in a manner similar to the layout diagram.

  In FIG. 19, the capacitor 104 is formed as a MOS capacitor. That is, when the MOS capacitor is considered as a transistor, the source terminal and the drain terminal are connected, the contact is used as one terminal of the capacitor, and the gate terminal is used as the other terminal of the capacitor. When a capacitor is formed using a MOS capacitor in this manner, the capacitance value can be increased. Note that in this case, it is preferable that the polarity when the capacitor 104 is considered to be a transistor be the same as that of the transistor TR1. Because, in this case, when it is considered that the MOS capacitor is a transistor, it is necessary to keep the transistor turned on. If the transistor is turned off, the capacitance value of the MOS capacitor becomes zero. Therefore, in order to turn on the capacitance element 104, it is desired to have the same polarity as the transistor TR1.

  FIG. 20 shows a layout diagram of the source follower circuit of FIG. A transistor has a gate insulating film layer over the semiconductor layer 4201 made of polycrystalline silicon or the like and a gate wiring (first wiring) 4202 thereover as a transistor. An interlayer insulating film is provided in a layer above the gate wiring (first wiring) 4202, and a second wiring 4204 is provided thereon. The second wiring 4204 and the semiconductor layer 4201 and the second wiring 4204 and the gate wiring (first wiring) 4202 are connected by opening a contact 4203.

  If a known technique is used using a layout diagram as shown in FIG. 20, the electric circuit of the present invention can be realized.

  Note that the transistor TR1 and the transistor TR2 usually operate in a saturation region in many cases. In an ideal transistor, the amount of current flowing between the source and the drain does not change in the saturation region even if the voltage between the source and the drain changes. However, actually, the amount of current flowing between the source and the drain of the transistor changes even in a saturation region due to a phenomenon called a kink effect or an Early effect. Therefore, the current value changes and an error occurs. Therefore, in order to reduce the kink effect, the Early effect, and the like, in FIG. 20, the gate length L of the transistor TR1 and the transistor TR2 is increased. Note that there are other methods for reducing the kink effect, the Early effect, and the like, such as adding a transistor in series, and the method can be applied to the present application.

  In the case of performing an ideal operation, the voltage of the capacitor 104 does not change between the correction operation and the normal operation. However, in practice, the applied voltage is divided by the parasitic capacitance (gate capacitance) of the transistor (here, the transistor TR1) whose capacitor 104 is connected to the gate terminal. As a result, the voltage of the capacitor 104 slightly changes between the correction operation and the normal operation. As a result, an error occurs. In order to reduce the error, the capacitance of the capacitor 104 needs to be sufficiently larger than the parasitic capacitance (gate capacitance) of the transistor to which the capacitor 104 is connected to the gate terminal. Specifically, it is desired that the capacitance of the capacitor 104 be at least five times the parasitic capacitance (gate capacitance) of the transistor to which the capacitor 104 is connected to the gate terminal.

  Note that this example can be arbitrarily combined with Embodiments 1 to 5.

(Embodiment 7)
Examples of the electronic device using the present invention include a video camera, a digital camera, a goggle-type display (head-mounted display), a navigation system, a sound reproducing device (such as a car audio and an audio component), a notebook personal computer, a game device, and a portable information terminal. (A mobile computer, a mobile phone, a portable game machine, an electronic book, or the like), and an image reproducing apparatus provided with a recording medium (specifically, a recording medium such as a Digital Versatile Disc (DVD) can be reproduced and its image can be displayed. Display device). FIG. 36 shows specific examples of these electronic devices.

  FIG. 36A illustrates a display device, which includes a housing 13001, a support 13002, a display portion 13003, a speaker portion 13004, a video input terminal 13005, and the like. The present invention can be used for an electric circuit included in the display portion 13003. According to the present invention, the display device shown in FIG. 36A is completed. As the display portion 13003, an organic EL display, a liquid crystal display, or the like can be used. The display devices include all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

  FIG. 36B illustrates a digital still camera, which includes a main body 13101, a display portion 13102, an image receiving portion 13103, operation keys 13104, an external connection port 13105, a shutter 13106, and the like. The present invention can be used for an electric circuit included in the display portion 13102. According to the present invention, a digital still camera shown in FIG. 36B is completed.

  FIG. 36C illustrates a laptop personal computer, which includes a main body 13201, a housing 13202, a display portion 13203, a keyboard 13204, an external connection port 13205, a pointing mouse 13206, and the like. The present invention can be used for an electric circuit included in the display portion 13203. According to the present invention, the display device shown in FIG. 36C is completed.

  FIG. 36D shows a mobile computer, which includes a main body 13301, a display portion 13302, a switch 13303, operation keys 13304, an infrared port 13305, and the like. The invention can be used for an electric circuit included in the display portion 13302. According to the present invention, the mobile computer shown in FIG. 36D is completed.

  FIG. 36E illustrates a portable image reproducing device (specifically, a DVD reproducing device) including a recording medium, which includes a main body 13401, a housing 13402, a display portion A 13403, a display portion B 13404, and a recording medium (DVD or the like). A reading unit 13405, operation keys 13406, a speaker unit 13407, and the like are included. The display portion A13403 mainly displays image information and the display portion B13404 mainly displays character information. The present invention can be used for an electric circuit included in the display portions A, B13403, and 13404. Note that the image reproducing device provided with the recording medium includes a home game machine and the like. According to the present invention, the DVD reproducing device shown in FIG.

  FIG. 36F illustrates a goggle-type display (head-mounted display), which includes a main body 13501, a display portion 13502, and an arm portion 13503. The present invention can be used for an electric circuit included in the display portion 13502. Further, according to the present invention, the goggle type display shown in FIG. 36 (F) is completed.

  FIG. 36G illustrates a video camera, which includes a main body 13601, a display portion 13602, a housing 13603, an external connection port 13604, a remote control receiving portion 13605, an image receiving portion 13606, a battery 13607, a voice input portion 13608, operation keys 13609, and the like. . The present invention can be used for an electric circuit included in the display portion 13602. According to the present invention, the video camera shown in FIG. 36G is completed.

  FIG. 36H illustrates a mobile phone, which includes a main body 13701, a housing 13702, a display portion 13703, a voice input portion 13704, a voice output portion 13705, operation keys 13706, an external connection port 13707, an antenna 13708, and the like. The present invention can be used for an electric circuit included in the display portion 13703. Note that the display portion 13703 can reduce current consumption of the mobile phone by displaying white characters on a black background. According to the present invention, the mobile phone shown in FIG. 36H is completed.

  If the emission luminance of the display material increases in the future, it becomes possible to enlarge and project the light including the output image information with a lens or the like and use it for a front-type or rear-type projector.

  In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the response speed of the light-emitting material is extremely high, the light-emitting device is preferable for displaying moving images.

  Further, in the light emitting device, the light emitting portion consumes power. Therefore, it is desirable to display information so that the light emitting portion is reduced as much as possible. Therefore, when a light emitting device is used for a portable information terminal, particularly a display portion mainly for character information such as a mobile phone or a sound reproducing device, the character information is driven by a light emitting portion with a non-light emitting portion as a background. It is desirable to do.

  As described above, the applicable range of the present invention is extremely wide, and the present invention can be used for electronic devices in all fields. Further, the electronic device of this embodiment may use an electric circuit or a semiconductor device having any of the structures described in Embodiments 1 to 6.

FIG. 2 illustrates a configuration of a differential circuit of the present invention. FIG. 4 illustrates an operation of the differential circuit of the present invention. FIG. 4 illustrates an operation of the differential circuit of the present invention. FIG. 4 illustrates an operation of the differential circuit of the present invention. FIG. 4 illustrates an operation of the differential circuit of the present invention. FIG. 4 illustrates an operation of the differential circuit of the present invention. FIG. 2 illustrates a configuration of a source follower circuit of the present invention. FIG. 2 illustrates a configuration of a switching amplifier circuit of the present invention. FIG. 2 is a diagram illustrating a configuration of a display device of the present invention. FIG. 2 is a diagram illustrating a configuration of a display device of the present invention. FIG. 4 illustrates an example of a configuration of a signal line driver circuit of the present invention. FIG. 4 illustrates an example of a configuration of a signal line driver circuit of the present invention. FIG. 2 illustrates a configuration of a source follower circuit of the present invention. FIG. 2 illustrates a configuration of a source follower circuit of the present invention. FIG. 2 illustrates a configuration of a source follower circuit of the present invention. FIG. 2 illustrates a configuration of a cascode circuit of the present invention. FIG. 2 illustrates a configuration of a source follower circuit of the present invention. FIG. 2 illustrates a configuration of a source follower circuit of the present invention. FIG. 2 illustrates a configuration of a source follower circuit of the present invention. FIG. 3 is a diagram illustrating a layout of a source follower circuit of the present invention. FIG. 4 illustrates a configuration of a conventional source follower circuit. FIG. 2 illustrates a structure of a basic circuit of the present invention. FIG. 2 illustrates a structure of a basic circuit of the present invention. FIG. 4 illustrates a configuration of a conventional source follower circuit. FIG. 2 illustrates a configuration of a differential amplifier circuit of the present invention. FIG. 2 illustrates a configuration of a differential amplifier circuit of the present invention. FIG. 2 illustrates a configuration of a differential amplifier circuit of the present invention. FIG. 2 illustrates a configuration of a differential amplifier circuit of the present invention. FIG. 2 is a diagram illustrating an example of a configuration of an operational amplifier according to the present invention. FIG. 2 is a diagram illustrating an example of a configuration of an operational amplifier according to the present invention. FIG. 2 is a diagram illustrating an example of a configuration of an operational amplifier according to the present invention. FIG. 2 illustrates a configuration of a common-source amplifier circuit of the present invention. FIG. 4 is a diagram illustrating the operation of the common-source amplifier circuit of the present invention. FIG. 4 is a diagram illustrating the operation of the common-source amplifier circuit of the present invention. FIG. 2 illustrates a configuration of a common-source amplifier circuit of the present invention. 1 is a diagram of an electronic device to which the present invention is applied.

Claims (7)

A first transistor, a first capacitor, a first switch, a first terminal, a second terminal, a second transistor, a second capacitor, a second switch, a third terminal, and a fourth terminal. An analog circuit having a terminal and
A gate terminal of the first transistor and one terminal of the first capacitor are electrically connected;
A gate terminal of the second transistor and one terminal of the second capacitor are electrically connected;
A source terminal of the first transistor and a source terminal of the second transistor are electrically connected;
The first terminal and one terminal of the first capacitor are electrically connected through the first switch,
The third terminal is electrically connected to one terminal of the second capacitor through the second switch.
A means for electrically connecting the other terminal of the first capacitor element and one of the second terminal and a source terminal of the first transistor;
A terminal electrically connected to the other terminal of the second capacitor and one of the fourth terminal and a source terminal of the second transistor. Analog circuit. In claim 1,
Means for supplying a current,
An analog circuit, wherein a source terminal of the first transistor and a means for supplying the current are electrically connected. In claim 1 or claim 2,
Means for interrupting a current flowing through the first transistor;
Means for interrupting a current flowing through the second transistor. In any one of claims 1 to 3,
The first terminal and the second terminal are electrically connected,
An analog circuit, wherein the third terminal and the fourth terminal are electrically connected. The analog circuit according to any one of claims 1 to 4,
An analog circuit comprising any one of a differential amplifier circuit, an operational amplifier, and a signal line driver circuit.   A display device comprising the analog circuit according to claim 1. An electronic apparatus comprising the display device according to claim 6.

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