JP5024760B2 - Signal level conversion circuit - Google Patents

Description

The present invention relates to a signal level converting circuits for converting a low-level input signal to the high level output signal.

In recent years, in control drive circuits for display devices, it has become possible to lower the drive voltage of controller ICs as the transistor threshold voltage has decreased due to advances in semiconductor technology, and lower power consumption for applications. Therefore, the output signal of the controller IC tends to decrease in amplitude. In addition to the above, in order to reduce unnecessary radiation (EMI) noise, low amplitude transmission of the interface signal is strongly desired, and various proposals have been made for these. (For example, see Patent Documents 1 and 2.)
Japanese Patent Laid-Open No. 2001-85888 JP 2005-31790 A

  However, in the case where peripheral circuits are formed on the same glass substrate using the same process for forming pixel transistors, such as liquid crystal display devices using thin film transistors and EL display devices, single crystal silicon semiconductors are used. When the threshold value of the transistor is difficult to control and the level shifter circuit formed on the glass substrate in response to the low-amplitude signal output from the controller IC does not operate normally due to the large threshold voltage fluctuation caused by process variations. It was a cause of high costs.

  FIG. 11 is a circuit diagram showing an example of the configuration of a conventional level shifter circuit. The level shifter circuit 30 shown in the figure converts a signal IN operating with a low-voltage power supply VIH-GND and its inverted signal XIN into a signal OUT operating with a positive high-voltage power supply VDD-GND and its inverted signal XOUT. Therefore, high-voltage N-type MOS transistors (hereinafter referred to as NMOS) 22a and 22b and high-voltage P-type MOS transistors (hereinafter referred to as PMOS) 24a and 24b in the input stage are provided.

  Here, signals IN and XIN are input to the gates of the NMOSs 22a and 22b, respectively, and their sources are connected to GND. The gates of the PMOSs 24a and 24b are connected to the internal nodes B and A, respectively, their sources are connected to the power supply VDD, and their drains are connected to the drains of the NMOSs 22a and 22b, respectively. Signals XOUT and OUT are output from the internal nodes A and B, respectively.

  In the following description, the power supply VDD> the power supply VIH> GND, the high levels of the signals IN and XIN are the power supply VIH, the low level is the GND potential, the high levels of the signals OUT and XOUT are the power supply VDD, and the low level is the GND potential. It is.

  In the level shifter circuit 30, when the signal IN is at a high level and the inverted signal XIN is at a low level, the NMOS 22a is turned on and the NMOS 22b is turned off. Therefore, the signal XOUT is connected to GND via the NMOS 22a and becomes low level. The PMOS 24b is turned on by the low level of the signal XOUT, and the signal OUT is connected to the power supply VDD via the PMOS 24b and becomes the high level. The PMOS 24a is turned off by the high level of the signal OUT.

  Subsequently, when the signal IN is at a low level and the signal XIN is at a high level, the NMOS 22a is turned off and the NMOS 22b is turned on. Therefore, the signal OUT is connected to GND through the NMOS 22b and becomes low level. The PMOS 24a is turned on by the low level of the signal OUT, and the signal XOUT is connected to the power supply VDD via the PMOS 24a and becomes high level. Then, the PMOS 24b is turned off by the high level of the signal XOUT.

  By the way, in the level shifter circuit 30, when the signals IN and XIN change, the PMOS 24a and NMOS 22a, or the PMOS 24b and NMOS 22b are temporarily turned on simultaneously, and a through current flows from the power supply VDD to GND. For example, when the signal IN changes from low level to high level and the signal XIN changes from high level to low level, the NMOS 22a is turned on and the NMOS 22b is turned off. At this time, the PMOS 24a is still on and the PMOS 24b is off.

  Accordingly, a through current flows from the power supply VDD to GND through the PMOS 24a and the NMOS 22a in the on state. In a state where this through current flows, the PMOS 24b is turned on by extracting the charge of the gate of the PMOS 24b by the drive capability of the NMOS 22a. When the signal OUT becomes high level via the PMOS 24b which is turned on, the PMOS 24a is turned off, and the signal XOUT becomes low level via the NMOS 22a.

  Therefore, in the level shifter circuit 30, it is necessary to increase the drive capability of the NMOSs 22a and 22b in the input stage, that is, the transistor size as the level shift amount (potential difference between VDD and VIH) increases. was there.

  Further, in the level shifter circuit 30, the level shifter circuit is operated using two-phase input signals IN and XIN having opposite polarities. Therefore, a pair of connection terminals is required as a signal interface. As the number of necessary internal signals increases, the number of signal interface connection terminals increases, which complicates the wiring work and impedes the compact mounting of devices such as connectors and FPCs (flexible cables). There was a problem that the cost related to mounting was increased.

The present invention has been made in view of the above circumstances, and the object of the present invention is that signal level conversion can be normally performed even for a low-amplitude input signal less than the threshold value of the transistor, and the power supply voltage can be reduced. variation and high operation reliability against variations in transistor characteristics, and configuration is to provide a simple signal level converting circuits.

The present invention for solving the above-mentioned problems is a transistor having the same polarity channel with each other, a first input transistor and a second input transistor for converting a low-amplitude input signal into a high-amplitude output signal, A transistor having the same polarity channel as the first input transistor and the second input transistor, connected to a first current source for supplying current, and adding a first offset voltage to the input signal to A first offset transistor applied to the gate of one input transistor, and a transistor having the same polarity channel as the first input transistor and the second input transistor, and connected to a second current source for supplying current And adding a second offset voltage to the first bias voltage superimposed on the input signal, thereby adding the second input transistor. And a second offset transistors to be applied to the gate of said first offset transistor has n N-channel transistor having a drain connected to the gate, these n pieces of N-channel transistors are n-stage cascade To the first offset transistor, and the second offset transistor has m N-channel transistors whose drains are connected to the gate, and these m N-channel transistors are m The second offset transistor is connected in cascade to form the second offset transistor, and the cascaded m-stage N-channel transistor constituting the second offset transistor is the cascaded n-stage N constituting the first offset transistor. many stages as compared to channel transistor, ie it is n <m signal level It is a conversion circuit.

  According to the present invention, it is possible to normally perform signal level conversion even for a low-amplitude input signal that does not reach the threshold of the transistor, and the operation reliability is high and simple with respect to fluctuations in power supply voltage and transistor characteristics. A signal level conversion circuit having a simple structure and a liquid crystal display device using the circuit can be obtained.

  Hereinafter, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a signal level conversion circuit according to Embodiment 1 of the present invention. The signal level conversion circuit of the present embodiment shown in FIG. 1 outputs an input signal 9 which is a low level control signal of, for example, about 1V supplied from a controller or the like as an output signal 14 of high level of, for example, about 5V. This signal level conversion circuit has first and second input transistors 1 and 2 composed of N-channel thin film transistors constituting signal level conversion means for converting a low level input signal 9 into a high level output signal 14. . The source of the first input transistor 1 is set to the GND potential, and the input signal 9 is applied to the source of the second input transistor 2.

  The first and second input transistors 1 and 2 are connected to the high-level power supply VDD via load transistors 20 and 21 each having a drain made of a P-channel thin film transistor. The gates of the load transistors 20 and 21 are connected to the drains of the load transistors, respectively, and to the drains of the first input transistor 1 and the second input transistor 2, respectively. That is, load transistors 20 and 21 constitute a flip-flop.

  The gate of the first input transistor 1 is connected to the anode of the one-stage diode 17 constituting the first offset means, is connected to the power supply VDD via the first current source 15, and is further connected to the cathode. When the input signal 9 is applied to the cathode of the diode 17, the voltage corresponding to the threshold voltage of one stage of the transistor constituting the diode is applied between the cathode and the anode of the diode 17. A voltage signal obtained by adding the threshold voltage as an offset voltage to the input signal 9 is generated at the anode of the diode 17 and applied to the gate of the first input transistor 1.

  Similarly, the anode of the two-stage cascaded diode 18 constituting the second offset means is connected to the gate of the second input transistor 2 and is connected to the power supply VDD via the second current source 16. The cathode is at GND potential. As a result, a voltage corresponding to a voltage corresponding to two threshold levels of the transistor constituting the diode is generated between the cathode and the anode of the diode 18. As a result, a voltage signal obtained by adding the threshold voltage (for two stages) to the GND potential as an offset voltage is generated at the anode of the diode 18 and applied to the gate of the second input transistor 2.

FIG. 2 is an example in which the circuit configuration shown in FIG. 1 is described more specifically in consideration of the transistor size.
In the circuit shown in FIG. 2, N-channel transistors are used as the diodes 17 and 18 constituting the first and second offset means.

  That is, the drain of the N-channel transistor 17 constituting the first offset means is connected to the gate of the first input transistor 1, and the drain is connected to the gate of the transistor and the first current source 15 is connected. Via the power supply VDD. Further, the input signal 9 is applied to the source of the N-channel transistor 17. As a result, when the input signal 9 is applied to the source of the N-channel transistor 17, a voltage corresponding to the threshold voltage of the transistor is generated between the source and gate of the N-channel transistor 17, and the threshold voltage is applied to the input signal 9. Is added to the drain of the N-channel transistor 17 and applied to the gate of the first input transistor 1.

  Similarly, the drain of the two-stage cascaded N-channel transistor 18 constituting the second offset means is connected to the gate of the second input transistor 2, and the drain is connected to the gate of the transistor and is connected to the second transistor. Two power sources 16 are connected to the power supply VDD. As a result, a voltage corresponding to the threshold voltage (for two stages) of the N-channel transistor 18 is generated between the source and the gate of the N-channel transistor 18, and this voltage signal is generated at the drain of the N-channel transistor 18. 2 is applied to the gate.

  As described above, in the signal level conversion circuit according to the present embodiment, the transistors 17 and 18 constituting the offset means are set as the N channel, and the same N channel as the first and second input transistors 1 and 2 is used. The second input transistors 1 and 2 and the N channel transistors 17 and 18 constituting the offset means are formed by the same manufacturing process. This prevents the signal level conversion circuit from being affected by variations in transistor characteristics due to process variations.

  The current source 15 is formed of a current source transistor composed of a P-channel transistor having a gate connected to the bias voltage 19 and a source connected to the power supply VDD. The current source 16 is composed of a current source transistor composed of a P-channel transistor having a gate connected to the input signal 9 and a source connected to the power supply VDD.

  The second input transistor 2 is composed of four N-channel transistors connected in parallel. The first input transistor 1 is composed of two N-channel transistors connected in parallel. Load transistors 20 and 21 are each composed of two P-channel transistors connected in series.

  That is, the W / L of the first input transistor 1 is smaller than the W / L of the second input transistor 2, and the W / L of the first load transistor 20 is the first input transistor. The W / L of the second load transistor 21 is smaller than the W / L of the second input transistor 2.

Since the channel width W / channel length L of the transistor determines the current capability of the transistor, the current capability of the first input transistor 1 is smaller than that of the second input transistor 2. The current capability of the first load transistor 20 is smaller than that of the first input transistor 1, and the current capability of the second load transistor 21 is smaller than that of the second input transistor 2. It can be said that it is getting smaller.
In addition, the current source P-channel transistors 15 and 16 and the N-channel transistors 17 and 18 constituting the offset means have a channel length L smaller than the channel length of the transistors constituting the circuit unit to which the high amplitude signal is applied. In addition, since the threshold voltage of the transistor depends on the channel length L, the threshold voltage is shifted to a low voltage.

  Next, the operation in the present embodiment configured as described above will be described. In this description, the low level voltage of the input signal 9 is set to 0 V which is substantially equal to the ground voltage, the high level voltage is set to the input amplitude voltage VIH, the bias voltage 19 which is constantly output is set to VREF, and the offset voltage Is Va.

  In the signal level conversion circuit of FIG. 2, when a high level input signal 9 is first applied to the source of the N-channel transistor 17 and the source of the second input transistor 2, the N-channel transistor 17 is not connected between the source and gate. A voltage corresponding to the drain threshold voltage is generated. A voltage (VIH + Va) obtained by adding the threshold voltage as the offset voltage Va to the high level voltage VIH of the input signal 9 is generated at the drain of the N-channel transistor 17 and applied to the gate of the first input transistor 1.

  At this time, since the source of the first input transistor 1 is the GND potential, the voltage Von applied between the source and gate of the first input transistor 1 is expressed by the following equation.

Von = VIH + Va
Therefore, by adjusting the fixed bias VREF 19 and setting the offset voltage Va so that the voltage Von is larger than the threshold voltage of the first input transistor 1, the first input transistor 1 is turned on. Since the load transistor 21 has the same gate potential as GND, the load transistor 21 is turned on. Further, since the gate potential of the load transistor 20 becomes VDD level from the load transistor 21, the load transistor 20 is turned off.

FIG. 3 is a diagram for explaining the generation of the offset voltage.
FIG. 3 (1) shows a state in which VREF is applied to the bias voltage 19. At this time, a current Iconstant determined by VREF flows through the current source transistor 15. Then, as shown in the current-voltage characteristics of the diode-connected transistor in (2) of FIG. 3, a voltage Va is generated at the drain of the N-channel transistor 17 so as to be superimposed on the additional voltage VG.

  Next, a voltage generated at the drain of the N-channel transistor 18 whose source is the GND potential will be described.

  In the embodiment of the present invention, since the gate of the current source transistor 16 is connected to the input signal 9, and the channel length L of the current source transistor 16 is set small as described above, the threshold value is small. As a result, even if the input signal 9 is a low-amplitude signal that is less than the threshold value, the current amount of the current source 16 is small when the input signal 9 is at a high level voltage.

FIG. 4 is a diagram for explaining a method of switching the offset voltage.
(1) in FIG. 4 shows a state in which the input signal 9 is at a low level. Since the current source transistor 16 is a PMOS transistor, it is turned on, and a large current Ilarge flows through the N-channel transistor 18. Then, as shown in the current-voltage characteristic of the diode-connected transistor in (3) of FIG. 4, a voltage of GND + Va1 is generated at the drain of the N-channel transistor 18.

  (2) in FIG. 4 shows a state in which the input signal 9 is at a high level. Since the current source transistor 16 is a PMOS transistor, it is turned off, and a small current Ismall flows through the N-channel transistor 18. Then, as shown in the current-voltage characteristic of the diode-connected transistor in (3) of FIG. 4, a voltage of GND + Va2 is generated at the drain of the N-channel transistor 18.

  Thus, the offset voltage Va for one stage automatically becomes a small voltage and a weak offset voltage Va2 in accordance with the current-voltage characteristics of the diode-connected transistor.

FIG. 5 shows an offset voltage when a diode-connected transistor having a two-stage connection configuration is used. As shown in (2) of FIG. 5, the offset voltage is (Va2 + Va2).
In this manner, a voltage signal (GND (0V) + Va2 + Va2 = 2 × Va2) obtained by adding two stages of the weak offset voltage Va2 to the GND potential is generated at the drain of the N-channel transistor 18, and the second input transistor 2 is applied to the gate. At this time, since the voltage VIH of the high-level input signal 9 is applied to the source of the second input transistor 2, the voltage Voff applied between the gate and the source of the second input transistor 2 is expressed by the following equation: It is represented by

Voff = (2 × Va2) −VIH
Since Va2 is a sufficiently small voltage as described above, the voltage Voff is smaller than the threshold voltage of the second input transistor 2, and the second input transistor 2 is sufficiently turned off.

It should be noted that the offset voltage (2 × Va2) exceeds VIH and becomes larger than the threshold voltage of the input transistor 2 due to excessive offset, so that the malfunction does not occur when the input transistor 2 is turned on. Thus, the channel length L of the transistors 17 and 18 is set small.
Due to the channel length dependence of the threshold characteristics of the transistors, the threshold values of the transistors 17 and 18 have small characteristics. Therefore, even if the threshold voltage increases due to variations in the characteristics of the transistors, the offset amount becomes too large and malfunctions. Will not trigger.

  That is, when a high-level input signal 9 is applied to the signal level conversion circuit shown in FIG. 2, the load transistor 21 is turned on and the second input transistor 2 is turned off at the same time, whereby the second input transistor 2 is turned on. The drain voltage is a maximum voltage substantially equal to the voltage of the power supply VDD via the load transistor 21 that is turned on, and this maximum voltage is output as the output signal 14.

  FIG. 6 is a diagram showing signal waveforms. In the present embodiment, the output signal 14 is an output signal whose amplitude is the power supply VDD of the thin film transistor integrated circuit as indicated by reference numeral 345. The high level voltage VIH of the input signal 9 has a signal waveform as indicated by reference numeral 41. The signal waveform of the voltage obtained by applying the offset voltage Va to the high level voltage VIH of the input signal 9 is indicated by reference numeral 343. It becomes like this.

The responsiveness of the output signal 14 is determined by the ratio between the on-current of the load transistor 21 and the off-current of the second input transistor 2.
In the present invention shown in FIG. 2, as described above, the first and second input transistors 1 and 2 and the N-channel transistors 17 and 18 constituting the offset means can be formed in the same manufacturing process by the same polarity N-channel transistor. Consists of. As a result, when the threshold values of the input transistors 1 and 2 are small, the threshold values of the N-channel transistors 17 and 18 constituting the offset unit are similarly reduced, so that the offset bias is automatically suppressed. Therefore, the second input transistor 2 can be appropriately turned off. As a result, the responsiveness of the output signal 14 with respect to process variations is better than that of the conventional signal level conversion circuit, and high-speed operation can be realized.

  At this time, since the load transistor 20 is off, the current flowing from VDD to GND can be cut off, so that the operation current consumption when the output 14 outputs a high level voltage can be reduced.

Next, a case where a low level input signal 9 is input will be described.
The voltage generated at the drain of the N-channel transistor 18 whose source is the GND potential is such that the gate of the current source transistor 16 is connected to the input signal 9 and the input signal 9 is at the GND potential. As shown in (1) and (3) of FIG. 4, the offset voltage Va for one stage is automatically increased according to the current-voltage characteristics of the diode-connected transistor. The voltage Va1. Therefore, in this embodiment in which the diodes are connected in a two-stage cascade configuration, (Va1 + Va1) is obtained as shown in (1) of FIG.

Accordingly, the voltage Von applied between the gate and the source of the second input transistor 2 is expressed by the following equation, and thus the second input transistor 2 is sufficiently turned on.
Von = Va1 + Va1-GND (0V) = 2 × Va1
The gate potential of the load transistor 20 is lowered to the same potential as the input signal 9 (0 V) by the second input transistor 2 and is turned on.

Subsequently, the gate potential of the load transistor 21 is raised to the same potential as Vdd by the load transistor 20 which is turned on, and is turned off.
The voltage Voff applied between the gate and source of the first input transistor 1 is Va from the following equation.
Voff = Va-GND (0V) = Va
By adjusting the fixed bias VREF19 and setting the offset voltage Va so that the voltage Voff becomes smaller than the threshold voltage of the first input transistor 1, the first input transistor 1 is turned off and the load transistor 21 is stronger. Turns off.
In this way, the output signal 14 from the drain of the second input transistor 2 becomes a voltage of 0 V which is substantially equal to the ground voltage of the signal level conversion circuit.

  That is, when the low-level input signal 9 is applied, the second input transistor 2 is turned on, and at the same time, the first input transistor 1 is turned off and the load transistor 21 is turned off. As a result, the drain potential of the second input transistor 2 becomes 0 V, which is substantially equal to the ground voltage, and this 0 V voltage is output as the output signal 14.

  Further, since the current capability of the input transistor 1 is smaller than the current capability of the input transistor 2, the offset bias Va becomes a value close to the threshold value of the input transistor 1 when the voltage VREF of the bias voltage 19 fluctuates. Even so, since the ON state of the input transistor 2 is stronger, the ON / OFF states of the load transistor 20 and the load transistor 21 are determined, and malfunction can be prevented.

  Even when the threshold value of the N-channel transistor is deep and the mobility is low and the threshold value of the P-channel transistor is shallow and the mobility is high due to variations in the transistor manufacturing process, the current of the input transistor 2 is increased. Since the current capability of the load transistor 21 is smaller than the capability, it is possible to prevent erroneous inversion of the output 14 and deterioration of the falling delay.

  Further, the current capability of the input transistor 1 and the input transistor 2 is determined by the transistor size. However, due to process variations and the like, the size difference between the input transistor 1 and the input transistor 2 is small, so that the difference in current capability between the transistors is small. There may be cases. Even in such a case, the N-channel transistor 17 serving as an input signal offset means has a single-stage configuration, and the N-channel transistor 18 has a two-stage configuration. The gate potential is high. Accordingly, since the on state of the input transistor 2 is stronger, the on / off states of the load transistor 20 and the load transistor 21 are determined, and malfunction can be prevented.

In this case, the response of the output signal 14 is determined by the ratio of the off current of the load transistor 21 and the on current of the second input transistor 2. Also in this case, as described above, the N-channel transistors 17 and 18 constituting the offset means and the first and second input transistors 1 and 2 are constituted by N-channel transistors having the same polarity that can be formed by the same manufacturing process. As a result, even when the threshold values of the input transistors 1 and 2 are large, the threshold values of the N-channel transistors 17 and 18 constituting the offset means are also increased, so that the offset bias can be automatically increased. Thus, the second input transistor 2 can be sufficiently turned on.
As a result, even when the output signal 14 becomes a low level output, the responsiveness of the output signal 14 to the process variation is better than that of the conventional signal level conversion circuit, as in the case of the high level output. Can be realized.

Next, a method for setting the voltage VREF of the bias voltage 19 will be described.
As described above, the bias voltage 19 is set so that the voltage Von (= VIH + Va) is larger than the threshold voltage of the first input transistor 1 when the input signal 9 is at a high level. When VREF is set and the input signal 9 is at a low level, the voltage Voff (= Va) may be set to be smaller than the threshold voltage of the first input transistor 1.

Here, when the threshold voltage of the first input transistor 1 is set to Vt, the above is arranged as follows.
Von = VIH + Va> Vt
Voff = Va <Vt
That is,
VIH + Va>Vt> Va
VREF may be set so that Va satisfies the above formula.

  In particular, when VIH is larger than Vt, Va may be a sufficiently small value. Therefore, VREF can be set to a somewhat high voltage, and power consumption can be reduced.

In addition, as described above, even if Va increases to about Vt, the current capability of the input transistors 1 and 2 is increased or decreased, so that a malfunction may occur in principle for fluctuations in the VREF voltage. It is difficult to achieve high operational reliability.
In addition, when the input transistor is turned on, the offset amount becomes large and the transistor is turned on more. When the input transistor is turned off, the offset amount becomes smaller and the transistor is turned off. The ratio of the on-state current to the off-state current of the driving transistor can be increased. As a result, the operation speed is increased, and high operation reliability can be ensured even with respect to transistor characteristic fluctuations, power supply voltage fluctuations, and even VIH fluctuations.

In addition, the offset transistor 17 has a single-stage configuration and the offset transistor 18 has a two-stage configuration, so that even when the current capability difference between the input transistors 1 and 2 due to variations in process processing accuracy is small, high operational reliability is achieved. realizable. That is, even when the difference in current that can be passed through the input transistors 1 and 2 is small, the reliability can be improved by providing a difference in the number of stages in the configuration of the offset transistor.
In this way, it is possible to provide a low power consumption single phase signal level conversion circuit having high operation reliability with respect to transistor characteristic fluctuations and power supply voltage fluctuations and having high-speed response characteristics.

  Note that the channel width W and the channel length L of the input transistor and the load transistor are not limited to the sizes described in the present embodiment, and can be any one as long as the current capability described above can be obtained for each transistor. Any size is acceptable.

(Embodiment 2)
FIG. 7 is a circuit diagram showing a circuit configuration of a signal level conversion circuit according to the second embodiment of the present invention.

  The signal level conversion circuit of the embodiment shown in the figure is different from the signal level conversion circuit of the embodiment shown in FIG. 2 only in that the bias voltage VREF19 is replaced with the GND potential, and the other configurations and operations are the same. The same components are denoted by the same reference numerals.

  As already described, even if the bias voltage VREF19 is replaced with the GND potential, the current capability of the input transistors 1 and 2 is increased or decreased, so that a highly reliable and high-speed level conversion operation can be obtained.

  In this way, a low power consumption single-phase signal level conversion circuit that has high operation reliability with respect to transistor characteristic fluctuations and power supply voltage fluctuations and high-speed response characteristics without requiring a fixed bias power supply VREF. Could be provided.

(Embodiment 3)
FIG. 8 is a circuit diagram showing a circuit configuration of a signal level conversion circuit according to the second embodiment of the present invention.

  The signal level conversion circuit of the embodiment shown in the figure is the same as the signal level conversion circuit of the embodiment shown in FIG. 2 except that the second bias voltage VREF ′ 19a is applied to the sources of the first input transistor 1 and the offset transistor 18, respectively. The other components and operations are the same, and the same components are denoted by the same reference numerals.

Thus, when the high level input signal 9 is applied to the source of the N-channel transistor 17 and the source of the second input transistor, it is applied between the source and gate of the first input transistor 1 as described above. The voltage Von is expressed by the following formula.
Von = VIH + Va-VREF '
Therefore, by setting VREF ′ so that the voltage Von is larger than the threshold voltage of the first input transistor 1, the load transistor 21 can be turned on and the load transistor 20 can be turned off as described above.
On the other hand, a voltage signal of 2Va + VREF ′ is generated at the drain of the offset transistor 18 to which the bias voltage VREF ′ is applied. Therefore, when the high level input signal 9 is applied, the voltage Voff applied between the source and gate of the second input transistor 2 is expressed by the following equation.
Voff = 2Va + VREF'- VIH
Therefore, the second input transistor 2 can be turned off by setting VREF ′ so that the voltage Voff becomes smaller than the threshold voltage of the second input transistor 2.

  Thus, by setting not only the bias voltage VREF but also the bias voltage VREF ′, a level conversion circuit with high operation reliability can be provided as in the above-described embodiment.

(Embodiment 4)
Next, with reference to FIG. 9, an active matrix type liquid crystal display device using the signal level conversion circuit of each embodiment described above will be described.

  An active matrix type liquid crystal display device 901 shown in FIG. 9 is, for example, a flat panel type liquid crystal display device, and is configured by an integrated circuit using thin film transistors. The signal level conversion circuit 911 of each of the above-described embodiments is used. Built-in.

  The controller 902 is composed of a CMOS gate array, for example, and controls the liquid crystal display device 901. A control signal 912 having a low signal amplitude of, for example, 1 V from the controller 902 is input as the input signal 9 to the signal level conversion circuit 911 built in the liquid crystal display device 901, and the output signal is output from the signal level conversion circuit 911. 14 is converted into a control signal 913 having a high signal amplitude of about 5 V, for example. The control signal 913 having the high signal amplitude is supplied to the source driving circuit 909 and the gate driving circuit 910.

  A plurality of parallel gate lines g1, g2, g3,... Gn output from the gate driving circuit 910 and a plurality of parallel source lines s1 output from the source driving circuit 909 and intersecting the gate lines. , S2, s3,... Sm is provided with a thin film transistor 903 having a gate connected to the gate line and a source connected to the source line. A pixel portion including a storage capacitor 904 connected to one electrode and a liquid crystal capacitor 905 connected in parallel to the storage capacitor 904 is provided at the drain of the thin film transistor 903. Each counter electrode of the storage capacitor 904 and the liquid crystal capacitor 905 is connected to the common electrode line 908.

  The gate drive circuit 910 and the source drive circuit 909 are supplied with the control signal converted to a high signal amplitude of, for example, about 5 V from the signal level conversion circuit 911 as described above. The gate drive circuit 910 sequentially scans each gate line in accordance with the control signal, and the source drive circuit 909 performs video via the source line for each pixel portion specified by the gate line selected by the gate drive circuit 910. Input the signal. Thereby, an image is displayed.

  As described above, by incorporating the signal level conversion circuit in the active matrix type liquid crystal display device 901 using thin film transistors, it is possible to directly control using a small signal from, for example, a CMOSIC gate array. As a result, a liquid crystal display device corresponding to a high-speed interface signal can be realized, and high-resolution video and video expression in accordance with a standard with a high operating frequency can be realized.

  Further, by mounting the signal level conversion circuit of the present invention, the amplitude of the interface signal can be made lower than the threshold voltage of a transistor formed in the liquid crystal display device 901. And unnecessary radiation (EMI) noise can be reduced.

  In the above configuration, a liquid crystal display device using a thin film transistor and a signal level conversion circuit can be formed by the same manufacturing process, and a general low power supply voltage CMOS circuit is used without using a special interface element. Enables fast and direct interface with.

  In the above configuration, in the case where the driving circuit of the liquid crystal display device is formed on the same glass substrate using the same manufacturing process for forming the switching element composed of the thin film transistor for driving the pixel, the signal level conversion circuit is formed with a small number of transistors. The frame around the display unit of the liquid crystal display device can be reduced. In addition, the number of control signal lines for driving the liquid crystal display device can be reduced, the device can be mounted in a compact manner, and the material cost and the price related to the mounting can be suppressed.

  In addition, although the example of the liquid crystal display device was given here, the same interface circuit can be applied to the EL display device, and an EL display device having the same effect as the liquid crystal display device described above is realized. Can do.

(Embodiment 5)
Next, a semiconductor memory device using the signal level conversion circuit of each embodiment described above will be described with reference to FIG.

  FIG. 10 is a schematic diagram showing a memory data read circuit. The read circuit is provided with a memory cell array 51, a word line 52, a selector circuit 53, and a sense amplifier 54. The bit line 56 is provided to connect the sense amplifier 54 and the selector circuit 53, respectively. The bit line 57 collectively indicates a plurality of bit lines extending from the memory cell array 51.

  Next, the operation will be described. The word line 52 to which the memory cell to be detected is connected is set to the “H” level, and the bit line 57 and the bit line 56 to which the memory cell to be detected is connected by the selector circuit 53. Redistribution of the charge on the bit line is performed based on the charge of the memory cell.

The sense amplifier circuit 54 is a circuit for amplifying the voltage read from the memory cell array 51 to the bit line 56. The voltage read to the bit line 56 is as small as several hundred mV. In order to determine the logical data of the memory cell to be detected, that is, “0” or “1”, it is necessary to amplify this voltage to a level at which it can be handled as a digital level.
In the fifth embodiment of the present invention, the signal level conversion circuit of each embodiment described above is used as the sense amplifier circuit 54.

  In this way, a binary logic state (“0”, “1”) signal with a minute amplitude that does not reach the threshold value of the transistor can be read out by converting the signal to a level capable of driving the transistor. Flash memory that can reduce power consumption, and can be reduced in chip size with a simple circuit configuration, is low cost, and has high operation reliability regardless of variations in transistor characteristics due to process variations. Alternatively, a ferroelectric memory can be provided.

  The plurality of memory cells described above can be a flash memory cell including a field effect transistor having a floating gate, or a ferroelectric memory cell including a ferroelectric capacitor and a switching transistor.

[Effect of the embodiment]
According to the above-described embodiment, the first and second drive transistors and the first and second offset transistors constituting the signal level conversion circuit are configured by transistors of the same polarity channel formed by the same manufacturing process. Therefore, when the threshold value of the driving transistor is large, the offset amount of the signal for controlling the driving transistor automatically increases according to the threshold value, and when the threshold value of the driving transistor is small, the signal for controlling the driving transistor. The offset amount is automatically reduced according to the threshold value. For this reason, it is possible to provide a high-speed response signal level conversion circuit that does not depend on fluctuations in the threshold value variation of the transistors and has high operation reliability even with respect to fluctuations in the power supply voltage.

  According to the above-described embodiment, the amount of current supplied from the current source to the offset transistor fluctuates in conjunction with fluctuations in the logic level of the input signal, so that the offset voltage Va superimposed on the input signal is automatically varied. When the drive transistor is turned on, the offset amount is increased, and the transistor is turned on more. When the drive transistor is turned off, the offset amount is reduced, and the transistor is turned off. As a result, the ratio of the on-state current to the off-state current of the drive transistor can be increased, the operation is fast, and high operation reliability can be ensured even with respect to transistor characteristic fluctuations and power supply voltage fluctuations. it can.

  According to the above-described embodiment, the first offset transistor has n N-channel transistors whose drains are connected to the gates, and these n N-channel transistors are connected in n stages in cascade. The second offset transistor has m N-channel transistors whose drains are connected to the gate, and these m N-channel transistors are connected in m stages in cascade. Thus, the second offset transistor is configured. The cascaded m-stage N-channel transistor constituting the second offset transistor has a larger number of stages than the cascaded n-stage N-channel transistor constituting the first offset transistor, that is, n <m. Thereby, the offset amount of the first offset transistor can be made larger than the offset amount of the first offset transistor when the input signal is at a low level, and it does not depend on fluctuations in threshold variation of the transistor, Further, it is possible to provide a signal level conversion circuit with high operation reliability against fluctuations in power supply voltage.

  According to the above-described embodiment, the channel length of the second current source transistor is made smaller than the channel length of the transistors constituting the circuit unit to which the high amplitude signal is applied. Since the threshold value of the transistor depends on the channel length, the threshold value of the current source transistor can be reduced, and by controlling the current more sensitively according to the logic state of the low amplitude input signal, the control signal of the driving transistor can be An offset linked to the input signal can be more effectively performed.

  According to the above-described embodiment, the channel length of the first offset transistor and the channel length of the second offset transistor are smaller than the channel length of the transistors constituting the circuit unit to which the high amplitude signal is applied. is doing. Since the threshold value of the transistor depends on the channel length, it is possible to suppress the offset amount from becoming too large due to variations in the transistor threshold value by reducing the threshold value of the offset transistor.

  According to the above-described embodiment, the liquid crystal display device or the EL display device is configured using the signal level conversion circuit. Therefore, the interface signal amplitude can be set to a low amplitude that does not reach the threshold value of the transistor. In addition, since it is not necessary to invert the input signal, the number of signal lines can be reduced, the costs associated with components and mounting can be reduced, and the frame area around the display portion can be reduced. In addition, a liquid crystal display device or an EL display device having high operation reliability and high-speed response characteristics regardless of transistor characteristic fluctuations due to process variations, etc., low power consumption, and reduced unnecessary radiation (EMI) noise Can provide.

  According to the above-described embodiment, the flash memory or the ferroelectric memory is configured by using the signal level conversion circuit as a sense amplifier. Therefore, a binary logic state (“0”, Since the “1”) signal can be read out by converting the signal to a level capable of driving the transistor, power consumption can be reduced. Further, it is possible to provide a flash memory or a ferroelectric memory that is low in cost because a chip size can be reduced with a simple circuit configuration and that has high operation reliability regardless of transistor characteristics variation due to process variations. Can do.

  In the above-described embodiment, the first and second offset transistors are used as the offset means. However, the present invention is not limited to this embodiment, and a diode may be used.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

It is a circuit diagram which shows the structure of the signal level conversion circuit concerning (Embodiment 1) of this invention. It is a circuit diagram which shows the structure of the signal level conversion circuit concerning (Embodiment 1) of this invention. It is explanatory drawing of the offset bias concerning (Embodiment 1) of this invention. It is explanatory drawing of the offset bias concerning (Embodiment 1) of this invention. It is explanatory drawing of the offset bias concerning (Embodiment 1) of this invention. It is a wave form diagram which shows the signal waveform of each part of the signal level conversion circuit concerning (Embodiment 1) of this invention. It is a circuit diagram which shows the structure of the signal level conversion circuit concerning (Embodiment 2) of this invention. FIG. 6 is a circuit diagram showing a configuration of a signal level conversion circuit according to (Embodiment 3) of the present invention. 1 is a block diagram showing a circuit configuration of an active matrix type liquid crystal display device using a signal level conversion circuit of the present invention. 1 is a block diagram showing a circuit configuration of a semiconductor memory device using a signal level conversion circuit of the present invention. It is a circuit diagram which shows the structure of the conventional 2 phase input signal level conversion circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... 1st input transistor, 2 ... 2nd input transistor, 20, 21 ... Load transistor, 15, 16 ... Current source transistor, 17, 18 ... N channel transistor (diode), 9 ... Input signal, 14 ... Output Signal, VREF: bias voltage, VREF ′: bias voltage, 41: signal waveform of single-phase input signal, 343: signal waveform of biasing single-phase input signal, 345: signal waveform of output signal in single-phase input level conversion circuit, 901: Liquid crystal display device, 903: Thin film transistor, 904: Storage capacitor, 905 ... Liquid crystal capacitor, 909 ... Source drive circuit, 910 ... Gate drive circuit, 911 ... Signal level conversion circuit, 51 ... Memory cell array, 52 ... Word line, 53 ... Selector circuit 54 ... Sense amplifier circuit 56 ... Connect sense amplifier and selector circuit Bit lines provided so as, a plurality of bit lines extending from 57 ... memory cell array blocks.

Claims (5)

First and second input transistors for converting a low-amplitude input signal into a high-amplitude output signal, the transistors having the same polarity channel;
A transistor having the same polarity channel as the first input transistor and the second input transistor, connected to a first current source for supplying current, and adding a first offset voltage to the input signal to A first offset transistor applied to the gate of one input transistor;
A transistor having the same polarity channel as the first input transistor and the second input transistor, and is connected to a second current source that supplies current, and a second bias voltage that is superimposed on the input signal is A second offset transistor that applies the offset voltage and applies to the gate of the second input transistor ,
The first offset transistor has n N-channel transistors whose drains are connected to the gate, and the n N-channel transistors are connected in cascade in n stages to constitute the first offset transistor. And
The second offset transistor has m N-channel transistors whose drains are connected to the gate, and these m N-channel transistors are connected in m stages to form the second offset transistor. And
The cascaded m-stage N-channel transistor constituting the second offset transistor has a larger number of stages than the cascaded n-stage N-channel transistor constituting the first offset transistor, that is, n <m. Signal level conversion circuit. 2. The signal level conversion circuit according to claim 1 , wherein a channel length of the second current source transistor is smaller than a channel length of a transistor constituting a circuit unit to which a high amplitude signal is applied. The channel length of the first offset transistor and the channel length of the second offset transistor, according to claim 1 or, characterized in smaller than the channel length of the transistor constituting the circuit portion high amplitude signal is applied 3. The signal level conversion circuit according to 2. Signal level conversion circuit according to any one of claims 1 to 3, wherein the first bias voltage is a ground potential. The first bias voltage and the second bias voltage signal level conversion circuit according to any one of claims 1 to 3, characterized in that a ground potential.

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