CN116886087B

CN116886087B - Switching circuit for reducing load radiation

Info

Publication number: CN116886087B
Application number: CN202310953215.4A
Authority: CN
Inventors: 杨宇
Original assignee: Gl Microelectronics Inc
Current assignee: Gl Microelectronics Inc
Priority date: 2023-07-31
Filing date: 2023-07-31
Publication date: 2024-02-02
Anticipated expiration: 2043-07-31
Also published as: CN116886087A

Abstract

The present specification provides a switching circuit for reducing load radiation, comprising: the driving circuit, the first switching tube and the second switching tube, wherein the size of the second switching tube is larger than that of the first switching tube; the first switching tube, the second switching tube, the energy supply signal and the load form a power consumption loop; the input end of the driving circuit is connected with the control signal, the first output end of the driving circuit is connected with the grid electrode of the first switching tube, and the second output end of the driving circuit is connected with the second switching tube; the driving circuit is used for sequentially starting the first switching tube and the second switching tube when receiving a control signal with a rising edge, so that the power consumption loop is started, the starting time of a load can be prolonged through the small-sized first switching tube, the ratio between the voltage and current variable quantity at two ends of the load and the conducting time variable quantity is reduced, radiation generated by the load is reduced, the power loss during conducting can be reduced through the second switching tube, and the balance of electromagnetic radiation and power loss is realized.

Description

Switching circuit for reducing load radiation

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a switching circuit for reducing load radiation.

Background

With the rapid development of electronic Power, power field effect transistors (Power MOSFETs), which are called Power switching transistors for short, are widely used in high-performance switching Power supplies, chopper Power supplies, motor drives, and class d circuits. As shown in fig. 1, in the conventional circuit system, a single power type switching tube is driven by a driving circuit, so as to control the change of load current, thereby achieving the purposes of controlling a high-voltage large-current signal by using a low-voltage signal and controlling a strong electric signal by using a weak electric signal. However, since the switching tube of this type is usually connected to a high-voltage high-current signal, the current flowing through the load at the moment of switching on or off of the single power switching tube is significantly changed, which will cause larger electromagnetic radiation interference and surge current, endangering the safety and reliability of the system, and then the switching tube of smaller size can reduce electromagnetic radiation generated when being switched on, but larger power loss is generated when the switching tube of smaller size is continuously switched on, and serious heat is generated, so that a switching circuit is needed, which reduces the electromagnetic radiation of the load at the moment of switching on, and can reduce the power loss after switching on.

Disclosure of Invention

The present disclosure provides a switching circuit for reducing load radiation, so as to solve the problem that the switching circuit in the prior art cannot balance electromagnetic radiation and power loss.

In order to solve the technical problems, the specific technical scheme in the specification is as follows:

in one aspect, the present specification provides a switching circuit for reducing load radiation, comprising:

the device comprises a driving circuit, a first switching tube and a second switching tube, wherein the size of the second switching tube is larger than that of the first switching tube;

the first switching tube, the second switching tube, the energy supply signal and the load form a power consumption loop;

the input end of the driving circuit is connected with a control signal, the first output end of the driving circuit is connected with the grid electrode of the first switching tube, and the second output end of the driving circuit is connected with the second switching tube;

the driving circuit is used for sequentially starting the first switching tube and the second switching tube when receiving a control signal with a rising edge, so that the power consumption loop is started.

As an embodiment of the present disclosure, the drains of the first switching tube and the second switching tube each receive the energy supply signal, the sources of the first switching tube and the second switching tube are both connected to the input end of the load, and the output end of the load is grounded.

As an embodiment of the present disclosure, the input end of the load receives the energy supply signal, the drains of the first switching tube and the second switching tube are connected to the output end of the load, and the sources of the first switching tube and the second switching tube are grounded.

As one embodiment of the present specification, the driving circuit includes a buffer sub-circuit, an impedance sub-circuit, and a rising edge delay circuit;

the buffer sub-circuit is used for receiving the control signal, amplifying the control signal and then sending the control signal to the impedance sub-circuit;

the impedance subcircuit comprises a first branch and a second branch, wherein the output end of the first branch is connected with the grid electrode of the first switching tube, and the output end of the second branch is connected with the grid electrode of the second switching tube;

the rising edge delay circuit is used for sampling the control signal, and when the control signal has the rising edge, a first switch signal is generated to the first branch so as to reduce the impedance of the first branch.

As one embodiment of the present specification, the buffer sub-circuit includes a first inverter and a second inverter;

the input end of the first inverter receives the control signal and is connected with the input end of the rising edge delay circuit, and the output end of the first inverter is connected with the input end of the second inverter;

the output end of the second inverter is connected with the impedance sub-circuit.

As one embodiment of the present specification, the impedance sub-circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a first switch;

The first resistor, the second resistor and the first switch form the first branch; the third resistor and the fourth resistor form the second branch;

the first resistor and the third resistor are electrically connected to the output end of the second inverter; the first resistor is connected with the second resistor in series, and is connected with a third resistor and a fourth resistor which are connected in series in parallel; the first switch is connected in parallel with the first resistor, the second resistor is electrically connected with the grid electrode of the second switching tube, and the fourth resistor is electrically connected with the grid electrode of the second switching tube;

after the first switch receives the first switch signal, the first resistor is short-circuited so that the impedance of the first branch circuit is reduced.

As one embodiment of the present specification, the rising edge delay circuit includes a rising edge delay sub-circuit, a first inverting sub-circuit, and an and logic circuit;

the rising edge delay sub-circuit is used for receiving the control signal, sampling the rising edge of the control signal, and generating a first signal after delaying the rising edge by a fixed time;

the first reverse sub-circuit receives the first signal and generates a reverse first signal after inverting the first signal;

And the AND logic circuit receives and performs AND operation on the reverse first signal and the control signal and outputs the first switch signal.

As one embodiment of the present disclosure, the rising edge delay sub-circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a fifth resistor, a first capacitor, and a first schmitt trigger;

the sources of the first PMOS tube and the second PMOS tube receive high-level signals;

the sources of the first NMOS tube and the second NMOS tube are grounded;

the gates of the first PMOS tube and the first NMOS tube both receive the control signal, and the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube through the fifth resistor;

the first capacitor is electrically connected between the drain electrode of the first PMOS tube and the ground;

the input end of the first Schmitt trigger is electrically connected with the drain electrode of the first PMOS tube, and the output end of the first Schmitt trigger is respectively connected with the grid electrode of the second PMOS tube and the grid electrode of the second NMOS tube;

the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the second PMOS tube outputs the first signal.

As an embodiment of the present disclosure, the first inverting subcircuit includes a third PMOS transistor and a third NMOS transistor;

the source electrode of the third PMOS tube receives a high-level signal, and the source electrode of the third NMOS tube is grounded;

the gates of the third PMOS tube and the third NMOS tube both receive the first signal, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the third PMOS tube outputs the reverse first signal.

As an embodiment of the present disclosure, the and logic circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;

the sources of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube all receive high-level signals, and the sources of the fifth NMOS tube and the sixth NMOS tube are all grounded;

the gates of the fourth PMOS tube and the fifth NMOS tube respectively receive the reverse first signal, and the drain electrode of the fourth PMOS tube is respectively connected with the drain electrode of the fifth PMOS tube, the drain electrode of the fourth NMOS tube, the gate electrode of the sixth PMOS tube and the gate electrode of the sixth NMOS tube;

the grid electrode of the fifth PMOS tube and the grid electrode of the fourth NMOS tube both receive the control signal, and the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube;

The drain electrode of the sixth PMOS tube is connected with the drain electrode of the sixth NMOS tube, and the drain electrode of the sixth PMOS tube outputs the first switching signal.

As one embodiment of the present disclosure, the driving circuit is further configured to sequentially turn off the second switching tube and the first switching tube when receiving a control signal having a falling edge, and further includes a falling edge delay circuit and a second switch;

the falling edge delay circuit is used for sampling the control signal, and when the control signal has a falling edge, a second switching signal is generated to the second branch;

and the second switch is connected with the fourth resistor in parallel, and after receiving the second switch signal, the second switch short-circuits the fourth resistor so as to reduce the impedance of the second branch.

As one embodiment of the present specification, a falling edge delay sub-circuit, a second inverting sub-circuit, and a nor logic circuit are included;

the falling edge delay sub-circuit receives the control signal, samples the falling edge of the control signal, delays the falling edge by a fixed time and generates a second signal;

the second inverting sub-circuit receives the second signal and inverts the second signal to generate an inverted second signal;

And the NOR logic circuit receives and outputs the second switch signal after performing NOR operation on the inverted second signal and the control signal.

As one embodiment of the present disclosure, the falling edge delay subcircuit includes a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a sixth resistor, a second capacitor, and a second schmitt trigger;

the sources of the seventh PMOS tube and the eighth PMOS tube all receive high-level signals;

the sources of the seventh NMOS tube and the eighth NMOS tube are all grounded;

the gates of the seventh PMOS tube and the seventh NMOS tube both receive the control signal, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the seventh NMOS tube through the sixth resistor; the second capacitor is electrically connected between the drain electrode of the seventh NMOS tube and the high-level signal;

the input end of the second schmitt trigger is connected with the drain electrode of the seventh NMOS tube, the output end of the second schmitt trigger is respectively connected with the grid electrode of the eighth PMOS tube and the grid electrode of the eighth NMOS tube, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the eighth NMOS tube, and the drain electrode of the eighth NMOS tube outputs the second signal.

As an embodiment of the present disclosure, the second inverting subcircuit includes a ninth PMOS transistor and a ninth NMOS transistor;

the source electrode of the ninth PMOS tube receives a high-level signal, and the source electrode of the ninth NMOS tube is grounded;

the gates of the ninth PMOS tube and the ninth NMOS tube both receive the second signal, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube, and the drain electrode of the ninth PMOS tube outputs the reverse second signal.

As an embodiment of the present disclosure, the nor logic circuit includes a tenth PMOS transistor, an eleventh PMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor;

the source electrode of the tenth PMOS tube receives a high-level signal, and the source electrodes of the tenth NMOS tube and the eleventh NMOS tube are grounded;

the grid electrode of the tenth PMOS tube and the grid electrode of the tenth NMOS tube both receive the control signal, and the drain electrode of the tenth PMOS tube is connected with the source electrode of the eleventh PMOS tube;

the grid electrode of the eleventh PMOS tube and the grid electrode of the eleventh NMOS tube are respectively connected with the drain electrode of the tenth NMOS tube and the drain electrode of the eleventh NMOS tube, and the drain electrode of the eleventh PMOS tube is respectively connected with the drain electrode of the eleventh NMOS tube;

And the drain electrode of the eleventh PMOS tube outputs the second switching signal.

As one embodiment of the present specification, the driving circuit is configured to sequentially turn on the first switching tube and the second switching tube when receiving a control signal having a rising edge, and sequentially turn off the second switching tube and the first switching tube when receiving a control signal having a falling edge;

the driving circuit comprises a third inverter, a twelfth PMOS tube, a thirteenth PMOS tube, a twelfth NMOS tube and a thirteenth NMOS tube;

the source electrode of the twelfth PMOS tube is connected with the first current source, the source electrode of the thirteenth PMOS tube is connected with the second current source, the source electrode of the twelfth NMOS tube is connected with the third current source, and the source electrode of the thirteenth NMOS tube is connected with the fourth current source;

the current of the second current source is larger than the current of the first current source, and the current of the third current source is larger than the current of the fourth current source;

the input end of the third inverter receives the control signal, and the output end of the third inverter is respectively connected with the gates of the twelfth PMOS tube, the twelfth NMOS tube, the thirteenth PMOS tube and the thirteenth NMOS tube;

The drain electrode of the twelfth PMOS tube is respectively connected with the drain electrode of the twelfth NMOS tube and the grid electrode of the first switch tube;

the drain electrode of the thirteenth PMOS tube is respectively connected with the drain electrode of the thirteenth NMOS tube and the grid electrode of the second switch tube.

By adopting the technical scheme, the starting time of the load can be prolonged through the first switching tube with small size, the ratio between the voltage and current variation at two ends of the load and the conduction time variation is reduced, the radiation generated by the load is reduced, after the load is conducted, the first switching tube is connected with the second switching tube with larger size in parallel, the power loss during conduction can be reduced, and the balance of electromagnetic radiation and power loss is realized.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present description, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 shows a prior art schematic diagram of an embodiment of the present description;

FIG. 2 shows a schematic diagram of a switching circuit for reducing load radiation in an embodiment of the present disclosure;

FIG. 3 shows a first schematic diagram of a drive circuit according to an embodiment of the present disclosure;

FIG. 4 shows a rising edge delay circuit schematic diagram of an embodiment of the present disclosure;

FIG. 5 shows a rising edge delay circuit waveform diagram of an embodiment of the present disclosure;

FIG. 6 shows a second schematic diagram of a drive circuit of an embodiment of the present disclosure;

FIG. 7 shows a falling edge delay circuit schematic diagram of an embodiment of the present disclosure;

FIG. 8 shows a falling edge delay circuit waveform diagram of an embodiment of the present disclosure;

FIG. 9 shows a schematic diagram of another implementation of the drive circuit of the present description embodiment;

FIG. 10 is a schematic diagram showing the connection relationship between the first load and the switch circuit according to the embodiment of the present disclosure;

fig. 11 is a schematic diagram showing a connection relationship between the second load and the switching circuit according to the embodiment of the present disclosure. Description of the drawings:

1. a driving circuit;

2. a first switching tube;

3. a second switching tube;

4. a buffer sub-circuit;

5. an impedance sub-circuit;

6. a rising edge delay circuit;

601. a rising edge delay sub-circuit;

602. a first inverting subcircuit;

603. And logic circuitry;

7. a falling edge delay circuit;

701. a falling edge delay sub-circuit;

702. a second inverting subcircuit;

703. nor logic circuitry;

11. a first PMOS tube;

12. a second PMOS tube;

13. a third PMOS tube;

14. a fourth PMOS tube;

15. a fifth PMOS tube;

16. a sixth PMOS tube;

17. a seventh PMOS transistor;

18. an eighth PMOS tube;

19. a ninth PMOS transistor;

110. a tenth PMOS tube;

111. an eleventh PMOS tube;

112. a twelfth PMOS tube;

113. thirteenth PMOS transistor;

21. a first NMOS tube;

22. a second NMOS tube;

23. a third NMOS tube;

24. a fourth NMOS tube;

25. a fifth NMOS tube;

26. a sixth NMOS tube;

27. a seventh NMOS tube;

28. an eighth NMOS tube;

29. a ninth NMOS transistor;

210. a tenth NMOS tube;

211. an eleventh NMOS transistor;

212. a twelfth NMOS transistor;

213. a thirteenth NMOS transistor;

31. a first resistor;

32. a second resistor;

33. a third resistor;

34. a fourth resistor;

35. a fifth resistor;

36. a sixth resistor;

41. a first inverter;

42. a second inverter;

43. a third inverter;

51. a first capacitor;

52. a second capacitor;

61. a first switch;

62. a second switch;

71. A first schmitt trigger;

72. a second schmitt trigger.

Detailed Description

The technical solutions of the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is apparent that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.

It should be noted that the terms "first," "second," and the like in the description and the claims, and in the foregoing figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the present description described herein may be capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or device.

The prior art schematic diagram shown IN fig. 1 comprises a driving circuit and switching tubes N0 and VD are high-voltage power supply, IN is a control signal, IN the actual use process, VS is connected with the power input end of the load, the other end of the load is grounded, when the control signal is high level, the driving circuit is enabled to send a high-level signal to conduct the switching tubes, at the moment, the potential at the VS is gradually equal to VD, the transition speed of the potential at the VS and the I of the switching tubes _ds Correlation (I) _ds Is a switchDrain-source current of tube), I _ds Usually related to the size of the switching tube, I when the switching tube is large in size _ds Larger, when the size of the switching tube is smaller, its I _ds Smaller. In this process, a parasitic capacitance can be equivalently applied between the power input terminal of the load and the ground, and when VS charges the parasitic capacitance, the load is started. According to formula I _ds t=cv, where C is the parasitic capacitance at both ends of the load, V is the turn-on voltage of the load, and I is known _ds Inversely proportional to t, it is known from the electromagnetic radiation formula that the magnitude of electromagnetic radiation is positively correlated with DeltaV/Deltat, since DeltaV eventually needs to reach VD in the ideal case, deltaV can be equivalent to a constant, deltaT is consistent with t, and when Deltat is smaller, the larger the electromagnetic radiation, the larger the Deltat, the smaller the electromagnetic radiation. It can be seen that I can be reduced in order to achieve the effect of reducing electromagnetic radiation _ds I.e. decreasing the size of the switching tube and increasing Δt.

However, the size of the switching tube also affects the heat generated after the circuit is conducted, and the smaller the size of the switching tube is, the more the heat generated after the circuit is conducted, the larger the size of the switching tube is, and the less the heat generated after the circuit is conducted. Therefore, in the prior art, electromagnetic radiation and heat cannot be balanced, and the reliability of a circuit is poor.

In order to balance electromagnetic radiation and heat, the specification uses a mode of opening the switching tube in a multi-stage mode, when a circuit is conducted, the switching tube with smaller size is used for extending the conduction time delta t, and after a load is opened, the switching tube with larger size is conducted again to reduce the heat.

A switching circuit schematic for reducing load radiation as shown in fig. 2, comprising:

a driving circuit 1, a first switching tube 2 and a second switching tube 3, wherein the size of the second switching tube 3 is larger than that of the first switching tube 2;

the first switching tube 2, the second switching tube 3, the energy supply signal and the load form a power consumption loop;

the input end of the driving circuit 1 is connected with a control signal, the first output end of the driving circuit 1 is connected with the grid electrode of the first switching tube 2, and the second output end of the driving circuit 1 is connected with the second switching tube 3;

The driving circuit 1 is configured to sequentially turn on the first switching tube 2 and the second switching tube 3 when receiving a control signal having a rising edge.

The on time of the load can be prolonged through the first switch tube 2 with small size, the ratio between the voltage and current variation at two ends of the load and the conduction time variation is reduced, the radiation generated by the load is reduced, after the load is conducted, the first switch tube 2 is connected in parallel with the second switch tube 3 with larger size, the power loss during conduction can be reduced, and the balance of electromagnetic radiation and power loss is realized.

Specifically, in the present specification, the size of the second switching tube 3 may be identical to that of the switching tube N0 in the prior art, and the second switching tube 3 is used to reduce power loss (heat loss) after the load is turned on.

As an embodiment of the present specification, the connection manner of the load and the switching circuit includes two types.

As shown in a schematic diagram of a connection relationship between a first load and a switching circuit in fig. 10, drains of the first switching tube and the second switching tube both receive the energy supply signal, sources of the first switching tube and the second switching tube are both connected with an input end of the load, and an output end of the load is grounded.

The connection relationship between the second load and the switching circuit is shown in fig. 11, the input end of the load receives the energy supply signal, the drains of the first switching tube and the second switching tube are connected with the output end of the load, and the sources of the first switching tube and the second switching tube are grounded.

A particular person skilled in the art may place a load in the switching circuit in any way to reduce the radiation induced when switching on or off.

As shown in a first schematic diagram of the driving circuit in fig. 3, as an embodiment of the present specification, the driving circuit 1 includes a buffer sub-circuit 4, an impedance sub-circuit 5, and a rising edge delay circuit 6;

the buffer sub-circuit 4 is configured to receive the control signal, amplify the control signal, and send the amplified control signal to the impedance sub-circuit 5;

the impedance sub-circuit 5 comprises a first branch and a second branch, the output end of the first branch is connected with the grid electrode of the first switching tube 2, and the output end of the second branch is connected with the grid electrode of the second switching tube 3;

the rising edge delay circuit 6 is configured to sample the control signal, and when the control signal generates the rising edge, generate a first switching signal to the first branch, so as to reduce impedance of the first branch.

The buffer sub-circuit 4 comprises a first inverter 41 and a second inverter 42;

the input end of the first inverter 41 receives the control signal and is connected with the input end of the rising edge delay circuit 6, and the output end of the first inverter 41 is connected with the input end of the second inverter 42;

the output of the second inverter 42 is connected to the impedance sub-circuit 5.

In the present specification, the first inverter 41 and the second inverter 42 are used as buffers to enhance the control capability of the control signal, and of course, those skilled in the art may add more even serial inverters to the buffer sub-circuit 4 according to the need, which is not limited in the present specification.

The impedance sub-circuit 5 comprises a first resistor 31, a second resistor 32, a third resistor 33, a fourth resistor 34 and a first switch 61;

the first resistor 31, the second resistor 32 and the first switch 61 form the first branch; the third resistor 33 and the fourth resistor 34 form the second branch;

the first resistor 31 and the third resistor 33 are electrically connected to the output end of the second inverter 42; the first resistor 31 is connected in series with the second resistor 32 and is connected in parallel with a third resistor 33 and a fourth resistor 34 which are connected in series; the first switch 61 is connected in parallel with the first resistor 31, the second resistor 32 is electrically connected to the gate of the second switching tube 3, and the fourth resistor 34 is electrically connected to the gate of the second switching tube 3;

After receiving the first switching signal, the first switch 61 shorts the first resistor 31 to reduce the first branch impedance.

In this specification, the first branch may be provided with a plurality of resistors connected in series, the resistance value of the second resistor 32 may be smaller than the sum of the third resistor 33 and the fourth resistor 34, when the first switch 61 connected in parallel to the first resistor 31 is turned off, the first resistor 31 is short-circuited, at this time, the resistance value of the second resistor 32 is smaller than the sum of the third resistor 33 and the fourth resistor 34, when the same voltage passes through the first branch and the second branch, the impedance of the first branch is smaller than the impedance of the second branch, and the current of the first branch is larger than the current of the second branch. And the first switching tube 2 is smaller in size than the second switching tube 3, the first switching tube 2 may be turned on preferentially, and then the second switching tube 3 is turned on again.

Specifically, as shown in the rising edge delay circuit schematic diagram in fig. 4, the rising edge delay circuit 6 includes a rising edge delay sub-circuit 601, a first inverting sub-circuit 602, and an and logic circuit 603;

the rising edge delay sub-circuit 601 is configured to receive the control signal, sample a rising edge of the control signal, delay the rising edge by a fixed time, and generate a first signal;

The first inverting sub-circuit 602 receives the first signal, inverts the first signal, and generates an inverted first signal;

the and logic circuit 603 receives and performs an and operation on the inverted first signal and the control signal, and outputs the first switching signal.

The rising edge delay subcircuit 601 comprises a first PMOS tube 11, a second PMOS tube 12, a first NMOS tube 21, a second NMOS tube 22, a fifth resistor 35, a first capacitor 51 and a first Schmitt trigger 71;

the sources of the first PMOS transistor 11 and the second PMOS transistor 12 both receive high-level signals;

the sources of the first NMOS tube 21 and the second NMOS tube 22 are grounded;

the gates of the first PMOS 11 and the first NMOS 21 receive the control signal, and the drain of the first PMOS 11 is electrically connected to the drain of the first NMOS 21 through the fifth resistor 35;

the first capacitor 51 is electrically connected between the drain of the first PMOS 11 and ground;

the input end of the first schmitt trigger 71 is electrically connected with the drain electrode of the first PMOS tube 11, and the output end of the first schmitt trigger 71 is respectively connected with the gate electrode of the second PMOS tube and the gate electrode of the second NMOS tube 22;

The drain electrode of the second PMOS transistor is connected to the drain electrode of the second NMOS transistor 22, and the drain electrode of the second PMOS transistor outputs the first signal.

The first inverting sub-circuit 602 includes a third PMOS transistor 13 and a third NMOS transistor 23;

the source electrode of the third PMOS transistor 13 receives a high level signal, and the source electrode of the third NMOS transistor 23 is grounded;

the gates of the third PMOS transistor 13 and the third NMOS transistor 23 both receive the first signal, the drain of the third PMOS transistor 13 is connected to the drain of the third NMOS transistor 23, and the drain of the third PMOS transistor 13 outputs the reverse first signal.

The AND logic circuit 603 comprises a fourth PMOS tube 14, a fifth PMOS tube 15, a sixth PMOS tube 16, a fourth NMOS tube 24, a fifth NMOS tube 25 and a sixth NMOS tube 26;

the sources of the fourth PMOS transistor 14, the fifth PMOS transistor 15 and the sixth PMOS transistor 16 all receive high-level signals, and the sources of the fifth NMOS transistor 25 and the sixth NMOS transistor 26 are all grounded;

the gates of the fourth PMOS transistor 14 and the fifth NMOS transistor 25 each receive the reverse first signal, and the drain of the fourth PMOS transistor 14 is connected to the drain of the fifth PMOS transistor 15, the drain of the fourth NMOS transistor 24, the gate of the sixth PMOS transistor 16, and the gate of the sixth NMOS transistor 26, respectively;

The gate of the fifth PMOS 15 and the gate of the fourth NMOS 24 both receive the control signal, and the source of the fourth NMOS 24 is connected to the drain of the fifth NMOS 25;

the drain electrode of the sixth PMOS transistor 16 is connected to the drain electrode of the sixth NMOS transistor 26, and the drain electrode of the sixth PMOS transistor 16 outputs the first switching signal.

As shown IN fig. 5, IN fig. 5 is a control signal, point a is a first signal, point B is an inverted first signal, and point OUT1 is a first switching signal. The rising edge time delay t corresponding to the control signal can be obtained through the fifth resistor and the first capacitor ₁ First signal, t, with falling edge not delayed ₁ R is the resistance of the fifth resistor, and C is the capacitance of the first capacitor. Corresponding waveform A

The first inverting sub-circuit 602 is obtained through the third PMOS transistor 13 and the third NMOS transistor 23, when the first signal is at a high level, the third NMOS transistor 23 is turned on, and outputs a low level signal, and when the first signal is at a low level, the third PMOS transistor 13 is turned on, and outputs a high level signal, and the corresponding waveform is a waveform of B.

Then, the and logic circuit 603 performs an and operation on the inverted first signal and the control signal, and outputs a first switching signal. The method comprises the following steps: when the reverse first signal is at a high level and the control signal is at a high level, the first switch signal is at a high level;

When the reverse first signal is at a high level and the control signal is at a low level, the first switch signal is at a low level;

when the reverse first signal is at a low level and the control signal is at a high level, the first switch signal is at a low level;

when the inverted first signal is low, the control signal is low, and the first switch signal is low. The corresponding waveform is the waveform of OUT 1. When the first switch signal is at a high level, the first switch is turned on, shorting the first resistor 31, so that the first switch tube 2 is turned on preferentially, and the second switch tube 3 is turned on subsequently.

On the other hand, as shown in fig. 2, when the driving circuit 1 turns off the switching tube, in order to prevent the ratio Δv/Δt from being too large due to too short turn-off time, it is necessary to keep the turn-off time longer so that the VS potential is not suddenly equal to ground, according to formula I _ds t=cv, see I _ds Is equal to tInversely proportional, it is known from the electromagnetic radiation formula that the magnitude of electromagnetic radiation is positively correlated with DeltaV/Deltat, since DeltaV eventually needs to reach 0 from VS under ideal conditions after switching off the switching tube, deltaV can be equivalently a constant, and when DeltaT is smaller, the larger the electromagnetic radiation, the larger the DeltaT, and the smaller the electromagnetic radiation. It can be seen that I can be reduced in order to achieve the effect of reducing electromagnetic radiation _ds I.e. decreasing the size of the switching tube and increasing Δt. Therefore, the second switching tube can be turned off before the first switching tube is turned off. Thus Δt can be made larger and electromagnetic radiation reduced compared to closing the first switching tube first.

In order to reduce electromagnetic radiation, the conduction time delta t is extended in a mode of closing the large-size switching tube firstly and then closing the small-size switching tube.

As shown in a second schematic diagram of the driving circuit in fig. 6, as an embodiment of the present disclosure, the driving circuit 1 is further configured to sequentially turn off the second switching tube 3 and the first switching tube 2 when receiving a control signal having a falling edge, and further includes a falling edge delay circuit 7 and a second switch 62;

the falling edge delay circuit 7 is configured to sample the control signal, and generate a second switching signal to the second branch when the control signal has a falling edge;

the second switch 62 is connected in parallel with the fourth resistor 34, and after the second switch 62 receives the second switch signal, the fourth resistor 34 is short-circuited, so that the impedance of the second branch is reduced.

As shown in fig. 7, the falling edge delay circuit 7 includes a falling edge delay sub-circuit 701, a second inverting sub-circuit 702, and a nor logic circuit 703;

The falling edge delay sub-circuit 701 receives the control signal, samples the falling edge of the control signal, delays the falling edge by a fixed time, and generates a second signal;

the second inverting sub-circuit 702 receives the second signal, inverts the second signal, and generates an inverted second signal;

the nor logic circuit 703 receives and performs a nor operation on the inverted second signal and the control signal, and outputs the second switching signal.

The falling edge delay sub-circuit 701 comprises a seventh PMOS transistor 17, an eighth PMOS transistor 18, a seventh NMOS transistor 27, an eighth NMOS transistor 28, a sixth resistor 36, a second capacitor 52, and a second schmitt trigger 72;

the sources of the seventh PMOS 17 and the eighth PMOS 18 each receive a high level signal;

the sources of the seventh NMOS transistor 27 and the eighth NMOS transistor 28 are all grounded;

the gates of the seventh PMOS 17 and the seventh NMOS 27 receive the control signal, and the drain of the seventh PMOS 17 is connected to the drain of the seventh NMOS 27 through the sixth resistor 36; the second capacitor 52 is electrically connected between the drain of the seventh NMOS transistor 27 and the high level signal;

The input end of the second schmitt trigger 72 is connected to the drain of the seventh NMOS transistor 27, the output end of the second schmitt trigger 72 is connected to the gate of the eighth PMOS transistor 18 and the gate of the eighth NMOS transistor 28, the drain of the eighth PMOS transistor 18 is connected to the drain of the eighth NMOS transistor 28, and the drain of the eighth NMOS transistor 28 outputs the second signal.

The second inverting sub-circuit 702 includes a ninth PMOS transistor 19 and a ninth NMOS transistor 29;

the source electrode of the ninth PMOS transistor 19 receives a high level signal, and the source electrode of the ninth NMOS transistor 29 is grounded;

the gates of the ninth PMOS transistor 19 and the ninth NMOS transistor 29 both receive the second signal, the drain of the ninth PMOS transistor 19 is connected to the drain of the ninth NMOS transistor 29, and the drain of the ninth PMOS transistor 19 outputs the inverted second signal.

The nor logic circuit 703 includes a tenth PMOS transistor 110, an eleventh PMOS transistor 111, a tenth NMOS transistor 210, and an eleventh NMOS transistor 211;

the source of the tenth PMOS 110 receives a high level signal, and the sources of the tenth NMOS 210 and the eleventh NMOS 211 are both grounded;

the gate of the tenth PMOS transistor 110 and the gate of the tenth NMOS transistor 210 both receive the control signal, and the drain of the tenth PMOS transistor 110 is connected to the source of the eleventh PMOS transistor 111;

The gate of the eleventh PMOS transistor 111 and the gate of the eleventh NMOS transistor 211 both receive the inverted second signal, and the drain of the eleventh PMOS transistor 111 is connected to the drain of the tenth NMOS transistor 210 and the drain of the eleventh NMOS transistor 211, respectively

The drain of the eleventh PMOS transistor 111 outputs the second switching signal.

As shown IN fig. 8, IN fig. 8 is a control signal, point C is a second signal, point D is an inverted second signal, and point OUT2 is a second switching signal. The falling edge delay t corresponding to the control signal can be obtained by the sixth resistor 36 and the second capacitor 52 ₂ A second signal with non-delayed rising edge, t ₂ R is the resistance of the sixth resistor 36, and C is the capacitance of the second capacitor 52. Corresponding waveform of C

The second inverting sub-circuit 702 is obtained through the ninth PMOS transistor 19 and the ninth NMOS transistor 29, when the second signal is at a high level, the ninth NMOS transistor 29 is turned on, and outputs a low level signal, and when the second signal is at a low level, the ninth PMOS transistor 19 is turned on, and outputs a high level signal, corresponding to a waveform of D.

Then, the and logic circuit 603 performs a nor operation on the inverted second signal and the control signal, and outputs a second switching signal. The method comprises the following steps: when the reverse second signal is at a high level and the control signal is at a high level, the second switch signal is at a low level;

When the reverse second signal is at a high level and the control signal is at a low level, the second switch signal is at a low level;

when the reverse second signal is at a low level and the control signal is at a high level, the second switch signal is at a low level;

when the inverted second signal is low, the control signal is low, and the second switching signal is high. The corresponding waveform is the waveform of OUT 2. When the second switch signal is at a high level, the second switch is turned on, shorting the third resistor 33, and thus the second switching tube 3 is turned off preferentially, and the first switching tube 2 is turned off subsequently.

As an example of the present specification, another embodiment of the driving circuit shown in fig. 9 is a schematic diagram, and the present specification also adopts another driving circuit 1 of different current intensity designs, which can perform front-back control between the first switching tube 2 and the second switching tube 3 according to a control signal,

the driving circuit 1 is configured to sequentially turn on the first switching tube 2 and the second switching tube 3 when receiving a control signal having a rising edge, and sequentially turn off the second switching tube 3 and the first switching tube 2 when receiving a control signal having a falling edge;

the driving circuit 1 includes a third inverter 43, a twelfth PMOS transistor 112, a thirteenth PMOS transistor 113, a twelfth NMOS transistor 212, and a thirteenth NMOS transistor 213;

The source of the twelfth PMOS 112 is connected to the first current source, the source of the thirteenth PMOS 113 is connected to the second current source, the source of the twelfth NMOS 212 is connected to the third current source, and the source of the thirteenth NMOS 213 is connected to the fourth current source;

the input end of the third inverter 43 receives the control signal, and the output end of the third inverter 43 is connected to the gates of the twelfth PMOS transistor 112, the twelfth NMOS transistor 212, the thirteenth PMOS transistor 113 and the thirteenth NMOS transistor 213, respectively;

the drain electrode of the twelfth PMOS 112 is connected to the drain electrode of the twelfth NMOS 212 and the gate electrode of the second switching transistor 3, respectively;

the drain electrode of the thirteenth PMOS transistor 113 is connected to the drain electrode of the thirteenth NMOS transistor 213 and the gate electrode of the first switching transistor 2, respectively.

In this specification, the current of the first current source is smaller than the current of the second current source, and the current of the third current source is much larger than the current of the fourth current source. When the control signal changes from low level to high level, the twelfth PMOS transistor 112 and the thirteenth PMOS transistor 113 are turned on, the second current source and the first current source charge the gate capacitors of the first switching transistor 2 and the second switching transistor 3, respectively, and since the size of the first switching transistor 2 is far smaller than the size of the second switching transistor 3 and the current of the second current source is larger than the current of the first current source, the gate voltage of the first switching transistor 2 reaches the threshold voltage first, the first switching transistor 2 is turned on first, and the second switching transistor 3 is turned on later. When the control signal is changed from high level to low level, the twelfth NMOS transistor 212 and the thirteenth NMOS transistor 213 are turned on, the gate capacitances of the first switching transistor 2 and the second switching transistor 3 are discharged through the fourth current source and the third current source, respectively, and the current of the third current source is far greater than the current of the fourth current source, so that the gate capacitance of the second switching transistor 3 is discharged at first, thereby controlling the second switching transistor 3 to be turned off first, and the first switching transistor 2 to be turned off later.

The problem of balancing the power loss caused by radiation and subsequent conducting circuits when the switching tube is started can be solved in the mode.

It should also be understood that, in the embodiments of the present specification, the term "and/or" is merely one association relationship describing the association object, meaning that three relationships may exist. For example, a and/or B may represent: a exists alone, A and B exist together, and B exists alone. In the present specification, the character "/" generally indicates that the front and rear related objects are an or relationship.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, or elements, or may be an electrical, mechanical, or other form of connection.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purposes of the embodiments of the present description.

In addition, each functional unit in each embodiment of the present specification may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The principles and embodiments of the present specification are explained in this specification using specific examples, the above examples being provided only to assist in understanding the method of the present specification and its core ideas; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope based on the ideas of the present specification, the present description should not be construed as limiting the present specification in view of the above.

Claims

1. A switching circuit for reducing load radiation, comprising:

the device comprises a driving circuit, a first switching tube and a second switching tube, wherein the size of the second switching tube is larger than that of the first switching tube, and the first switching tube and the second switching tube are connected between a potential VD and a potential VS in parallel;

the driving circuit is used for sequentially starting the first switching tube and the second switching tube when receiving a control signal with a rising edge, so that the power consumption loop is started; the driving circuit comprises a buffer sub-circuit, an impedance sub-circuit and a rising edge delay circuit;

The rising edge delay circuit is used for sampling the control signal, and when the control signal has a rising edge, a first switch signal is generated to the first branch so as to reduce the impedance of the first branch.

2. The switching circuit for reducing load radiation according to claim 1, wherein drains of the first switching tube and the second switching tube each receive the energy supply signal, sources of the first switching tube and the second switching tube are connected to an input terminal of the load, and an output terminal of the load is grounded.

3. The switching circuit for reducing load radiation according to claim 1, wherein the input terminal of the load receives the power supply signal, the drains of the first switching tube and the second switching tube are connected to the output terminal of the load, and the sources of the first switching tube and the second switching tube are grounded.

4. The load-radiation-reducing switching circuit of claim 1, wherein the buffer sub-circuit comprises a first inverter and a second inverter;

5. The load-radiation-reducing switching circuit of claim 4, wherein the impedance sub-circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, and a first switch;

the first resistor and the third resistor are electrically connected to the output end of the second inverter; the first resistor is connected with the second resistor in series, and is connected with a third resistor and a fourth resistor which are connected in series in parallel; the first switch is connected in parallel with the first resistor, the second resistor is electrically connected with the grid electrode of the first switching tube, and the fourth resistor is electrically connected with the grid electrode of the second switching tube;

6. The load radiation reduction switching circuit according to claim 1, wherein the rising edge delay circuit comprises a rising edge delay sub-circuit, a first inverting sub-circuit, and an and logic circuit;

7. The switch circuit for reducing load radiation according to claim 6, wherein the rising edge delay sub-circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a fifth resistor, a first capacitor, and a first schmitt trigger;

the sources of the first NMOS tube and the second NMOS tube are grounded;

8. The load-radiation-reducing switching circuit of claim 6, wherein the first inverting subcircuit comprises a third PMOS transistor and a third NMOS transistor;

9. The switch circuit for reducing load radiation according to claim 6, wherein the AND logic circuit comprises a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;

10. The switching circuit for reducing load radiation according to claim 5, wherein the driving circuit is further configured to sequentially turn off the second switching tube and the first switching tube when receiving a control signal having a falling edge, and further comprises a falling edge delay circuit and a second switch;

11. The load-radiation-reducing switching circuit of claim 10, comprising a falling edge delay sub-circuit, a second inverting sub-circuit, and a nor logic circuit;

12. The switch circuit for reducing load radiation according to claim 11, wherein the falling edge delay sub-circuit comprises a seventh PMOS transistor, an eighth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a sixth resistor, a second capacitor, and a second schmitt trigger;

the sources of the seventh NMOS tube and the eighth NMOS tube are all grounded;

13. The load-radiation-reducing switching circuit of claim 11, wherein the second inverting subcircuit comprises a ninth PMOS transistor and a ninth NMOS transistor;

14. The switch circuit for reducing load radiation according to claim 11, wherein the nor logic circuit comprises a tenth PMOS transistor, an eleventh PMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor;

15. A switching circuit for reducing load radiation, comprising:

The driving circuit is used for sequentially opening the first switching tube and the second switching tube when receiving a control signal with a rising edge, and also used for sequentially closing the second switching tube and the first switching tube when receiving a control signal with a falling edge, so that the power consumption loop is opened;

the source electrode of the twelfth PMOS tube is connected with a first current source, the source electrode of the thirteenth PMOS tube is connected with a second current source, the source electrode of the twelfth NMOS tube is connected with a third current source, and the source electrode of the thirteenth NMOS tube is connected with a fourth current source;

the drain electrode of the twelfth PMOS tube is respectively connected with the drain electrode of the twelfth NMOS tube and the grid electrode of the second switch tube;

The drain electrode of the thirteenth PMOS tube is respectively connected with the drain electrode of the thirteenth NMOS tube and the grid electrode of the first switch tube.