WO2021258888A1

WO2021258888A1 - Shift register, gate driving circuit, and display panel

Info

Publication number: WO2021258888A1
Application number: PCT/CN2021/093347
Authority: WO
Inventors: 谢勇贤; 王慧; 杨通; 邵贤杰; 马睿
Original assignee: 京东方科技集团股份有限公司; 合肥鑫晟光电科技有限公司
Priority date: 2020-06-24
Filing date: 2021-05-12
Publication date: 2021-12-30
Also published as: CN111768741A

Abstract

A shift register, a gate driving circuit, and a display panel. In the shift register, a forward input module (1) is used for providing a signal of a forward power supply voltage end (VNN) to a first node (PU) by means of a first transistor (M1) and a second transistor (M2) in sequence under the control of a forward input end; a reverse input module (2) is used for providing a signal of a reverse power supply voltage end (VBB) to the first node (PU) by means of a third transistor (M3) and a fourth transistor (M4) in sequence under the control of a reverse input end; an output module (4) is used for providing a signal of a clock signal end (CLK) to an output end under the control of the first node (PU), or providing a signal of a first reference signal end (VGL) to the output end under the control of a second node (PD); a node control module (3) is used for controlling potentials of the first node (PU) and the second node (PD) to be opposite; and a leakage prevention module (5) is used for transmitting the signal of the first reference signal end (VGL) to the position between the first transistor (M1) and the second transistor (M2) and the position between the third transistor (M3) and the fourth transistor (M4) respectively under the control of the clock signal end (CLK).

Description

Shift register, grid drive circuit and display panel

Cross-references to related applications

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office, the application number is 202010589629.X, and the application name is "a shift register, gate drive circuit and display panel" on June 24, 2020, all of which The content is incorporated in this application by reference.

Technical field

This application relates to the field of display technology, in particular to a shift register, a gate drive circuit and a display panel.

Background technique

With the rapid development of display technology, displays are increasingly developing towards high integration and low cost. Among them, GOA (Gate Driver on Array, array substrate row drive) technology integrates a TFT (Thin Film Transistor, thin film transistor) gate switch circuit on the array substrate of the display panel to form a scanning drive for the display panel, which can save The bonding area of the gate integrated circuit (IC, Integrated Circuit) and the wiring space of the fan-out area can not only reduce the product cost in terms of material cost and manufacturing process, but also make the display panel do To the aesthetic design with symmetrical sides and narrow borders; and, this integrated process can also eliminate the bonding process in the direction of the gate scan line, thereby improving productivity and yield.

A general gate driving circuit is composed of a plurality of cascaded shift registers, and the scanning signals are sequentially input to each row of gate lines on the display panel through the shift registers of various levels. However, in order to be able to check which row the defects of the gate drive circuit specifically appear in or to achieve image inversion without changing the data signal transmission sequence in the display panel, the gate drive circuit is required to be able to realize the function of reverse scanning.

Summary of the invention

The embodiments of the present application provide a shift register, a gate driving circuit, and a display panel. The specific solutions are as follows:

A shift register provided by an embodiment of the present application includes: a forward input module, a reverse input module, a node control module, an output module, and an anti-leakage module; wherein:

The forward input module includes: a first transistor and a second transistor; the forward input module is used to sequentially pass the signal of the forward power supply voltage terminal through the first transistor and the second transistor under the control of the forward input terminal. The transistor is provided to the first node;

The reverse input module includes: a third transistor and a fourth transistor; the reverse input module is used to sequentially pass the signal of the reverse power supply voltage terminal through the third transistor and the fourth transistor under the control of the reverse input terminal. A transistor is provided to the first node;

The output module is configured to provide the signal of the clock signal terminal to the output terminal under the control of the first node, or provide the signal of the first reference signal terminal to the output terminal under the control of the second node;

The node control module is used to control the electric potentials of the first node and the second node to be opposite;

The leakage prevention module is used to transmit the signal of the first reference signal terminal to between the first transistor and the second transistor and the third transistor and the first transistor under the control of the clock signal terminal. Between four transistors.

Optionally, in the embodiment of the present application, the leakage prevention module includes a fifth transistor and a sixth transistor; wherein:

The gate of the fifth transistor is connected to the clock signal terminal, the first electrode of the fifth transistor is connected to the first reference signal terminal, and the second electrode of the fifth transistor is connected to the first reference signal terminal. The second pole of the transistor is connected to the first pole of the second transistor;

The gate of the sixth transistor is connected to the clock signal terminal, the first electrode of the sixth transistor is connected to the first reference signal terminal, and the second electrode of the sixth transistor is connected to the third terminal respectively. The second pole of the transistor is connected to the first pole of the fourth transistor.

Optionally, in the embodiment of the present application, in the forward input module:

The gate of the first transistor is connected to the forward input terminal, the first electrode of the first transistor is connected to the forward power supply voltage terminal, and the second electrode of the first transistor is connected to the second The first pole of the transistor is connected;

The gate of the second transistor is connected to the forward input terminal, and the second electrode of the second transistor is connected to the first node.

Optionally, in the embodiment of the present application, in the reverse input module:

The gate of the third transistor is connected to the reverse input terminal, the first electrode of the third transistor is connected to the reverse power supply voltage terminal, and the second electrode of the third transistor is connected to the fourth The first pole of the transistor is connected;

The gate of the fourth transistor is connected to the reverse input terminal, and the second electrode of the fourth transistor is connected to the first node.

Optionally, in the embodiment of the present application, the output module includes: a seventh transistor, an eighth transistor, and a first capacitor; wherein:

The gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the clock signal terminal, and the second electrode of the seventh transistor is connected to the output terminal;

The gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is connected to the first reference signal terminal, and the second electrode of the eighth transistor is connected to the output terminal ；

The first pole of the first capacitor is connected to the first node, and the second pole of the first capacitor is connected to the output terminal.

Optionally, in the embodiment of the present application, the node control module includes: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; wherein:

The gate of the ninth transistor is connected to the second reference signal terminal, the first electrode of the ninth transistor is connected to the second reference signal terminal, and the second electrode of the ninth transistor is connected to the tenth transistor的Grid connection;

A first pole of the tenth transistor is connected to the second reference signal terminal, and a second pole of the tenth transistor is connected to the second node;

The gate of the eleventh transistor is connected to the first node, and the first electrode of the eleventh transistor is connected to the first reference signal terminal;

The gate of the twelfth transistor is connected to the first node, the first electrode of the twelfth transistor is connected to the first reference signal terminal, and the second electrode of the twelfth transistor is connected to the Second node connection;

The gate of the thirteenth transistor is connected to the second node, the first electrode of the thirteenth transistor is connected to the first reference signal terminal, and the second electrode of the thirteenth transistor is connected to the The first node is connected.

Optionally, in the embodiment of the present application, a reset module is further included;

The reset module is used to provide the signal of the first reference signal terminal to the output terminal under the control of the reset signal terminal.

Optionally, in the embodiment of the present application, the reset module includes a fourteenth transistor;

The gate of the fourteenth transistor is connected to the reset signal terminal, the first electrode of the fourteenth transistor is connected to the first reference signal terminal, and the second electrode of the fourteenth transistor is connected to the The output terminal is connected.

Correspondingly, an embodiment of the present application also provides a gate driving circuit, including a plurality of cascaded shift registers provided in the embodiments of the present application.

Correspondingly, an embodiment of the present application also provides a display panel, including the above-mentioned gate driving circuit provided by the embodiment of the present application.

Description of the drawings

Figure 1 is a schematic diagram of the structure of a shift register in the related art;

2 is a schematic structural diagram of a shift register provided by an embodiment of the application;

3 is a schematic structural diagram of another shift register provided by an embodiment of the application;

4 is a schematic structural diagram of yet another shift register provided by an embodiment of the application;

FIG. 5a is a timing diagram of the corresponding circuit when the shift register shown in FIG. 3 is scanned in the forward direction;

FIG. 5b is a timing diagram of the corresponding circuit of the shift register shown in FIG. 3 during reverse scanning;

Fig. 6a is a circuit timing diagram corresponding to the shift register shown in Fig. 4 during forward scanning;

Fig. 6b is a circuit timing diagram corresponding to the shift register shown in Fig. 4 during reverse scanning.

detailed description

Figure 1 shows the structure of a common shift register with bidirectional scanning function. During forward scanning, VNN is a high potential voltage. When transistor M1 is turned on, node PU is charged to a high potential. VBB is a low potential voltage. When M2 is turned on, the node PU is reset to a low potential, and then the node PU always maintains a low potential to ensure the stability of the shift register. However, during forward scanning, the voltage at the forward input terminal INPUT is a pulse signal, and the source and drain of transistor M1 are connected to VNN and node PU respectively, but after node PU is charged, the drain of transistor M1 still maintains a high voltage VNN for a long time. At this time, the transistor M1 has Vgs=0V, and Vds=VNN-VBB (larger voltage, usually 28V-38V). Therefore, the leakage current through the transistor M1 is relatively large, and the node PU will have relatively large noise. During the reverse scan, during the non-working time of the node PU, VBB leaks to the node PU through the transistor M2, and the same problem exists. Especially after the reliability, due to the drift of the threshold voltage Vth of the transistor, the noise reduction ability decreases, the noise increases to a certain extent, and the display abnormality occurs.

In view of this, the embodiments of the present application provide a shift register, a gate driving circuit, and a display panel, which are used to improve the output stability of the shift register.

In order to make the above objectives, features, and advantages of the application more obvious and understandable, the application will be further described below in conjunction with the accompanying drawings and embodiments. However, the example embodiments can be implemented in various forms, and should not be construed as being limited to the embodiments set forth herein; on the contrary, the provision of these embodiments makes this application more comprehensive and complete, and fully conveys the concept of the example embodiments To those skilled in the art. The same reference numerals in the figures indicate the same or similar structures, and thus their repeated description will be omitted. The words expressing position and direction described in this application are all illustrated by taking the drawings as examples, but they can also be changed according to needs, and the changes are all included in the protection scope of this application. The drawings in this application are only used to illustrate the relative position relationship and do not represent the true ratio.

It should be noted that specific details are set forth in the following description in order to fully understand the application. However, this application can be implemented in a variety of other ways different from those described herein, and those skilled in the art can make similar promotion without violating the connotation of this application. Therefore, this application is not limited by the specific embodiments disclosed below. The following description of the specification is a preferred embodiment for implementing the application, but the description is for the purpose of explaining the general principles of the application, and is not intended to limit the scope of the application. The scope of protection of this application shall be subject to those defined by the appended claims.

Hereinafter, in conjunction with the accompanying drawings, the shift register, the gate driving circuit, and the display panel provided by the embodiments of the present application will be described in detail.

A shift register provided by an embodiment of the present application, as shown in FIG. 2, includes: a forward input module 1, a reverse input module 2, a node control module 3, an output module 4, and an anti-leakage module 5; among them:

The forward input module 1 includes: a first transistor M1 and a second transistor M2; the forward input module 1 is used to pass the signal of the forward power supply voltage terminal VNN through the first transistor M1 and the second transistor M1 and the second transistor M1 under the control of the positive input terminal INPUT. The two transistors M2 are provided to the first node PU;

The reverse input module 2 includes: a third transistor M3 and a fourth transistor M4; the reverse input module 2 is used to pass the signal of the reverse power supply voltage terminal VBB through the third transistor M3 and the third transistor M3 and the first transistor under the control of the reverse input terminal RESET. Four transistors M4 are provided to the first node PU;

The output module 4 is configured to provide the signal of the clock signal terminal CLK to the output terminal OUT under the control of the first node PU, or provide the signal of the first reference signal terminal VGL to the output terminal OUT under the control of the second node PD;

The node control module 3 is used to control the electric potentials of the first node PU and the second node PD to be opposite;

The leakage prevention module 5 is used for transmitting the signal of the first reference signal terminal VGL to between the first transistor M1 and the second transistor M2 and between the third transistor M3 and the fourth transistor M4 under the control of the clock signal terminal CLK.

The above-mentioned shift register provided by the embodiment of the present application includes: a forward input module 1, a reverse input module 2, a node control module 3, an output module 4, and an anti-leakage module 5; wherein, the forward input module 1 is used for Under the control of the forward input terminal INPUT, the signal of the forward power supply voltage terminal VNN is sequentially provided to the first node PU through the first transistor M1 and the second transistor M2; the reverse input module 2 is used to control the RESET at the reverse input terminal Next, the signal of the reverse power supply voltage terminal VBB is sequentially provided to the first node PU through the third transistor M3 and the fourth transistor M4; in the forward scan, the leakage prevention module 5 controls the first reference node PU under the control of the clock signal terminal CLK. The signal of the signal terminal VGL is respectively transmitted between the first transistor M1 and the second transistor M2, so that the forward power supply voltage terminal VNN originally flows to the first node PU through the second transistor M2, and the leakage is directed to the first reference signal terminal by the leakage prevention module 5 VGL, thereby reducing the noise of the first node PU. At the same time, for the reverse input module 2, the electrical potential of the signal provided by the anti-leakage module 5 to the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4 is the same as that of the reverse power supply voltage terminal VBB. Therefore, the reset of the first node PU by the inverted input module 2 will not be affected. During the reverse scan, the leakage prevention module 5 causes the reverse power supply voltage terminal VBB to flow to the first node PU through the fourth transistor M4, and the leakage is directed to the first reference signal terminal VGL by the leakage prevention module 5, thereby reducing the noise of the first node PU. . At the same time, for the positive input module 1, the potential of the signal provided by the leakage prevention module 5 to the first reference signal terminal VGL between the first transistor M1 and the second transistor M2 is the same as the signal of the positive power supply voltage terminal VNN. Therefore, it will not affect the reset of the first node PU by the forward input module 1. Therefore, the above-mentioned shift register provided by the embodiment of the present application can effectively reduce the noise of the first node PU and improve the stability of the shift register.

In specific implementation, in the embodiment of the present application, when the effective pulse signal of the positive input terminal INPUT is a high potential signal, the potential of the first reference signal terminal VGL is a low potential; in the forward scan, the forward power supply voltage The potential of the terminal VNN is a high potential, and the potential of the reverse power supply voltage terminal VBB is a low potential; during reverse scanning, the potential of the forward power supply voltage terminal VNN is a low potential, and the potential of the reverse power supply voltage terminal VBB is a high potential. When the effective pulse signal of the positive input terminal INPUT is a low potential signal, the potential of the first reference signal terminal VGL is a high potential. During forward scanning, the potential of the forward power supply voltage terminal VNN is low, and the potential of the reverse power supply voltage terminal VBB is high. During the reverse scan, the potential of the forward power supply voltage terminal VNN is a high potential, and the potential of the reverse power supply voltage terminal VBB is a low potential.

The application will be described in detail below in conjunction with specific embodiments. It should be noted that the purpose of this embodiment is to better explain the application, but does not limit the application.

Optionally, in the shift register provided in the embodiment of the present application, as shown in FIG. 3 and FIG. 4, in the forward input module 1:

The gate of the first transistor M1 is connected to the forward input terminal INPUT, the first electrode of the first transistor M1 is connected to the forward power supply voltage terminal VNN, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2 ；

The gate of the second transistor M2 is connected to the positive input terminal INPUT, and the second electrode of the second transistor M2 is connected to the first node PU.

In specific implementation, when the forward input terminal INPUT controls the conduction state of the first transistor M1 and the second transistor M2, the signal of the forward power supply voltage terminal VNN is sequentially transmitted to the first transistor M1 and the second transistor M2 by turning on the first transistor M1 and the second transistor M2. A node PU charges the first node PU during forward scanning, and resets the first node PU during reverse scanning.

Optionally, in the above-mentioned shift register provided in the embodiment of the present application, the first transistor M1 and the second transistor M2 form a double-gate transistor.

Optionally, in the shift register provided in the embodiment of the present application, as shown in FIG. 3 and FIG. 4, in the reverse input module 2:

The gate of the third transistor M3 is connected to the reverse input terminal RESET, the first electrode of the third transistor M3 is connected to the reverse power supply voltage terminal VBB, and the second electrode of the third transistor M3 is connected to the first electrode of the fourth transistor M4 ；

The gate of the fourth transistor M4 is connected to the reverse input terminal RESET, and the second electrode of the fourth transistor M4 is connected to the first node PU.

In specific implementation, when the reverse input terminal RESET controls the conduction state of the third transistor M3 and the fourth transistor M4, the signal of the reverse power supply voltage terminal VBB is sequentially transmitted to the first transistor M3 and the fourth transistor M4 by turning on the third transistor M3 and the fourth transistor M4. A node PU charges the first node PU during the reverse scan, and resets the first node PU during the forward scan.

Optionally, in the above-mentioned shift register provided in the embodiment of the present application, the third transistor M3 and the fourth transistor M4 form a double-gate transistor.

Optionally, in the shift register provided by the embodiment of the present application, as shown in FIG. 3 and FIG. 4, the leakage prevention module 5 includes a fifth transistor M5 and a sixth transistor M6; wherein:

The gate of the fifth transistor M5 is connected to the clock signal terminal CLK, the first electrode of the fifth transistor M5 is connected to the first reference signal terminal VGL, and the second electrode of the fifth transistor M5 is connected to the second electrode of the first transistor M1 and The first pole of the second transistor M2 is connected;

The gate of the sixth transistor M6 is connected to the clock signal terminal CLK, the first electrode of the sixth transistor M6 is connected to the first reference signal terminal VGL, and the second electrode of the sixth transistor M6 is connected to the second electrode of the third transistor M3 and The first pole of the fourth transistor M4 is connected.

In specific implementation, the clock signal terminal CLK controls the fifth transistor M5 and the sixth transistor M6 to be turned on. When scanning in the forward direction, the turned-on fifth transistor M5 causes the forward power supply voltage terminal VNN to flow to the second transistor through the second transistor M2. The leakage of a node PU is directed to the first reference signal terminal VGL, thereby reducing the noise of the first node PU. At the same time, the turned-on sixth transistor M6 provides the signal of the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4, because the potential of the first reference signal terminal VGL is the same as the potential of the reverse power supply voltage terminal VBB. The same, so it will not affect the reset of the first node PU. Similarly, when scanning in the reverse direction, the turned-on sixth transistor M6 causes the reverse power supply voltage terminal VBB to flow to the first node PU through the fourth transistor M4 and the leakage is directed to the first reference signal terminal VGL, thereby reducing the power of the first node PU. noise. At the same time, the turned-on fifth transistor M5 provides the signal of the first reference signal terminal VGL between the first transistor M1 and the second transistor M2, because the potential of the first reference signal terminal VGL is the same as the potential of the forward power supply voltage terminal VNN. The same, so it will not affect the reset of the first node PU.

The above is only an example to illustrate the specific structure of the anti-leakage module 5 in the shift register. In specific implementation, the specific structure of the anti-leakage module 5 is not limited to the above-mentioned structure provided in the embodiment of the present application, and may be other known to those skilled in the art. The structure is not limited here.

Optionally, in the shift register provided by the embodiment of the present application, as shown in FIG. 3 and FIG. 4, the output module 4 includes: a seventh transistor M7, an eighth transistor M8, and a first capacitor C1; among them:

The gate of the seventh transistor M7 is connected to the first node PU, the first electrode of the seventh transistor M7 is connected to the clock signal terminal CLK, and the second electrode of the seventh transistor M7 is connected to the output terminal OUT;

The gate of the eighth transistor M8 is connected to the second node PD, the first electrode of the eighth transistor M8 is connected to the first reference signal terminal VGL, and the second electrode of the eighth transistor M8 is connected to the output terminal OUT;

The first pole of the first capacitor C1 is connected to the first node PU, and the second pole of the first capacitor C1 is connected to the output terminal OUT.

In specific implementation, when the first node PU controls the seventh transistor M7 to turn on, the signal of the clock signal terminal CLK is transmitted to the output terminal OUT through the turned-on seventh transistor M7; when the second node PD controls the eighth transistor M8 to turn on When on, the signal from the first reference signal terminal VGL is transmitted to the output terminal OUT, and the first capacitor C1 is used to keep the potential of the first node PU stable.

The above is only an example to illustrate the specific structure of the output module 4 in the shift register. In specific implementation, the specific structure of the output module 4 is not limited to the above-mentioned structure provided by the embodiment of the present application, and may also be other structures known to those skilled in the art. There is no limitation here.

Optionally, in the shift register provided by the embodiment of the present application, as shown in FIG. 3 and FIG. 4, the node control module 3 includes: a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor. Transistor M12 and the thirteenth transistor M13; among them:

The gate of the ninth transistor M9 is connected to the second reference signal terminal VDD, the first electrode of the ninth transistor M9 is connected to the second reference signal terminal VDD, and the second electrode of the ninth transistor M9 is connected to the gate of the tenth transistor M10 ；

The first electrode of the tenth transistor M10 is connected to the second reference signal terminal VDD, and the second electrode of the tenth transistor M10 is connected to the second node PD;

The gate of the eleventh transistor M11 is connected to the first node PU, and the first electrode of the eleventh transistor M11 is connected to the first reference signal terminal VGL;

The gate of the twelfth transistor M12 is connected to the first node PU, the first electrode of the twelfth transistor M12 is connected to the first reference signal terminal VGL, and the second electrode of the twelfth transistor M12 is connected to the second node PD;

The gate of the thirteenth transistor M13 is connected to the second node PD, the first electrode of the thirteenth transistor M13 is connected to the first reference signal terminal VGL, and the second electrode of the thirteenth transistor M13 is connected to the first node PU.

In specific implementation, the second reference signal terminal VDD controls the ninth transistor M9 to be in the on state; when the first node PU controls the eleventh transistor M11 and the twelfth transistor M12 to conduct, the signal of the first reference signal terminal VGL It is transmitted to the second node PD through the turned-on twelfth transistor M12, so that the potential of the second node PD is opposite to the potential of the first node PU; the signal of the first reference signal terminal VGL is transmitted through the turned-on eleventh transistor M11 To the gate of the tenth transistor M10, and the signal of the second reference signal terminal VDD is transmitted through the turned-on ninth transistor M9 to the gate of the tenth transistor M10. Under the joint action of the ninth transistor M9 and the tenth transistor M10, The tenth transistor M10 is turned off to prevent the signal of the second reference signal terminal VDD from being transmitted to the second node PD, and to ensure that the potential of the second node PD is stable. When the second node PD controls the thirteenth transistor M13 to turn on, the signal of the first reference signal terminal VGL is transmitted to the first node PU through the turned-on thirteenth transistor M13, so that the potential of the first node PU is the same as that of the second node PU. The potential of PD is opposite. At the same time, the turned-on ninth transistor M9 controls the tenth transistor M10 to turn on, and the signal of the second reference signal terminal VDD is transmitted to the second node PD through the turned-on tenth transistor M10 to ensure the second node PD The potential is stable.

The above is only an example to illustrate the specific structure of the node control module 3 in the shift register. In specific implementation, the specific structure of the node control module 3 is not limited to the above-mentioned structure provided in the embodiment of the present application, and may also be other known to those skilled in the art. The structure is not limited here.

Optionally, the shift register provided in the embodiment of the present application, as shown in FIG. 4, further includes a reset module 6;

The reset module 6 is used to provide the signal of the first reference signal terminal VGL to the output terminal OUT under the control of the reset signal terminal RES, reset the output terminal OUT, and further improve the output stability of the shift register.

Optionally, in the shift register provided by the embodiment of the present application, as shown in FIG. 4, the reset module 6 includes a fourteenth transistor M14;

The gate of the fourteenth transistor M14 is connected to the reset signal terminal RES, the first electrode of the fourteenth transistor M14 is connected to the first reference signal terminal VGL, and the second electrode of the fourteenth transistor M14 is connected to the output terminal OUT.

In specific implementation, when the reset signal terminal RES controls the fourteenth transistor M14 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on fourteenth transistor M14, thereby resetting the output terminal OUT .

The above is only an example to illustrate the specific structure of the reset module 6 in the shift register. In specific implementation, the specific structure of the reset module 6 is not limited to the above-mentioned structure provided by the embodiment of the present application, and may also be other structures known to those skilled in the art. There is no limitation here.

Optionally, in the shift register provided in the embodiment of the present application, all transistors are N-type transistors, or all transistors are P-type transistors, which is not limited herein. When all the transistors are N-type transistors, the effective pulse signals of the forward input terminal INPUT and the reverse input terminal RESET are high potential signals; when all the transistors are P-type transistors, the forward input terminal INPUT and the reverse input The effective pulse signals of the terminal RESET are all low-level signals.

Specifically, the N-type transistor is in the on state when its gate potential is high, and it is in the off state when its gate potential is low; the P-type transistor is in the on state when its gate potential is low. When the gate potential is high, it is in the off state.

It should be noted that the transistor mentioned in the foregoing embodiments of the present application may be a thin film transistor (TFT, Thin Film Transistor), or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor), which is not limited herein.

In specific implementation, the functions of the first pole and the second pole of these transistors can be interchanged according to the transistor type and the input signal, and no specific distinction is made here.

The working process of the above-mentioned shift register provided in the embodiment of the present application will be described below in conjunction with a circuit timing diagram. In the following description, 1 represents a high-potential signal, and 0 represents a low-potential signal. Among them, 1 and 0 represent their logical potentials, which are only used to better explain the working process of the above-mentioned shift register provided in the embodiments of the present application, not The potential applied to the gate of each switching transistor during specific implementation.

Specifically, the structure of the shift register shown in FIG. 3 is taken as an example to describe its working process. Among them, in the shift register shown in FIG. 3, all switching transistors are N-type switching transistors; first reference The potential of the signal terminal VGL is a low potential, and the potential of the second reference signal terminal VDD is a high potential. When scanning in the forward direction, the corresponding input and output timing diagram is shown in Figure 5a, and when scanning in the reverse direction, the corresponding input and output timing diagram is shown in Figure 5b.

When scanning forward, as shown in Figure 5a, in the first stage T1, INPUT=1, CLK=0, and RESET=0.

The first transistor M1 and the second transistor M2 are turned on, and the high potential signal of the positive power supply voltage terminal VNN is transmitted to the first node PU through the turned-on first transistor M1 and the second transistor M2 in turn, and the potential of the first node PU is high Potential. The first node PU controls the eleventh transistor M11 and the twelfth transistor M12 to be turned on, and the signal of the first reference signal terminal VGL is transmitted to the second node PD through the turned-on twelfth transistor M12 to make the potential of the second node PD Is a low potential; the signal of the first reference signal terminal VGL is transmitted to the gate of the tenth transistor M10 through the turned-on eleventh transistor M11, while the signal of the second reference signal terminal VDD is transmitted through the turned-on ninth transistor M9. The gate of the tenth transistor M10. Under the joint action of the ninth transistor M9 and the tenth transistor M10, the tenth transistor M10 is turned off to prevent the signal of the second reference signal terminal VDD from being transmitted to the second node PD, and to ensure the potential of the second node PD stability. Under the control of the first node PU, the seventh transistor M7 is turned on, the signal of the clock signal terminal CLK is transmitted to the output terminal OUT through the turned-on seventh transistor M7, and the potential of the output terminal OUT is low.

In the second stage T2, INPUT=0, CLK=1, and RESET=0.

Under the function of the first capacitor C1, the potential of the first node PU remains high, the first node PU controls the eleventh transistor M11 and the twelfth transistor M12 to turn on, and the signal of the first reference signal terminal VGL passes through the turned on The twelve transistors M12 are transmitted to the second node PD, so that the potential of the second node PD is low; the signal of the first reference signal terminal VGL is transmitted to the gate of the tenth transistor M10 through the turned-on eleventh transistor M11, and at the same time The signal of the second reference signal terminal VDD is transmitted through the turned-on ninth transistor M9 to the gate of the tenth transistor M10. Under the joint action of the ninth transistor M9 and the tenth transistor M10, the tenth transistor M10 is turned off to avoid the second reference The signal of the signal terminal VDD is transmitted to the second node PD to ensure that the potential of the second node PD is stable. Under the control of the first node PU, the seventh transistor M7 is turned on, the signal of the clock signal terminal CLK is transmitted to the output terminal OUT through the turned-on seventh transistor M7, and the potential of the output terminal OUT becomes a high potential. Since the potential of the output terminal OUT changes from a low potential to a high potential, the bootstrap action of the first capacitor C1 causes the potential of the first node PU to be further pulled up, thereby ensuring the stability of the output.

In this phase, the clock signal terminal CLK controls the fifth transistor M5 and the sixth transistor M6 to be turned on, and the turned-on fifth transistor M5 causes the signal of the first reference signal terminal VGL to be transmitted between the first transistor M1 and the second transistor M2 ; But at this stage the second transistor M2 is in the off state, although the second transistor M2 will leak to the first node PU, but because the potential of the first node PU in this stage is further pulled up, so this leakage The impact on the potential of the first node PU will not affect the output of the output terminal OUT. At the same time, the turned-on sixth transistor M6 provides the signal of the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4, because the potential of the first reference signal terminal VGL is the same as the potential of the reverse power supply voltage terminal VBB. The same, so it will not affect the potential of the first node PU.

In the third stage T3, INPUT=0, CLK=0, and RESET=0.

Under the function of the first capacitor C1, the potential of the first node PU remains high, the first node PU controls the eleventh transistor M11 and the twelfth transistor M12 to turn on, and the signal of the first reference signal terminal VGL passes through the turned on The twelve transistors M12 are transmitted to the second node PD, so that the potential of the second node PD is low; the signal of the first reference signal terminal VGL is transmitted to the gate of the tenth transistor M10 through the turned-on eleventh transistor M11, and at the same time The signal of the second reference signal terminal VDD is transmitted through the turned-on ninth transistor M9 to the gate of the tenth transistor M10. Under the joint action of the ninth transistor M9 and the tenth transistor M10, the tenth transistor M10 is turned off to avoid the second reference The signal of the signal terminal VDD is transmitted to the second node PD to ensure that the potential of the second node PD is stable. Under the control of the first node PU, the seventh transistor M7 is turned on, the signal of the clock signal terminal CLK is transmitted to the output terminal OUT through the turned-on seventh transistor M7, and the potential of the output terminal OUT becomes a low potential. Since the potential of the output terminal OUT changes from a high potential to a low potential, the bootstrap action of the first capacitor C1 causes the potential of the first node PU to be pulled down, but the potential of the first node PU is still high.

In the fourth stage T4, INPUT=0, CLK=1, and RESET=1.

The reverse input terminal RESET controls the third transistor M3 and the fourth transistor M4 to turn on, and the signal of the reverse power supply voltage terminal VBB is sequentially provided to the first node PU through the third transistor M3 and the fourth transistor M4, and the potential of the first node PU Becomes low. At the same time, the second reference signal terminal VDD controls the ninth transistor M9 to be turned on, the turned-on ninth transistor M9 controls the tenth transistor M10 to turn on, and the signal of the second reference signal terminal VDD is transmitted through the turned-on tenth transistor M10 To the second node PD, the potential of the second node PD becomes a high potential. The second node PD controls the thirteenth transistor M13 to be turned on, and the signal of the first reference signal terminal VGL is transmitted to the first node PU through the turned-on thirteenth transistor M13 to further ensure that the potential of the first node PU is stable. The second node PD controls the eighth transistor M8 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on eighth transistor M8, and the potential of the output terminal OUT returns to a low potential.

In this stage, the clock signal terminal CLK controls the fifth transistor M5 and the sixth transistor M6 to turn on. The turned-on fifth transistor M5 causes the forward power supply voltage terminal VNN to flow to the first node PU through the second transistor M2, and the leakage current leads to the first node PU. Refer to the signal terminal VGL, thereby reducing the noise of the first node PU. At the same time, the turned-on sixth transistor M6 provides the signal of the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4, because the potential of the first reference signal terminal VGL is the same as the potential of the reverse power supply voltage terminal VBB. The same, so it will not affect the reset of the first node PU.

In the fifth stage T5, INPUT=0, CLK=0, and RESET=0.

The second reference signal terminal VDD controls the ninth transistor M9 to be turned on, the turned-on ninth transistor M9 controls the tenth transistor M10 to turn on, and the signal of the second reference signal terminal VDD is transmitted to the second through the turned-on tenth transistor M10. For the second node PD, the potential of the second node PD continues to maintain a high potential. The second node PD controls the thirteenth transistor M13 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the first node PU through the turned-on thirteenth transistor M13, and the potential of the first node PU continues to maintain a low potential. The second node PD controls the eighth transistor M8 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on eighth transistor M8, and the potential of the output terminal OUT continues to maintain a low potential.

In the sixth stage T6, INPUT=0, CLK=1, and RESET=0.

The second reference signal terminal VDD controls the ninth transistor M9 to be turned on, the turned-on ninth transistor M9 controls the tenth transistor M10 to turn on, and the signal of the second reference signal terminal VDD is transmitted to the second through the turned-on tenth transistor M10. Two-node PD, the potential of the second node PD continues to maintain a high potential. The second node PD controls the thirteenth transistor M13 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the first node PU through the turned-on thirteenth transistor M13, and the potential of the first node PU continues to maintain a low potential. The second node PD controls the eighth transistor M8 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on eighth transistor M8, and the potential of the output terminal OUT continues to maintain a low potential.

In the above-mentioned shift register provided by the embodiment of the present application, after the sixth stage, the working processes of the fifth stage and the sixth stage are repeatedly executed, and the fifth transistor M5 is periodically turned on to prevent the forward power supply voltage terminal VNN The second transistor M2 leaks electricity to the first node PU, thereby improving the output stability of the shift register.

When scanning in the reverse direction, as shown in FIG. 5b, the working principle of the shift register is similar to that of the forward scanning, and will not be repeated here. The main difference is that in the T1 phase, the first transistor M1 and the second transistor M2 are turned off, and the third transistor M3 and the fourth transistor M4 are turned on; in the T4 phase, the first transistor M1 and the second transistor M2 are turned on, and the third transistor is turned on. M3 and the fourth transistor M4 are turned off.

Specifically, the structure of the shift register shown in FIG. 4 is taken as an example to describe its working process. Among them, in the shift register shown in FIG. 4, all switching transistors are N-type switching transistors; first reference The potential of the signal terminal VGL is a low potential, and the potential of the second reference signal terminal VDD is a high potential. When scanning in the forward direction, the corresponding input and output timing diagram is shown in Figure 6a, and when scanning in the reverse direction, the corresponding input and output timing diagram is shown in Figure 6b.

When scanning forward, as shown in Fig. 6a, in the first stage T1, INPUT=1, CLK=0, RESET=0, RES=0.

In the second stage T2, INPUT=0, CLK=1, RESET=0, and RES=0.

In the third stage T3, INPUT=0, CLK=0, RESET=1, and RES=1.

The reverse input terminal RESET controls the third transistor M3 and the fourth transistor M4 to turn on, and the signal of the reverse power supply voltage terminal VBB is sequentially provided to the first node PU through the third transistor M3 and the fourth transistor M4, and the potential of the first node PU Becomes low. At the same time, the second reference signal terminal VDD controls the ninth transistor M9 to be turned on, the turned-on ninth transistor M9 controls the tenth transistor M10 to turn on, and the signal of the second reference signal terminal VDD is transmitted through the turned-on tenth transistor M10 To the second node PD, the potential of the second node PD becomes a high potential. The second node PD controls the thirteenth transistor M13 to be turned on, and the signal of the first reference signal terminal VGL is transmitted to the first node PU through the turned-on thirteenth transistor M13 to further ensure that the potential of the first node PU is stable. The second node PD controls the eighth transistor M8 to be turned on, the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on eighth transistor M8, and the potential of the output terminal OUT returns to a low potential. At the same time, the reset signal terminal RES controls the fourteenth transistor M14 to be turned on, and the signal of the first reference signal terminal VGL is transmitted to the output terminal OUT through the turned-on fourteenth transistor M14, resets the output terminal OUT, and further improves the shift register The output stability.

In the fourth stage T4, INPUT=0, CLK=1, RESET=0, and RES=0.

In this stage, the clock signal terminal CLK controls the fifth transistor M5 and the sixth transistor M6 to turn on. The turned-on fifth transistor M5 causes the forward power supply voltage terminal VNN to flow to the first node PU through the second transistor M2, and the leakage current leads to the first node PU. Refer to the signal terminal VGL, thereby reducing the noise of the first node PU. At the same time, the turned-on sixth transistor M6 provides the signal of the first reference signal terminal VGL between the third transistor M3 and the fourth transistor M4, because the potential of the first reference signal terminal VGL is the same as the potential of the reverse power supply voltage terminal VBB. The same, so it will not affect the potential of the first node PU.

In the fifth stage T5, INPUT=0, CLK=0, RESET=0, and RES=0.

In the above-mentioned shift register provided by the embodiment of the present application, after the fifth stage, the working processes of the fourth stage and the fifth stage are repeatedly executed, and the fifth transistor M5 is periodically turned on to prevent the forward power supply voltage terminal VNN The second transistor M2 leaks electricity to the first node PU, thereby improving the output stability of the shift register.

When scanning in the reverse direction, as shown in FIG. 6b, the working principle of the shift register is similar to that of the forward scanning, and will not be repeated here. The main difference is that in the T1 phase, the first transistor M1 and the second transistor M2 are turned off, and the third transistor M3 and the fourth transistor M4 are turned on; in the T3 phase, the first transistor M1 and the second transistor M2 are turned on, and the third transistor is turned on. M3 and the fourth transistor M4 are turned off.

In the above-mentioned embodiment of the present application, the main difference between FIG. 6a and FIG. 5a is that the reset time of the first node PU is different. Regardless of the resetting method used by the first node PU, it is within the protection scope of the present application. The main advantage of the present application is that no matter what method the first node PU uses to reset, after the first node PU is reset, the leakage prevention module 5 can periodically perform noise reduction processing on the first node.

Based on the same inventive concept, an embodiment of the present application also provides a gate driving circuit, which includes any of the above-mentioned shift registers provided by a plurality of cascaded embodiments of the present invention. Since the principle of the gate drive circuit to solve the problem is similar to the aforementioned shift register, the implementation of the gate drive circuit can refer to the implementation of the aforementioned shift register, and the repetition will not be repeated.

Based on the same inventive concept, an embodiment of the present application also provides a display panel, including the above-mentioned gate driving circuit provided by the embodiment of the present application. The display panel can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, etc. The other indispensable components of the display panel are understood by those of ordinary skill in the art, and will not be repeated here, and should not be used as a limitation to the application.

In specific implementation, the above-mentioned display panel provided by the embodiment of the present application may be a liquid crystal display panel or an organic electroluminescence display panel, which is not limited herein.

The above-mentioned shift register, gate drive circuit, and display panel provided by the embodiments of the present application, wherein the shift register includes: a forward input module, a reverse input module, a node control module, an output module, and an anti-leakage module; The reverse input module is used to supply the signal of the forward power supply voltage terminal to the first node through the first transistor and the second transistor under the control of the forward input terminal; the reverse input module is used to reverse the signal under the control of the reverse input terminal. The signal from the power supply voltage terminal is sequentially supplied to the first node through the third transistor and the fourth transistor; during forward scanning, the leakage prevention module transmits the signal from the first reference signal terminal to the first transistor and the second transistor under the control of the clock signal terminal. Between the transistors, the forward power voltage terminal originally flows to the first node through the second transistor and the leakage current is directed to the first reference signal terminal by the leakage prevention module, thereby reducing the noise of the first node. At the same time, for the reverse input module, the signal provided by the leakage prevention module to the first reference signal terminal between the third transistor and the fourth transistor has the same potential as the signal at the reverse power supply voltage terminal, so that the reverse will not be affected. Enter the module's reset to the first node. During the reverse scan, the leakage prevention module causes the reverse power voltage terminal to flow to the first node through the fourth transistor and the leakage prevention module is directed to the first reference signal terminal, thereby reducing the noise of the first node. At the same time, for the positive input module, the signal provided by the anti-leakage module to the first reference signal terminal between the first transistor and the second transistor has the same potential as the signal at the forward power supply voltage terminal, so that it will not affect the forward direction. Enter the module's reset to the first node. Therefore, the above-mentioned shift register provided by the embodiment of the present application can effectively reduce the noise of the first node and improve the stability of the shift register.

Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application also intends to include these modifications and variations.

Claims

A shift register, which includes: a forward input module, a reverse input module, a node control module, an output module, and an anti-leakage module; wherein:

The forward input module includes: a first transistor and a second transistor; the forward input module is used to sequentially pass the signal of the forward power supply voltage terminal through the first transistor and the second transistor under the control of the forward input terminal. The transistor is provided to the first node;

The reverse input module includes: a third transistor and a fourth transistor; the reverse input module is used to sequentially pass the signal of the reverse power supply voltage terminal through the third transistor and the fourth transistor under the control of the reverse input terminal. A transistor is provided to the first node;

The output module is configured to provide the signal of the clock signal terminal to the output terminal under the control of the first node, or provide the signal of the first reference signal terminal to the output terminal under the control of the second node;

The node control module is used to control the electric potentials of the first node and the second node to be opposite;

The leakage prevention module is used to transmit the signal of the first reference signal terminal to between the first transistor and the second transistor and the third transistor and the first transistor under the control of the clock signal terminal. Between four transistors.
3. The shift register of claim 1, wherein the leakage prevention module includes a fifth transistor and a sixth transistor; wherein:

The gate of the fifth transistor is connected to the clock signal terminal, the first electrode of the fifth transistor is connected to the first reference signal terminal, and the second electrode of the fifth transistor is connected to the first reference signal terminal. The second pole of the transistor is connected to the first pole of the second transistor;

The gate of the sixth transistor is connected to the clock signal terminal, the first electrode of the sixth transistor is connected to the first reference signal terminal, and the second electrode of the sixth transistor is connected to the third terminal respectively. The second pole of the transistor is connected to the first pole of the fourth transistor.
The shift register according to claim 1, wherein in the forward input module:

The gate of the first transistor is connected to the forward input terminal, the first electrode of the first transistor is connected to the forward power supply voltage terminal, and the second electrode of the first transistor is connected to the second The first pole of the transistor is connected;

The gate of the second transistor is connected to the forward input terminal, and the second electrode of the second transistor is connected to the first node.
The shift register of claim 1, wherein in the reverse input module:

The gate of the third transistor is connected to the reverse input terminal, the first electrode of the third transistor is connected to the reverse power supply voltage terminal, and the second electrode of the third transistor is connected to the fourth The first pole of the transistor is connected;

The gate of the fourth transistor is connected to the reverse input terminal, and the second electrode of the fourth transistor is connected to the first node.
The shift register of claim 1, wherein the output module comprises: a seventh transistor, an eighth transistor and a first capacitor; wherein:

The gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the clock signal terminal, and the second electrode of the seventh transistor is connected to the output terminal;

The gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is connected to the first reference signal terminal, and the second electrode of the eighth transistor is connected to the output terminal ；

The first pole of the first capacitor is connected to the first node, and the second pole of the first capacitor is connected to the output terminal.
The shift register of claim 1, wherein the node control module comprises: a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; wherein:

The gate of the ninth transistor is connected to the second reference signal terminal, the first electrode of the ninth transistor is connected to the second reference signal terminal, and the second electrode of the ninth transistor is connected to the tenth transistor的Grid connection;

A first pole of the tenth transistor is connected to the second reference signal terminal, and a second pole of the tenth transistor is connected to the second node;

The gate of the eleventh transistor is connected to the first node, and the first electrode of the eleventh transistor is connected to the first reference signal terminal;

The gate of the twelfth transistor is connected to the first node, the first electrode of the twelfth transistor is connected to the first reference signal terminal, and the second electrode of the twelfth transistor is connected to the Second node connection;

The gate of the thirteenth transistor is connected to the second node, the first electrode of the thirteenth transistor is connected to the first reference signal terminal, and the second electrode of the thirteenth transistor is connected to the The first node is connected.
The shift register according to claim 1, further comprising a reset module;

The reset module is used to provide the signal of the first reference signal terminal to the output terminal under the control of the reset signal terminal.
The shift register of claim 1, wherein the reset module includes a fourteenth transistor;

The gate of the fourteenth transistor is connected to the reset signal terminal, the first electrode of the fourteenth transistor is connected to the first reference signal terminal, and the second electrode of the fourteenth transistor is connected to the The output terminal is connected.
A gate driving circuit, which comprises a plurality of shift registers according to any one of claims 1-8, which are cascaded.
A display panel comprising the gate driving circuit according to claim 9.