JP2009294617A - Electrophoretic display device, its driving method and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrophoretic display device capable of suppressing the occurrence of an overwrite state and capable of obtaining a display of even density. <P>SOLUTION: The electrophoretic display device includes the followings provided for every pixel 40: a pixel electrode 35; a first latch circuit LAT1; a first selective transistor ST1 connected to the first latch circuit LAT1; a second latch circuit LAT2; a second selective transistor ST2 connected to the second latch circuit LAT2; a first switch circuit SC1 connected to the first latch circuit LAT1; and a second switch circuit SC2 connected to the second latch circuit LAT2, the first switch circuit SC1 and the pixel electrode 35. The electrophoretic display device further has first and second control lines 91, 92 connected to the first switch circuit SC1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electrophoretic display device, a driving method thereof, and an electronic apparatus.

2. Description of the Related Art As an active matrix electrophoretic display device, one having a switching transistor and a memory circuit (SRAM: Static Random Access Memory) in a pixel is known (see Patent Document 1). The display device described in Patent Literature 1 has a configuration in which microcapsules containing charged particles are bonded to a substrate on which switching transistors and pixel electrodes are formed. Then, an image is displayed by controlling the charged particles by an electric field generated between the pixel electrode sandwiching the microcapsules and the common electrode.
JP 2003-84314 A

In the electrophoretic display device described in Patent Document 1, in order to display black and white of an image, one of black and white binary is set as a potential (high level / low level) in an SRAM (pixel SRAM circuit) provided in the pixel. Remember. And the display was performed by applying the voltage based on the memorize | stored electric potential to a microcapsule.
When the display image is updated in this type of electrophoretic display device, there is a problem that the density of display in the display region becomes non-uniform. This is because when the display image is updated, an electric field in the same direction as when the image before update is displayed on the pixel that maintains black display or white display acts on the microcapsule again, so that the display is changed. This is because the time during which the electric field acts on the microcapsules becomes longer. As a result, an overwrite state is achieved in which the black display is blacker and the white display is whiter. In addition, in such an overwritten pixel, when the display color is reversed, it is difficult for the electrophoretic particles to move, and there is a problem that the density of the displayed color is insufficient and the density of the display area is uneven. .
Furthermore, if the same color is maintained over a long period of time, an electric field in one direction continues to act on the microcapsule, and discoloration and corrosion due to an electrochemical reaction occur in ITO (indium tin oxide) constituting the counter electrode. This is likely to occur and may cause a problem in reliability.

  The present invention has been made in view of the above-described problems of the prior art, and provides an electrophoretic display device capable of suppressing the occurrence of an overwrite state and obtaining a uniform density display, and a driving method thereof. Is one of the purposes.

  In order to solve the above problems, the present invention provides an electrophoretic display device having an electrophoretic element including electrophoretic particles between a pair of substrates and having a display unit composed of a plurality of pixels. , A pixel electrode, a first memory circuit, a first switching element connected to the first memory circuit, a second memory circuit, and a second switching connected to the second memory circuit. An element; a first switch circuit connected to the first memory circuit; and a second switch circuit connected to the second memory circuit, the first switch circuit, and the pixel electrode. And having first and second control lines connected to the first switch circuit.

According to this configuration, the connection state between the first or second control line and the second switch circuit can be switched by the first memory circuit and the first switch circuit. The connection state between the first switch circuit and the pixel electrode can be switched by the memory circuit and the second switch circuit. Therefore, in addition to being able to input the potential of the first control line or the potential of the second control line to the pixel electrode, it is possible to enter a high impedance state. That is, two types of voltages to be applied to the electrophoretic element can be selected, and a state in which no voltage is applied to the electrophoretic element can be selected.
Therefore, when the display state of the pixel does not change, by selecting a state in which no voltage is applied to the electrophoretic element, it is possible to avoid an electric field in the same direction from acting repeatedly on the electrophoretic element, and the pixel is overloaded. Can be prevented from being written.
As described above, according to the present invention, it is possible to provide an electrophoretic display device capable of obtaining a display with a uniform density.

The second switch circuit is a transmission gate, the output terminal of the first switch circuit is connected to the input terminal of the transmission gate, and the pixel electrode is connected to the output terminal. Can do.
That is, the second switch circuit can be configured using one transmission gate. By setting the transmission gate to the off state, the pixel electrode can be in a high impedance state, and a state where an electric field does not act on the electrophoretic element can be easily realized.

A configuration having a third control line connected to the second switch circuit may also be adopted.
In this case, the second switch circuit switches a connection state between the first switch circuit and the third control line and the pixel electrode. By providing the third control line, it is possible to input three kinds of potentials to the pixel electrode, and the selection range of the driving form is expanded.

The second switch circuit includes first and second transmission gates, an output terminal of the first switch circuit is connected to an input terminal of the first transmission gate, and the second transmission gate Preferably, the third control line is connected to an input terminal, and the pixel electrode is connected to output terminals of the first and second transmission gates.
In this way, the second switch circuit can be configured by two transmission gates.

It is preferable that a counter electrode sandwiching the electrophoretic element is sandwiched together with the pixel electrode, and a signal synchronized with a signal input to the counter electrode can be input to the third control line.
With such a configuration, it is possible to select a state in which the pixel electrode and the common electrode have the same potential. Even in this state, since no voltage is applied to the electrophoretic element, it is possible to effectively prevent pixel overwriting.

A first data line connected to the data input terminal of the first memory circuit via the first switching element; and a data input terminal of the second memory circuit via the second switching element. And a second data line connected thereto.
With such a configuration, a configuration in which different signals can be input to the first and second memory circuits can be easily realized. More preferably, the control terminals for controlling on / off of the first and second switching elements are connected to the same signal wiring. In this case, signals can be input simultaneously to the first and second memory circuits, and a simple driving method can be employed.

An image analysis unit that generates pixel control data corresponding to a control signal supplied to the second data line, wherein the image analysis unit includes the first image data and the first image data to be displayed. The second image data immediately before is compared with pixel data corresponding to the same pixel, and the gradation is different depending on whether the gradation matches or does not match in the comparison between the pixel data. By generating the control pixel data, the pixel control data composed of a data string of the control pixel data can be generated.
With such a configuration, an electrophoretic display device that can generate a control signal supplied to the second data line based on image data can be realized.

  Next, in the driving method of the electrophoretic display device of the present invention, an electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, a display unit including a plurality of pixels is provided, and a pixel electrode is provided for each pixel. A first memory circuit; a first switching element connected to the first memory circuit; a second memory circuit; a second switching element connected to the second memory circuit; A first switch circuit connected to the first memory circuit; a second switch circuit connected to the second memory circuit, the first switch circuit, and the pixel electrode; An electrophoretic display device driving method having first and second control lines connected to one switch circuit, the image signal being input to the first memory circuit via the first switching element Is the first memory A control signal for outputting a signal for turning off the second switch circuit is input to the second memory circuit when the gradation is the same as that of the image signal held in the path. .

  According to this driving method, when the gray level of the pixel is not changed, the pixel electrode can be in a high impedance state, so that an electric field in the same direction can be avoided from being repeatedly applied to the electrophoretic element, and the pixel is overloaded. It can be prevented from being written. Therefore, high-quality display with uniform density becomes possible.

  In addition, the driving method of the electrophoretic display device of the present invention includes an electrophoretic element including electrophoretic particles between a pair of substrates, a display unit including a plurality of pixels, and a pixel electrode for each pixel. A first memory circuit; a first switching element connected to the first memory circuit; a second memory circuit; a second switching element connected to the second memory circuit; A first switch circuit connected to one memory circuit; and a second switch circuit connected to the second memory circuit, the first switch circuit, and the pixel electrode. A method for driving an electrophoretic display device, comprising: a first control line connected to a switch circuit; a second control line connected to the second switch circuit; and a third control line connected to the second switch circuit. The first through a switching element; When the image signal input to the memory circuit has the same gradation as the image signal held in the first memory circuit, the second memory circuit is connected to the second signal via the second switch circuit. A control signal for outputting a signal for connecting a third control line and the pixel electrode is input.

  According to this driving method, the potential of the third control line can be input to the pixel electrode when the gradation of the pixel is not changed. Accordingly, a potential different from the first and second control lines for inputting the potential corresponding to the first gradation and the second gradation can be input to the pixel electrode. By appropriately selecting the potential, it is possible to prevent the electric field in the same direction from repeatedly acting on the electrophoretic element and to prevent the pixel from being overwritten. Therefore, high-quality display with uniform density becomes possible.

It is preferable that a counter electrode that sandwiches the electrophoretic element together with the pixel electrode is formed on the substrate, and a signal synchronized with a signal input to the counter electrode is input to the third control line.
Thereby, when the gradation of the pixel is not changed, the pixel electrode and the common electrode can be set to the same potential, so that an electric field does not act on the electrophoretic element and the pixel is prevented from being overwritten. Can do.

  In the step of displaying an image on the display unit, the third control line may be held in a high impedance state. Also in this case, since the electric field does not substantially act on the electrophoretic element, it is possible to prevent the pixel from being overwritten.

Next, an electronic apparatus according to the present invention includes the electrophoretic display device according to the present invention described above.
According to this configuration, an electronic apparatus including a display device with high image quality and excellent reliability can be provided.

Hereinafter, an active matrix electrophoretic display device according to an embodiment of the present invention will be described with reference to the drawings.
Note that this embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. Moreover, in the following drawings, in order to make each configuration easy to understand, the actual structure is different from the scale and number of each structure.

(First embodiment)
FIG. 1 is a schematic configuration diagram of an electrophoretic display device 100 according to the present embodiment.
The electrophoretic display device 100 includes a display unit 5 in which a plurality of pixels 40 are arranged in a matrix. Around the display unit 5, a scanning line driving circuit 61, a data line driving circuit 62, a controller (control unit) 63, and a common power supply modulation circuit 64 are arranged. The scanning line driving circuit 61, the data line driving circuit 62, and the common power supply modulation circuit 64 are each connected to the controller 63. The controller 63 comprehensively controls the above circuit based on image data and a synchronization signal supplied from the host device.

  A plurality of scanning lines 66 extending from the scanning line driving circuit 61 and a plurality of first data lines 68 and a plurality of second data lines 69 extending from the data line driving circuit 62 are formed on the display unit 5. . Pixels 40 are provided corresponding to the intersection positions of the first data lines 68 and the scanning lines 66.

  The scanning line driving circuit 61 is connected to each pixel 40 via m scanning lines 66 (Y1, Y2,..., Ym). Under the control of the controller 63, the first to mth rows are connected. The scanning lines 66 up to are sequentially selected. The scanning line driving circuit 61 supplies a selection signal for defining an on timing to the first selection transistor ST1 and the second selection transistor ST2 (see FIG. 2) provided in the pixel 40 through the selected scanning line 66. To do.

The data line driving circuit 62 is connected to n first data lines 68 (X1, X2,..., Xn) and n second data lines 69 (P1, P2,..., Pn), respectively. Connected to the pixel 40. The data line driving circuit 62 supplies an image signal defining 1-bit pixel data corresponding to each pixel 40 to the pixel 40 via the first data line 68 under the control of the controller 63.
Further, the data line driving circuit 62 supplies a control signal for operation control corresponding to each of the pixels 40 to the pixels 40 via the second data lines 69 under the control of the controller 63.
In the present embodiment, a low level (L) image signal is supplied to the pixel 40 when the pixel data “0” is defined, and a high level (H) image is defined when the pixel data “1” is defined. It is assumed that a signal is supplied to the pixel 40.

  The display unit 5 also includes five global wirings (low potential power line 49, high potential power line 50, first control line 91, second control line 92, and third power line extending from the common power modulation circuit 64. A control line 93) is provided, and each wiring is connected to the pixel 40. Under the control of the controller 63, the common power supply modulation circuit 64 generates various signals to be supplied to each of the above wirings, and electrically connects and disconnects these wirings (high impedance). The common power supply modulation circuit 64 is connected to the common electrode 37 (see FIG. 3) common to the plurality of pixels 40, and supplies the potential Vcom to the common electrode 37 and increases the impedance of the common electrode 37.

FIG. 2 is a circuit configuration diagram of the pixel 40.
The pixel 40 includes a first selection transistor ST1 (first switching element), a first latch circuit LAT1 (first memory circuit), a first switch circuit SC1, and a second selection transistor ST2 ( A second switching element), a second latch circuit LAT2 (second memory circuit), a second switch circuit SC2, an electrophoretic element 32, a pixel electrode 35, and a common electrode 37. Yes. The electrophoretic element 32 is sandwiched between the pixel electrode 35 and the common electrode 37.
The pixel 40 has an SRAM (Static Random Access Memory) type configuration in which an image signal is held as a potential by the first latch circuit LAT1.

The first selection transistor ST1 is a switching element formed of an N-MOS (Negative Metal Oxide Semiconductor) transistor. The gate terminal of the first selection transistor ST1 is connected to the scanning line 66, the source terminal is connected to the first data line 68, and the drain terminal is connected to the data input terminal N11 of the first latch circuit LAT1.
The data input terminal N11 and the data output terminal N12 of the first latch circuit LAT1 are connected to the first switch circuit SC1. Further, the first switch circuit SC1 is connected to the second switch circuit SC2, the first control line 91, and the second control line 92.

The second selection transistor ST2 is a switching element composed of an N-MOS transistor. The gate terminal of the second selection transistor ST2 is connected to the common scanning line 66 with the gate terminal of the first selection transistor ST1, and the source terminal is connected to the second data line 69 paired with the first data line 68. The drain terminal is connected to the data input terminal N21 of the second latch circuit LAT2.
The data input terminal N21 and the data output terminal N22 of the second latch circuit LAT2 are connected to the second switch circuit SC2. The second switch circuit SC2 is connected to the first switch circuit SC1, the third control line 93, and the pixel electrode 35.

  The first latch circuit LAT1 includes a transfer inverter INV1 and a feedback inverter INV2. Both the transfer inverter INV1 and the feedback inverter INV2 are C-MOS inverters. The transfer inverter INV1 and the feedback inverter INV2 have a loop structure in which the other output terminal is connected to each other's input terminal, and each inverter has a high potential connected via a high potential power supply terminal PH1. A high potential power supply voltage is supplied from the power supply line 50, and a low potential power supply voltage is supplied from the low potential power supply line 49 connected via the low potential power supply terminal PL1.

  The transfer inverter INV1 includes a P-MOS (Positive Metal Oxide Semiconductor) transistor PM1 and an N-MOS transistor NM1 each having a drain terminal connected to the data output terminal N12. The source terminal of the P-MOS transistor PM1 is connected to the high potential power supply terminal PH1, and the source terminal of the N-MOS transistor NM1 is connected to the low potential power supply terminal PL1. The gate terminals of the P-MOS transistor PM1 and the N-MOS transistor NM1 (the input terminal of the transfer inverter INV1) are connected to the data input terminal N11 (the output terminal of the feedback inverter INV2).

  The feedback inverter INV2 includes a P-MOS transistor PM2 and an N-MOS transistor NM2 whose drain terminals are connected to the data input terminal N11. The gate terminals of the P-MOS transistor PM2 and the N-MOS transistor NM2 (input terminal of the feedback inverter INV2) are connected to the data output terminal N12 (output terminal of the transfer inverter INV1).

  In the first latch circuit LAT1 configured as described above, when a high level (H) image signal (pixel data “1”) is stored, a low level (L) is output from the data output terminal N12 of the first latch circuit LAT1. A signal is output. On the other hand, when a low level (L) image signal (pixel data “0”) is stored in the first latch circuit LAT1, a high level (H) signal is output from the data output terminal N12.

The first switch circuit SC1 includes a first transmission gate TG1 and a second transmission gate TG2.
The first transmission gate TG1 includes a P-MOS transistor PM3 and an N-MOS transistor NM3.
The source terminals (input terminals of the first transmission gate TG1) of the P-MOS transistor PM3 and the N-MOS transistor NM3 are connected to the first control line 91, and the drain terminals of the P-MOS transistor PM3 and the N-MOS transistor NM3. The (output terminal of the first transmission gate TG1) is connected to the input terminal of the second switch circuit SC2 (third transmission gate TG3) together with the output terminal of the second transmission gate TG2.
The gate terminal of the P-MOS transistor PM3 is connected to the data input terminal N11 of the first latch circuit LAT1, and the gate terminal of the N-MOS transistor NM3 is connected to the data output terminal N12 of the first latch circuit LAT1. Yes.

The second transmission gate TG2 includes a P-MOS transistor PM4 and an N-MOS transistor NM4.
The source terminals of the P-MOS transistor PM4 and the N-MOS transistor NM4 (the input terminal of the second transmission gate TG2) are connected to the second control line 92, and the drain terminals of the P-MOS transistor PM4 and the N-MOS transistor NM4. The (output terminal of the second transmission gate TG2) is connected to the input terminal of the second switch circuit SC2 (third transmission gate TG3) together with the output terminal of the first transmission gate TG1.
The gate terminal of the P-MOS transistor PM4 is connected to the data output terminal N12 of the first latch circuit LAT1, and the gate terminal of the N-MOS transistor NM4 is connected to the data input terminal N11 of the first latch circuit LAT1. Yes.

  The second latch circuit LAT2 is a latch circuit having a configuration similar to that of the first latch circuit LAT1, and includes a transfer inverter INV3 including a P-MOS transistor PM5 and an N-MOS transistor NM5, and a P-MOS transistor. A feedback inverter INV4 including PM6 and an N-MOS transistor NM6 is included. Also in the second latch circuit LAT2, when a high level (H) control signal is stored, a low level (L) signal is output from the data output terminal N22 of the second latch circuit LAT2. On the other hand, when a low level (L) control signal is stored in the second latch circuit LAT2, a high level (H) signal is output from the data output terminal N22.

The second switch circuit SC2 includes a third transmission gate TG3 and a fourth transmission gate TG4.
The third transmission gate TG3 includes a P-MOS transistor PM7 and an N-MOS transistor NM7.
The source terminals of the P-MOS transistor PM7 and the N-MOS transistor NM7 (input terminals of the third transmission gate TG3) are connected to the output terminals of the first and second transmission gates TG1 and TG2, and the P-MOS transistor PM7. The drain terminal of the N-MOS transistor NM7 (the output terminal of the third transmission gate TG3) is connected to the pixel electrode 35.
The gate terminal of the P-MOS transistor PM7 is connected to the data input terminal N21 of the second latch circuit LAT2, and the gate terminal of the N-MOS transistor NM7 is connected to the data output terminal N22 of the second latch circuit LAT2. Yes.

The fourth transmission gate TG4 includes a P-MOS transistor PM8 and an N-MOS transistor NM8.
The source terminals of the P-MOS transistor PM8 and the N-MOS transistor NM8 (the input terminal of the fourth transmission gate TG4) are connected to the third control line 93, and the drain terminals of the P-MOS transistor PM8 and the N-MOS transistor NM8. (Output terminal of the fourth transmission gate TG4) is connected to the pixel electrode 35 together with the output terminal of the third transmission gate TG3.
The gate terminal of the P-MOS transistor PM8 is connected to the data output terminal N22 of the second latch circuit LAT2, and the gate terminal of the N-MOS transistor NM8 is connected to the data input terminal N21 of the second latch circuit LAT2. Yes.

  In the pixel 40 described above, the first switch circuit SC1 is controlled by the output signal (holding potential) of the first latch circuit LAT1, and the second switch is controlled by the output signal (holding potential) of the second latch circuit LAT2. The circuit SC2 is controlled. Then, one of the first to third control lines 91 to 93 is connected to the pixel electrode 35 by the switching operation by the first and second switch circuits SC1 and SC2, and the potentials S1 to S3 of these control lines are connected. Either is input to the pixel electrode 35.

First, when a low level (L) image signal (pixel data “0”) is stored in the first latch circuit LAT1, and a high level (H) signal is output from the data output terminal N12, the first transmission The gate TG1 is turned on to electrically connect the first control line 91 and the second switch circuit SC2, and the potential S1 of the first control line 91 is input to the second switch circuit SC2.
On the other hand, when a high level (H) image signal (pixel data “1”) is stored in the first latch circuit LAT1, and a low level (L) signal is output from the data output terminal N12, the second transmission The gate TG2 is turned on, and the potential S2 of the second control line 92 is input to the second switch circuit SC2.

At this time, if a low level (L) control signal is stored in the second latch circuit LAT2 and a high level (H) signal is output from the data output terminal N22, the third transmission gate TG3 is turned on. Thus, the pixel electrode 35 and the first switch circuit SC1 are connected. As a result, the first control line 91 or the second control line 92 selected by the first switch circuit SC1 based on the output signal of the first latch circuit LAT1 is connected to the pixel electrode 35, and the potential S1 or S2 is Input to the pixel electrode 35.
On the other hand, when a high level (H) control signal is stored in the second latch circuit LAT2 and a low level (L) signal is output from the data output terminal N22, the fourth transmission gate TG4 is turned on. Thus, the pixel electrode 35 and the third control line 93 are connected. As a result, the potential S3 of the third control line 93 is input to the pixel electrode 35.

  Next, FIG. 3 is a partial cross-sectional view of the electrophoretic display device 100 in the display unit 5. The electrophoretic display device 100 has a configuration in which an electrophoretic element 32 formed by arranging a plurality of microcapsules 20 is sandwiched between an element substrate 30 and a counter substrate 31. In the display unit 5, a plurality of pixel electrodes 35 are arranged on the electrophoretic element 32 side of the element substrate 30, and the electrophoretic elements 32 are bonded to the pixel electrodes 35 through an adhesive layer 33.

  The element substrate 30 is a substrate made of glass, plastic, or the like and is not required to be transparent because it is disposed on the side opposite to the image display surface. The pixel electrode 35 is an electrode in which nickel plating and gold plating are laminated in this order on a Cu foil, or an electrode formed of Al, ITO (indium tin oxide), or the like. Although not shown, between the pixel electrode 35 and the element substrate 30, the scanning line 66, the first and second data lines 68 and 69, the first and second data lines shown in FIGS. The selection transistors ST1 and ST2, the first and second latch circuits LAT1 and LAT2, the first and second switch circuits SC1 and SC2, and the like are formed.

  On the other hand, the counter substrate 31 is a substrate made of glass, plastic, or the like, and is a transparent substrate because it is disposed on the image display side. A planar common electrode (opposite electrode) 37 facing the plurality of pixel electrodes 35 is formed on the counter substrate 31 on the side of the electrophoretic element 32, and the electrophoretic element 32 is provided on the common electrode 37. The common electrode 37 is a transparent electrode formed of MgAg, ITO, IZO (indium / zinc oxide), or the like.

  In general, the electrophoretic element 32 is formed in advance on the counter substrate 31 side, and is handled as an electrophoretic sheet including the adhesive layer 33. In the manufacturing process, the electrophoretic sheet is handled in a state where a protective release sheet is attached to the surface of the adhesive layer 33. And the display part 5 is formed by affixing the said electrophoretic sheet which peeled off the peeling sheet with respect to the element board | substrate 30 (The pixel electrode 35, various circuits, etc.) which were manufactured separately. For this reason, the adhesive layer 33 exists only on the pixel electrode 35 side of the electrophoretic element 32.

  FIG. 4 is a schematic cross-sectional view of the microcapsule 20. The microcapsule 20 has a particle size of, for example, about 50 μm and encloses therein a dispersion medium 21, a plurality of white particles (electrophoretic particles) 27, and a plurality of black particles (electrophoretic particles) 26. It is a spherical body. As shown in FIG. 3, the microcapsule 20 is sandwiched between the common electrode 37 and the pixel electrode 35, and one or more microcapsules 20 are arranged in one pixel 40.

The outer shell portion (wall film) of the microcapsule 20 is formed using a translucent polymer resin such as an acrylic resin such as polymethyl methacrylate or polyethyl methacrylate, a urea resin, or gum arabic.
The dispersion medium 21 is a liquid that disperses the white particles 27 and the black particles 26 in the microcapsules 20. Examples of the dispersion medium 21 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.). ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrachloride) Element, and 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

The white particles 27 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 26 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used by being charged positively, for example.
These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.
Further, instead of the black particles 26 and the white particles 27, for example, pigments such as red, green, and blue may be used. According to such a configuration, red, green, blue, or the like can be displayed on the display unit 5.

FIG. 5 is an operation explanatory diagram of the electrophoretic element. FIG. 5A shows the case where the pixel 40 displays white, and FIG. 5B shows the case where the pixel 40 displays black.
In the electrophoretic display device 100, a first latch circuit LAT1 that stores an image signal input via the first selection transistor ST1 and a first signal that stores a control signal input via the second selection transistor ST2. The second latch circuit LAT2 controls the first switch circuit SC1 and the second switch circuit SC2, respectively, and electrically connects one of the first to third control lines 91 to 93 to the pixel electrode 35. . As a result, a predetermined potential is input to the pixel electrode 35, and the pixel 40 is displayed in black or white based on the potential difference between the pixel electrode 35 and the common electrode 37, as shown in FIG.

5A, the common electrode 37 is held at a relatively high potential and the pixel electrode 35 is held at a relatively low potential. As a result, the negatively charged white particles 27 are attracted to the common electrode 37, while the positively charged black particles 26 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side which is the display surface side, white (W) is recognized.
In the case of black display shown in FIG. 5B, the common electrode 37 is held at a relatively low potential, and the pixel electrode 35 is held at a relatively high potential. As a result, the positively charged black particles 26 are attracted to the common electrode 37, while the negatively charged white particles 27 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side, black (B) is recognized.

[Control unit]
FIG. 6 is a block diagram showing details of the controller 63 provided in the electrophoretic display device 100.
The controller 63 includes a control circuit 161 as a CPU (Central Processing Unit), a storage unit 162 including an EEPROM (Electrically-Erasable and Programmable Read-Only Memory), a voltage generation circuit 163, a data buffer 164, and a frame memory. 165, a memory control circuit 166, and an image analysis circuit 167.

The control circuit 161 generates control signals (timing pulses) such as a clock signal CLK, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync, and supplies these control signals to each circuit arranged around the control circuit 161.
The storage unit 162 stores setting values (mode setting values and volume values) required for operation control of each circuit by the control circuit 161. For example, the setting value of the drive sequence for each operation mode is stored as a LUT (Look Up Table). The storage unit 162 can also store preset image data and the like used for displaying the operating state of the electrophoretic display device. Note that the storage unit 162 may be configured by a non-volatile memory other than the EEPROM, and may be configured by a volatile memory when a power source for the storage unit 162 can be secured.
The voltage generation circuit 163 is a circuit that supplies a driving voltage to the scanning line driving circuit 61, the data line driving circuit 62, and the common power supply modulation circuit 64.
The data buffer 164 is an interface unit with the host device in the controller 63, holds image data Dat input from the host device, and transmits the image data Dat to the control circuit 161.

The frame memory 165 is a RAM (Random Access Memory) having a readable / writable memory space corresponding to the arrangement of the pixels 40 of the display unit 5. The memory control circuit 166 expands the image data supplied from the control circuit 161 in the frame memory 165 according to the control signal.
In the present embodiment, since the pixel control data Ds is supplied together with the image data Dat from the control circuit 161 to the memory control circuit 166, the frame memory 165 includes a memory space for the image data Dat and a memory for the pixel control data Ds. With space.

Then, the memory control circuit 166 develops the image data Dat and the pixel control data Ds supplied from the control circuit 161 in accordance with the pixel array of the display unit 5 in accordance with the control signal, and writes them in the frame memory 165. The frame memory 165 sequentially transmits a data group including the stored image data Dat and pixel control data Ds to the data line driving circuit 62 as an image signal Dx and a control signal Dp, respectively.
The data line driving circuit 62 latches the image signal Dx and the control signal Dp transmitted from the frame memory 165 one line at a time based on the control signal supplied from the control circuit 161. Then, the latched image signal Dx is input to the first data line 68 and the control signal Dp is input to the second data line 69 in synchronization with the sequential selection operation of the scanning lines 66 by the scanning line driving circuit 61.

  The image analysis circuit (image analysis unit) 167 generates pixel control data Ds based on the image data Dat supplied from the control circuit 161. The image analysis circuit 167 includes a storage area for holding a plurality of image data Dat therein, and holds image data Dat for at least two frames in the storage area. In addition, an arithmetic unit that executes arithmetic processing using a plurality of image data Dat held in the storage area is provided.

  Here, FIG. 7 is an explanatory diagram used for explaining the operation of the image analysis circuit 167. FIG. 7A is a diagram illustrating two image data Dat held in the image analysis circuit 167. FIG. 7B is a diagram illustrating pixel control data Ds generated in the image analysis circuit 167. FIG. 7C is a diagram illustrating the image signal Dx and the control signal Dp output from the frame memory 165 to the data line driving circuit 62.

  In the following, an image corresponding to the image data DAT1 (image data Dat) shown in FIG. 7A is displayed on the display unit 5, and the image is updated to an image corresponding to the image data DAT2 (image data Dat). The operation of the image analysis circuit will be described.

  First, the image analysis circuit 167 holds the image data DAT1 (Dat) transferred to the display unit 5 immediately before in an internal storage area. In this state, when the display image update operation is started, the image data DAT2 is input from the control circuit 161 to the image analysis circuit 167 as the image data Dat.

Receiving the input of the image data DAT2, the image analysis circuit 167 stores the image data DAT2 in the storage area. Thereafter, the pixel control data Ds is generated by executing arithmetic processing using the image data DAT1 and the image data DAT2 stored in the storage area.
Specifically, as shown in FIGS. 7A and 7B, the gradation values of the pixel data corresponding to the image data DAT1 and the image data DAT2 (pixel data corresponding to the same pixel 40) match. If the grayscale values do not match, “1” is generated as the control pixel data constituting the pixel control data Ds. Data having a gradation value different from “1”).
By executing this arithmetic processing over all the pixel data of the image data DAT1 and DAT2, pixel control data Ds corresponding to the image data DAT2 can be obtained.

The calculation process of the pixel control data Ds can be executed by, for example, performing an XOR operation on the image data DAT1 and DAT2 and inverting the operation result (NOT operation).
In some cases, the XOR operation of the image data DAT1 and DAT2 can be used as it is as the pixel control data Ds. However, in this case, it is necessary to change the connection structure between the second latch circuit LAT2 to which the control signal Dp corresponding to the pixel control data Ds is input and the second switch circuit SC2.

  If the pixel control data Ds is generated by the above processing, the image analysis circuit 167 outputs the pixel control data Ds to the control circuit 161. Thereafter, the image data DAT1 held in the storage area is discarded, and the image data DAT2 is continuously held. That is, the process shifts to a state of waiting for input of image data Dat of the next frame.

  Note that the image analysis circuit 167 may be built in the control circuit 161. Alternatively, the image processing circuit 167 may not be provided in the controller 63, and arithmetic processing may be performed in the host device. When the calculation is performed by the host device, the pixel control data Ds is supplied to the controller 63 as control data accompanying the image data Dat input from the host device.

[Driving method]
Next, FIG. 8 is a flowchart showing a driving method of the electrophoretic display device having the above configuration.
As shown in FIG. 8, in the driving method of the present embodiment, the step S101 for displaying the first image, the step S102 for holding the display image, the step S103 for displaying the second image, and the step for holding the display image are performed. S104 and step S105 for displaying the third image are included.

FIG. 9 is an explanatory diagram showing a display state of the display unit 5 corresponding to steps S101, S103, and S105 shown in FIG.
FIG. 9 shows only pixels of 8 rows and 8 columns (64 pixels) out of the pixels 40 arranged in the display unit 5. Further, the display unit 5 shown in each drawing of FIG. 9 is virtually divided into four regions A to D each consisting of 4 rows and 4 columns (16 pixels) 40, and the regions A to Hereinafter, the pixels 40 belonging to each of D are distinguished from the pixels 40A, 40B, 40C, and 40D.

FIG. 10 is a timing chart corresponding to FIG.
FIG. 10 shows the potential N11 _A of the data input terminal N11 of the first latch circuit LAT1 of the pixel 40A belonging to the region A shown in FIG. 9, the potential N21 _A of the data input terminal N21 of the second latch circuit LAT2, and _A potential _VA of the pixel electrode 35 is shown. Similarly to the pixel 40A, the pixels 40B to 40D have the potentials N11 _{B to} N11 _D of the data input terminal N11 of the first latch circuit LAT1 and the potentials N21 _{B to} N21 of the data input terminal N21 of the second latch circuit LAT2. _D and potentials V _{B to} V _D of the pixel electrode 35 are shown.
FIG. 10 shows the potential Vcom of the common electrode 37, the potential S1 of the first control line 91, the potential S2 of the second control line 92, and the potential S3 of the third control line 93. ing.
Note that the potential Vdd of the high potential power supply line 50 and the potential Vss of the low potential power supply line 49 are not shown in FIG. 10, but at least in steps S101, S103, and S105, the high level potential VH and the low level potential VL, respectively. Retained.

  In the driving method of the electrophoretic display device of the present embodiment, first, the first image (DATA1) is displayed on the display unit 5 in step S101. In a partial region of the display unit 5 shown in FIG. 9A, the regions A and C are displayed in black, and the regions B and D are displayed in white.

Hereinafter, the operation of step S101 will be described in detail.
First, image data DATA1 corresponding to the first image is input to the controller 63 shown in FIG. 6 as image data Dat, and the image data DATA1 is framed by the memory control circuit 166 that receives the input of the image data DATA1 from the control circuit 161. Expanded in the memory 165. Then, the data line driving circuit 62 latches the image signal Dx (pixel data “0”, “1”) transmitted from the frame memory 165 and synchronizes with the selection operation of the scanning line 66 by the scanning line driving circuit 61. An image signal Dx is supplied to 40. The image signal Dx is written into the first latch circuit LAT1 of each pixel 40 via the first selection transistor ST1.

  As a result, the low-level image signal Dx corresponding to the pixel data “0” (black) is input to the first latch circuits LAT1 of the pixel 40A belonging to the region A and the pixel 40C belonging to the region C. The high-level image signal Dx corresponding to the pixel data “1” (white) is input to the first latch circuits LAT1 of the pixel 40B belonging to the region B and the pixel 40D belonging to the region D.

In step S101, the control signal Dp is input to the pixels 40A to 40D.
However, since the image display operation in step S101 is the first image display operation on the display unit 5, only the image data DATA1 is input to the image analysis circuit 167. Therefore, the image analysis circuit 167 does not perform the operation for generating the pixel control data Ds. However, also in step S101, the pixel control data Ds for controlling the second switch circuit SC2 is necessary so that the image signal Dx based on the image data DATA1 can be input to the pixel electrode 35.

  Therefore, the image analysis circuit 167 connects the output terminal of the first switch circuit SC1 and the pixel electrode 35 in the second switch circuit SC2 when only one image data Dat is held. Pixel control data Ds is generated. In the present embodiment, pixel control data Ds consisting only of control pixel data having a gradation value “0” corresponding to the low-level control signal Dp is generated in the image analysis circuit 167 and output to the control circuit 161. The

  Upon receiving the pixel control data Ds, the control circuit 161 outputs the pixel control data Ds to the memory control circuit 166. The memory control circuit 166 expands the received pixel control data Ds in the frame memory 165, and the pixel control data Ds is output from the frame memory 165 to the data line driving circuit 62 as the control signal Dp together with the image signal Dx. The data line driving circuit 62 supplies the control signal Dp to the pixels 40 via the second data line 69. In each pixel 40, the control signal Dp is written to the second latch circuit LAT2 via the second selection transistor ST2.

  Note that the pixel control data Ds generated in step S101 is fixed data corresponding to the circuit configuration of the pixel 40, and is therefore stored as preset data in the image analysis circuit 167, the control circuit 161, the storage unit 162, and the like. Also good. When stored in the storage unit 162, the control circuit 161 reads it out on its own work memory as necessary.

In addition, a command for supplying a potential to the first and second control lines 91 and 92 is output from the control circuit 161 to the common power supply modulation circuit 64. As a result, as shown in FIG. 10, the high level potential VH is supplied from the common power supply modulation circuit 64 to the first control line 91, and the low level potential VL is supplied to the second control line 92.
On the other hand, since the third control line 93 is not used for the first image display operation, it is maintained in a high impedance state, for example, as shown in FIG. In step S101, the potential S3 of the third control line 93 can be set to any potential between the low level potential VL and the high level potential VH.

Here, FIG. 11 is a schematic diagram illustrating a connection state of the pixel circuits of the pixels 40A to 40D in step S101. FIG. 11 shows pixels 40A to 40D and first to third control lines 91 to 93, and represents a switching operation by the first and second switch circuits SC1 and SC2 constituting the pixel circuit.
In FIG. 11, in order to make the drawing easy to see, the pixels 40 </ b> A to 40 </ b> D are displayed differently from the actual arrangement and arranged in a line in the horizontal direction of the drawing.

As shown in FIGS. 10 and 11, in the pixels 40A and 40C in which the first latch circuit LAT1 holds the low-level image signal Dx, the low-level output from the data input terminal N11 of the first latch circuit LAT1. The first transmission gate TG1 is turned on by the signals (potentials N11 _A and N11 _C ) and the high level signal output from the data output terminal N12, and the first control line 91 and the second switch circuit SC2 Is connected.
In addition, since the second latch circuit LAT2 of the pixels 40A and 40C holds the low-level control signal Dp, the low-level signals (potentials N21 _A and N21 _C ) output from the data input terminal N21, and The third transmission gate TG3 is turned on by the high level signal output from the data output terminal N22, and the first switch circuit SC1 and the pixel electrode 35 are electrically connected.
Thereby, in the pixels 40A and 40C, the pixel electrode 35 and the first control line 91 are electrically connected, and the potentials V _A and V _C of the pixel electrodes 35 of the pixels 40A and 40C are both high-level potential VH. (Potential S1).

On the other hand, in the pixels 40B and 40D, high level signals (potentials N11 _B and N11 _D ) output from the data input terminal N11 of the first latch circuit LAT1 and low level signals output from the data output terminal N12. The second transmission gate TG2 is turned on, and the second control line 92 and the second switch circuit SC2 are connected.
Further, the third transmission gate TG3 is generated by the low level signals (potentials N21 _B and N21 _D ) output from the data input terminal N21 of the second latch circuit LAT2 and the high level signal output from the data output terminal N22. Is turned on, and the first switch circuit SC1 and the pixel electrode 35 are electrically connected.
Thereby, in the pixels 40B and 40D, the pixel electrode 35 and the second control line 92 are electrically connected, and the potentials V _B and V _D of the pixel electrode 35 are both low level potential VL (potential S2). Become.

The common electrode 37 (potential Vcom) receives a rectangular wave pulse that repeats the high level potential VH and the low level potential VL in a predetermined cycle.
Then, in the pixels 40A and 40C, the electrophoretic element 32 is driven by a potential difference generated between each pixel electrode 35 (high level potential VH) in a period in which the potential Vcom of the common electrode 37 is the low level potential VL. . As a result, as shown in FIG. 5B, the pixels 40A and 40C are displayed in black.
During the period when the potential Vcom of the common electrode 37 is the high level potential VH, the potentials V _A , V _C and the potential Vcom are the same potential, so the electrophoretic element 32 is not driven, and the display of the pixels 40A, 40C is It does not change.

On the other hand, in the pixels 40B and 40D, the electrophoretic element 32 is driven by a potential difference generated between each pixel electrode 35 (low level potential VL) during the period when the potential Vcom of the common electrode 37 is the high level potential VH. . Thereby, as shown in FIG. 5A, the pixels 40B and 40D are displayed in white.
During the period when the potential Vcom of the common electrode 37 is the low level potential VL, the potentials V _B , V _D and the potential Vcom are the same potential, so the electrophoretic element 32 is not driven, and the display of the pixels 40B, 40D is It does not change.

  If a 1st image is displayed on the display part 5 by step S101, it will transfer to step S102 which hold | maintains a display image. In step S102, the first to third control lines 91 to 93 are all in a high impedance state. As described above, the pixel electrodes 35 belonging to the pixels 40A to 40D are connected to the first control line 91 or the second control line 92 via the first switch circuit SC1 and the second switch circuit SC2. Therefore, all the pixel electrodes 35 are in a high impedance state. The common electrode 37 is also brought into a high impedance state by the common power supply modulation circuit 64.

  In step S102, the high-potential power line 50 and the low-potential power line 49 are also in a high impedance state. As a result, the first and second latch circuits LAT1 and LAT2 are in a power-off state, and power consumption during a period of holding an image can be suppressed.

Note that in step S102, the high potential power supply line 50 and the low potential power supply line 49 may be in a state of holding predetermined high level potential and low level potential. In this case, since the first and second latch circuits LAT1 and LAT2 maintain the energized state, the image signal Dx and the control signal Dp corresponding to the first image input in step S101 can be held.
Further, when the energized state of the first and second latch circuits LAT1 and LAT2 is maintained, the power supply voltage of the first and second latch circuits LAT1 and LAT2 is lowered to such an extent that the retained data is not lost. May be. For example, when the electrophoretic element 32 is driven in step S101, the power supply voltage of the first and second latch circuits LAT1 and LAT2 needs to be about 10 to 15 V. In step S102, this power supply voltage is set to 2 It can be reduced to about -5V. Thereby, the power consumption of the pixel circuit in step S102 can be suppressed.

In step S102, the pixel electrode 35 and the common electrode 37 sandwiching the electrophoretic element 32 are both in a high impedance state, and no voltage is applied to the electrophoretic element 32. Thereby, it is possible to hold the first image displayed on the display unit 5 while suppressing the occurrence of leakage current through the electrophoretic element 32 and the adhesive layer 33.
Note that step S102 may be provided as necessary. For example, although the power consumption increases, a driving method that holds the potential state in step S101 for a predetermined period may be employed.

If the operation of updating the first image displayed on the display unit 5 to the second image (DATA2) is selected in step S102 for holding the display image, the process proceeds to step S103.
Step S103 includes a pixel control data generation step ST30, an image signal input step ST31, and an image display step ST32, as shown in FIGS. The second image written in step S103 is an image in which the areas A and D are displayed in white and the areas B and C are displayed in black as shown in FIG. 9B.

First, in the pixel control data generation step ST30, the controller 63 generates pixel control data Ds based on the image data DATA2 of the second image that is an image for updating the display of the display unit 5.
Specifically, the image data DATA2 (Dat) is input to the controller 63 illustrated in FIG. 6, and the input image data DATA2 is supplied from the control circuit 161 to the image analysis circuit 167. The image analysis circuit 167 that has received the input of the image data DATA2 stores the image data DATA2 in the storage area, and then executes arithmetic processing on the image data DATA1 and the image data DATA2 held in the storage area. Control data Ds is generated.

In the present embodiment, when the first image shown in FIG. 9A and the second image shown in FIG. 9B are compared, the gradations (display state) of the pixels 40A and 40B belonging to the regions A and B are compared. Changes, but the display state of the pixels 40C and 40D belonging to the regions C and D does not change. Accordingly, the pixel control data Ds is data in which the control pixel data corresponding to the pixels 40A and 40B has the gradation value “0” and the control pixel data corresponding to the pixels 40C and 40D has the gradation value “1”. Generated as a column.
The pixel control data Ds generated as described above is input from the image analysis circuit 167 to the control circuit 161.

  In the pixel control data generation step ST30, the first to third control lines 91 to 93, the common electrode 37, the high potential power line 50, and the low potential power line 49 all have the high impedance set in step S102. The state is maintained.

Next, in the image signal input step ST31, the image signal Dx corresponding to the image data DATA2 of the second image and the control signal Dp corresponding to the pixel control data Ds are input to the pixels 40 of the display unit 5. .
In the image signal input step ST31, first, a predetermined high level potential (Vdd) and low level potential (Vss) are supplied from the common power supply modulation circuit 64 to the high potential power supply line 50 and the low potential power supply line 49, respectively. . The potential supplied to these power supply lines in this step may be any potential that enables signal writing to the first and second latch circuits LAT1 and LAT2. For example, the potential Vdd is 5V and the potential Vss is 0V. can do.

Then, in the controller 63 shown in FIG. 6, the image data DATA2 (Dat) of the second image and the pixel control data Ds are input to the memory control circuit 166, and the image data DATA2 and the pixel control data Ds are input by the memory control circuit 166. The frame memory 165 is expanded.
Thereafter, the image data DATA2 is output as an image signal Dx from the frame memory 165, and is written into the first latch circuit LAT1 of the pixel 40 by the scanning line driving circuit 61 and the data line driving circuit 62. On the other hand, the pixel control data Ds is output as a control signal Dp from the frame memory 165 in synchronization with the image signal Dx, and is written in the second latch circuit LAT2 of the pixel 40 by the scanning line driving circuit 61 and the data line driving circuit 62. .

Accordingly, the high-level image signal Dx corresponding to the pixel data “1” (white) is input to the first latch circuits LAT1 of the pixels 40A and 40D belonging to the regions A and D shown in FIG. 9B. The low level image signal Dx corresponding to the pixel data “0” (black) is input to the first latch circuits LAT1 of the pixels 40B and 40C belonging to the regions B and C.
On the other hand, the low-level control signal Dp corresponding to the control pixel data “0” is input to the second latch circuit LAT2 of the pixels 40A and 40B belonging to the regions A and B shown in FIG. A high level control signal Dp corresponding to the control pixel data “1” is input to the second latch circuits LAT2 of the pixels 40C and 40D belonging to C and D.

  As shown in FIG. 10, in the image signal input step ST31, all of the first to third control lines 91 to 93 are set in a high impedance state. By the signal input to the first and second latch circuits LAT1 and LAT2, the pixel electrode 35 of the pixel 40 is connected to one of the first to third control lines 91 to 93 based on the output of the latch circuit. Therefore, all the pixel electrodes 35 of the display unit 5 are in a high impedance state. Therefore, even if the holding potentials of the first and second latch circuits LAT1 and LAT2 are rewritten by the image signal input operation, an electric field acting on the electrophoretic element 32 is not formed, and the image signal input step ST31 is being executed. The display on the display unit 5 is never updated.

  Next, when proceeding to the image display step ST32, as shown in FIG. 10, the high level potential VH is input to the first control line 91 (potential S1), and the low level is input to the second control line 92 (potential S2). The potential VL is input. Further, a rectangular wave pulse that periodically repeats the high level potential VH and the low level potential VL is input to the third control line 93 (potential S3) and the common electrode 37 (potential Vcom). The pulse input to the third control line 93 is a pulse synchronized with the pulse input to the common electrode 37, and the potential S3 of the third control line 93 and the common electrode 37 are applied during the image display step ST32. The potential Vcom is held at the same potential.

Here, FIG. 12 is a schematic diagram showing the connection state of the pixel circuits of the pixels 40A to 40D in the image display step ST32, and corresponds to FIG.
As shown in FIG. 12, as a result of inputting predetermined signals to the first and second latch circuits LAT1 and LAT2 in the image signal input step ST31, based on the outputs of the first and second latch circuits LAT1 and LAT2. The switch states of the first and second switch circuits SC1 and SC2 are defined, and the pixel electrodes 35 of the pixels 40A to 40D are electrically connected to any one of the first to third control lines 91 to 93. Accordingly, when potentials are input to the first to third control lines 91 to 93, the first to third control lines corresponding to the pixel electrodes 35 belonging to the respective pixels 40A to 40D of the display unit 5 are provided. The potentials S1 to S3 of 91 to 93 are input.

More specifically, in the pixel 40A belonging to the region A, since the pixel electrode 35 and the second control line 92 are electrically connected, the potential _VA of the pixel electrode 35 is the low level potential VL (potential S2). Become. Then, during a period in which the potential Vcom of the common electrode 37 is the high level potential VH, the electrophoretic element 32 is driven by the potential difference generated between the pixel electrode 35 and the common electrode 37, and as shown in FIG. The pixels 40A belonging to the region A are displayed in white.
During the period in which the common electrode 37 is at the low level potential VL, no potential difference is generated between the pixel electrode 35 and the common electrode 37, so the electrophoretic element 32 is not driven and the display state of the pixel 40A does not change. .

Further, in the pixel 40B belongs to the area B, since the pixel electrode 35 and the first control line 91 is electrically connected, the potential V _B of the pixel electrode 35 becomes the high level potential VH (potential S1). Then, during a period in which the potential Vcom of the common electrode 37 is the low level potential VL, the electrophoretic element 32 is driven by the potential difference generated between the pixel electrode 35 and the common electrode 37, and as shown in FIG. The pixels 40B belonging to the region B are displayed in black.

On the other hand, in the pixels 40C and 40D belonging to the regions C and D, the pixel electrode 35 and the third control line 93 are electrically connected. Since the potential S3 of the third control line 93 is the same as the potential Vcom of the common electrode 37, substantially no voltage is applied to the electrophoretic elements 32 belonging to the pixels 40C and 40D, and the pixels 40C and 40D. The display state of is not changed and remains black and white.
In this way, as shown in FIG. 9B, the second image in which the right areas A and D are displayed in white and the left areas B and C are displayed in black is displayed on the display unit 5.

  If a 2nd image is displayed on the display part 5 by step S103, it will transfer to step S104 which hold | maintains a display image. The operation in step S104 is the same as that in step S102 described above. That is, the first to third control lines 91 to 93, the common electrode 37, the high potential power supply line 50, and the low potential power supply line 49 are in a high impedance state, and all the pixel electrodes 35 and the common electrode 37 are in a high impedance state. State. Thereby, the second image displayed on the display unit 5 is held.

  Next, if the operation for updating the second image displayed on the display unit 5 to the third image (DATA3) is selected in step S104, the process proceeds to step S105. Step S105 is a step of executing the same image display operation as in the previous step S103.

  As shown in FIGS. 9 and 10, step S105 includes a pixel control data generation step ST50, an image signal input step ST51, and an image display step ST52. As shown in FIG. 9C, the third image written in step S105 is an image in which the upper areas A and C in the figure are displayed in white and the lower areas B and D in the figure are displayed in black.

  In the pixel control data generation step ST50, based on the image data DATA3 of the third image input to the controller 63 and the image data DATA2 of the second image held in the image analysis circuit 167, the image analysis circuit 167 performs pixel processing. Control data Ds is generated.

When updating the second image to the third image, the display state of the region A and the region B does not change from white display and black display, respectively, and the display state of the region C and region D changes from black display to white display, respectively. The display changes from white to black.
Therefore, the image analysis circuit 167 is data in which the control pixel data corresponding to the pixels 40A and 40B has the gradation value “1”, and the control pixel data corresponding to the pixels 40C and 40D has the gradation value “0”. Pixel control data Ds composed of columns is generated. The generated pixel control data Ds is output from the image analysis circuit 167 to the control circuit 161.

Next, in the image signal input step ST51, the pixel 40 of the display unit 5 corresponds to the image signal Dx corresponding to the image data DATA3 of the third image and the pixel control data Ds generated by the image analysis circuit 167. A control signal Dp is input.
As a result, the first latch circuit LAT1 of the pixels 40A and 40C belonging to the regions A and C shown in FIG. 9C has a high level corresponding to the pixel data “1” (white) as shown in FIG. The low-level image signal Dx corresponding to the pixel data “0” (black) is input to the first latch circuit LAT1 of the pixels 40B and 40D belonging to the regions B and D.

  On the other hand, the second latch circuit LAT2 of the pixels 40A and 40B belonging to the regions A and B shown in FIG. 9C receives the high-level control signal Dp corresponding to the pixel data “1” as shown in FIG. , And a low level control signal Dp corresponding to the pixel data “0” is input to the second latch circuits LAT2 of the pixels 40C and 40D belonging to the regions C and D.

  In the image signal input step ST51, the first to third control lines 91 to 93 are all in a high impedance state, and the display on the display unit 5 is updated during the execution of the image signal input step ST51. Absent.

  Next, when proceeding to the image display step ST52, the high level potential VH is supplied to the first control line 91, and the low level potential VL is supplied to the second control line 92. Further, the third control line 93 and the common electrode 37 are input with a rectangular wave pulse that periodically repeats the high level potential VH and the low level potential VL. The pulse input to the third control line 93 is a pulse synchronized with the pulse supplied to the common electrode 37. During the period of the image display step ST52, the potential S3 of the third control line 93 and the common electrode 37 are supplied. The potential Vcom is the same potential.

In the pixel 40C belonging to the region C, since the high-level image signal Dx is held in the first latch circuit LAT1, the second control line 92 and the second switch are connected via the second transmission gate TG2. The circuit SC2 is connected. Further, since the low-level control signal Dp is held in the second latch circuit LAT2, the first switch circuit SC1 and the pixel electrode 35 are connected via the third transmission gate TG3.
Thus, the pixel electrodes 35 of pixels 40C is connected to the second control line 92, the potential _{V C,} as shown in FIG. 10, a low level electric potential VL (potential S2). Then, during a period in which the potential Vcom of the common electrode 37 is the high level potential VH, the electrophoretic element 32 is driven by the potential difference generated between the pixel electrode 35 and the common electrode 37, and as shown in FIG. The pixels 40C belonging to the region C are displayed in white.

In the pixel 40D in the region D, the first latch circuit LAT1 holds the low-level image signal Dx, and the second latch circuit LAT2 holds the low-level control signal Dp. The first control line 91 and the pixel electrode 35 are connected via two switch circuits SC1 and SC2.
Accordingly, the potential V _D of the pixel electrode 35 of the pixel 40D becomes the high level potential VH (potential S1), and the pixel electrode 35 and the common electrode 37 are in a period in which the potential Vcom of the common electrode 37 is the low level potential VL. The electrophoretic element 32 is driven by the potential difference generated in FIG. 9, and the pixel 40D belonging to the region D is displayed in black as shown in FIG.

  On the other hand, in the pixel 40A belonging to the region A, since the high-level image signal Dx is held in the first latch circuit LAT1, the second transmission gate TG2 of the first switch circuit SC1 is in the on state. In the pixel 40B belonging to the region B, since the low-level image signal Dx is held in the first latch circuit LAT1, the first transmission gate TG1 is in the ON state.

However, since the second latch circuit LAT2 of the pixels 40A and 40B holds the high-level control signal Dp, the fourth transmission gate TG4 of the second switch circuit SC2 is turned on and the third latch circuit LAT2 is turned on. The control line 93 and the pixel electrode 35 are connected. Therefore, the potential S3 of the third control line 93 is input to the pixel electrodes 35 of the pixels 40A and 40B regardless of the holding potential of the first latch circuit LAT1.
Since the potential S3 of the third control line 93 is the same as the potential Vcom of the common electrode 37, substantially no voltage is applied to the electrophoretic elements 32 of the pixels 40A and 40B. The display state of 40B does not change and remains white display and black display, respectively.
In this way, as shown in FIG. 9C, the third image in which the upper areas A and C are displayed in white and the lower areas B and D are displayed in black is displayed on the display unit 5.

According to the electrophoretic display device and the driving method of the present embodiment described above, it is possible to prevent the pixels 40 of the display unit 5 from being overwritten, and display with uniform density is possible.
In the electrophoretic display device 100 according to the present embodiment, the first switch circuit SC1 and the second switch circuit SC2 are provided, so that the first to third control lines 91 to 93 and the pixel electrode 35 are connected. The state can be freely controlled. Thus, in the series of image display operations in steps S101 to S105, when each pixel 40 maintains the state in which the previous image is displayed, the third control line 93 is applied to the pixel electrode 35 of the pixel 40. The same potential as the potential Vcom of the common electrode 37 can be input.
More specifically, in the pixels 40A and 40B, the potential V _A and the potential V _B of the pixel electrode 35 are set to the same potential as the potential Vcom of the common electrode 37 in the image display step ST53 of step S105. potential _{V C} and the potential _{V D} of the pixel electrode 35 is the same potential as the potential Vcom in the image display step ST32.

Therefore, in the electrophoretic display device 100 and the driving method thereof according to the present embodiment, when the display state of the pixel 40 does not change before and after the image update, the pixel electrode 35 and the common electrode 37 are not affected even when the image display operation is performed. It is possible to prevent an electric field from being formed therebetween and to prevent the electrophoretic element 32 from being driven.
Therefore, it is possible to prevent the pixels 40 from being overwritten due to repeated application of an electric field in the same direction to the electrophoretic element 32, and an image can be displayed with a uniform density.

Further, in the electrophoretic display device 100 of the present embodiment, the pixel electrode 35 is set to the same potential as the potential Vcom of the common electrode 37 or in a high impedance state in all periods in which the display state of the pixel 40 does not change, and the electrophoretic element. The electric field acts on 32 only when the display state changes from white display to black display or from black display to white display.
Then, since the electric field acting on the electrophoretic element 32 of the pixel 40 is reversed every time the display state is changed, the polarity of the pixel electrode 35 and the common electrode 37 can be avoided from being fixed. It is possible to make the electrochemical reaction in the common electrode 37 difficult to proceed. Therefore, the reliability of the electrode can be improved.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS.
FIG. 13 is a diagram illustrating a pixel circuit provided in the electrophoretic display device according to the second embodiment. FIG. 14 is a timing chart showing a driving method suitable for the electrophoretic display device according to the second embodiment.

  The basic configuration of the electrophoretic display device of this embodiment is the same as that of the electrophoretic display device 100 according to the first embodiment, and the only difference between the two is the configuration of the pixel circuit. Therefore, in the following description, unless otherwise specified, the electrophoretic display device 200 according to the present embodiment will be described as including the components of the electrophoretic display device 100 according to the first embodiment. In FIG. 13 and FIG. 14, the same reference numerals are given to the same components as those in the first embodiment, and detailed description thereof will be omitted.

An electrophoretic display device 200 according to the second embodiment includes a display unit 5 in which pixels 140 shown in FIG. 13 are arranged in a matrix.
The pixel 140 includes a first latch circuit LAT1, a first switch circuit SC1, a second latch circuit LAT2, a second switch circuit SC2A, a pixel electrode 35, an electrophoretic element 32, and a common electrode 37. And. The pixel 140 includes a scanning line 66, a first data line 68, a second data line 69, a high potential power line 50, a low potential power line 49, a first control line 91, and a second control line. 92 is connected.

The second switch circuit SC2A provided in the pixel 140 is configured by only the third transmission gate TG3. The output terminal of the first switch circuit SC1 is connected to the input terminal of the third transmission gate TG3, and the pixel electrode 35 is connected to the output terminal of the third transmission gate TG3.
That is, the pixel 140 has a configuration in which the third control line 93 and the fourth transmission gate TG4 of the pixel 40 are omitted from the electrophoretic display device 100 according to the first embodiment.

  The electrophoretic display device 200 of the present embodiment having the above configuration can display an image on the display unit 5 by being driven in the same manner as the electrophoretic display device 100 according to the first embodiment.

Specifically, the image signal Dx is input to the data input terminal N11 of the first latch circuit LAT1 via the first selection transistor ST1, and the image signal Dx is stored in the first latch circuit LAT1 as a potential. Further, the control signal Dp is input to the data input terminal N21 of the second latch circuit LAT2 via the second selection transistor ST2, and the control signal Dp is stored as a potential in the second latch circuit LAT2.
A predetermined potential is input to each of the first and second control lines 91 and 92 and the common electrode 37.

Then, the first switch line SC1 or the second control line 92 is operated by the first switch circuit SC1 that operates based on the potentials output from the data input terminal N11 and the data output terminal N12 of the first latch circuit LAT1. The second switch circuit SC2A is connected. Further, the first switch circuit SC1 and the pixel electrode 35 are connected by the second switch circuit SC2A that operates based on the potentials output from the data input terminal N21 and the data output terminal N22 of the second latch circuit LAT2. The
As a result, a potential corresponding to the image signal Dx is input to the pixel electrode 35 from the potentials S1 and S2 of the first or second control lines 91 and 92, and is common to the pixel electrode 35 as shown in FIG. The pixel 140 is displayed in black or white based on the potential difference from the electrode 37.

  FIG. 14 is a timing chart when the same display operation as that of the first embodiment is executed in the electrophoretic display device 200 according to the second embodiment. FIG. 14 corresponds to the flowchart shown in FIG. 8 and shows the potential of each part similar to the timing chart according to the first embodiment shown in FIG.

  As shown in FIG. 14, the operation in step S101 in the driving method of the present embodiment is the same as that of the driving method according to the first embodiment. The operations in steps S102 and S104 for holding an image are also the same as in the driving method according to the first embodiment.

Next, in step S103 in the driving method of the present embodiment, first, pixel control data Ds based on the image data DATA2 of the second image is generated in the pixel control data generation step ST30.
Also in the driving method of the present embodiment, the operation of the controller 63 shown in FIG. 6 is the same. That is, the image analysis circuit 167 that has received the supply of the image data DATA2 stores the image data DATA2 in the storage area, and then performs arithmetic processing on the image data DATA1 and the image data DATA2 held in the storage area. . As a result, the same pixel control data Ds as in step S103 of the first embodiment is generated and transmitted to the control circuit 161.

  Next, in the image signal input step ST31, the image signal Dx corresponding to the image data DATA2 of the second image is input to the first latch circuit LAT1 of the pixel 40, and the pixel control data Ds corresponds to the second latch circuit LAT2. The control signal Dp to be input is input.

The high level image signal Dx corresponding to the pixel data “1” (white) is input to the first latch circuit LAT1 of the pixels 40A and 40D belonging to the regions A and D shown in FIG. The low-level image signal Dx corresponding to the pixel data “0” (black) is input to the first latch circuits LAT1 of the pixels 40B and 40C belonging to B and C.
On the other hand, the low-level control signal Dp corresponding to the pixel data “0” is input to the second latch circuits LAT2 of the pixels 40A and 40B belonging to the regions A and B, and the pixels 40C and 40D belonging to the regions C and D are input. The second latch circuit LAT2 receives a high-level control signal Dp corresponding to the pixel data “1”.

  Next, when proceeding to the image display step ST32, as shown in FIG. 14, the high level potential VH is input to the first control line 91 (potential S1), and the low level is input to the second control line 92 (potential S2). The potential VL is input. Further, the common electrode 37 receives a rectangular wave pulse that repeats the high level potential VH and the low level potential VL in a predetermined cycle.

In the pixel 40A belonging to the region A, the pixel electrode 35 and the second control line are connected via the first and second switch circuits SC1 and SC2A that operate based on the outputs of the first and second latch circuits LAT1 and LAT2. 92 is electrically connected, the potential _VA of the pixel electrode 35 becomes the low level potential VL, and the pixel 40A is displayed in white.
Further, in the pixel 40B belongs to the area B, since the pixel electrode 35 and the first control line 91 is electrically connected, the potential V _B of the pixel electrode 35 becomes the high level potential VH. Thereby, the pixel 40B is displayed in black.

On the other hand, in the pixels 40C and 40D belonging to the regions C and D, since the second latch circuit LAT2 holds the high-level control signal Dp, the second switch circuit SC2A is turned off. Therefore, the pixel electrodes 35 of the pixels 40C and 40D are in a high impedance state that is electrically disconnected. Then, no voltage is applied to the electrophoretic elements 32 of the pixels 40C and 40D regardless of the potential Vcom of the common electrode 37, and the display state of the pixels 40C and 40D does not change and remains black and white, respectively. It is.
In this way, as shown in FIG. 9B, the second image in which the right areas A and D are displayed in white and the left areas B and C are displayed in black can be displayed on the display unit 5 as shown in FIG. it can.

Next, Step S105 in the driving method of the present embodiment is the same as Step S105 of the driving method according to the first embodiment.
First, in the pixel control data generation step ST50, the image analysis circuit 167 is based on the image data DATA3 of the third image input to the controller 63 and the image data DATA2 of the second image held in the image analysis circuit 167. Thus, pixel control data Ds is generated and transmitted to the control circuit 161.

Next, in the image signal input step ST51, the pixel 40 of the display unit 5 corresponds to the image signal Dx corresponding to the image data DATA3 of the third image and the pixel control data Ds generated by the image analysis circuit 167. A control signal Dp is input.
As a result, the high-level image signal Dx corresponding to the pixel data “1” (white) is input to the first latch circuits LAT1 of the pixels 40A and 40C belonging to the regions A and C shown in FIG. 9C. The low level image signal Dx corresponding to the pixel data “0” (black) is input to the first latch circuits LAT1 of the pixels 40B and 40D belonging to the regions B and D.
On the other hand, the high-level control signal Dp corresponding to the pixel data “1” is input to the second latch circuits LAT2 of the pixels 40A and 40B belonging to the regions A and B, and the pixels 40C and 40D belonging to the regions C and D are input. The second latch circuit LAT2 receives a low level control signal Dp corresponding to the pixel data “0”.

  Next, when proceeding to the image display step ST52, the high level potential VH is supplied to the first control line 91, and the low level potential VL is supplied to the second control line 92. In addition, a rectangular wave pulse that periodically repeats a high level potential VH and a low level potential VL is input to the common electrode 37.

In the pixel 40C in the region C, since the second control line 92 and the pixel electrode 35 are connected via the first and second switch circuits SC1 and SC2A, the potential V _C of the pixel electrode 35 is It becomes a low level potential VL. Therefore, the pixel 40C is displayed in white.
In the pixel 40D in the region D, since the first control line 91 and the pixel electrode 35 are connected, the potential V _D of the pixel electrode 35 becomes the high level potential VH. Accordingly, the pixel 40D is displayed in black.

  On the other hand, in the pixel 40A belonging to the region A, since the high-level image signal Dx is held in the first latch circuit LAT1, the second transmission gate TG2 of the first switch circuit SC1 is in the on state. In the pixel 40B belonging to the region B, since the low-level image signal Dx is held in the first latch circuit LAT1, the first transmission gate TG1 is in the ON state.

However, since the second latch circuit LAT2 of the pixels 40A and 40B holds the high-level control signal Dp, the second switch circuit SC2 is in the off state. Accordingly, the pixel electrodes 35 of the pixels 40A and 40B are in a high impedance state regardless of the state of the first switch circuit SC1. Therefore, substantially no voltage is applied to the electrophoretic elements 32 of the pixels 40A and 40B, and the display states of the pixels 40A and 40B do not change and remain white display and black display, respectively.
In this way, as shown in FIG. 9C, the third image in which the upper areas A and C are displayed in white and the lower areas B and D are displayed in black is displayed on the display unit 5.

As described above in detail, the electrophoretic display device 200 according to the second embodiment can perform the same display operation as the electrophoretic display device 100 according to the first embodiment.
In the image display step ST32 in step S103 and the image display step ST52 in step S105, the electric field does not act on the electrophoretic element 32 during the period in which the pixel electrode 35 is in a high impedance state. By acting, it is possible to prevent the pixel 40 from being overwritten. Therefore, also in the electrophoretic display device 200 according to the present embodiment, it is possible to obtain a display with high density and uniform density.

  Further, in the electrophoretic display device 200 of the present embodiment, it is not necessary to route the third control line 93 to the display unit 5, and the pixel circuit of the pixel 140 does not need the fourth transmission gate TG4. High definition is easy compared with the electrophoretic display device 100 according to the embodiment.

  Also, in the electrophoretic display device 200 of the present embodiment, similarly to the electrophoretic display device 100 according to the first embodiment, the electric field in the reverse direction is alternately applied to the electrophoretic elements 32 of all the pixels 140 for each synchronization period. Works. Accordingly, it is possible to prevent the polarity of the pixel electrode 35 and the common electrode 37 from being fixed, and it is possible to make it difficult for the electrochemical reaction in the common electrode 37 made of ITO or the like to proceed. Therefore, the reliability of the electrode can be improved.

[Electronics]
Next, the case where the electrophoretic display device 100 (200) of each of the above embodiments is applied to an electronic device will be described.
FIG. 15 is a front view of the wrist watch 1000. The wrist watch 1000 includes a watch case 1002 and a pair of bands 1003 connected to the watch case 1002.
A display unit 1005 including the electrophoretic display device 100 (200) of each of the above embodiments, a second hand 1021, a minute hand 1022, and an hour hand 1023 are provided on the front surface of the watch case 1002. On the side surface of the watch case 1002, a crown 1010 and an operation button 1011 are provided as operation elements. The crown 1010 is connected to a winding stem (not shown) provided inside the case, and is integrally provided with the winding stem so that it can be pushed and pulled in multiple stages (for example, two stages) and can be rotated. . The display unit 1005 can display a background image, a character string such as date and time, or a second hand, a minute hand, and an hour hand.

FIG. 16 is a perspective view illustrating a configuration of the electronic paper 1100. An electronic paper 1100 includes the electrophoretic display device 100 (200) of each of the above embodiments in a display area 1101.
The electronic paper 1100 is flexible and includes a main body 1102 made of a rewritable sheet having the same texture and flexibility as conventional paper.

  FIG. 17 is a perspective view showing the configuration of the electronic notebook 1200. An electronic notebook 1200 is obtained by bundling a plurality of the electronic papers 1100 and sandwiching them between covers 1201. The cover 1201 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

According to the wristwatch 1000, the electronic paper 1100, and the electronic notebook 1200 described above, since the electrophoretic display device according to the present invention is employed in the display unit, a display unit capable of high-quality display and excellent in reliability. It is an electronic device equipped with.
In addition, the electronic device shown in each figure illustrates the electronic device which concerns on this invention, and does not limit the technical scope of this invention. For example, the electrophoretic display device according to the present invention can be suitably used for a display portion of an electronic device such as a mobile phone or a portable audio device.

1 is a schematic configuration diagram of an electrophoretic display device 100 according to a first embodiment. The circuit block diagram of a pixel. The fragmentary sectional view of the electrophoretic display device in a display part. The schematic cross section of a microcapsule. Operation | movement explanatory drawing of an electrophoretic element. The block diagram which shows the detail of a controller. The figure used for operation | movement description of an image analysis circuit. The flowchart which shows the drive method which concerns on 1st Embodiment. Explanatory drawing which shows the display state corresponding to each step. The timing chart of the drive method which concerns on 1st Embodiment. The figure which shows the state of the pixel circuit corresponding to step S101. The figure which shows the state of the pixel circuit corresponding to step S103. FIG. 6 is a diagram illustrating a pixel circuit of an electrophoretic display device according to a second embodiment. The timing chart of the drive method which concerns on 2nd Embodiment. The front view of the wristwatch which is an example of an electronic device. The perspective view of the electronic paper which is an example of an electronic device. The perspective view of the electronic notebook which is an example of an electronic device.

Explanation of symbols

  100, 200 electrophoretic display device, 5 display unit, 32 electrophoretic element, 35 pixel electrode, 37 common electrode (counter electrode), 40, 40A, 40B, 40C, 40D, 140 pixel, 49 low potential power line, 50 high Potential power supply line, 61 scan line drive circuit, 62 data line drive circuit, 63 controller (control unit), 91 first control line, 92 second control line, 93 third control line, 161 control circuit, 162 EEPROM (Storage unit), 163 voltage generation circuit, 164 data buffer, 165 frame memory, 166 memory control circuit, 167 image analysis circuit (image analysis unit), Dat, DAT1, DAT2, DATA1, DATA2, DATA3 image data, Ds pixel control Data, Dx image signal, Dp control signal, LAT1 first latch circuit (first memory Memory circuit), LAT2 second latch circuit (second memory circuit), SC1 first switch circuit, SC2, SC2A second switch circuit, ST1 first selection transistor (first switching element), ST2 first 2 selection transistors (second switching elements), TG1, TG2, TG3, TG4 Transmission gate

Claims (12)

An electrophoretic display device having an electrophoretic element including electrophoretic particles between a pair of substrates and having a display unit composed of a plurality of pixels,
For each pixel, a pixel electrode, a first memory circuit, a first switching element connected to the first memory circuit, a second memory circuit, and a second memory circuit A second switching element; a first switch circuit connected to the first memory circuit; a second switch circuit connected to the second memory circuit, the first switch circuit, and the pixel electrode; And comprising
An electrophoretic display device comprising first and second control lines connected to the first switch circuit. The second switch circuit is a transmission gate;
2. The electrophoretic display device according to claim 1, wherein the output terminal of the first switch circuit is connected to the input terminal of the transmission gate, and the pixel electrode is connected to the output terminal.   The electrophoretic display device according to claim 1, further comprising a third control line connected to the second switch circuit. The second switch circuit comprises first and second transmission gates;
An output terminal of the first switch circuit is connected to an input terminal of the first transmission gate;
The third control line is connected to an input terminal of the second transmission gate;
4. The electrophoretic display device according to claim 3, wherein the pixel electrode is connected to output terminals of the first and second transmission gates. A counter electrode sandwiching the electrophoretic element together with the pixel electrode;
5. The electrophoretic display device according to claim 3, wherein a signal synchronized with a signal input to the counter electrode can be input to the third control line. 6. A first data line connected to a data input terminal of the first memory circuit via the first switching element;
A second data line connected to the data input terminal of the second memory circuit via the second switching element;
The electrophoretic display device according to claim 1, comprising: An image analysis unit that generates pixel control data corresponding to a control signal supplied to the second data line;
The image analysis unit compares the first image data to be displayed and the second image data immediately before the first image data with pixel data corresponding to the same pixel,
The pixel control data including the data string of the control pixel data is generated by generating the control pixel data by changing the gradation between the case where the gradations match and the case where the gradations do not match in the comparison between the pixel data. The electrophoretic display device according to claim 6, wherein the electrophoretic display device is generated. An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and a display unit including a plurality of pixels is provided. For each pixel, a pixel electrode, a first memory circuit, and the first memory circuit A first switching element connected to the second switching circuit, a second memory circuit, a second switching element connected to the second memory circuit, and a first switching circuit connected to the first memory circuit. And a second switch circuit connected to the pixel electrode, and a first control circuit connected to the first switch circuit, and a second control circuit connected to the first switch circuit. A method for driving an electrophoretic display device having lines,
When the image signal input to the first memory circuit via the first switching element has the same gradation as the image signal held in the first memory circuit,
A driving method of an electrophoretic display device, wherein a control signal for outputting a signal for turning off the second switch circuit is input to the second memory circuit. An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and a display unit including a plurality of pixels is provided. For each pixel, a pixel electrode, a first memory circuit, and the first memory circuit A first switching element connected to the second switching circuit, a second memory circuit, a second switching element connected to the second memory circuit, and a first switching circuit connected to the first memory circuit. And a second switch circuit connected to the pixel electrode, and a first control circuit connected to the first switch circuit, and a second control circuit connected to the first switch circuit. A method of driving an electrophoretic display device comprising: a line; and a third control line connected to the second switch circuit,
When the image signal input to the first memory circuit via the first switching element has the same gradation as the image signal held in the first memory circuit,
A control signal for outputting a signal for connecting the third control line and the pixel electrode is input to the second memory circuit via the second switch circuit. Driving method. A counter electrode that sandwiches the electrophoretic element together with the pixel electrode is formed on the substrate,
The driving method of the electrophoretic display device according to claim 9, wherein a signal synchronized with a signal input to the counter electrode is input to the third control line.   The method for driving an electrophoretic display device according to claim 9, wherein in the step of displaying an image on the display unit, the third control line is held in a high impedance state.   An electronic apparatus comprising the electrophoretic display device according to claim 1.

Images