JP2009198689A - Electrophoretic display apparatus and its driving method, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrophoretic display apparatus excellent in operation reliability such that writing of data in a memory circuit and holding of data are ensured. <P>SOLUTION: In the electrophoretic display, selection transistors 41a and 41b (pixel switching element) are single gate transistors. During an image display period ST12 of time when images are displayed by driving at least electrophoretic elements 32, data lines 68a and 68b connected to the source terminals of the selection transistors 41a and 41b of a single gate are held at an intermediate potential VD between the low level VL and the high level potential VH at which they are held by latch circuits 70a and 70b (memory circuit). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electrophoretic display device, a driving method thereof, and an electronic apparatus.

2. Description of the Related Art As an active matrix electrophoretic display device, one having a switching transistor and a memory circuit (SRAM: Static Random Access Memory) in a pixel is known (see Patent Document 1). The display device described in Patent Document 1 includes a configuration in which microcapsules containing charged particles are bonded to a substrate on which switching transistors and pixel electrodes are formed, and includes a pixel electrode and a common electrode sandwiching the microcapsules. An image was displayed by controlling charged particles by an electric field generated between them.
JP 2003-84314 A

  In the electrophoretic display device described in Patent Document 1, in order to display black and white of an image, one of black and white binary values is stored as a potential (high level / low level) in an SRAM (latch circuit) provided in the pixel. To do. Here, FIG. 22A is a diagram illustrating a pixel configuration of an electrophoretic display device including a latch circuit. A pixel 400 illustrated in FIG. 22A includes a selection transistor 441 connected to the scanning line 66 and the data line 68, and a latch circuit 70 connected between the selection transistor 41 and the pixel electrode 35. The selection transistor 441 is a double-gate N-MOS (Negative Metal Oxide Semiconductor) transistor. Note that details of each part constituting the pixel 400 have been described with reference to FIG. 2 in the subsequent embodiment.

In the pixel 400, when data is stored in the latch circuit 70, a sufficient current needs to flow from the data line 68 to the latch circuit 70 via the selection transistor 441.
For example, in order to write a high-level (H) image signal, a sufficient current is supplied to the low-potential power line 49 through the selection transistor 441 and the N-MOS transistor 74 of the feedback inverter 70f, and the drain potential of the N-MOS transistor 74 is increased. The logic threshold of the latch circuit 70 must be exceeded. If this current is insufficient, the drain potential of the N-MOS transistor 74 does not exceed the threshold value of the transfer inverter 70t, and data cannot be written to the latch circuit 70.
Similarly, when a low level (L) image signal is written, a sufficient current is supplied to the data line 68 through a P-MOS (Positive Metal Oxide Semiconductor) transistor 73 and a selection transistor 441 of the latch circuit 70, and The logic must be switched.

  However, since the pixel 400 uses a double gate transistor as the selection transistor 441, the on-resistance is large, and it is difficult to secure an on-current. In particular, when a selection transistor or a latch circuit transistor is formed using a low-temperature polysilicon film, the on-resistance of the transistor tends to be nonuniform. For this reason, the ON current of the selection transistor 441 is insufficient due to manufacturing variations, and the pixels 400 that fail to write data to the latch circuit 70 are likely to occur.

In order to secure a sufficient on-current in the selection transistor 441, it is a simple measure to employ a single-gate selection transistor 441s as shown in FIG. However, in this case, insufficient voltage resistance of the single gate transistor may be a problem.
More specifically, after the image signal is written in the latch circuit 70, the voltage between the latch circuit 70 and the data line 68 is applied to the selection transistor 441s in the off state. In order to prevent the potential of the latch circuit 70 (the potential of the data input terminal N1) from changing, it is necessary to have a sufficient withstand voltage. In this regard, the double gate selection transistor 441 shown in FIG. 22A can ensure a sufficient withstand voltage margin, but the single gate selection transistor 441s may have insufficient withstand voltage.

  The present invention has been made in view of the above-mentioned problems of the prior art, and provides an electrophoretic display device excellent in operation reliability capable of reliably writing data to a memory circuit and a driving method thereof. One of the purposes.

In order to solve the above problems, an electrophoretic display device of the present invention has an electrophoretic element including electrophoretic particles between a pair of substrates, and has a display unit including a plurality of pixels. In addition, a pixel electrode, a pixel switching element, and a memory circuit connected between the pixel electrode and the pixel switching element are provided, and the pixel switching element is a single gate transistor. The data line connected to the source terminal of the single gate transistor is connected to the high level potential VH and the low level held in the memory circuit at least during a period in which the electrophoretic element is driven to display an image on the display unit. It is characterized by being held at a potential VD that is intermediate to the potential VL.
In this configuration, the potential of the data line is held at an intermediate potential VD between the high level potential VH and the low level potential VL in an image display period in which the data input terminal of the memory circuit is at a relatively high potential. Thereby, the voltage applied between the source and the drain of the selection transistor during the same period becomes (VH−VD) or (VD−VL). Therefore, the voltage applied to the selection transistor is lower by the potential VD than when the data line is held at the low level during the image display period.
Therefore, according to the present invention, the withstand voltage of the selection transistor can be made lower than the high level voltage VH, and the margin of the withstand voltage of the selection transistor is increased. Therefore, the selection transistor has a single gate structure. The problem of withstand voltage can be avoided.
As described above, according to the present invention, since the selection transistor has a single gate structure, sufficient current driving capability can be secured, and the problem of withstand voltage in the single gate transistor can be avoided, so that excellent operation reliability is achieved. Can be realized.

A data line driver circuit that inputs an image signal to the data line is connected exclusively to the data line, and may include a protective potential wiring that supplies the potential VD to the data line.
According to this configuration, since the potential VD is supplied by the protective potential wiring provided independently of the data line driving circuit, the potential VD can be supplied to the data line regardless of the operating state of the data line driving circuit. Even in a relatively long image display period, the potential of the data line can be reliably held.

The potential VD is not less than 2/3 and not more than 3/2 of an intermediate potential (VH + VL) / 2 between the high-level potential VH and the low-level potential VL held in the memory circuit during the image display period. preferable.
With such a configuration, the voltage applied to the selection transistor can be 2/3 or less of the difference (VH−VL) between the high level potential VH and the low level potential VL. The required withstand voltage can be lowered by 30% or more. Therefore, according to this configuration, better operational reliability can be obtained.

The potential VD is preferably (VH + VL) / 2.
With this configuration, the voltage applied between the source and drain of the selection transistor is minimized regardless of the potential (high level potential VH, low level potential VL) held in the memory circuit. The margin of the withstand voltage of the transistor can be maximized. Therefore, according to this configuration, further excellent operational reliability can be obtained.

The potential VD may be a high level potential VM of an image signal input to the memory circuit through the data line.
According to this configuration, since the data line is held at the high level potential of the image signal during the image display period, it is possible to apply the potential VD to the data line using a normally provided data line driving circuit.

The potential VD is within a withstand voltage range of a data line driving circuit for inputting an image signal to the data line, and a high level potential VH and a low level potential VL held in the memory circuit in a period for displaying the image It is preferable that the potential is close to the intermediate potential (VH + VL) / 2.
According to this configuration, when the potential VD is input to the data line by the data line driving circuit, the voltage applied between the source and drain of the selection transistor can be minimized. Therefore, it is possible to secure the maximum withstand voltage margin of the selection transistor while minimizing structural changes.

It is preferable to have a buffer circuit connected to the data line.
When the potential VD is input to the data line by driving the data line driving circuit, it is preferable that the signal for supplying the potential VD is current-amplified by a buffer circuit connected to the data line. As a result, the potential VD can be prevented from decreasing during the image display period, and the leakage of the selection transistor can be effectively prevented.

Next, the driving method of the electrophoretic display device of the present invention includes an electrophoretic element including electrophoretic particles between a pair of substrates, a display unit including a plurality of pixels, and for each pixel, A method for driving an electrophoretic display device, comprising: a pixel electrode; a pixel switching element; and a memory circuit connected between the pixel electrode and the pixel switching element. The pixel switching element is a single gate transistor. Then, the step of displaying an image on the display unit is configured to apply an voltage to the pixel electrode based on an image signal input period in which an image signal is input to the memory circuit, and an output of the memory circuit. An image display period for driving to display an image, and at least in the image display period, the source terminal of the single gate transistor The connection data line, characterized in that retaining the higher potential VD than the low level electric potential VL is held in the memory circuit in the image display period.
According to this driving method, since the data line is held at the potential VD during the image display period, the voltage applied between the source and drain of the selection transistor during the synchronization can be lowered by the amount of the potential VD. Therefore, it is possible to avoid the problem of withstand voltage caused by adopting a single gate structure for the selection transistor.
Therefore, in this driving method, a sufficient current driving capability can be ensured by making the selection transistor a single gate structure, and the problem of withstand voltage in the single gate transistor can be avoided, so that excellent operation reliability can be obtained. This is a driving method that can

The potential VD is preferably not less than 2/3 and not more than 3/2 of an intermediate potential (VH + VL) / 2 between the high level potential VH and the low level potential VL held in the memory circuit in the image display period.
According to this driving method, the voltage applied to the selection transistor can be 2/3 or less of the difference (VH−VL) between the high level potential VH and the low level potential VL. The withstand voltage can be reduced by 30% or more. Therefore, according to this driving method, more excellent operation reliability can be obtained.

The potential VD is preferably (VH + VL) / 2.
According to this driving method, the voltage applied between the source and drain of the selection transistor is minimized regardless of the potential (high level potential VH, low level potential VL) held in the memory circuit. A large margin of withstand voltage can be obtained. Therefore, according to this driving method, further excellent operational reliability can be obtained.

A driving method in which the high-level potential VM of the image signal input to the memory circuit via the data line may be employed.
According to this driving method, since the data line is held at the high level potential of the image signal during the image display period, the driving method is capable of applying the potential VD to the data line using a normally provided data line driving circuit. can do.

The potential VD is within the range of the withstand voltage of the data line driving circuit that supplies an image signal to the data line, and is intermediate between the high level potential VH and the low level potential VL held in the memory circuit in the image display period. It is preferably a potential close to the potential (VH + VL) / 2.
According to this driving method, when the potential VD is input to the data line by the data line driving circuit, the voltage applied between the source and drain of the selection transistor can be minimized. Therefore, the driving method configuration is capable of ensuring the maximum withstand voltage margin of the selection transistor while minimizing structural changes.

  Next, an electronic apparatus according to the present invention includes the electrophoretic display device described above. According to this configuration, it is possible to provide an electronic device including a display unit having excellent operation reliability.

Hereinafter, an active matrix electrophoretic display device according to the present invention will be described with reference to the drawings.
Note that this embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. Moreover, in the following drawings, in order to make each configuration easy to understand, the actual structure is different from the scale and number of each structure.

(First embodiment)
FIG. 1 is a schematic configuration diagram of an electrophoretic display device 100 according to the embodiment.
The electrophoretic display device 100 includes a display unit 5 in which a plurality of pixels 40 are arranged in a matrix. Around the display unit 5, a scanning line driving circuit 61, a first data line driving circuit 62, a second data line driving circuit 162, a controller (control unit) 63, and a common power supply modulation circuit 64 are arranged. . The scanning line drive circuit 61, the first data line drive circuit 62, the second data line drive circuit 162, and the common power supply modulation circuit 64 are each connected to the controller 63. The controller 63 comprehensively controls these circuits based on image data and synchronization signals supplied from the host device.

  A plurality of scanning lines 66 extending from the scanning line driving circuit 61 and a plurality of data lines 68 extending from the first data line driving circuit 62 are formed in the display unit 5, and pixels corresponding to these intersection positions are formed. 40 is provided.

  The scanning line driving circuit 61 is connected to each pixel 40 via m scanning lines 66 (Y1, Y2,..., Ym). Under the control of the controller 63, the first to mth rows are connected. The scanning lines 66 are sequentially selected, and a selection signal defining the ON timing of the selection transistor 41 (see FIG. 2) provided in the pixel 40 is supplied via the selected scanning line 66.

  The first data line driving circuit 62 is connected to each pixel 40 via n data lines 68 (X1, X2,..., Xn), and each pixel 40 is controlled under the control of the controller 63. An image signal defining 1-bit pixel data corresponding to is supplied to the pixel 40. The first data line driving circuit 62 includes a driver circuit 263 and a plurality of first switching elements 67 provided corresponding to each data line 68, and is directly connected to each data line 68. It is a drive circuit of the form which inputs an image signal.

The driver circuit 263 switches the first switching element 67 based on a control signal input from the controller 63. As a result, the data line 68 and the data signal wiring 167 are electrically connected via the first switching element 67, and an image signal is supplied from the data signal wiring 167 to the data line 68.
In the present embodiment, a low level (L) image signal is supplied to the pixel 40 when the pixel data “0” is defined, and a high level (H) image is defined when the pixel data “1” is defined. It is assumed that a signal is supplied to the pixel 40.

  The second data line driving circuit 162 is provided on the side opposite to the first data line driving circuit 62 with respect to the display unit 5, and a second switching provided corresponding to each data line 68. An element 65 is provided. The second switching element 65 is connected to the end of the data line 68 opposite to the first switching element 67 and is an element for switching electrical connection and disconnection between the data line 68 and the protective potential wiring 58. is there. The protective potential wiring 58 is connected to the common power supply modulation circuit 64.

The second data line driving circuit 162 connects the data line 68 and the protection potential wiring 58 via the second switching element 65 under the control of the controller 63, and the protection potential wiring 58 with respect to the data line 68. Input the potential.
Note that the second data line driver circuit 162 may include a driver circuit (263) similar to the first data line driver circuit 62, and a plurality of second data line driver circuits 162 may be controlled by a control signal input from the controller 63. It is good also as a structure which switches the switching element 65 collectively.

  The display unit 5 is also provided with a low potential power line 49, a high potential power line 50, and a common electrode wiring 55 extending from the common power modulation circuit 64, and each wiring is connected to the pixel 40. Under the control of the controller 63, the common power supply modulation circuit 64 generates various signals to be supplied to each of the above wirings, and electrically connects and disconnects these wirings (high impedance).

FIG. 2 is a circuit configuration diagram of the pixel 40.
The pixel 40 is provided with a selection transistor (Thin Film Transistor) 41 (pixel switching element), a latch circuit (memory circuit) 70, an electrophoretic element 32, a pixel electrode 35, and a common electrode 37. A scanning line 66, a data line 68, a low potential power line 49, and a high potential power line 50 are arranged so as to surround these elements. The pixel 40 has an SRAM (Static Random Access Memory) type configuration in which the latch circuit 70 holds an image signal as a potential.

  The selection transistor 41 is a pixel switching element composed of a single gate N-MOS (Negative Metal Oxide Semiconductor) transistor. The selection transistor 41 has a gate terminal connected to the scanning line 66, a source terminal connected to the data line 68, and a drain terminal connected to the data input terminal N 1 of the latch circuit 70. The data output terminal N2 of the latch circuit 70 is connected to the pixel electrode 35. The electrophoretic element 32 is sandwiched between the pixel electrode 35 and the common electrode 37.

  The latch circuit 70 includes a transfer inverter 70t and a feedback inverter 70f. Both the transfer inverter 70t and the feedback inverter 70f are C-MOS inverters. The transfer inverter 70t and the feedback inverter 70f have a loop structure in which the other output terminal is connected to each other's input terminal, and each inverter has a high potential connected via a high potential power supply terminal PH. A power supply voltage is supplied from the power supply line 50 and the low potential power supply line 49 connected via the low potential power supply terminal PL.

  The transfer inverter 70t includes a P-MOS (Positive Metal Oxide Semiconductor) transistor 71 and an N-MOS transistor 72 each having a drain terminal connected to the data output terminal N2. The source terminal of the P-MOS transistor 71 is connected to the high potential power supply terminal PH, and the source terminal of the N-MOS transistor 72 is connected to the low potential power supply terminal PL. The gate terminals of the P-MOS transistor 71 and the N-MOS transistor 72 (input terminal of the transfer inverter 70t) are connected to the data input terminal N1 (output terminal of the feedback inverter 70f).

  The feedback inverter 70f has a P-MOS transistor 73 and an N-MOS transistor 74 whose drain terminals are connected to the data input terminal N1. The gate terminals of the P-MOS transistor 73 and the N-MOS transistor 74 (input terminal of the feedback inverter 70f) are connected to the data output terminal N2 (output terminal of the transfer inverter 70t).

  When the high-level (H) image signal (pixel data “1”) is stored in the latch circuit 70 configured as described above, a low-level (L) signal is output from the data output terminal N2 of the latch circuit 70. . On the other hand, when a low level (L) image signal (pixel data “0”) is stored in the latch circuit 70, a high level (H) signal is output from the data output terminal N2.

  The pixel electrode 35 is an electrode for applying a voltage to the electrophoretic element 32 formed of Al (aluminum) or the like. The common electrode 37 is an electrode for applying a voltage to the electrophoretic element 32 together with the pixel electrode 35, and is formed of MgAg (magnesium silver), ITO (indium tin oxide), IZO (indium zinc oxide) or the like. It is a transparent electrode. A common electrode potential Vcom is supplied to the common electrode 37 via the common electrode wiring 55. The electrophoretic element 32 displays an image by an electric field generated by a potential difference between the pixel electrode 35 and the common electrode 37.

  FIG. 3 is a partial cross-sectional view of the electrophoretic display device 100 in the display unit 5. The electrophoretic display device 100 has a configuration in which an electrophoretic element 32 formed by arranging a plurality of microcapsules 20 is sandwiched between an element substrate 30 and a counter substrate 31. In the display unit 5, a plurality of pixel electrodes 35 are arranged on the electrophoretic element 32 side of the element substrate 30, and the electrophoretic elements 32 are bonded to the pixel electrodes 35 through an adhesive layer 33. A common electrode 37 having a planar shape facing the plurality of pixel electrodes 35 is formed on the electrophoretic element 32 side of the counter substrate 31, and the electrophoretic element 32 is provided on the common electrode 37.

  The element substrate 30 is a substrate made of glass, plastic, or the like and is not required to be transparent because it is disposed on the side opposite to the image display surface. Although not shown, the scanning line 66, the data line 68, the selection transistor 41, the latch circuit 70, and the like shown in FIGS. 1 and 2 are formed between the pixel electrode 35 and the element substrate 30. . On the other hand, the counter substrate 31 is a substrate made of glass, plastic, or the like, and is a transparent substrate because it is disposed on the image display side.

  In general, the electrophoretic element 32 is formed in advance on the counter substrate 31 side, and is handled as an electrophoretic sheet including the adhesive layer 33. In the manufacturing process, the electrophoretic sheet is handled in a state where a protective release sheet is attached to the surface of the adhesive layer 33. And the display part 5 is formed by sticking the said electrophoretic sheet which peeled the release sheet with respect to the element board | substrate 30 (The pixel electrode 35, various circuits, etc.) which were manufactured separately. For this reason, the adhesive layer 33 exists only on the pixel electrode 35 side.

  FIG. 4 is a schematic cross-sectional view of the microcapsule 20. The microcapsule 20 has a particle size of, for example, about 50 μm and encloses therein a dispersion medium 21, a plurality of white particles (electrophoretic particles) 27, and a plurality of black particles (electrophoretic particles) 26. It is a spherical body. As shown in FIG. 3, the microcapsule 20 is sandwiched between the common electrode 37 and the pixel electrode 35, and one or more microcapsules 20 are arranged in one pixel 40.

The outer shell portion (wall film) of the microcapsule 20 is formed using a translucent polymer resin such as an acrylic resin such as polymethyl methacrylate or polyethyl methacrylate, a urea resin, or gum arabic.
The dispersion medium 21 is a liquid that disperses the white particles 27 and the black particles 26 in the microcapsules 20. Examples of the dispersion medium 21 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.). ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrachloride) Element, and 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

The white particles 27 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 26 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used by being charged positively, for example.
These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.
Further, instead of the black particles 26 and the white particles 27, for example, pigments such as red, green, and blue may be used. According to such a configuration, red, green, blue, or the like can be displayed on the display unit 5.

FIG. 5 is an operation explanatory diagram of the electrophoretic element. FIG. 5A shows the case where the pixel 40 displays white, and FIG. 5B shows the case where the pixel 40 displays black.
In the electrophoretic display device 100, an image signal is input to the data input terminal N1 of the latch circuit 70 via the selection transistor 41, and the image signal is stored in the latch circuit 70 as a potential. As a result, a potential corresponding to the image signal is input from the data output terminal N2 of the latch circuit 70 to the pixel electrode 35, and the pixel 40 is blackened based on the potential difference between the pixel electrode 35 and the common electrode 37 as shown in FIG. Or it is displayed in white.

5A, the common electrode 37 is held at a relatively high potential and the pixel electrode 35 is held at a relatively low potential. As a result, the negatively charged white particles 27 are attracted to the common electrode 37, while the positively charged black particles 26 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side which is the display surface side, white (W) is recognized.
In the case of black display shown in FIG. 5B, the common electrode 37 is held at a relatively low potential, and the pixel electrode 35 is held at a relatively high potential. As a result, the positively charged black particles 26 are attracted to the common electrode 37, while the negatively charged white particles 27 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side, black (B) is recognized.

[Driving method]
Next, FIG. 6 is a timing chart showing a driving method of the electrophoretic display device 100 having the above configuration. As shown in FIG. 6, in the driving method of the present embodiment, the electrophoretic element 32 is driven by the image signal input period ST <b> 11 in which an image signal is input to the latch circuit 70 of the pixel 40 and the potential difference between the pixel electrode 35 and the common electrode 37. It includes an image display period ST12 in which an image is displayed on the display unit 5 by driving, and an image holding period ST13 in which an image displayed on the display unit 5 is held.

FIG. 7 is a diagram illustrating a potential state of the two pixels 40A and 40B in the image signal input period ST11. FIG. 8 is a diagram illustrating a potential state of the pixels 40A and 40B in the image display period ST12.
In FIGS. 7 and 8, the subscripts “A”, “B”, “a”, and “b” of the reference numerals indicate the two pixels 40 (40A, 40B) that are the objects of the description and the components that belong to them. It is given for clear distinction and has no other intention.

  6 shows the potential G of the scanning line 66, the potential Vdd of the high potential power supply line 50, the potential Vss of the low potential power supply line 49, the potential Da of the data line 68a connected to the pixel 40A, and the data connected to the pixel 40B. The potential Db of the line 68b, the potential of the data input terminal N1a of the latch circuit 70a, the potential of the data input terminal N1b of the latch circuit 70b, the potential Vcom of the common electrode 37, the potential Va of the pixel electrode 35a, and the potential Vb of the pixel electrode 35b. It is shown.

  In the state shown in FIG. 7, the pixel 40A is displayed in white and the pixel 40B is displayed in black. FIG. 6 is a timing chart when the pixels 40A and 40B are updated to black display and white display, respectively. In FIG. 8, the pixel 40A updated to black display in the image display period ST12 and white display are updated. A pixel 40B is shown.

  First, in the display unit 5 before the image signal input period ST11, as shown in FIG. 6, after the image display in the previous frame is performed, each wiring is electrically connected to hold the image without consuming power. The high impedance state (Hi-Z) is disconnected. The same is true when the electrophoretic display device 100 is in the power-off state.

In order to display an image on the display unit 5 in such a state, first, in the image signal input period ST11, each wiring of each drive circuit is electrically connected to enable a signal input, and the latch circuit By supplying a power supply voltage to 70, an image signal can be stored.
In the present embodiment, the potential G of the scanning line 66 and the potentials Da and Db of the data lines 68a and 68b are both at a low level (L; 0V), and the potential Vdd of the high potential power supply line 50 is used for image signal input. The high level potential VM (for example, 5V) is set to be low, and the potential Vss of the low potential power line 49 is set to the low level potential VL (0V).

  In the present embodiment, it is assumed that the low level (L) potential of the data line 68 and the low level potential VL of the low potential power supply line 49 are both 0 (zero) V. Further, the potentials of 0V, 5V, 15V, etc. shown in each part of FIG. 6 are given as an example for explaining the invention, and the potential of each wiring is not limited to these specific numerical values. .

  Thereafter, an image signal is input to the latch circuit 70 of each pixel 40. Specifically, a high level (H) pulse as a selection signal is input from the scanning line driving circuit 61 to the scanning line 66, and the selection transistor 41 of the pixel 40 is turned on. Further, an image signal synchronized with the selection operation by the scanning line driving circuit 61 is supplied from the first data line driving circuit 62 to the data line 68 and is connected to the data line 68 through the selection transistor 41 in the on state. The image signal is input to the latch circuit 70.

In the pixel 40A updated to black display by the above image signal input operation, a low level (L) image signal is input from the data line 68a to the latch circuit 70a via the selection transistor 41a, and the data input to the latch circuit 70a is performed. The potential of the terminal N1a becomes low level (L), and the potential of the data output terminal N2a becomes high level (H).
On the other hand, in the pixel 40B, a high level (H) image signal is input from the data line 68b to the latch circuit 70b via the selection transistor 41b, and the potential of the data input terminal N1b of the latch circuit 70b is high level (H). The potential of the output terminal N2b becomes low level (L).

In the image signal input period ST11, as shown in FIG. 7, the second switching element 65 of the second data line driving circuit 162 is in an OFF state.
Further, in the image signal input period ST11, the potential Va of the pixel electrode 35a connected to the latch circuit 70a becomes a high-level potential VM (for example, 5V) for image signal input, and the pixel electrode 35b connected to the latch circuit 70b Although the potential Vb becomes the low level potential VL (0 V), the display state of the electrophoretic element 32 does not change because the common electrode 37 is in a high impedance state.

If an image signal is input to each of the pixels 40A and 40B, the process proceeds to the image display period ST12.
In the image display period ST12, the potential Vdd of the high potential power supply line 50 is raised from the high level potential VM (for example, 5V) for image signal input to the high level potential VH (for example, 15V) for image display. The potential Vss of the power supply line 49 is set to a low level potential VL (0 V). In addition, a rectangular pulse that repeats the high level potential VH and the low level potential VL in a predetermined cycle is input to the common electrode 37.

  Thereby, in the pixel 40A, the potential of the data output terminal N2a of the latch circuit 70a rises to the high level potential VH, and the potential Va of the pixel electrode 35a becomes the high level potential VH. The electrophoretic element 32 is driven by the potential difference between the pixel electrode 35 a and the common electrode 37 during a period in which the common electrode 37 to which the rectangular pulse is input is at the low level potential VL. That is, as shown in FIG. 5B, the positively charged black particles 26 are attracted to the common electrode 37 side, the negatively charged white particles 27 are attracted to the pixel electrode 35a side, and the pixel 40A is black. Is displayed.

  On the other hand, in the pixel 40B, since the data output terminal N2b of the latch circuit 70 is at the low level potential VL, the potential Vb of the pixel electrode 35b is also at the low level potential VL. The electrophoretic element 32 is driven by the potential difference between the pixel electrode 35 b and the common electrode 37 during a period in which the common electrode 37 is at the high level potential VH. That is, as shown in FIG. 5A, the negatively charged white particles 27 are attracted to the common electrode 37 side, the positively charged black particles 26 are attracted to the pixel electrode 35a side, and the pixel 40B is white. Is displayed.

Further, in the case of the present embodiment, in the image display period ST12, as shown in FIG. 8, the first switching element 67 (67a, 67b) of the first data line driving circuit 62 is turned off, while the second The second switching element 65 of the data line driving circuit 162 is turned on. In addition, a predetermined protection potential VD is supplied from the common power supply modulation circuit 64 to the protection potential wiring 58.
Thereby, all the data lines 68 are electrically connected to the protection potential wiring 58 via the second switching element 65, and the protection potential VD of the protection potential wiring 58 is inputted to the data lines 68 (68a, 65b). Is done. Specifically, a potential (VH / 2) that is ½ of the high-level potential VH for image display is input to the data line 68 as the protective potential VD.
Since the first switching element 67 and the second switching element 65 are exclusively turned on / off as described above, the image signal and the protection potential VD are simultaneously supplied to the data line 68. There is no end to it.

Through the series of operations in the image signal input period ST11 and the image display period ST12, an image based on the image data can be displayed on the display unit 5.
When the image display operation is completed, as shown in FIG. 6, the process proceeds to an image holding period ST13. In the image holding period ST13, each wiring connected to the pixel 40 is in a high impedance state. Accordingly, the pixel electrodes 35a and 35b and the common electrode 37 are in a high impedance state, and the electrophoretic element 32 is electrically isolated. Therefore, an image can be held without consuming power.

  According to the electrophoretic display device of this embodiment described in detail above, an image signal can be reliably written to the latch circuit 70 in the image signal input period ST11, and the driving method of this embodiment is employed. Thus, the potential fluctuation of the latch circuit 70 in the image display period ST12 can also be suppressed. Therefore, according to the present embodiment, an electrophoretic display device excellent in operation reliability can be realized. Hereinafter, this function and effect will be described in detail.

  First, in the electrophoretic display device 100 of the present embodiment, the pixel 40 is provided with a selection transistor 41 that is a single-gate N-MOS transistor. Since the single-gate structure selection transistor 41 has a lower on-resistance than the double-gate structure selection transistor 441 shown in FIG. 22A, latching is performed when an image signal is input to the latch circuit 70 in the image signal input period ST11. A sufficient current can be passed through the P-MOS transistor 73 or the N-MOS transistor 74 of the circuit 70. Therefore, in the pixel 40 according to the present embodiment, the potential of the data input terminal N1 of the latch circuit 70 can be reliably defined, and the image signal can be stored as a potential.

  On the other hand, when the selection transistor 41 has a single gate structure, the withstand voltage of the selection transistor 41 becomes a problem. That is, in the double gate structure, the voltage between the source and the drain is divided and applied to two channels, so that it is easy to ensure the withstand voltage. However, in the single gate structure, the above voltage is applied to one channel, so It is easy to run out of voltage. Therefore, in the electrophoretic display device 100 of the present embodiment, as shown in FIG. 8, the protective potential VD is input to the data line 68 in the image display period ST12, and the voltage applied between the source and drain of the selection transistor 41 is set. Thus, it is possible to avoid the occurrence of problems due to the provision of the selection transistor 41 having a single gate structure.

Specifically, in the image display period ST12, all the data lines 68 of the display unit 5 are connected to the protective potential wiring 58 via the second switching element 65, and the potential of the data line 68 is set to 1/2 of the high level potential VH. It was decided to hold at the potential. As a result, the voltage applied to the selection transistor 41 is ½ that when no potential is input to the data line 68 (when 0 V is applied).
In the pixel 40A displayed in black shown in FIG. 8, since the potential of the data input terminal N1a is the low level potential VL (0 V), the voltage applied between the source and drain of the selection transistor 41a is VH / 2. . If the high level potential VH is 15V, the voltage applied to the selection transistor 41a is 7.5V.
On the other hand, in the pixel 40B that displays white, since the potential of the data input terminal N1b is the high level potential VH (for example, 15V), the voltage applied between the source and drain of the selection transistor 41b is still VH / 2 (for example, 7V). .5V).

As described above, according to the driving method of the present embodiment, the voltage applied to the selection transistor 41 in the image display period ST12 can be reduced. For example, the withstand voltage of the selection transistor 41 is higher than the high level potential VH due to manufacturing variations. However, if the withstand voltage is higher than VH / 2, the occurrence of leakage in the select transistor 41 can be prevented.
Therefore, according to the electrophoretic display device 100 of the present embodiment, excellent operational reliability can be obtained. In addition, since it is possible to suppress the occurrence of problems due to manufacturing variations of the selection transistor 41, it is possible to manufacture at a high yield.

In the present embodiment, the protection potential VD input to the data line 68 in the image display period ST12 is set to VH / 2. This is because the low level potential VL is set to 0 V in the present embodiment, and the low level potential VL. When is not 0V, the set value of the protective potential VD is also changed in accordance with the low level potential VL. Specifically, the protection potential VD is set to (VH + VL) / 2, which is an intermediate potential between the high level potential VH and the low level potential VL.
If the set value of the protection potential VD is set to the intermediate potential (VH + VL) / 2 as described above, the maximum value of the voltage applied to the selection transistor 41 is minimized, so that the margin of withstand voltage of the selection transistor 41 is increased. It is desirable because it can be taken.

  However, it is not necessary to strictly set the protective potential VD to the intermediate potential (VH + VL) / 2, and the set value of the protective potential VD may be changed in consideration of the mode and degree of characteristic variation of the selection transistor 41 in the manufacturing process. it can.

  The range of the protection potential VD that can be specifically set is a range of (VH + VL) / 3 or more and 2 (VH + VL) / 3 or less. That is, the protective potential VD can be shifted in the range of (VH + VL) / 6 vertically with the intermediate potential (VH + VL) / 2 as the center. When the low level potential VL is 0 V, the protection potential VD is in the range of (VH / 3) to (2VH / 3). With such a range, the allowable value of the withstand voltage of the selection transistor 41 can be lowered by at least about 30%.

  In the present embodiment, in the image holding period ST13, the high potential power line 50 and the low potential power line 49 connected to the latch circuit 70 are shifted to a high impedance state. Can be maintained, and the latch circuit 70 can hold the potential (memory content). In this case, since the voltage is applied between the source and drain of the selection transistor 41 by the holding potential of the latch circuit 70, the protection potential VD is continuously input to the data line 68 until the image holding period ST13. preferable.

  In the driving method according to the present embodiment, a rectangular pulse that periodically repeats the high level potential VH and the low level potential VL is input to the common electrode 37 for a plurality of periods in the image display period ST12. This driving method is referred to as “common swing driving” in the present application. The definition of the common swing driving is a driving method in which a pulse that repeats the high level potential VH and the low level potential VL is applied to the common electrode 37 for at least one period in the image display period ST12.

According to this common swing driving method, the black particles and the white particles can be moved to the desired electrode more reliably, so that the contrast can be increased. In addition, since the potential applied to the pixel electrode and the common electrode can be controlled by binary values of the high level potential VH and the low level potential VL, the voltage can be reduced and the circuit configuration can be simplified. Further, when a TFT is used as the switching element of the pixel electrode 35, there is an advantage that the reliability of the TFT can be secured by low voltage driving.
In addition, it is preferable that the frequency and the number of cycles of the common swing drive are appropriately determined according to the specifications and characteristics of the electrophoretic element 32.

Note that a driving method in which the common swing driving is not performed in the image display period ST12 may be employed.
In this case, the image display period ST12 is divided into a black image display period and a white image display period, the common electrode 37 is held at the low level potential VL in the black image display period, and the common electrode 37 in the white image display period. Is held at the high level potential VH. Thereby, the pixel 40A is displayed in black in the black image display period, and the pixel 40B is displayed in white in the white image display period, so that an image based on the image data can be displayed on the display unit 5 as in the above embodiment. .

[Modification of First Embodiment]
In the first embodiment, the first data line driving circuit 62 is configured to electrically connect and disconnect the data signal wiring 167 and the data line 68 by the plurality of first switching elements 67. As the data line driving circuit 62, the first data line driving circuit 62A shown in FIG. 9 may be adopted.

  A first data line driving circuit 62A shown in FIG. 9 includes a shift register 621, a first latch circuit 622, a second latch circuit 623, a level shifter 624, a buffer 625, and a plurality of first switching elements 67. It is equipped with.

An outline of the operation of the first data line driving circuit 62A will be briefly described below.
In the first data line driving circuit 62A, first, the start pulse ST is input to the shift register 621 in a state where the clock pulse CLK is input. When the start pulse ST is input, a latch signal is transmitted from the shift register 621 to the first latch circuit 622 in the order from X1 to Xn of the data line 68.

  The first latch circuit 622 includes a storage element that holds an image signal for each data line 68, and takes in the image signal D from a data signal wiring (not shown) in synchronization with the latch signal. When the capture of the image signal D to all the storage elements is completed, the image signal D held in the first latch circuit 622 is transmitted to the second latch circuit 623 all at once. Similar to the first latch circuit 622, the second latch circuit 623 includes storage elements provided for each data line 68, and holds the image signal D transmitted from the first latch circuit 622 in these storage elements. .

  The image signal D held in the second latch circuit 623 is input to the buffer 625 after the potential is adjusted by the level shifter 624. Then, the image signal D current-amplified by the buffer 625 is input to the data line 68 at a timing according to the horizontal synchronization signal Hsync via the first switching element 67 that operates based on the switching signal Sw. The image signal D input to the data line 68 is input to the latch circuit 70 of the pixel 40 belonging to the scanning line 66 to which the selection signal is input from the scanning line driving circuit 61.

In the first data line driving circuit 62A described above, the first switching element 67 is interposed between the buffer 625 and the data line 68 as shown in FIG. This is because the potential of the data line 68 is prevented from changing from the protective potential VD due to the image signal held in the buffer 625 when the second data line driving circuit 162 is operated. In addition, it is necessary to electrically disconnect the buffer 625 and the data line 68.
Even when the first data line driving circuit 62A is provided, the image display operation can be performed by the driving method described above, and the same effects can be obtained.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 10 is a diagram illustrating a schematic configuration of an electrophoretic display device 200 according to the second embodiment.
In the drawings referred to below, the same reference numerals are given to the same components as those in the first embodiment, and detailed description thereof will be omitted.

  As shown in FIG. 10, the electrophoretic display device 200 includes a display unit 5, a scanning line driving circuit 61 provided around the display unit 5, a data line driving circuit 262, a controller 63, and a common power supply modulation circuit. 64. That is, the electrophoretic display device 200 of this embodiment has a configuration including a data line driving circuit 262 instead of the first data line driving circuit 62 and the second data line driving circuit 162 in the first embodiment. .

  The data line driving circuit 262 includes a driver circuit 263, a plurality of switching elements 67 connected to the driver circuit 263, and a buffer circuit 69 connected between the switching element 67 and the data line 68. The data line driving circuit 262 has a configuration in which a buffer circuit 69 is further added to the first data line driving circuit 62 according to the first embodiment.

The driver circuit 263 outputs a switching signal to the switching element 67 in the order from X1 to Xn of the data line 68 under the control of the controller 63. The switching element 67 is turned on by the input of this switching signal, and the data signal wiring 167 and the buffer circuit 69 are connected. As a result, the image signal supplied via the data signal wiring 167 is input to the buffer circuit 69, and the image signal current-amplified by the buffer circuit 69 is input to the data line 68.
Therefore, also in the data line driving circuit 262 according to the present embodiment, the image signal is supplied to the pixel 40 by the input of the control signal and the image signal similar to those in the first data line driving circuit 62 according to the first embodiment. It can be carried out.

The buffer circuit 69 is a circuit having at least a function of amplifying a current of an image signal input from the data signal wiring 167 via the switching element 67. As the buffer circuit 69, various configurations can be adopted as shown in FIG.
A buffer circuit 69a (69) shown in FIG. 11A includes a buffer BUF1 having four inverters INV connected in series between the switching element 67 and the data line 68. Or it is good also as a structure provided with the buffer which connected two inverter INV in series.
A buffer circuit 69b (69) shown in FIG. 11B includes a latch circuit LAT in which an input-side inverter INV1 and an output-side inverter INV2 are connected in a loop. In the buffer circuit 69b, the potential of the signal input to the latch circuit LAT via the switching element 67 can be held.
A buffer circuit 69c (69) shown in FIG. 11C has a configuration in which a latch circuit LAT and a buffer BUF2 having two inverters INV connected in series are connected in series.

  Furthermore, a configuration in which a level shifter is added to the buffer circuits 69a to 69c may be used. In this case, in the buffer circuit 69a, a level shifter is added between the buffer BUF1 and the switching element 67. In the buffer circuit 69b, a level shifter is added between the latch circuit LAT and the data line 68. In the buffer circuit 69c, a level shifter is added between the latch circuit LAT and the buffer BUF2.

[Driving method]
Next, FIG. 12 is a timing chart showing a driving method of the electrophoretic display device 200 having the above configuration. As shown in FIG. 12, the driving method of the present embodiment includes an image signal input period ST11 for inputting an image signal to the latch circuit 70 of the pixel 40, a protection potential input period ST11a for inputting a protection potential to the data line 68, The electrophoretic element 32 is driven by the potential difference between the pixel electrode 35 and the common electrode 37, and an image display period ST12 for displaying an image on the display unit 5 and an image holding period ST13 for holding the image displayed on the display unit 5 are provided. Including.

FIG. 13 is a diagram illustrating a potential state of the two pixels 40A and 40B in the image signal input period ST11. FIG. 14 is a diagram illustrating a potential state of the pixels 40A and 40B in the protection potential input period ST11a. FIG. 15 is a diagram illustrating a potential state of the pixels 40A and 40B in the image display period ST12.
In FIG. 13 to FIG. 15, the subscripts “A”, “B”, “a”, and “b” of the reference numerals indicate the two pixels 40 (40A, 40B) that are objects of explanation and the components that belong to them. It is given for clear distinction and has no other intention.

  In FIG. 12, the potential G of the scanning line 66, the potential Vdd of the high potential power supply line 50, the potential Vss of the low potential power supply line 49, the potential Da of the data line 68a connected to the pixel 40A, and the data connected to the pixel 40B. The potential Db of the line 68b, the potential of the data input terminal N1a of the latch circuit 70a, the potential of the data input terminal N1b of the latch circuit 70b, the potential Vcom of the common electrode 37, the potential Va of the pixel electrode 35a, and the potential Vb of the pixel electrode 35b. It is shown. FIG. 12 is a timing chart when the white display pixel 40A is updated to black display and the black display pixel 40B is updated to white display.

  First, the driving process in the image signal input period ST11 is the same as the image signal input period according to the first embodiment. In other words, after each wiring is electrically connected in each driving circuit to enable signal input, the scanning line driving circuit 61 and the data line driving circuit 262 are operated, and an image signal is sent to the latch circuit 70 of each pixel 40. input.

As shown in FIG. 13, in the pixel 40A updated to black display, a low level (L) image signal is input from the data line 68a to the latch circuit 70a via the selection transistor 41a, and the data input terminal of the latch circuit 70a. The potential of N1a becomes low level (L), and the potential of the data output terminal N2a becomes high level (H).
On the other hand, in the pixel 40B, a high level (H) image signal is input from the data line 68b to the latch circuit 70b via the selection transistor 41b, and the potential of the data input terminal N1b of the latch circuit 70b is high level (H). The potential of the output terminal N2b becomes low level (L).

If an image signal is input to each of the pixels 40A and 40B, the process proceeds to the protective potential input period ST11a.
In the protection potential input period ST11a, the protection potential VD is input to the data line 68 by driving only the data line driving circuit 262 while keeping the scanning line 66 in a non-selected state. In the case of the present embodiment, as shown in FIGS. 12 and 14, the switching element 67 of the data line driving circuit 262 is turned on, whereby a high level potential VM (for example, 5 V) for inputting an image signal to the data line 68 is obtained. Is input as the protective potential VD.

When the protection potential VD is input, the data line driving circuit 262 is operated in the same manner as in the image signal input period ST11 in a state where the protection potential VD (high level potential VM) is supplied to the data signal wiring 167, and the data lines 68 are sequentially connected. Select and input the protective potential VD.
Alternatively, if the data line driving circuit 262 has a function of selecting all the data lines 68 (setting all the switching elements 67 on), the protection potential VD can be input more easily. it can. In other words, the data signal wiring 167 and all the data lines 68 are electrically connected to all the data lines 68 only by enabling the above function while the protection potential VD is supplied to the data signal wiring 167. Thus, the protective potential VD can be input.

If the protective potential VD is input to the data line 68 (68a, 68b), the process proceeds to the image display period ST12. The driving process in the image display period ST12 is the same as that in the first embodiment.
As shown in FIG. 12, in the image display period ST12, the potential Vdd of the high potential power supply line 50 is changed from the high level potential VM (for example, 5V) for image signal input to the high level potential VH (for example, 15V) for image display. The potential Vss of the low potential power supply line 49 is set to the low level potential VL (0 V). In addition, a rectangular pulse that repeats the high level potential VH and the low level potential VL in a predetermined cycle is input to the common electrode 37.

Thereby, as shown in FIG. 15, in the pixel 40A, the pixel electrode 35a becomes the high level potential VH (for example, 15V). Then, during the period in which the common electrode 37 to which the rectangular pulse is input is at the low level potential VL, the electrophoretic element 32 is driven by the potential difference between the pixel electrode 35a and the common electrode 37, and the pixel 40A is displayed in black.
On the other hand, in the pixel 40B, since the pixel electrode 35b is at the low level potential VL, the electrophoretic element 32 is driven by the potential difference between the pixel electrode 35b and the common electrode 37 during the period when the common electrode 37 is at the high level potential VH. The pixel 40B is displayed in white.

By the series of operations in the image signal input period ST11, the protection potential input period ST11a, and the image display period ST12, an image based on the image signal can be displayed on the display unit 5.
When the image display operation is completed, as shown in FIG. 12, the image holding period ST13 is started. In the image holding period ST13, each wiring connected to the pixel 40 is in a high impedance state. Accordingly, the pixel electrodes 35a and 35b and the common electrode 37 are in a high impedance state, and the electrophoretic element 32 is electrically isolated. Therefore, an image can be held without consuming power.

  According to the electrophoretic display device 200 of the present embodiment described above, similarly to the electrophoretic display device 100 of the first embodiment, the data line 68 is protected in the protective potential input period ST11a and the image display period ST12. By inputting the potential VD and reducing the voltage applied between the source and drain of the selection transistor 41, it is possible to avoid the occurrence of problems due to the selection transistor 41 having a single gate structure.

More specifically, in the present embodiment, in the protection potential input period ST11a, the protection potential VD (high level potential VM) is input to all the data lines 68 of the display unit 5, and the protection potential VD is applied to the image display period. It was decided to hold during ST12.
As a result, the voltage applied to the selection transistor 41 in the image display period ST12 is lower by the protection potential VD than when no potential is input to the data line 68 (when 0 V is set).
In the pixel 40A displayed in black shown in FIG. 14, since the potential of the data input terminal N1a is the low level potential VL (0V), the voltage applied between the source and the drain of the selection transistor 41a is VM (for example, 5V). It becomes. On the other hand, in the pixel 40B displayed in white, since the potential of the data input terminal N1b is the high level potential VH (for example, 15V), the voltage applied between the source and drain of the selection transistor 41b is VH-VM (for example, 10V). ) And lower than the high level potential VH.

  Therefore, according to the driving method of the present embodiment, the voltage applied to the selection transistor 41 in the image display period ST12 can be reduced, so that the withstand voltage of the selection transistor 41 is lower than the high level potential VH due to manufacturing variation. Even if it is, if the withstand voltage is higher than the higher potential of VM or (VH−VM), the occurrence of leakage in the select transistor 41 can be prevented. For example, when the potential VM is 5 V and the potential VH is 15 V, the withstand voltage of the selection transistor 41 only needs to be higher than 10 V (= VH−VM).

In order to reliably prevent leakage in the selection transistor 41, it is necessary to keep the potential of the data line 68 substantially at the protection potential VD in the image display period ST12. Therefore, in the present embodiment, the buffer circuit 69 is provided between the switching element 67 and the data line 68 so that the potential of the data line 68 in the image display period ST12 can be held substantially at the protection potential VD.
Further, the provision of the buffer circuit 69 provides an advantage that it is possible to make it difficult to cause defective writing of an image signal to the latch circuit 70 even when the number of pixels 40 belonging to the data line 68 increases.

  Thus, according to the electrophoretic display device 200 of the present embodiment, excellent operational reliability can be obtained. In addition, since it is possible to suppress the occurrence of defects due to manufacturing variations of the selection transistor 41, it is possible to manufacture with a high yield.

[Modification of Second Embodiment]
In the second embodiment, the protection potential VD input to the data line 68 in the protection potential input period ST11a is the image signal input high level potential VM (for example, 5V), but the protection potential VD is the high level potential. A potential different from VM may be input. Hereinafter, a case where the protection potential VD is varied will be described as a modification.
In this modification, the configuration of the electrophoretic display device is the same as that of the second embodiment, and thus the description of the configuration is omitted. Also, the driving method will be described with omission as appropriate because only the potential input to the data line 68 is different in the protection potential input period.

  FIG. 16 is a timing chart of the driving method according to the modification, and corresponds to FIG. 12 referred to in the second embodiment. FIG. 17 is a diagram illustrating a potential state of the two pixels 40A and 40B in the image display period ST12 illustrated in FIG. 16, and corresponds to FIG.

As shown in FIG. 16, the driving method according to the modification includes an image signal input period ST11, a protective potential input period ST11b, an image display period ST12, and an image holding period ST13.
In the driving method according to the modified example, in the protection potential input period ST11b, the potential VH / 2 (for example, 7.5V) that is 1/2 of the high-level potential VH (for example, 15V) for image display is used as the protection potential VD. 68a and data line 68b. That is, in the protection potential input period ST11b, the data line driving circuit 262 is operated in a state where the potential VH / 2 is supplied to the data signal wiring 167, and the potential VH / 2 of the data signal wiring 167 is applied to all the data lines 68. input.
The potential input to the data line 68 in the protection potential input period ST11b is stably held during the image display period ST12 by the buffer circuit 69 provided corresponding to each data line 68.

  According to the driving method according to the modification described above, the data line 68 is held at the potential VH / 2 in the image display period ST12. Therefore, as shown in FIG. 17, the selection transistor 41a and the pixel 40B of the pixel 40A The voltage applied between the source and the drain of the selection transistor 41b is VH / 2. That is, when the high level potential VH is 15V, the voltage applied to the selection transistors 41a and 41b is 7.5V.

Therefore, according to the driving method according to the modification, the maximum value of the voltage applied to the selection transistor 41 can be made lower than the driving method according to the second embodiment described above, and the withstand voltage of the selection transistor 41 A large margin can be taken.
Therefore, also in this modification, the problem of withstand voltage in the single gate transistor can be avoided, so that a single gate structure transistor is adopted as the selection transistor 41, and sufficient current driving capability can be obtained.

  Also in this modification, the protection potential VD becomes VH / 2 when the low level potential VL is 0 V, and the protection potential VD input to the data line 68 is the same as in the first embodiment. It is changed according to the low level potential VL. Specifically, the protection potential VD is set to (VH + VL) / 2, which is an intermediate potential between the high level potential VH and the low level potential VL. If the set value of the protection potential VD is set to the intermediate potential (VH + VL) / 2, the maximum value of the voltage applied to the selection transistor 41 becomes the smallest, so that a margin of the withstand voltage of the selection transistor 41 can be increased. This is a desirable configuration.

  In this modification, it is not necessary to strictly set the protective potential VD to the intermediate potential (VH + VL) / 2, and the set value of the protective potential VD is set in consideration of the mode and degree of characteristic variation of the selection transistor 41 in the manufacturing process. Can be changed. The range of the protection potential VD that can be specifically set is a range of (VH + VL) / 3 or more and 2 (VH + VL) / 3 or less, as in the first embodiment. With such a range, the allowable value of the withstand voltage of the selection transistor 41 can be lowered by at least about 30%.

When a high level potential VM (for example, 5 V) for inputting an image signal is input as the protective potential VD as in the second embodiment, the data line driving circuit 262 inputs the data line 68 to the data line 68 in the image signal input period ST11. Since the high level potential to be applied and the protection potential VD are the same, it is not necessary to consider the withstand voltage of the data line driving circuit 262.
However, in the driving method according to the modification, the protection potential VD having a higher potential (for example, 7.5 V) than the image signal input period ST11 may be input to the data line 68. Therefore, when the driving method according to the modification is performed, the protection potential VD is determined in consideration of the withstand voltage of the data line driving circuit 262.
For example, when the withstand voltage of the data line driver circuit 262 is 7V, a potential less than 7V (for example, 6.5V) is input to the data line 68 as the protective potential VD. That is, the protection potential VD is set to a potential as close as possible to (VH + VL) / 2 within the withstand voltage range of the data line driving circuit 262. Even when such a potential is set, the voltage applied to the selection transistor 41 is reduced as compared with the case where the high-level potential VM of 5 V is input as the protection potential VD.

However, since the level shifter can be provided in the buffer circuit 69 as described above, the withstand voltage of the data line driving circuit 262 can be obtained by adopting a configuration in which the potential level of the protection potential VD is adjusted (boosted) by the level shifter. It is possible to input a potential exceeding 1 to the data line 68.
In the case where a level shifter is provided, a level shifter dedicated to generating the protection potential VD may be provided. In this case, a configuration in which the protection potential VD is supplied from one level shifter to the plurality of data lines 68 can be employed, so that an increase in circuit scale of the data line driving circuit 262 can be suppressed. .

(Third embodiment)
In the first and second embodiments described above, the electrophoretic display device including the pixel 40 having the configuration in which the pixel electrode 35 is directly connected to the data output terminal N2 of the latch circuit 70 has been described. As the pixel structure of the electrophoretic display device, the pixel 140 shown in FIG. 18 can also be employed.

A pixel 140 illustrated in FIG. 18 includes a selection transistor 41, a latch circuit 70, a switch circuit 80, a pixel electrode 35, an electrophoretic element 32, and a common electrode 37. A scanning line 66, a data line 68, a low potential power line 49, a high potential power line 50, a first control line 91, and a second control line 92 are connected to the pixel 140. .
The switch circuit 80 is interposed between the latch circuit 70 and the pixel electrode 35, and includes a first transmission gate TG1 and a second transmission gate TG2.

  The first transmission gate TG1 includes a P-MOS transistor 81 and an N-MOS transistor 82. The source terminals of the P-MOS transistor 81 and the N-MOS transistor 82 are connected to the first control line 91, and the drain terminals are connected to the pixel electrode 35. The gate terminal of the P-MOS transistor 81 is connected to the data input terminal N1 (the drain terminal of the selection transistor 41) of the latch circuit 70, and the gate terminal of the N-MOS transistor 82 is connected to the data output terminal N2 of the latch circuit 70. Yes.

  The second transmission gate TG2 includes a P-MOS transistor 83 and an N-MOS transistor 84. The source terminals of the P-MOS transistor 83 and the N-MOS transistor 84 are connected to the second control line 92, and the drain terminals are connected to the pixel electrode 35. The gate terminal of the P-MOS transistor 83 is connected to the data output terminal N 2 of the latch circuit 70, and the gate terminal of the N-MOS transistor 84 is connected to the data input terminal N 1 of the latch circuit 70.

In the electrophoretic display device of the present embodiment having the above configuration, in order to display an image on the display unit 5, an image signal is input to the data input terminal N 1 of the latch circuit 70 via the selection transistor 41, and the latch circuit 70 is input. The image signal is stored as a potential.
Then, the switch circuit 80 operates based on the potentials output from the data input terminal N1 and the data output terminal N2 of the latch circuit 70, and the first transmission gate TG1 or the second transmission gate TG2 is used for the first transmission gate TG2. The control line 91 or the second control line 92 and the pixel electrode 35 are connected.
As a result, a potential for image display is input to the pixel electrode 35 from the first or second control line 91, 92, and the pixel based on the potential difference between the pixel electrode 35 and the common electrode 37 as shown in FIG. 140 is displayed in black or white.

Also in the electrophoretic display device having the pixel structure shown in FIG. 18, the configuration of the selection transistor 41 and the scanning line 66 and the data line 68 connected to the selection transistor 41 are the same as those in the first and second embodiments. The configuration according to the invention can be employed.
That is, the selection transistor 41 has a single gate structure to ensure a sufficient current driving capability, so that an image signal can be reliably written to the latch circuit 70. The problem of withstand voltage in a single-gate transistor can also be avoided by controlling the data line potential during the image display period. Therefore, the electrophoretic display device of the present embodiment also has excellent operational reliability and manufacturability.

  In the electrophoretic display device of this embodiment, since the switch circuit 80 is interposed between the latch circuit 70 and the pixel electrode 35, the first and second control lines 91 connected to the switch circuit 80. , 92 can be controlled to perform display control of the display unit 5 regardless of the holding potential of the latch circuit 70.

For example, the high level potential VH and the low level potential VL input to the first and second control lines 91 and 92 are switched, and the common electrode 37 has a rectangular shape that repeats the high level potential VH and the low level potential VL at a predetermined cycle. By inputting a pulse, the display image of the display unit 5 can be inverted and displayed.
In the electrophoretic display device of this embodiment, the erasing operation of the display unit 5 can be performed without transferring the image signal to the latch circuit 70. That is, if the high-level potential VH is input to both the first and second control lines 91 and 92 and the low-level potential VL is input to the common electrode 37, the display unit 5 can be erased by the entire black display. . Alternatively, if the low-level potential VL is input to both the first and second control lines 91 and 92 and the high-level potential VH is input to the common electrode 37, the display unit 5 can be erased by the entire white display. .

[Electronics]
Next, the case where the electrophoretic display device 100 (200) of each of the above embodiments is applied to an electronic device will be described.
FIG. 19 is a front view of the wrist watch 1000. The wrist watch 1000 includes a watch case 1002 and a pair of bands 1003 connected to the watch case 1002.
A display unit 1005 including the electrophoretic display device 100 (200) of each of the above embodiments, a second hand 1021, a minute hand 1022, and an hour hand 1023 are provided on the front surface of the watch case 1002. On the side surface of the watch case 1002, a crown 1010 and an operation button 1011 are provided as operation elements. The crown 1010 is connected to a winding stem (not shown) provided inside the case, and is integrally provided with the winding stem so that it can be pushed and pulled in multiple stages (for example, two stages) and can be rotated. . The display unit 1005 can display a background image, a character string such as date and time, or a second hand, a minute hand, and an hour hand.

  FIG. 20 is a perspective view illustrating a configuration of the electronic paper 1100. An electronic paper 1100 includes the electrophoretic display device 100 (200) of each of the above embodiments in a display area 1101. The electronic paper 1100 is flexible and includes a main body 1102 made of a rewritable sheet having the same texture and flexibility as conventional paper.

  FIG. 21 is a perspective view showing the configuration of the electronic notebook 1200. An electronic notebook 1200 is obtained by bundling a plurality of the electronic papers 1100 and sandwiching them between covers 1201. The cover 1201 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

According to the wristwatch 1000, the electronic paper 1100, and the electronic notebook 1200 described above, since the electrophoretic display device 100 (200) according to the present invention is employed in the display unit, an electronic device having a display unit with excellent power saving performance. It is a device.
Note that the electronic devices illustrated in FIGS. 19 to 21 are examples of the electronic device according to the present invention, and do not limit the technical scope of the present invention. For example, the electrophoretic display device according to the present invention can be suitably used for a display portion of an electronic device such as a mobile phone or a portable audio device.

1 is a schematic configuration diagram of an electrophoretic display device according to a first embodiment. FIG. 2 is a circuit configuration diagram of the pixel shown in FIG. 1. 1 is a partial cross-sectional view of an electrophoretic display device according to an embodiment. The schematic cross section of a microcapsule. Operation | movement explanatory drawing of an electrophoretic element. 4 is a timing chart in the driving method according to the first embodiment. The figure which shows the electric potential state of a pixel. The figure which shows the electric potential state of a pixel. The figure which shows the 1st data line drive circuit which concerns on a modification. FIG. 6 is a schematic configuration diagram of an electrophoretic display device according to a second embodiment. FIG. 9 illustrates a configuration example of a buffer circuit. The timing chart in the drive method which concerns on 2nd Embodiment. The figure which shows the electric potential state of a pixel. The figure which shows the electric potential state of a pixel. The figure which shows the electric potential state of a pixel. The timing chart in the drive method which concerns on a modification. The figure which shows the electric potential state of a pixel. The circuit block diagram of the pixel with which the electrophoretic display device which concerns on 3rd Embodiment was equipped. FIG. 9 illustrates a wrist watch that is an example of an electronic apparatus. FIG. 11 illustrates electronic paper which is an example of an electronic device. FIG. 11 illustrates an electronic notebook which is an example of an electronic device. Explanatory drawing which shows the pixel provided with the memory circuit.

Explanation of symbols

  100, 200 electrophoretic display device, 5 display unit, 32 electrophoretic element, 35, 35a, 35b pixel electrode, 37 common electrode, 40, 40A, 40B, 140 pixel, 41, 41a, 41b selection transistor (pixel switching element) 49 Low potential power supply line, 50 High potential power supply line, 58 Protection potential wiring, 62, 62A First data line drive circuit, 162 Second data line drive circuit, 262 Data line drive circuit, 63 Controller (control unit) 69, 69a, 69b, 69c buffer circuit, 70, 70a, 70b latch circuit (memory circuit), 80 switch circuit, 91 first control line, 92 second control line, 167 data signal wiring

Claims (13)

An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and the display unit includes a plurality of pixels. For each pixel, a pixel electrode, a pixel switching element, the pixel electrode, and the pixel An electrophoretic display device including a memory circuit connected between the switching element and the pixel switching element being a single gate transistor,
At least during the period in which the electrophoretic element is driven to display an image on the display unit, the data line connected to the source terminal of the single gate transistor has a high level potential VH and a low level potential held in the memory circuit. An electrophoretic display device characterized in that the electrophoretic display device is held at a potential VD intermediate to VL.   The data line driving circuit for inputting an image signal to the data line is connected exclusively to the data line, and has a protective potential wiring for supplying the potential VD to the data line. Electrophoretic display device.   The potential VD is not less than 2/3 and not more than 3/2 of an intermediate potential (VH + VL) / 2 between the high-level potential VH and the low-level potential VL held in the memory circuit during the image display period. The electrophoretic display device according to claim 1 or 2.   The electrophoretic display device according to claim 3, wherein the potential VD is (VH + VL) / 2.   2. The electrophoretic display device according to claim 1, wherein the potential VD is a high-level potential VM of an image signal input to the memory circuit via the data line.   The high potential VH and the low potential VL held in the memory circuit in the period of displaying the image within the range of the withstand voltage of the data line driving circuit that inputs the image signal to the data line. The electrophoretic display device according to claim 1, wherein the electrophoretic display device has an intermediate potential (VH + VL) / 2.   The electrophoretic display device according to claim 5, further comprising a buffer circuit connected to the data line. An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and the display unit includes a plurality of pixels. For each pixel, a pixel electrode, a pixel switching element, the pixel electrode, and the pixel A method of driving an electrophoretic display device comprising a memory circuit connected between the switching element and the pixel switching element being a single gate transistor,
The step of displaying an image on the display unit includes an image signal input period in which an image signal is input to the memory circuit, and a voltage is applied to the pixel electrode based on the output of the memory circuit to drive the electrophoretic element. And an image display period for displaying the image.
At least in the image display period, the data line connected to the source terminal of the single gate transistor is set to an intermediate potential VD between the high level potential VH and the low level potential VL held in the memory circuit in the image display period. A method for driving an electrophoretic display device, comprising: holding the electrophoretic display device.   The potential VD is not less than 2/3 and not more than 3/2 of an intermediate potential (VH + VL) / 2 between a high level potential VH and a low level potential VL held in the memory circuit in the image display period. The method for driving an electrophoretic display device according to claim 8.   The method of driving an electrophoretic display device according to claim 9, wherein the potential VD is (VH + VL) / 2.   9. The method for driving an electrophoretic display device according to claim 8, wherein the potential VD is a high level potential VM of an image signal input to the memory circuit via the data line.   The potential VD is within the range of the withstand voltage of the data line driving circuit that supplies an image signal to the data line, and is intermediate between the high level potential VH and the low level potential VL held in the memory circuit in the image display period. The method for driving an electrophoretic display device according to claim 8, wherein the potential is close to a potential (VH + VL) / 2.   An electronic apparatus comprising the electrophoretic display device according to claim 1.

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