JP2010181618A - Method of driving electrophoretic display device, electrophoretic display device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of driving an electrophoretic display device capable of displaying an image without generating afterimage while suppressing power consumption, to provide the electrophoretic display device, and to provide an electronic apparatus. <P>SOLUTION: In the method of driving the electrophoretic display device which holds an electrophoretic element containing electrophoretic particles between a pair of substrates and has a display unit comprising a plurality of pixels, an operation for performing writing so that a first gradation is displayed in the pixel forming an image component and an operation for performing writing so that a second gradation different from the first gradation is displayed in the pixel forming a contour of the pixel component are simultaneously performed at an image writing step for writing an image of the display unit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for driving an electrophoretic display device, an electrophoretic display device, and an electronic apparatus.

In an electrophoretic display device, it is known that a thin afterimage along the contour of an image is generated when image erasure is executed by driving only pixels that form a displayed image component. This afterimage is generated when an image in which the contour region is expanded is generated by generating an oblique electric field that crosses between the pixel forming the contour and the pixel forming the background during image display.
Therefore, a driving method for erasing an image by executing erasure on all pixels including pixels whose gradation is not changed is disclosed so that an afterimage of the previous image does not remain when the image is updated (Patent Document). 1).

Special table 2007-512571 gazette

  However, in such a driving method, the electrophoretic particles are driven so that the final display gradation does not change even for a pixel having no change in display. Power consumption at the time increases.

  Accordingly, an object of the present invention is to provide an electrophoretic display device driving method, an electrophoretic display device, and an electronic apparatus that can display an image without generating an afterimage while suppressing power consumption.

  An electrophoretic display device driving method according to the present invention is an electrophoretic display device driving method in which an electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and the display unit includes a plurality of pixels. In the image writing step of writing the image of the display unit, writing is performed so that the first gradation is displayed on the pixel forming the image component, and at the same time, the pixel forming the contour of the image component is Writing is performed so that a second gradation different from the first gradation is displayed.

  According to the present invention, since different gradations are displayed simultaneously for the pixels forming the image component and the pixels forming the contour of the image component, display is performed while preventing afterimages from occurring. It can be performed. For this reason, it is not necessary to perform additional writing for erasing the afterimage, and power consumption can be suppressed. Thereby, it is possible to display an image without generating an afterimage while suppressing power consumption.

In the driving method of the electrophoretic display device, the second gradation is an inverted gradation of the first gradation.
According to the present invention, since the second gradation is an inverted gradation of the first gradation, display with higher contrast is possible.

The driving method of the electrophoretic display device is characterized in that the second gradation is a gradation corresponding to a background color of the image.
According to the present invention, since the second gradation is a gradation corresponding to the background color of the image, it is possible to display with high contrast between the image and the background.

In the driving method of the electrophoretic display device, the contour of the image component has a width corresponding to one pixel.
According to the present invention, since the outline of the image portion has a width corresponding to one pixel, the number of pixels used to erase the afterimage can be suppressed to a minimum, and power consumption can be reduced.

In the driving method of the electrophoretic display device, the pair of substrates includes a first substrate in which first electrodes corresponding to the plurality of pixels are formed on the electrophoretic element side, and a plurality of substrates on the electrophoretic element side. A second substrate on which a second electrode facing the first electrode is formed, and in the image writing step, the first electrode corresponding to the pixel for displaying the first gradation is first on the first electrode. A potential is applied, a second potential is applied to the first electrode corresponding to the pixel for displaying the second gradation, and an intermediate potential between the first potential and the second potential is applied to the second electrode. Is applied.
According to the present invention, the first potential is applied to the first electrode corresponding to the pixel displaying the first gradation, and the second potential is applied to the first electrode corresponding to the pixel displaying the second gradation. In addition, since the intermediate potential between the first potential and the second potential is applied to the second electrode, it is possible to suppress power consumption and prevent afterimage generation while using the configuration of the existing electrophoretic display device. Can do.

In the image writing step, the electrophoretic display device driving method corresponds to the pixel that is different from the pixel that displays the first gradation and the pixel that displays the second gradation. The intermediate potential is applied to the first electrode.
According to the present invention, the first electrode corresponding to a pixel different from the pixel displaying the first gradation and the pixel displaying the second gradation is set to the same potential as the second electrode. It is possible to prevent the gradation of the pixels from changing.

  An electrophoretic display device according to the present invention includes an electrophoretic element including electrophoretic particles between a pair of substrates, and includes a display unit including a plurality of pixels, and a control unit that controls the display unit. In the display device, when the image of the display unit is written, the control unit causes the pixel forming the image component to perform writing so that the first gradation is displayed, and at the same time, Writing is performed so that the second gradation different from the first gradation is displayed on the pixel forming the outline.

  According to the present invention, since different gradations are displayed simultaneously for the pixels forming the image component and the pixels forming the contour of the image component, display is performed while preventing afterimages from occurring. It can be performed. For this reason, it is not necessary to perform additional writing for erasing the afterimage, and power consumption can be suppressed. Thereby, an electrophoretic display device capable of displaying an image without generating an afterimage while suppressing power consumption can be obtained.

In the electrophoretic display device, the second gradation is an inverted gradation of the first gradation.
According to the present invention, since the second gradation is an inversion gradation of the first gradation, an electrophoretic display device capable of displaying with higher contrast can be obtained.

In the electrophoretic display device, the second gradation is a gradation corresponding to a background color of the image.
According to the present invention, since the second gradation is a gradation corresponding to the background color of the image, it is possible to obtain an electrophoretic display device capable of displaying a high contrast between the image and the background. it can.

In the electrophoretic display device, the contour of the image component has a width corresponding to one pixel.
Since the outline of the image portion has a width corresponding to one pixel, an electrophoretic display device capable of minimizing the number of pixels used for erasing afterimages and reducing power consumption is obtained. Can do.

In the electrophoretic display device, the pair of substrates includes a first substrate on which the first electrodes corresponding to the plurality of pixels are formed on the electrophoretic element side, and a plurality of the first substrates on the electrophoretic element side. A second substrate on which a second electrode facing the electrode is formed, and when the control unit writes an image of the display unit, the control unit corresponds to the first pixel corresponding to the pixel that displays the first gradation. A first potential is applied to the electrode, a second potential is applied to the first electrode corresponding to the pixel for displaying the second gradation, and the first potential and the second potential are applied to the second electrode. And an intermediate potential is applied.
According to the present invention, the first potential is applied to the first electrode corresponding to the pixel displaying the first gradation, and the second potential is applied to the first electrode corresponding to the pixel displaying the second gradation. In addition, since an intermediate potential between the first potential and the second potential is applied to the second electrode, electrophoresis that can reduce power consumption and prevent afterimage generation while using an existing configuration. A display device can be obtained.

In the electrophoretic display device, when the control unit writes the image of the display unit, the pixel that is different from the pixel that displays the first gradation and the pixel that displays the second gradation The intermediate potential is applied to the first electrode corresponding to the above.
According to the present invention, the first electrode corresponding to a pixel different from the pixel displaying the first gradation and the pixel displaying the second gradation is set to the same potential as the second electrode. Thus, it is possible to obtain an electrophoretic display device that can prevent the gradation of the pixels from changing.

An electronic apparatus according to the present invention includes the above-described electrophoretic display device.
According to the present invention, since the electrophoretic display device capable of displaying an image without generating an afterimage while suppressing power consumption is provided, an electronic device having a long life and high display characteristics can be obtained. it can.

1 is a schematic configuration diagram of an electrophoretic display device 100. FIG. 2 is a circuit configuration diagram of a pixel 40. FIG. 3 is a partial cross-sectional view of an electrophoretic display device 100 in a display unit 5. FIG. 2 is a schematic cross-sectional view of a microcapsule 20. FIG. FIG. 5 is an operation explanatory diagram of the electrophoretic element 20. 3 is a block diagram showing details of a controller 63. FIG. It is a flowchart concerning image update. It is a timing chart concerning image update. It is a figure which shows the change of the display image at the time of image update. It is a figure which shows the electric potential relationship of pixel 40A, 40B, 40C. It is an arrangement diagram of image signals at the time of image writing. 3 is a diagram showing an image writing area R. FIG. It is a figure which shows the electric potential relationship of pixel 40A, 40B, 40C. It is a figure which shows the change of the display part 5 when the image P1 is selectively deleted. It is a figure which shows the electric potential relationship of pixel 40A, 40B, 40C. 1 is a front view of a wrist watch 1000. FIG. 1 is a perspective view illustrating a configuration of electronic paper 1100. FIG. 1 is a perspective view illustrating a configuration of an electronic notebook 1200. FIG. 1 is a schematic configuration diagram of an electrophoretic display device 200. FIG.

  Hereinafter, an active matrix electrophoretic display device according to an embodiment of the present invention will be described with reference to the drawings. The following embodiment shows one aspect of the present invention, does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. Moreover, in the following drawings, in order to make each configuration easy to understand, the actual structure is different from the scale and number of each structure.

FIG. 1 is a schematic configuration diagram of an electrophoretic display device 100 according to the present embodiment.
The electrophoretic display device 100 includes a display unit 5 in which a plurality of pixels 40 are arranged in a matrix. Around the display unit 5, a scanning line driving circuit 61, a data line driving circuit 62, a controller (control unit) 63, and a common power supply modulation circuit 64 are arranged. The scanning line driving circuit 61, the data line driving circuit 62, and the common power supply modulation circuit 64 are each connected to the controller 63. The controller 63 comprehensively controls these based on image data and synchronization signals supplied from the host device.

  A plurality of scanning lines 66 extending from the scanning line driving circuit 61 and a plurality of data lines 68 extending from the data line driving circuit 62 are formed in the display unit 5, and the pixels 40 are provided corresponding to the intersection positions thereof. It has been.

  The scanning line driving circuit 61 is connected to each pixel 40 via m scanning lines 66 (Y1, Y2,..., Ym). Under the control of the controller 63, the first to mth rows are connected. The scanning lines 66 are sequentially selected, and a selection signal defining the ON timing of the selection transistor 41 (see FIG. 2) provided in the pixel 40 is supplied via the selected scanning line 66.

  The data line driving circuit 62 is connected to each pixel 40 via n data lines 68 (X1, X2,..., Xn), and corresponds to each pixel 40 under the control of the controller 63. An image signal defining 1-bit pixel data is supplied to the pixel 40.

  In the present embodiment, a low level (L) image signal is supplied to the pixel 40 when the pixel data “0” is defined, and a high level (H) image is defined when the pixel data “1” is defined. It is assumed that a signal is supplied to the pixel 40. When the pixel data is not defined, a middle level (M) image signal is supplied to the pixel 40. The potential of the middle level (M) image signal can be set, for example, as an intermediate potential between a high level (H) potential and a low level (L) potential.

  The display unit 5 is also provided with a common electrode wiring 55 extending from the common power supply modulation circuit 64. The common electrode wiring 55 is connected to the pixel 40. The common power supply modulation circuit 64 generates various signals to be supplied to each of the common electrode wirings 55 under the control of the controller 63, and electrically connects and disconnects (high impedance) the common electrode wirings 55. .

FIG. 2 is a circuit configuration diagram of the pixel 40 provided in the display unit 5.
The pixel 40 includes a selection transistor 41, a capacitor 225, a pixel electrode 35, an electrophoretic element 32, and a common electrode 37. That is, the pixel 40 is configured to include a DRAM (1T1C) type pixel circuit.

  FIG. 3 is a partial cross-sectional view of the electrophoretic display device 100 in the display unit 5. The electrophoretic display device 100 includes a configuration in which an electrophoretic element 32 formed by arranging a plurality of microcapsules 20 is sandwiched between an element substrate (first substrate) 30 and a counter substrate (second substrate) 31. Yes.

  In the display unit 5, the circuit layer 34 on which the scanning line 66, the data line 68, the selection transistor 41, the latch circuit 70, and the like illustrated in FIGS. 1 and 2 are provided on the electrophoretic element 32 side of the element substrate 30. A plurality of pixel electrodes 35 are arranged on the circuit layer 34.

  The element substrate 30 is a substrate made of glass, plastic, or the like and is not required to be transparent because it is disposed on the side opposite to the image display surface. The pixel electrode 35 has a voltage applied to an electrophoretic element 32 formed by laminating nickel plating and gold plating on a Cu (copper) foil in this order, Al (aluminum), ITO (indium tin oxide), or the like. Is an electrode to which is applied.

  On the other hand, a planar common electrode 37 facing the plurality of pixel electrodes 35 is formed on the electrophoretic element 32 side of the counter substrate 31, and the electrophoretic element 32 is provided on the common electrode 37.

The counter substrate 31 is a substrate made of glass, plastic, or the like, and is a transparent substrate because it is disposed on the image display side. The common electrode 37 is an electrode for applying a voltage to the electrophoretic element 32 together with the pixel electrode 35, and is formed of MgAg (magnesium silver), ITO (indium tin oxide), IZO (indium zinc oxide) or the like. It is a transparent electrode.
Then, the electrophoretic element 32 and the pixel electrode 35 are bonded via the adhesive layer 33, so that the element substrate 30 and the counter substrate 31 are bonded.

  In general, the electrophoretic element 32 is formed in advance on the counter substrate 31 side, and is handled as an electrophoretic sheet including the adhesive layer 33. In the manufacturing process, the electrophoretic sheet is handled in a state where a protective release sheet is attached to the surface of the adhesive layer 33. And the display part 5 is formed by sticking the said electrophoretic sheet which peeled the release sheet with respect to the element board | substrate 30 (The pixel electrode 35, various circuits, etc.) which were manufactured separately. For this reason, the adhesive layer 33 exists only on the pixel electrode 35 side.

  FIG. 4 is a schematic cross-sectional view of the microcapsule 20. The microcapsule 20 has a particle size of, for example, about 50 μm and encloses therein a dispersion medium 21, a plurality of white particles (electrophoretic particles) 27, and a plurality of black particles (electrophoretic particles) 26. It is a spherical body. As shown in FIG. 3, the microcapsule 20 is sandwiched between the common electrode 37 and the pixel electrode 35, and one or more microcapsules 20 are arranged in one pixel 40.

The outer shell portion (wall film) of the microcapsule 20 is formed using a translucent polymer resin such as an acrylic resin such as polymethyl methacrylate or polyethyl methacrylate, a urea resin, or gum arabic.
The dispersion medium 21 is a liquid that disperses the white particles 27 and the black particles 26 in the microcapsules 20. Examples of the dispersion medium 21 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.). ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrachloride) Element, and 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

  The white particles 27 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 26 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used by being charged positively, for example. These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.

  Further, instead of the black particles 26 and the white particles 27, for example, pigments such as red, green, and blue may be used. According to such a configuration, red, green, blue, or the like can be displayed on the display unit 5.

  FIG. 5 is an explanatory diagram of the operation of the electrophoretic element 20. FIG. 5A shows a case where the pixel 40 displays white (second gradation), and FIG. 5B shows a case where the pixel 40 displays black (first gradation).

  5A, the common electrode 37 is held at a relatively high potential and the pixel electrode 35 is held at a relatively low potential. As a result, the negatively charged white particles 27 are attracted to the common electrode 37, while the positively charged black particles 26 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side which is the display surface side, white is recognized.

  In the case of black display shown in FIG. 5B, the common electrode 37 is held at a relatively low potential, and the pixel electrode 35 is held at a relatively high potential. As a result, the positively charged black particles 26 are attracted to the common electrode 37, while the negatively charged white particles 27 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side, black is recognized.

[Control unit]
FIG. 6 is a block diagram showing details of the controller 63 provided in the electrophoretic display device 100.
The controller 63 includes a control circuit 161 as a CPU (Central Processing Unit), an EEPROM (Electrically-Erasable and Programmable Read-Only Memory; storage unit) 162, a voltage generation circuit 163, a data buffer 164, and a frame memory 165. A memory control circuit 166 and an afterimage erasing area setting circuit 167.

  The control circuit 161 generates control signals (timing pulses) such as a clock signal CLK, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync, and supplies these control signals to each circuit arranged around the control circuit 161.

  The EEPROM 162 stores setting values and the like necessary for operation control of each circuit by the control circuit 161. The EEPROM 162 may store preset image information used for displaying the operating state of the electrophoretic display device.

  The voltage generation circuit 163 is a circuit that supplies a driving voltage to the scanning line driving circuit 61, the data line driving circuit 62, and the common power supply modulation circuit 64.

  The data buffer 164 is an interface unit with the host device in the controller 63, holds the image data D input from the host device, and transmits the image data D to the control circuit 161.

  The frame memory 165 has a readable / writable memory space corresponding to the arrangement of the pixels 40 of the display unit 5. The memory control circuit 166 develops the image data D supplied from the control circuit 161 in correspondence with the pixel array of the display unit 5 according to the control signal, and writes it in the frame memory 165. The frame memory 165 sequentially transmits a data group including the stored image data D as an image signal to the data line driving circuit 62.

  The data line driving circuit 62 latches the image signal transmitted from the frame memory 165 line by line based on the control signal supplied from the control circuit 161. Then, the latched image signal is supplied to the data line 68 in synchronization with the sequential selection operation of the scanning line 66 by the scanning line driving circuit 61.

  The image writing area setting circuit 167 sets an image writing area including pixels 40 to be driven when executing image writing based on the image data D developed in the frame memory 165, and sets the image writing area. The pixel information to be configured is output to the control circuit 161.

[Driving method]
Next, a driving method related to image update in the electrophoretic display device 100 will be described. In the present embodiment, as an example, a driving method in the case where a square image is displayed and then updated to a horizontally long rectangular image will be described.

  FIG. 7 is a flowchart relating to image update. Steps related to image updating include image display step S101, image erasing step S111, and updated image display step S121.

(Image display step)
First, the image display step S101 will be described. The image display step S101 is a step of displaying an image on the display unit 5. FIG. 8 is a timing chart relating to image update. FIG. 9 is a diagram illustrating a change in the display image when the image is updated. FIG. 10 is a diagram illustrating a potential relationship between the pixels 40A, 40B, and 40C in the image display step S101.

  8 and 9 show timing charts corresponding to the image display step S101 to the update image display step S121 and the display image on the display unit 5. FIG. Further, in the following description, when a pixel 40 in a certain area is pointed to and any one of the pixels 40A, 40B, and 40C is included in the area, as in “pixel 40 (40A)”, Symbols are added in parentheses.

9 and 10, the pixel 40A is the pixel 40 that forms the outer edge of the image P1, and the pixel 40B is the pixel 40 that is arranged adjacent to the pixel 40A and forms the contour of the image P1. The pixel 40C is a pixel 40 that is arranged adjacent to the pixel 40B and forms a background, and is the pixel 40 opposite to the pixel 40A with respect to the pixel 40B. A combination of these pixels 40A, 40B, and 40C can be arbitrarily selected. For example, the pixels 40A, 40B, and 40C illustrated in FIG. 10 are the pixels 40 that belong to the same scanning line 66, but the pixels 40 that belong to the same data line 68 may be used as 40A, 40B, and 40C.
In FIGS. 8 and 10, the subscripts “a”, “b”, and “c” of the reference numerals clearly indicate the three pixels 40 (40A, 40B, and 40C) to be described and the components that belong to them. It is attached to distinguish between the two and has no other intention.

  FIG. 8 shows the potential Va of the pixel electrode 35a, the potential Vb of the pixel electrode 35b, and the potential Vcom of the common electrode 37. In FIG. 9, a part of the display unit 5 on which the image P1 is displayed is extracted and displayed by 8 pixels × 8 pixels.

In the driving method of the present embodiment, an operation of writing an image from a state in which all the pixels 40 (40A, 40B, 40C) are in white display is described as an example.
The image display step S101 sets an image writing area composed of an area for forming the image P1 and an outline area bordering the outline of the image P1, and only the pixels 40 (40A, 40B) constituting the image writing area are set. Is executed to write the image P1 and the contour. In the image display step S101, the entire image writing area is simultaneously written so that the image P1 is displayed in black (first gradation) and the contour is displayed in white (second gradation). Execute.

  Here, a method for setting the image writing area R will be described. The image writing area setting circuit 167 extracts, from the image data D developed in the frame memory 165, the background side pixel 40 (40B) arranged adjacent to the pixel 40 (40A) forming the outline of the image P1. To do. The pixels 40 (40B) extracted in this way constitute a band-like region having a width corresponding to one pixel bordering the outline of the image P1. These pixels 40 (40B) may be extracted by a general method adopted in image processing software, for example.

  Then, the image writing area setting circuit 167 sets an area composed of the pixels 40 (40A) forming the image P1 and the pixels 40 (40B) bordering the outline of the image P1 as the image writing area R. As shown in FIG. 11, the set image writing area R is an area obtained by expanding the image P1 by one pixel outward.

  Pixel information constituting the image writing region R is output from the image writing region setting circuit 167 to the control circuit 161, and image data D for image writing is created in the control circuit 161. The image data D for image writing created by the control circuit 161 is developed in the frame memory 165 and then inputted to the pixel electrodes 35a, 35b, 35c of the respective pixels 40 (40A, 40B, 40C).

  In the present embodiment, the pixels 40 (40B) bordering the image P1 are extracted from the image data D after being developed in the frame memory 165. However, the control circuit 161 analyzes the image data D before being developed. By doing so, you may make it extract the pixel 40 (40B) which borders the outline of the image P1. In this case, the control circuit 161 consistently executes from the setting of the image writing area R to the creation of image data D for image writing.

  FIG. 11 is a diagram showing the image signal input at the time of image writing in association with the display unit 5. As shown in FIG. 11, a high level (H) image signal is input to the pixel 40 (40A) corresponding to the image P1. A low level (L) image signal is input to the pixel 40 (40B) corresponding to the contour region of the image P1. Middle level (M) image signals are input to the pixels 40 (40C) corresponding to the background other than the image writing region R.

  As shown in FIG. 10, in the pixel 40 (40A) that forms the image P1 and is displayed in black, a high level (H) potential VH (for example, +15 V) is supplied to the pixel electrode 35a via the driving TFT 41a. . In the pixel 40 (40B) forming the contour of the image P1, a low level (L) potential VL (for example, −15 V) is supplied to the pixel electrode 35b via the driving TFT 41b. In the pixel 40 (40C) forming the background of the image P1, a middle level (M) potential VM (for example, 0 V) is supplied to the pixel electrode 35c through the driving TFT 41c. A middle level (M) signal is input to the common electrode 37. Therefore, the common electrode 37 and the pixel electrode 35c are equipotential.

  Then, a voltage corresponding to the potential difference between the pixel electrode 35a and the common electrode 37 is applied to the electrophoretic element 32, and the positively charged black particles 26 are on the common electrode 37 side as shown in FIG. The white particles 27 that are negatively charged are attracted toward the pixel electrode 35a, and the pixel 40A is displayed in black, and a square image P1 shown in FIG. 9A is displayed.

  Further, a voltage corresponding to the potential difference between the pixel electrode 35b and the common electrode 37 is applied to the electrophoretic element 32, and as shown in FIG. 5A, the negatively charged white particles 27 are on the common electrode 37 side. The positively charged black particles 26 are attracted to the pixel electrode 35b side. For this reason, the pixel 40B which comprises the outline part of the image P1 becomes white display.

  Further, there is no potential difference between the pixel electrode 35 b and the common electrode 37, and no voltage is applied to the electrophoretic element 32. For this reason, the movement of the black particles 26 and the white particles 27 does not occur, and the pixel 40C maintains the white display.

(Image deletion step)
Next, the image erasing step S111 will be described.
FIG. 13 is a diagram illustrating a potential relationship between the pixels 40A, 40B, and 40C according to the image erasing step S111. FIG. 13 is a drawing corresponding to FIG. 10, and the same reference numerals are given to the components common to FIG. 10.

  The image erasing step S111 is a step for erasing the image P1 displayed in the image display step S101. When erasing the image P1 in the image erasing step S111, a low level (VL) potential is supplied to the pixel electrode 35 (35a) of the pixel 40 (40A) forming the image P1, and a middle level ( VM) is supplied. A middle level (VM) potential is supplied to the pixel electrode 35 (35b) of the pixel 40 (40B) corresponding to the contour region and the pixel electrode 35 (35c) of the pixel 40 (40C) corresponding to the background region.

  In the pixel 40 (40A) to which the low-level (L) image signal is input, the pixel electrode 35 (35a) is connected to the common electrode 37 during the period in which the middle-level (VM) potential is supplied to the common electrode 37. A voltage corresponding to the potential difference is applied to the electrophoretic element 32. Thereby, in the area where the image P1 is displayed, the black particles 26 move to the pixel electrode 35 side, the white particles 27 move to the common electrode 37 side, and the image P1 is erased.

For the pixels 40 (40B, 40C) corresponding to the outline region and the background region, the pixel electrode 35 (35b, 35c) and the common electrode 37 are the same during a period in which the middle level (VM) potential is supplied to the common electrode 37. It becomes a potential. For this reason, the movement of the black particles 26 and the white particles 27 is hardly affected, and the white display is held in the pixels 40 (40B, 40C) corresponding to the contour region and the background region.
As described above, as shown in FIG. 9B, when the image P1 is deleted, the display unit 5 displays white over the entire area.

  In the image display step S101, when no potential is supplied to the pixel electrode 35b of the pixel 40B constituting the contour portion, the electric field in the oblique direction from the pixel electrode 35a of the pixel 40A forming the image P1 toward the common electrode 37 on the background side. Will occur. Due to the electric field in the oblique direction, the vicinity of the boundary between the image P1 and the background is also displayed in black, and as shown in FIG. 14A, the contour portion of the image P1 swells slightly (P2). In this state, when the operation of deleting only the image P1 is performed in the image erasing step S111, only the swollen contour portion remains as shown in FIG. 14B, resulting in an afterimage P2.

  On the other hand, in the present embodiment, the positive and negative potentials are reversed so that the pixel electrode 35b of the pixel 40B constituting the contour portion of the image P1 displays an inverted gradation with respect to the pixel 40A forming the image P1. Supply. By this operation, an electric field in an oblique direction from the pixel electrode 35a of the pixel 40A toward the common electrode 37 is not generated, and the swelling of the image P1 does not occur. In this state, if an operation of deleting only the image P1 is performed in the image erasing step S111, the image P1 is deleted without generating an afterimage.

(Updated image display step)
The update image display step S121 is a step of displaying the update image P11 shown in FIG. The update image display step S121 is driven in the same manner as the image display step S101 after the image signal for the update image is input to the pixel electrode 35 of each pixel 40.

  FIG. 15 is a diagram illustrating a potential relationship between the pixels 40A, 40B, and 40C in the updated image display step S121. FIG. 15 is a drawing corresponding to FIG. 10 and FIG. 13, and components common to those drawings are denoted by the same reference numerals.

  When the process proceeds to the update image display step S <b> 121, the image data D for the update image is output from the control circuit 161 to the frame memory 165. In the frame memory 165, the image data D is developed into an image signal for each pixel 40, and then the image signal is input to the pixel electrode 35 of each pixel 40.

Since the pixels 40A, 40B, and 40C are all the pixels 40 that form the updated image P11, as shown in FIG. 15, the pixel electrodes 35a, 35b, and 35c of the respective pixels 40A, 40B, and 40C have a high level (H ) Image signal is input. The pixels 40 (40A, 40B, 40C) to which the high-level (H) image signal is input are displayed in black, and the horizontally-long rectangular update image P11 shown in FIG. 9C is displayed. The upper and lower one pixel columns in the drawing of the update image P11 are the outline region of the update image P11. A low level (L) image signal is input to the pixel 40 (40D) forming the contour region. Further, the pixels other than the updated image P11 and the outline region are the pixels 40 (40E) forming the background. A middle level (M) image signal is input to the pixel 40 (40E) forming the background. As a result, as shown in FIG. 9C, only the image P11 is displayed on the display unit 5.
When the image is continuously updated, the image erasing step S111 and the updated image display step S121 may be repeatedly executed.

According to the electrophoretic display device 100 provided with such a driving method, the following effects can be obtained.
First, since the image writing region R is set, which includes the pixel 40 (40A) that forms the image P1 and the pixel 40 (40B) that forms a band-shaped region for one pixel that borders the outline of the image P1. Thus, the number of pixels to be driven in the image erasing step S111 is minimized, and the image P1 can be erased without generating an afterimage while suppressing power consumption.

  Further, the image writing area R is preferably set according to the afterimage generation form which varies depending on the characteristics of the electrophoretic element 32. For example, an area where the image P1 is expanded by two pixels or more may be set as the image writing area R. In this case, since the number of pixels to be driven increases, the power consumption is inferior, but the afterimage can be prevented more reliably.

  The product of the voltage of the pulse applied to the electrophoretic element 32 and the voltage application time may be changed as necessary depending on the operating temperature range, applied voltage, individual difference of the electrophoretic sheet, and the like.

[Electronics]
Next, a case where the electrophoretic display device 100 of each of the above embodiments is applied to an electronic device will be described.
FIG. 16 is a front view of the wrist watch 1000. The wrist watch 1000 includes a watch case 1002 and a pair of bands 1003 connected to the watch case 1002.

  A display unit 1005 including the electrophoretic display device 100 (200) of each of the above embodiments, a second hand 1021, a minute hand 1022, and an hour hand 1023 are provided on the front surface of the watch case 1002. On the side surface of the watch case 1002, a crown 1010 and an operation button 1011 are provided as operation elements. The crown 1010 is connected to a winding stem (not shown) provided inside the case, and is integrally provided with the winding stem so that it can be pushed and pulled in multiple stages (for example, two stages) and can be rotated. . The display unit 1005 can display a background image, a character string such as date and time, or a second hand, a minute hand, and an hour hand.

  FIG. 17 is a perspective view illustrating a configuration of the electronic paper 1100. An electronic paper 1100 includes the electrophoretic display device 100 (200) of each of the above embodiments in a display area 1101. The electronic paper 1100 is flexible and includes a main body 1102 made of a rewritable sheet having the same texture and flexibility as conventional paper.

  FIG. 18 is a perspective view showing the configuration of the electronic notebook 1200. An electronic notebook 1200 is obtained by bundling a plurality of the electronic papers 1100 and sandwiching them between covers 1201. The cover 1201 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

According to the wristwatch 1000, the electronic paper 1100, and the electronic notebook 1200 described above, since the electrophoretic display device according to the present invention is employed in the display unit, a display unit capable of high-quality display and excellent in reliability. It is an electronic device equipped with.
In addition, the electronic device shown in each figure illustrates the electronic device which concerns on this invention, and does not limit the technical scope of this invention. For example, the electrophoretic display device according to the present invention can be suitably used for a display portion of an electronic device such as a mobile phone or a portable audio device.

The technical scope of the present invention is not limited to the above-described embodiment, and appropriate modifications can be made without departing from the spirit of the present invention.
In the above embodiment, the configuration including the DRAM (1T1C) type pixel circuit has been described as an example, but the present invention is not limited to this. For example, the present invention can also be applied to an electrophoretic display device 200 having pixels having the configuration shown in FIG. Hereinafter, the pixel configuration of the electrophoretic display device 200 will be described.
The pixel 140 includes a first selection transistor ST1 (first switching element), a first latch circuit LAT1 (first memory circuit), a first switch circuit SC1, and a second selection transistor ST2 ( A second switching element), a second latch circuit LAT2 (second memory circuit), a second switch circuit SC2, an electrophoretic element 132, a pixel electrode 135, and a common electrode 137. Yes. An electrophoretic element 132 is sandwiched between the pixel electrode 135 and the common electrode 137.
The pixel 140 has an SRAM (Static Random Access Memory) system configuration in which the first latch circuit LAT1 holds an image signal as a potential.

The first selection transistor ST1 is a switching element formed of an N-MOS (Negative Metal Oxide Semiconductor) transistor. The gate terminal of the first selection transistor ST1 is connected to the scanning line 166, the source terminal is connected to the first data line 168, and the drain terminal is connected to the data input terminal N11 of the first latch circuit LAT1.
The data input terminal N11 and the data output terminal N12 of the first latch circuit LAT1 are connected to the first switch circuit SC1. Further, the first switch circuit SC1 is connected to the second switch circuit SC2, the first control line 191 and the second control line 192.

The second selection transistor ST2 is a switching element composed of an N-MOS transistor. The gate terminal of the second selection transistor ST2 is connected to the common scanning line 166 with the gate terminal of the first selection transistor ST1, and the source terminal is connected to the second data line 169 paired with the first data line 168. The drain terminal is connected to the data input terminal N21 of the second latch circuit LAT2.
The data input terminal N21 and the data output terminal N22 of the second latch circuit LAT2 are connected to the second switch circuit SC2. The second switch circuit SC2 is connected to the first switch circuit SC1, the third control line 193, and the pixel electrode 135.

  The first latch circuit LAT1 includes a transfer inverter INV1 and a feedback inverter INV2. Both the transfer inverter INV1 and the feedback inverter INV2 are C-MOS inverters. The transfer inverter INV1 and the feedback inverter INV2 have a loop structure in which the other output terminal is connected to each other's input terminal, and each inverter has a high potential connected via a high potential power supply terminal PH1. A high potential power supply voltage is supplied from the power supply line 150, and a low potential power supply voltage is supplied from the low potential power supply line 149 connected via the low potential power supply terminal PL1.

  The transfer inverter INV1 includes a P-MOS (Positive Metal Oxide Semiconductor) transistor PM1 and an N-MOS transistor NM1 each having a drain terminal connected to the data output terminal N12. The source terminal of the P-MOS transistor PM1 is connected to the high potential power supply terminal PH1, and the source terminal of the N-MOS transistor NM1 is connected to the low potential power supply terminal PL1. The gate terminals of the P-MOS transistor PM1 and the N-MOS transistor NM1 (the input terminal of the transfer inverter INV1) are connected to the data input terminal N11 (the output terminal of the feedback inverter INV2).

  The feedback inverter INV2 includes a P-MOS transistor PM2 and an N-MOS transistor NM2 whose drain terminals are connected to the data input terminal N11. The gate terminals of the P-MOS transistor PM2 and the N-MOS transistor NM2 (input terminal of the feedback inverter INV2) are connected to the data output terminal N12 (output terminal of the transfer inverter INV1).

  In the first latch circuit LAT1 configured as described above, when a high level (H) image signal (pixel data “1”) is stored, a low level (L) is output from the data output terminal N12 of the first latch circuit LAT1. A signal is output. On the other hand, when a low level (L) image signal (pixel data “0”) is stored in the first latch circuit LAT1, a high level (H) signal is output from the data output terminal N12.

The first switch circuit SC1 includes a first transmission gate TG1 and a second transmission gate TG2.
The first transmission gate TG1 includes a P-MOS transistor PM3 and an N-MOS transistor NM3.
The source terminals of the P-MOS transistor PM3 and the N-MOS transistor NM3 (the input terminal of the first transmission gate TG1) are connected to the first control line 191, and the drain terminals of the P-MOS transistor PM3 and the N-MOS transistor NM3. The (output terminal of the first transmission gate TG1) is connected to the input terminal of the second switch circuit SC2 (third transmission gate TG3) together with the output terminal of the second transmission gate TG2.
The gate terminal of the P-MOS transistor PM3 is connected to the data input terminal N11 of the first latch circuit LAT1, and the gate terminal of the N-MOS transistor NM3 is connected to the data output terminal N12 of the first latch circuit LAT1. Yes.

The second transmission gate TG2 includes a P-MOS transistor PM4 and an N-MOS transistor NM4.
The source terminals of the P-MOS transistor PM4 and the N-MOS transistor NM4 (the input terminal of the second transmission gate TG2) are connected to the second control line 92, and the drain terminals of the P-MOS transistor PM4 and the N-MOS transistor NM4. The (output terminal of the second transmission gate TG2) is connected to the input terminal of the second switch circuit SC2 (third transmission gate TG3) together with the output terminal of the first transmission gate TG1.
The gate terminal of the P-MOS transistor PM4 is connected to the data output terminal N12 of the first latch circuit LAT1, and the gate terminal of the N-MOS transistor NM4 is connected to the data input terminal N11 of the first latch circuit LAT1. Yes.

  The second latch circuit LAT2 is a latch circuit having a configuration similar to that of the first latch circuit LAT1, and includes a transfer inverter INV3 including a P-MOS transistor PM5 and an N-MOS transistor NM5, and a P-MOS transistor. A feedback inverter INV4 including PM6 and an N-MOS transistor NM6 is included. Also in the second latch circuit LAT2, when a high level (H) control signal is stored, a low level (L) signal is output from the data output terminal N22 of the second latch circuit LAT2. On the other hand, when a low level (L) control signal is stored in the second latch circuit LAT2, a high level (H) signal is output from the data output terminal N22.

The second switch circuit SC2 includes a third transmission gate TG3 and a fourth transmission gate TG4.
The third transmission gate TG3 includes a P-MOS transistor PM7 and an N-MOS transistor NM7.
The source terminals of the P-MOS transistor PM7 and the N-MOS transistor NM7 (the input terminal of the third transmission gate TG3) are connected to the output terminals of the first and second transmission gates TG1 and TG2, and the P-MOS transistor PM7 The drain terminal of the N-MOS transistor NM7 (the output terminal of the third transmission gate TG3) is connected to the pixel electrode 35.
The gate terminal of the P-MOS transistor PM7 is connected to the data input terminal N21 of the second latch circuit LAT2, and the gate terminal of the N-MOS transistor NM7 is connected to the data output terminal N22 of the second latch circuit LAT2. Yes.

The fourth transmission gate TG4 includes a P-MOS transistor PM8 and an N-MOS transistor NM8.
The source terminals of the P-MOS transistor PM8 and the N-MOS transistor NM8 (the input terminal of the fourth transmission gate TG4) are connected to the third control line 193, and the drain terminals of the P-MOS transistor PM8 and the N-MOS transistor NM8. (Output terminal of the fourth transmission gate TG4) is connected to the pixel electrode 35 together with the output terminal of the third transmission gate TG3.
The gate terminal of the P-MOS transistor PM8 is connected to the data output terminal N22 of the second latch circuit LAT2, and the gate terminal of the N-MOS transistor NM8 is connected to the data input terminal N21 of the second latch circuit LAT2. Yes.

  In the pixel 140 described above, the first switch circuit SC1 is controlled by the output signal (holding potential) of the first latch circuit LAT1, and the second switch is controlled by the output signal (holding potential) of the second latch circuit LAT2. The circuit SC2 is controlled. Then, one of the first to third control lines 191 to 193 is connected to the pixel electrode 35 by the switching operation by the first and second switch circuits SC1 and SC2, and the potentials S1 to S3 of these control lines are connected. Either is input to the pixel electrode 35.

First, when a low level (L) image signal (pixel data “0”) is stored in the first latch circuit LAT1, and a high level (H) signal is output from the data output terminal N12, the first transmission The gate TG1 is turned on to electrically connect the first control line 191 and the second switch circuit SC2, and the potential S1 of the first control line 91 is input to the second switch circuit SC2.
On the other hand, when a high level (H) image signal (pixel data “1”) is stored in the first latch circuit LAT1, and a low level (L) signal is output from the data output terminal N12, the second transmission The gate TG2 is turned on, and the potential S2 of the second control line 192 is input to the second switch circuit SC2.

At this time, if a low level (L) control signal is stored in the second latch circuit LAT2 and a high level (H) signal is output from the data output terminal N22, the third transmission gate TG3 is turned on. Thus, the pixel electrode 35 and the first switch circuit SC1 are connected. Thus, the first control line 191 or the second control line 192 selected by the first switch circuit SC1 based on the output signal of the first latch circuit LAT1 is connected to the pixel electrode 135, and the potential S1 or S2 is It is input to the pixel electrode 135.
On the other hand, when a high level (H) control signal is stored in the second latch circuit LAT2 and a low level (L) signal is output from the data output terminal N22, the fourth transmission gate TG4 is turned on. Thus, the pixel electrode 135 and the third control line 193 are connected. Thus, the potential S3 of the third control line 193 is input to the pixel electrode 135. Thus, the pixel electrode 135 is moved to the high level (VH) in the above embodiment by the three signal lines S1, S2, and S3. The present invention can also be applied to a configuration using the electrophoretic display device 200 that can be set to three levels of a low level (VL) and a middle level (VM).

  Further, the present invention can be applied even when a segment type electrophoretic display device in which the pixel electrode 35 is directly connected to the pixel driving circuit is used. In this case, the potential of the pixel electrode 35 is directly adjusted by the pixel driving circuit so that the potential of the pixel electrode 35 becomes three levels of high level (VH), low level (VL), and middle level (VM). .

  In the above-described embodiment, an example is described in which the image P1 is written in a state where all the pixels 40 are displayed in white in the image input step S101. However, the present invention is not limited to this. The present invention can be applied even when the black image P1 is written in a state where the pixel 40 is displayed in a neutral color (gray).

  In this case, in a state where the common electrode 37 is at the middle level (M), a high level (H) potential is supplied to the pixels 40 (40A) forming the image P1 so as to display black as in the above embodiment. Then, a high level (H) potential is supplied to the pixels 40 (40B) forming the contour region of the image P1.

  When supplying a high level (H) potential to the pixel 40 (40B), for example, by adjusting the pulse width to be shorter than when supplying the pixel 40 (40A), the display color of the pixel 40 (40B) Can be adjusted. Here, the display color of the pixel 40 (40B) is controlled to be the same as the display color of the pixel 40 (40C) forming the background. By controlling in this way, the pixel 40 (40B) that forms the contour portion can be set to the same display color as the pixel 40 (40C) that forms the background portion, and avoid the swelling of the black display. Can do. As a result, it is possible to avoid the occurrence of an afterimage when the display of the image P1 is erased in the image erasing step S111.

  100, 200 electrophoretic display device, 5 display unit, 32 electrophoretic element, 35 pixel electrode, 37 common electrode (counter electrode), 40, 40A, 40B, 40C, 40D, 140 pixel, 61 scanning line drive circuit, 62 data Line drive circuit, 63 controller (control unit), 161 control circuit, 162 EEPROM, 163 voltage generation circuit, 164 data buffer, 165 frame memory, 166 memory control circuit, 167 image writing area setting circuit

Claims (13)

An electrophoretic display device driving method in which an electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates and a display unit including a plurality of pixels is provided.
In the image writing step of writing the image of the display unit,
Writing is performed so that a first gradation is displayed on the pixel forming the image component, and at the same time, a second gradation different from the first gradation is applied to the pixel forming the contour of the image component. The method of driving an electrophoretic display device is characterized in that writing is performed so as to be displayed. The method for driving an electrophoretic display device according to claim 1, wherein the second gradation is an inverted gradation of the first gradation. The driving method of the electrophoretic display device according to claim 1, wherein the second gradation is a gradation corresponding to a background color of the image. The driving method of the electrophoretic display device according to claim 1, wherein the contour of the image component has a width corresponding to one pixel. The pair of substrates is
A first substrate having first electrodes corresponding to the plurality of pixels formed on the electrophoretic element side;
A second substrate having a plurality of second electrodes opposed to the first electrodes on the side of the electrophoretic element;
In the image writing step,
Applying a first potential to the first electrode corresponding to the pixel for displaying the first gradation;
Applying a second potential to the first electrode corresponding to the pixel for displaying the second gradation;
The method for driving an electrophoretic display device according to claim 1, wherein an intermediate potential between the first potential and the second potential is applied to the second electrode. . In the image writing step,
The intermediate potential is applied to the first electrode corresponding to the pixel different from the pixel for displaying the first gradation and the pixel for displaying the second gradation. 6. A method for driving an electrophoretic display device according to 5. An electrophoretic display device having an electrophoretic element including electrophoretic particles between a pair of substrates and having a display unit composed of a plurality of pixels and a control unit for controlling the display unit,
When the control unit writes the image of the display unit,
Writing is performed so that the first gradation is displayed on the pixel forming the image component, and at the same time, a second floor different from the first gradation is applied to the pixel forming the outline of the image component. An electrophoretic display device, wherein writing is performed so that a tone is displayed. The electrophoretic display device according to claim 7, wherein the second gradation is an inversion gradation of the first gradation. The electrophoretic display device according to claim 7, wherein the second gradation is a gradation corresponding to a background color of the image. The electrophoretic display device according to claim 7, wherein the contour of the image component has a width corresponding to one pixel. The pair of substrates is
A first substrate having first electrodes corresponding to the plurality of pixels formed on the electrophoretic element side;
A second substrate having a plurality of second electrodes opposed to the first electrodes on the side of the electrophoretic element;
When the control unit writes the image of the display unit,
Applying a first potential to the first electrode corresponding to the pixel for displaying the first gradation;
Applying a second potential to the first electrode corresponding to the pixel for displaying the second gradation;
The electrophoretic display device according to any one of claims 7 to 10, wherein an intermediate potential between the first potential and the second potential is applied to the second electrode. When the control unit writes the image of the display unit,
The intermediate potential is applied to the first electrode corresponding to the pixel that is different from the pixel that displays the first gradation and the pixel that displays the second gradation. 11. The electrophoretic display device according to 11.   An electronic apparatus comprising the electrophoretic display device according to any one of claims 7 to 12.

Images