JP2009229850A - Pixel circuit, electrophoretic display device and its driving method, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform quickly display switching in an electrophoretic display device. <P>SOLUTION: In a first memory structure part 700 and a second memory structure part 800 in respective pixels 20 of a display part 3 of an electrophoretic display device 1, an image signal is supplied and written in a first memory circuit 250 of the first memory structure part 700 by a switch for control 24 in a state in which electrical connection for the second memory structure part 800 is cut off, while, in the second memory structure part 800, the image signal held in the first memory structure part 700 is written a second memory circuit 25 through the switch 24 for control, a potential of a pixel electrode 21 is controlled based on the image signal held in the second memory structure part 800. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technical field of a pixel circuit in an electrophoretic display device, an electrophoretic display device and a driving method thereof, and an electronic apparatus.

  This type of electrophoretic display device has a display unit that performs display as follows using a plurality of pixels. In each pixel, after writing an image signal to the memory circuit via the pixel switching element, the pixel electrode is driven by a potential corresponding to the written image signal, and a potential difference is generated between the pixel electrode and the common electrode. Thus, display is performed by driving the electrophoretic element between the pixel electrode and the common electrode. Patent Document 1 discloses a configuration in which such a pixel includes a DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory) in a memory circuit.

  Alternatively, according to research by the inventors of the present application, in order to drive the electrophoretic element, a pixel circuit having a switching circuit in addition to the memory circuit including the pixel switching element and the SRAM in each pixel is constructed. The display is performed on the display unit by the circuit. This pixel circuit is configured such that (ii) potential supply to the pixel electrode can be performed separately from (i) writing of an image signal in the memory circuit. According to such a pixel circuit, it is possible to drive each pixel with low power consumption as compared with the above-described pixel circuit according to Patent Document 1, and between adjacent pixels whose pixel electrodes have different potentials. Generation of leakage current can be more effectively prevented.

JP 2003-84314 A

  However, in the pixel circuit in which the above (i) and (ii) described above are performed separately, the following problems occur. That is, after displaying the X image as the first image, when switching from the X image to the Y image of the second image, the X inverted image obtained by inverting the gradation of the X image is displayed, and then the Y image is displayed. It is assumed that the Y image is displayed after displaying the Y inverted image obtained by reversing the gradation of the image. In this case, in the pixel circuit, the above-mentioned (ii) is performed based on the image signal written in the memory circuit at the time of displaying the X image to display the X inverted image. Similarly, the Y image is already displayed on the Y circuit. Since the reverse image is displayed based on the image signal written in the memory circuit at the time of displaying the reverse image, the operation (i) is not necessary in each case. On the other hand, when displaying the Y reversed image, the operation (i) is required, and the drive circuit for supplying the image signal to each pixel is required. Therefore, the time length required for switching from the X inverted image to the Y inverted image is larger than each of the switching from the X image to the X inverted image and the switching from the Y inverted image to the Y image. Accordingly, since it does not contribute at all to the original image display, the meaningless X inverted image is displayed on the display unit for a longer time, and the meaningless image (X As a result, a technical problem that display quality deteriorates may occur.

  The present invention has been made in view of the above problems, for example, and provides a pixel circuit, an electrophoretic display device, a driving method thereof, and an electronic apparatus to which these are applied, which can perform display switching quickly. Let it be an issue.

  In order to solve the above problems, a pixel circuit of the present invention constitutes each of a plurality of pixels in a display portion of an electrophoretic display device, and a potential difference applied between a pixel electrode and a common electrode facing the pixel electrode. A pixel circuit having an electrophoretic element driven on the basis of at least two memory structure units each having a memory circuit, and a control circuit for controlling electrical connection between each of the at least two memory structure units A switch, and an electrical connection between the memory circuit of one of the at least two memory structure units and the other memory structure unit of the at least two memory structure units by the control switch. An image signal is written during a period in which the pixel is selected in a state in which the connection is disconnected, and the memory circuit included in the other memory structure unit The image signal held in the one memory structure is written through the control switch, and the potential of the pixel electrode is controlled based on the image signal held in the other memory structure. The

  The pixel circuit of the present invention constitutes each of a plurality of pixels included in the display unit of the electrophoretic display device. In the pixel circuit of the present invention, by applying a voltage based on the potential difference between the pixel electrode and the common electrode, the electrophoretic particles contained in the electrophoretic element provided between the pixel electrode and the common electrode are transferred between the pixel electrode and the common electrode. The image is displayed by moving with.

  In addition to the electrophoretic element, the pixel circuit of the present invention has at least two memory structures that are electrically connected to each other via a control switch. When performing display in each pixel, a pixel is selected based on a selection signal from a drive circuit of the electrophoretic display device, and an image signal is supplied from the drive circuit during this selection period. The image signal supplied in this way is written into the memory circuit of one of the two memory structures. At this time, one memory structure is electrically disconnected from the other memory structure by a control switch.

  The image signal held in one memory structure is supplied to the other memory structure out of the at least two memory structures via the control switch, and is written in the memory circuit. The potential of the pixel electrode is controlled based on an image signal held in another memory structure portion.

  Accordingly, when the display unit sequentially displays the X image, the X inverted image, the Y inverted image, and the Y image on the display unit as described above, a predetermined value is applied to the pixel electrode based on the image signal held in the other memory structure unit. In a state where an electric potential is supplied and an X image or an X inverted image is displayed, each pixel can be selected and an image signal can be supplied to one memory structure portion. Thereby, the writing of the image signal (i) and the supply of the potential to the pixel electrode (ii) can be performed in parallel. Here, when an image signal is written from one memory structure to another memory structure, a potential cannot be supplied to the pixel electrode, but a drive circuit for supplying an image signal to each pixel is not provided. No action is required.

  Therefore, the time length required for writing the image signal (i) for displaying the Y inverted image after the X inverted image is compared with the case of performing (i) after displaying the X inverted image. It becomes possible to shorten it dramatically. Therefore, the time length required for switching from the X reverse image to the Y reverse image can be drastically shortened, and the time for displaying the meaningless X reverse image can be shortened. As a result, the display can be quickly switched from the X image to the Y image. For example, even when a moving image is displayed on the display unit, a higher quality display can be performed.

  In one aspect of the pixel circuit of the present invention, the memory circuit included in the other memory structure unit includes an SRAM.

  According to this aspect, the writing of the image signal from one memory structure to the other memory structure and the supply of the predetermined potential to the pixel electrode based on the image signal held in the other memory structure are mutually The memory circuit can be driven with different voltages. Specifically, for example, a minimum voltage required to drive the memory circuit is supplied, an image signal is written from one memory structure to another memory structure, and then, between the pixel electrode and the common electrode is written. In order to obtain a predetermined potential difference, the voltage required for driving the memory circuit is boosted, and a predetermined potential is supplied to the pixel electrode in this state.

  Therefore, it is possible to drive the pixel circuit with lower power consumption as compared with the case where the other memory structure is always driven with a voltage required for setting a predetermined potential difference between the pixel electrode and the common electrode.

  In another aspect of the pixel circuit of the present invention, the other memory structure unit performs switching control of the pixel electrode in accordance with an output based on the image signal from the memory circuit included in the other memory structure unit. And a switch circuit for supplying a predetermined potential to the pixel electrode.

  In this embodiment, the switch circuit in the other memory structure unit switches the electrical connection between the control line and the pixel electrode in accordance with the output based on the image signal from the memory circuit, so that a predetermined potential is controlled on the pixel electrode. Supplied via line and switch circuit. Here, in adjacent pixels in which the pixel electrodes are maintained at different potentials, the pixel electrodes are electrically connected to different control lines by a switch circuit, and a predetermined potential is supplied to one of the pixel electrodes via the control line. In this state, the control line corresponding to the other is in a high impedance state in which the electrical connection is cut off. Therefore, it is possible to effectively prevent a leak current from occurring between adjacent pixels in which the pixel electrodes are maintained at different potentials.

  In another aspect of the pixel circuit of the present invention, the memory circuit included in the one memory structure unit includes a storage capacitor.

  In this aspect, by configuring the memory circuit in one memory structure portion with a DRAM, the configuration can be simplified, and writing of an image signal to the memory circuit can be further simplified.

  In order to solve the above problems, an electrophoretic display device of the present invention includes the above-described pixel circuit of the present invention (including various aspects thereof).

  According to the electrophoretic display device of the present invention, since the image display is performed on the display unit by the above-described pixel circuit of the present invention, the display can be quickly switched and a high-quality display can be performed.

  To drive the electrophoretic display device of the present invention, an electrophoretic element driven based on a potential difference applied between a pixel electrode and a common electrode facing the pixel electrode, and a memory An electric circuit comprising a display unit including a plurality of pixels each provided with at least two memory structures each having a circuit and a control switch for controlling electrical connection between each of the at least two memory structures A method of driving an electrophoretic display device for driving an electrophoretic display device, wherein the control switch is selected for the memory circuit selected by the pixel and included in one of the at least two memory structure units. A first step of writing an image signal in a state in which the electrical connection with the other memory structure portion of the at least two memory structure portions is disconnected, and the other memory structure portion A second step of writing the image signal held in the one memory structure portion to the memory circuit through the control switch, and the image signal held in the other memory structure portion. And a third step of controlling the potential of the pixel electrode based on the third step.

  According to the driving method of the electrophoretic display device of the present invention, as in the above-described pixel circuit of the present invention, it is possible to switch the display quickly and to perform higher quality display in the electrophoretic display device.

  In order to solve the above problems, an electronic apparatus of the present invention includes the above-described electrophoretic display device of the present invention.

  According to the electronic apparatus of the present invention, since the electrophoretic display device of the present invention described above is provided, display switching can be performed quickly and high-quality display can be performed. Various electronic devices such as electronic paper, electronic notebooks, mobile phones, and portable audio devices can be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, the overall configuration of the electrophoretic display device according to the present embodiment will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a block diagram showing the overall configuration of the electrophoretic display device according to this embodiment.

  1, the electrophoretic display device 1 according to the present embodiment includes a display unit 3, a control unit 10, a scanning line driving circuit 60, a data line driving circuit 70, a power supply circuit 210, and a common potential supply circuit 220. And.

  In the display unit 3, m rows × n columns of pixels 20 are arranged in a matrix (in a two-dimensional plane). The display unit 3 includes m scanning lines 40 (that is, scanning lines Y1, Y2,..., Ym) and n data lines 50 (that is, data lines X1, X2,..., Xn). It is provided so as to cross each other. Specifically, the m scanning lines 40 extend in the row direction (that is, the X direction), and the n data lines 50 extend in the column direction (that is, the Y direction). The pixels 20 are arranged corresponding to the intersections of the m scanning lines 40 and the n data lines 50.

  The control unit 10 controls operations of the scanning line driving circuit 60, the data line driving circuit 70, the power supply circuit 210, and the common potential supply circuit 220. For example, the control unit 10 supplies timing signals such as a clock signal and a start pulse to each circuit. The control unit 10 supplies a control signal via a control signal line 96 to a control switch for each pixel 20 described later.

  The scanning line driving circuit 60 sequentially supplies a scanning signal in a pulsed manner to each of the scanning lines Y1, Y2,..., Ym based on the timing signal supplied from the control unit 10.

  The data line driving circuit 70 supplies image signals to the data lines X1, X2,..., Xn based on the timing signal supplied from the control unit 10. The image signal takes a binary level of a high potential level (hereinafter referred to as “high level”, for example, 5 V) or a low potential level (hereinafter referred to as “low level”, for example, 0 V).

  The power supply circuit 210 supplies the high potential power supply line 91 with the high potential power supply potential VEP, supplies the low potential power supply line 92 with the low potential power supply potential Vss, and supplies the first control line 94 with the first potential S1. The second potential S2 is supplied to the second control line 95. Although not shown here, each of the high potential power supply line 91, the low potential power supply line 92, the first control line 94, and the second control line 95 is connected to the power supply circuit 210 via an electrical switch. Electrically connected.

  The common potential supply circuit 220 supplies the common potential Vcom to the common potential line 93. Although not shown here, the common potential line 93 is electrically connected to the common potential supply circuit 220 via an electrical switch.

  Various signals are input / output to / from the control unit 10, the scanning line driving circuit 60, the data line driving circuit 70, the power supply circuit 210, and the common potential supply circuit 220, which are not particularly related to the present embodiment. Will not be described.

  FIG. 2 is an equivalent circuit diagram illustrating the electrical configuration of the pixel.

  The pixel 20 includes a pixel electrode 21, a common electrode 22 disposed so as to face the pixel electrode 21, an electrophoretic element 23 provided between the pixel electrode 21 and the common electrode 22, and a first memory structure unit The pixel circuit includes 700, a second memory structure unit 800, and a control switch 24 that controls electrical connection between the first memory structure unit 700 and the second memory structure unit 800.

  The first memory structure unit 700 includes a driving switch 240 and a first memory circuit 250 including a storage capacitor, and has a DRAM structure. According to such a configuration, the first memory circuit 250 can have a simpler configuration, and image signal writing as described below can be further simplified.

  The drive switch 240 is composed of, for example, an N-type transistor. The driving switch 240 has a gate electrically connected to the scanning line 40, a source electrically connected to the data line 50, and a drain electrically connected to the first memory circuit 250. Has been. The drive switch 240 pulses the image signal supplied from the data line driving circuit 70 (see FIG. 1) via the data line 50 via the scanning line 40 from the scanning line driving circuit 60 (see FIG. 1). The data is input to the first memory circuit 250 at a timing according to the supplied scanning signal. As a result, the image signal is written in the storage capacitor constituting the first memory circuit 250.

  The second memory structure unit 800 is configured to be electrically connectable to the first memory structure unit 700 via the control switch 24, and includes the second memory circuit 25 and the switch circuit 110.

  The control switch 24 is composed of, for example, an N-type transistor. The control switch 24 has a gate electrically connected to the control signal line 96, a source electrically connected to the first memory circuit 250, and a drain connected to the second memory circuit 25. It is electrically connected to the input terminal N1. The control switch 24 receives the image signal held in the first memory circuit 250 at a timing according to a control signal supplied in a pulse manner from the control unit 10 (see FIG. 1) via the control signal line 96. The data is output to the input terminal N1 of the second memory circuit 25.

  The second memory circuit 25 includes inverter circuits 25a and 25b, and is configured as an SRAM.

  The inverter circuits 25a and 25b have a loop structure in which the other output terminal is electrically connected to the input terminals of each other. That is, the input terminal of the inverter circuit 25a and the output terminal of the inverter circuit 25b are electrically connected to each other, and the input terminal of the inverter circuit 25b and the output terminal of the inverter circuit 25a are electrically connected to each other. The input terminal of the inverter circuit 25a is configured as the input terminal N1 of the memory circuit 25, and the output terminal of the inverter circuit 25a is configured as the output terminal N2 of the memory circuit 25.

  The inverter circuit 25a has an N-type transistor 25a1 and a P-type transistor 25a2. The gates of the N-type transistor 25 a 1 and the P-type transistor 25 a 2 are electrically connected to the input terminal N 1 of the second memory circuit 25. The source of the N-type transistor 25a1 is electrically connected to a low potential power supply line 92 to which a low potential power supply potential Vss is supplied. The source of the P-type transistor 25a2 is electrically connected to a high potential power supply line 91 to which a high potential power supply potential VEP is supplied. The drains of the N-type transistor 25 a 1 and the P-type transistor 25 a 2 are electrically connected to the output terminal N 2 of the second memory circuit 25.

  The inverter circuit 25b has an N-type transistor 25b1 and a P-type transistor 25b2. The gates of the N-type transistor 25 b 1 and the P-type transistor 25 b 2 are electrically connected to the output terminal N 2 of the second memory circuit 25. The source of the N-type transistor 25b1 is electrically connected to a low potential power supply line 92 to which a low potential power supply potential Vss is supplied. The source of the P-type transistor 25b2 is electrically connected to the high potential power supply line 91 to which the high potential power supply potential VEP is supplied. The drains of the N-type transistor 25 b 1 and the P-type transistor 25 b 2 are electrically connected to the input terminal N 1 of the second memory circuit 25.

  When the high-level image signal is input to the input terminal N1, the second memory circuit 25 outputs the low-potential power supply potential Vss from the output terminal N2, and the low-level image signal is input to the input terminal N1. Then, the high potential power supply potential VEP is output from the output terminal N2. That is, the second memory circuit 25 outputs the low potential power supply potential Vss or the high potential power supply potential VEP depending on whether the input image signal is at a high level or a low level. In other words, the second memory circuit 25 is configured to be able to store the input image signal as the low potential power supply potential Vss or the high potential power supply potential VEP.

  The high potential power supply line 91 and the low potential power supply line 92 are configured to be able to supply the high potential power supply potential VEP and the low potential power supply potential Vss from the power supply circuit 210, respectively. The high potential power supply line 91 is electrically connected to the power supply circuit 210 via the switch 91s, and the low potential power supply line 92 is electrically connected to the power supply circuit 210 via the switch 92s. The switches 91 s and 92 s are configured to be switched between an on state and an off state by the control unit 10. When the switch 91s is turned on, the high potential power supply line 91 and the power supply circuit 210 are electrically connected, and when the switch 91s is turned off, the high potential power supply line 91 is electrically disconnected. High impedance state. When the switch 92s is turned on, the low-potential power line 92 and the power circuit 210 are electrically connected, and when the switch 92s is turned off, the low-potential power line 92 is electrically disconnected. High impedance state.

  As an example, the switch circuit 110 includes a first transmission gate 111 and a second transmission gate 112.

  The first transmission gate 111 includes a P-type transistor 111p and an N-type transistor 111n. The sources of the P-type transistor 111p and the N-type transistor 111n are electrically connected to the first control line 94. The drains of the P-type transistor 111p and the N-type transistor 111n are electrically connected to the pixel electrode 21. The gate of the P-type transistor 111p is electrically connected to the input terminal N1 of the second memory circuit 25, and the gate of the N-type transistor 111n is electrically connected to the output terminal N2 of the second memory circuit 25. Has been.

  The second transmission gate 112 includes a P-type transistor 112p and an N-type transistor 112n. The sources of the P-type transistor 112p and the N-type transistor 112n are electrically connected to the second control line 95. The drains of the P-type transistor 112p and the N-type transistor 112n are electrically connected to the pixel electrode 21. The gate of the P-type transistor 112p is electrically connected to the output terminal N2 of the second memory circuit 25, and the gate of the N-type transistor 112n is electrically connected to the input terminal N1 of the second memory circuit 25. Has been.

  The switch circuit 110 selectively selects one of the first control line 94 and the second control line 95 according to the image signal input to the second memory circuit 25, One of the control lines is electrically connected to the pixel electrode 21.

  Specifically, when a high-level image signal is input to the input terminal N1 of the second memory circuit 25, a low-potential power supply potential is supplied from the second memory circuit 25 to the gates of the N-type transistor 111n and the P-type transistor 112p. Vss is output and the high potential power supply potential VEP is output to the gates of the P-type transistor 111p and the N-type transistor 112n, so that only the P-type transistor 112p and the N-type transistor 112n constituting the second transmission gate 112 are output. Is turned on, and the P-type transistor 111p and the N-type transistor 111n constituting the first transmission gate 111 are turned off. On the other hand, when a low-level image signal is input to the input terminal N1 of the second memory circuit 25, the high-potential power supply potential VEP is output from the second memory circuit 25 to the gates of the N-type transistor 111n and the P-type transistor 112p. In addition, since the low potential power supply potential Vss is output to the gates of the P-type transistor 111p and the N-type transistor 112n, only the P-type transistor 111p and the N-type transistor 111n constituting the first transmission gate 111 are turned on. Thus, the P-type transistor 112p and the N-type transistor 112n constituting the second transmission gate 112 are turned off. That is, when a high-level image signal is input to the input terminal N1 of the second memory circuit 25, only the second transmission gate 112 is turned on, while the input terminal N1 of the second memory circuit 25 is turned on. When a low level image signal is input to the first transmission gate 111, only the first transmission gate 111 is turned on.

  The first control line 94 and the second control line 95 are configured to be able to supply the first potential S1 and the second potential S2 from the power supply circuit 210, respectively. The first control line 94 is electrically connected to the power supply circuit 210 via the switch 94s, and the second control line 95 is electrically connected to the power supply circuit 210 via the switch 95s. The switches 94s and 95s are configured to be switched between an on state and an off state by the control unit 10. When the switch 94s is turned on, the first control line 94 and the power supply circuit 210 are electrically connected, and when the switch 94s is turned off, the first control line 94 is electrically connected. The disconnected high impedance state is obtained. When the switch 95s is turned on, the second control line 95 and the power supply circuit 210 are electrically connected, and when the switch 95s is turned off, the second control line 95 is electrically connected. The disconnected high impedance state is obtained.

  Each pixel electrode 21 of the plurality of pixels 20 is electrically connected to a control line 94 or 95 that is alternatively selected according to an image signal by the switch circuit 110. At that time, the pixel electrode 21 of each of the plurality of pixels 20 is supplied with the first potential S1 or the second potential S2 from the power supply circuit 210 according to the on / off state of the switch 94s or 95s, or is in a high impedance state. It is said.

  More specifically, for the pixel 20 to which the low-level image signal is supplied, only the first transmission gate 111 is turned on, and the pixel electrode 21 of the pixel 20 is electrically connected to the first control line 94. The first potential S1 is supplied from the power supply circuit 210 in accordance with the on / off state of the switch 94s, or a high impedance state is established. On the other hand, for the pixel 20 to which the high-level image signal is supplied, only the second transmission gate 112 is turned on, and the pixel electrode 21 of the pixel 20 is electrically connected to the second control line 95, The second potential S2 is supplied from the power supply circuit 210 in accordance with the on / off state of the switch 95s, or the high impedance state is set.

  The pixel electrode 21 is disposed so as to face the common electrode 22 through the electrophoretic element 23.

  The common electrode 22 is electrically connected to a common potential line 93 to which a common potential Vcom is supplied. The common potential line 93 is configured to be able to supply the common potential Vcom from the common potential supply circuit 220. The common potential line 93 is electrically connected to the common potential supply circuit 220 via the switch 93s. The switch 93 s is configured to be switched between an on state and an off state by the control unit 10. When the switch 93s is turned on, the common potential line 93 and the common potential supply circuit 220 are electrically connected, and when the switch 93s is turned off, the common potential line 93 is electrically disconnected. High impedance state.

  The electrophoretic element 23 is composed of a plurality of microcapsules each containing electrophoretic particles.

  Next, a specific configuration of the display unit of the electrophoretic display device according to the present embodiment will be described with reference to FIGS. 3 and 4.

  FIG. 3 is a partial cross-sectional view of the display unit of the electrophoretic display device according to this embodiment.

  In FIG. 3, the display unit 3 is configured such that an electrophoretic element 23 is sandwiched between an element substrate 28 and a counter substrate 29. In the present embodiment, description will be made on the assumption that an image is displayed on the counter substrate 29 side.

  The element substrate 28 is a substrate made of, for example, glass or plastic. Although not shown here on the element substrate 28, the control switch 24, the first and second memory structures, the scanning line 40, the data line 50, and the high-potential power line described above with reference to FIG. 91, a low-potential power line 92, a common potential line 93, a first control line 94, a second control line 95, and the like are formed. A plurality of pixel electrodes 21 are provided in a matrix on the upper layer side of the stacked structure.

  The counter substrate 29 is a transparent substrate made of, for example, glass or plastic. On the surface of the counter substrate 29 facing the element substrate 28, the common electrode 22 is formed in a solid shape so as to face the plurality of pixel electrodes 9a. The common electrode 22 is formed of a transparent conductive material such as magnesium silver (MgAg), indium / tin oxide (ITO), indium / zinc oxide (IZO), or the like.

  The electrophoretic element 23 is composed of a plurality of microcapsules 80 each including electrophoretic particles, and is fixed between the element substrate 28 and the counter substrate 29 by a binder 30 and an adhesive layer 31 made of, for example, resin. . In the electrophoretic display device 1 according to the present embodiment, in the manufacturing process, an electrophoretic sheet in which the electrophoretic element 23 is previously fixed to the counter substrate 29 side by the binder 30 is separately manufactured, such as the pixel electrode 21. It is bonded to the element substrate 28 side where is formed by an adhesive layer 31.

  One or a plurality of microcapsules 80 are sandwiched between the pixel electrode 21 and the common electrode 22 and arranged in one pixel 20 (in other words, with respect to one pixel electrode 21).

  FIG. 4 is a schematic diagram showing the configuration of the microcapsule. In addition, in FIG. 4, the cross section of the microcapsule is shown typically.

  In FIG. 4, a microcapsule 80 is formed by enclosing a dispersion medium 81, a plurality of white particles 82 and a plurality of black particles 83, which are electrophoretic particles, inside a coating 85. The microcapsule 80 is formed in a spherical shape having a particle size of about 50 μm, for example.

  The coating 85 functions as an outer shell of the microcapsule 80 and is formed of a translucent polymer resin such as acrylic resin such as polymethyl methacrylate and polyethyl methacrylate, urea resin, and gum arabic.

  The dispersion medium 81 is a medium for dispersing the white particles 82 and the black particles 83 in the microcapsules 80 (in other words, in the coating 85). Examples of the dispersion medium 81 include water, alcohol solvents such as methanol, ethanol, isopropanol, butanol, octanol, and methyl cellosolve, various esters such as ethyl acetate and butyl acetate, and ketones such as acetone, methyl ethyl ketone, and methyl isobutyl ketone. , Aliphatic hydrocarbons such as pentane, hexane and octane, alicyclic hydrocarbons such as cyclohexane and methylcyclohexane, benzene, toluene, xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecyl Aromatic hydrocarbons such as benzenes with long chain alkyl groups such as benzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene, etc., halo such as methylene chloride, chloroform, carbon tetrachloride, 1,2-dichloroethane, etc. Emissions of hydrocarbons, carboxylate or other oils may be used singly or as a mixture. In addition, a surfactant may be added to the dispersion medium 81.

  The white particles 82 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white (zinc oxide), and antimony trioxide, and are negatively charged, for example.

  The black particles 83 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are positively charged, for example.

  For this reason, the white particles 82 and the black particles 83 can move in the dispersion medium 81 by the electric field generated by the potential difference between the pixel electrode 21 and the common electrode 22.

  These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, charge control agents composed of particles such as compounds, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.

  3 and FIG. 4, when a voltage is applied between the pixel electrode 21 and the common electrode 22 so that the potential of the common electrode 22 is relatively high, the positively charged black particles 83 are While being attracted to the pixel electrode 21 side in the microcapsule 80 by the Coulomb force, the negatively charged white particles 82 are attracted to the common electrode 22 side in the microcapsule 80 by the Coulomb force. As a result, the white particles 82 gather on the display surface side (that is, the common electrode 22 side) inside the microcapsule 80, thereby displaying the color of the white particles 82 (that is, white) on the display surface of the display unit 3. Can do. Conversely, when a voltage is applied between the pixel electrode 21 and the common electrode 22 so that the potential of the pixel electrode 21 becomes relatively high, the negatively charged white particles 82 are generated by the Coulomb force. While attracted to the electrode 21 side, the positively charged black particles 83 are attracted to the common electrode 22 side by Coulomb force. As a result, the black particles 83 are collected on the display surface side of the microcapsule 80, whereby the color of the black particles 83 (that is, black) can be displayed on the display surface of the display unit 3.

  Furthermore, it is also possible to display an intermediate gradation between white and black depending on the distribution state of the white particles 82 and the black particles 83 between the pixel electrode 21 and the common electrode 22. Further, by replacing the pigments used for the white particles 82 and the black particles 83 with pigments such as red, green, and blue, for example, color display such as red, green, and blue is possible.

  Next, a display operation in the electrophoretic display device of this embodiment will be described with reference to FIG.

  FIG. 5 is a flowchart for explaining a display operation in the electrophoretic display device.

  In the present embodiment, as an example, a display operation when an X image is displayed as the first image on the display unit 3 in FIG. 1 and a Y image is switched as the second image will be described with reference to FIG. When switching from the X image to the Y image, an X inverted image obtained by inverting the gradation of the X image between the X image and the Y image, and a Y inverted image obtained by changing the gradation of the Y image following the X inverted image. It is assumed that an operation of deleting the X image is performed by drawing.

  1 and 5, first, the scanning line driving circuit 60 sequentially supplies scanning signals to the scanning lines Y1, Y2,... Ym, and one of the scanning lines Y1, Y2,. In a period in which one row of pixels 20 corresponding to the scanning line is selected, the data line driving circuit 70 supplies an image signal for X image drawing to the scanning lines Y1, Y2, and Xn through the data lines X1, X2,. Step S1). As a result, in each pixel 20, an image signal is written from the drive switch 240 (see FIG. 2) to the storage capacitor constituting the first memory circuit 250 in accordance with the scanning signal.

  Next, a control signal is supplied from the control unit 10 via the control signal line 96, and the control switch 24 is turned on (step S2).

  Subsequently, the image signal for X image drawing held in the first memory circuit 250 according to the control signal is input to the input terminal N1 of the second memory circuit 25 via the control switch 24 (step S1). S3).

  Here, in FIG. 1, the power supply circuit 210 supplies a high potential power supply potential VEP of a high level (for example, 5 V) and a low potential power supply potential Vss (for example, 0 V) of a low level. In FIG. 2, the high potential power supply potential VEP and the low potential power supply potential Vss are supplied to the high potential power supply line 91 and the low potential power supply line 92 via the switches 91s and 92s which are turned on, respectively. On the other hand, in the operation according to step S3, the power supply circuit 210 does not supply the first potential S1 and the second potential S2, the common potential supply circuit 220 does not supply the common potential Vcom, and the switch 93s, 94s and 95s are in an off state. Therefore, the common potential line 93, the first control line 94, and the second control line 95 shown in FIG. 2 are in a high impedance state.

  Subsequently, when the control unit 10 stops supplying the control signal to the control signal line 96, the control switch 24 is also turned off (step S4). As a result, the electrical connection between the first memory structure 700 and the second memory structure 800 in FIG. 2 is disconnected.

  Subsequently, the power supply circuit 210 boosts and supplies a high-level (for example, 15 V) high-potential power-supply potential VEP, supplies a low-level low-potential power-supply potential Vss (for example, 0 V), and supplies the first potential S1. The high potential (for example, 15V) is supplied, and the second potential S2 is supplied as the low level (for example, 0V) (step S5). In this case, the second potential S2 is not supplied in the period in which the first potential S1 is supplied, and the first potential S1 is not supplied in the period in which the second potential S2 is supplied.

  Further, the common potential supply circuit 220 preferably supplies the common potential Vcom by periodically varying it to either a low level (eg, 0 V) or a high level (eg, 15 V). As a result, so-called “common swing drive” is performed.

  The high potential power supply potential VEP and the low potential power supply potential Vss, the first potential S1 and the second potential S2, and the common potential Vcom supplied in this way are the switches 91s, 92s, 93s, 94s and 95s that are turned on. 2 is supplied to various wirings 91, 92, 93, 94 and 95 shown in FIG. However, during the period in which the first potential S1 is supplied, the first control line 94 is electrically connected to the power supply circuit 210 via the switch 94s, and the corresponding switch 95s is turned off in the second control line 95. Since it is in a state, it is in a high impedance state. On the other hand, in the period during which the second potential S2 is supplied, the second control line 95 is electrically connected to the power supply circuit 210 via the switch 95s, and the corresponding switch 94s is connected to the first control line 94. Since it is turned off, it is in a high impedance state.

  A low level or high level image signal is held in the second memory circuit 25 of each pixel 20. Therefore, in each pixel 20, the first transmission gate 111 and the second transmission gate 112 of the switch circuit 110 according to the outputs (the high potential power supply potential VEP and the low potential power supply potential Vss) from the second memory circuit 25. One of is in the on state.

  Specifically, in the pixel 20 to which a low-level image signal is input, only the first transmission gate 111 is in an on state, and the pixel electrode 21 is electrically connected to the first control line 94. In the pixel 20 to which a high-level image signal is input, only the second transmission gate 112 is on, and the pixel electrode 21 is electrically connected to the second control line 95.

  Accordingly, in the pixel 20 to which the low-level image signal is input, the first potential S1 (high level, for example, 15 V) is supplied from the first control line 94 to the pixel electrode 21 and supplied from the common potential line 93. Black display is performed based on the potential difference between the common electrode 22 and the common electrode 22 that occurs when the common potential Vcom is at a low level (eg, 0 V). On the other hand, in the pixel 20 to which the high-level image signal is input, the second potential S <b> 2 (low level, for example, 0 V) is supplied from the second control line 95 to the pixel electrode 21 and supplied from the common potential line 93. Based on the potential difference between the common electrode 22 and the common electrode 22 generated when the common potential Vcom is at a high level (for example, 15 V), white display is performed. As a result, the X image is drawn and displayed on the display unit 3.

  Here, the operation according to step S6 is performed in parallel with the operation according to step S5. In FIG. 1, the data line driving circuit 70 is connected to the data line during a period in which the pixels 20 in each row corresponding to each of the scanning lines Y1, Y2,... Ym are selected based on the scanning signal supplied from the scanning line driving circuit 60. Image signals for Y image drawing are supplied to X1, X2,... Xn (step S6). In FIG. 2, in each pixel 20, the image signal is written from the driving switch 240 to the storage capacitor constituting the first memory circuit 250 in accordance with the scanning signal. At this time, as described above, the control switch 24 is in an OFF state, and the electrical connection between the first memory structure portion 700 and the second memory structure portion 800 is disconnected.

  After the operation related to each of step S5 and step S6 is completed, an X inverted image for erasing the X image is drawn in order to perform display switching on the display unit 3 (step S7). At this time, the electrical connection between the first memory structure portion 700 and the second memory structure portion 800 is disconnected.

  In the operation according to step S7, similarly to the operation according to step S5, the high potential power supply potential VEP (high level, for example, 15V) and the low potential power supply potential Vss (low level, for example, 0V) are supplied, and the common potential Vcom. (High level, for example, 15 V or low level, for example, 0 V) is supplied, and common swing driving is preferably performed. Further, the power supply circuit 210 is supplied with the first potential S1 at a low level (eg, 0 V) and the second potential S2 at a high level (eg, 15 V). Note that, similarly to the operation according to step S5, the second potential S2 is not supplied in the period in which the first potential S1 is supplied, and the first potential S1 is supplied in the period in which the second potential S2 is supplied. Not. Therefore, the second control line 95 is in a high impedance state during the period during which the first potential S1 is supplied, and the first control line 94 is in a high impedance state during the period during which the second potential S2 is supplied. It becomes.

  At this time, in the display unit 3, in the pixel 20 to which the low-level image signal is input, only the first transmission gate 111 is on, and the pixel electrode 21 is electrically connected to the first control line 94. ing. In the pixel 20 to which a high-level image signal is input, only the second transmission gate 112 is on, and the pixel electrode 21 is electrically connected to the second control line 95.

  Accordingly, in the pixel 20 to which the low-level image signal is input, the first potential S1 (low level, for example, 0 V) is supplied from the first control line 94 to the pixel electrode 21 and is supplied from the common potential line 93. Based on the potential difference between the common electrode 22 and the common electrode 22 that occurs when the common potential Vcom is at a high level (for example, 15 V), white display is performed. On the other hand, in the pixel 20 to which the high-level image signal is input, the second potential S2 (high level, for example, 15 V) is supplied from the second control line 95 to the pixel electrode 21 and supplied from the common potential line 93. Black display is performed based on the potential difference with the common electrode 22 that occurs when the common potential Vcom is at a low level (eg, 0 V). As a result, the display unit 3 draws and displays an X inverted image in which the gradation of the X image is inverted.

  Thereafter, the supply of various power supplies from the power supply circuit 210 and the common potential supply circuit 220 is stopped, and the switches 91s, 92s, 93s, 94s, and 95s are turned off for the pixel 20 shown in FIG. 2 (step S8). . Accordingly, the high potential power supply line 91, the low potential power supply line 92, the common potential line 93, the first control line 94, and the second control line 95 are all in a high impedance state (Hi-Z).

  Subsequently, the control switch 24 is turned on in response to the control signal (step S9), and thereafter, the high potential power supply potential VEP (for example, 5 V) and the low potential from the power supply circuit 210 are the same as the operation according to step S3 described above. The second memory circuit 25 is driven by supplying the power supply potential Vss (for example, 0 V) (step S10). As a result, the image signal for Y image drawing held in the first memory circuit 250 is input to the input terminal N1 of the second memory circuit 25 via the control switch 24 (step S11). Thereafter, the control switch 24 is turned off, and the electrical connection between the first memory structure portion 700 and the second memory structure portion 800 is disconnected.

  Subsequently, the X inverted image is switched to a Y inverted image for erasing the X image in the same manner (step S12). At this time, as in the operation according to step S7, various potentials are supplied, and common swing driving is preferably performed.

  The second memory circuit 25 of each pixel 20 is in a state where a low-level or high-level image signal is held, and in the pixel 20 to which the low-level image signal is input, only the first transmission gate 111 is turned on. In this state, the pixel electrode 21 is electrically connected to the first control line 94. In the pixel 20 to which a high-level image signal is input, only the second transmission gate 112 is on, and the pixel electrode 21 is electrically connected to the second control line 95. Therefore, similar to the operation according to step S7, white display is performed on the pixel 20 to which the low-level image signal is input, and black display is performed on the pixel 20 to which the high-level image signal is input. As a result, a Y-reversed image obtained by reversing the tone of the Y image is drawn and displayed on the display unit 3.

  Thereafter, a Y image obtained by reversing the gradation of the Y inverted image is displayed (step S13). At this time, as in the operation according to step S12, various potentials are supplied, and common swing driving is preferably performed. Further, the power supply circuit 210 supplies the first potential S1 at a high level (for example, 15 V) and the second potential S2 at a low level (for example, 0 V). Note that, during the period in which the first potential S1 is supplied, the second control line 95 is in a high impedance state without being supplied with the second potential S2, and during the period in which the second potential S2 is supplied, The first control line 94 is not supplied with the first potential S1 and is in a high impedance state.

  In the pixel 20 to which the low-level image signal is input, only the first transmission gate 111 is in an on state, and the pixel electrode 21 is electrically connected to the first control line 94. Accordingly, the first potential S1 (high level, for example, 15V) is supplied from the first control line 94 to the pixel electrode 21, and black display is performed.

  In the pixel 20 to which a high-level image signal is input, only the second transmission gate 112 is on, and the pixel electrode 21 is electrically connected to the second control line 95. Therefore, the second potential S2 (low level, for example, 0 V) is supplied from the second control line 95 to the pixel electrode 21, and white display is performed. As a result, a Y image is displayed on the display unit 3.

  In the display operation as described above, in the second memory structure 800, the second memory circuit 25 constituted by the SRAM is a voltage based on a potential difference (for example, 5 V) between the high potential power supply potential VEP and the low potential power supply potential Vss. The image signal held in the first memory circuit 250 is written and when the X image, the X inverted image, the Y inverted image, and the Y image are displayed, the boosted high potential is applied. It is driven by a voltage based on a potential difference (for example, 15 V) between the power supply potential VEP and the low potential power supply potential Vss. That is, in this case, a minimum voltage required to drive the second memory circuit 25 is supplied to write an image signal, and then a predetermined potential difference (for example, 15 V) is applied between the pixel electrode 21 and the common electrode 22. Therefore, the voltage required for driving the second memory circuit 25 is boosted, and the first potential S1 or the second potential S2 is supplied to the pixel electrode 21 in this state.

  Therefore, each pixel 20 can be operated with lower power consumption as compared with the case where the second memory circuit 25 is always driven with a voltage required for setting a predetermined potential difference (for example, 15 V) between the pixel electrode 21 and the common electrode 22. Can be driven.

  Further, in order to display each of the X image, the X inverted image, the Y inverted image, and the Y image, adjacent pixels in which the pixel electrode 21 is maintained at different potentials (high level, for example, 15 V and low level, for example, 0 V). Reference numeral 20 denotes a state in which the pixel electrode 21 is electrically connected to the control lines 94 and 95 different from each other by the switch circuit 110 and the potential is supplied to the pixel electrode 21 on one side via the control line 94 or 95. The control line 94 or 95 corresponding to the other is in a high impedance state in which the electrical connection is cut off. Specifically, in the pixel 20 to which the low level image signal is input, the pixel electrode 21 is electrically connected to the first control line 94, and in the pixel 20 to which the high level image signal is input, the pixel electrode 21 is connected. Are electrically connected to the second control line 95. In addition, in a period in which the first potential S1 is supplied via the first control line 94, the second control line 95 is in a high impedance state, and the second potential S2 passes through the second control line 95. In the period supplied through the first control line 94, the first control line 94 is in a high impedance state. In each pixel 20, the first control line 94 and the second control line 95 are in a high impedance state during a period in which an image signal is written in the other second memory circuit 25. Therefore, it is possible to effectively prevent a leak current from occurring between adjacent pixels 20 in which the pixel electrodes 21 are maintained at different potentials.

  Next, only a main configuration different from the present embodiment will be described with respect to the comparative example with reference to FIG.

  FIG. 6 is an equivalent circuit diagram illustrating the electrical configuration of the pixel in the comparative example.

  In the comparative example, the main difference between the circuit configuration of the pixel 20 and the present embodiment is that the first memory structure unit 700 shown in FIG. 2 is not provided and the same memory as the second memory structure unit 800 is provided. It has a structure. That is, in FIG. 6, the pixel 20 is provided with a pixel switching transistor 24 similar to the drive switch 240 shown in FIG. 2, and includes a memory circuit 25 and a switch circuit 110 similar to the second memory circuit. Therefore, unlike the present embodiment, since the control switch 24 as shown in FIG. 2 is not provided, the control signal line 96 is not wired to the display unit 3 (see FIG. 1 or FIG. 2), and the control signal Is not supplied.

  In this case, when a display operation similar to that described with reference to FIG. 5 is performed, referring to FIG. 5, the scanning line driving circuit 60 and the data line driving circuit 70 are driven in the same manner as the operation according to step S1. Then, an image signal for drawing an X image is supplied to each pixel 20, and after the image signal is written in the memory circuit 25 as in step S3, the X image is displayed in the display unit 3 in the same manner as in the operation according to step S5. Is drawn and displayed. Thereafter, in order to perform erasure with the Y inverted image after erasure with the X inverted image is performed in the same manner as the operation according to step S7 in FIG. 5, the operation similar to the operation according to step S6 is performed to perform Y image drawing. It is necessary to write the image signal for use in the memory circuit 25.

  That is, the pixel 20 of the comparative example shown in FIG. 6 has a circuit configuration in which an image signal for Y image drawing cannot be written simultaneously with drawing of an X image or an X inverted image. . Therefore, since the time length required for switching from the X inverted image to the Y inverted image becomes larger, the time for which the display of the meaningless X inverted image is performed on the display unit 3 becomes longer.

  On the other hand, in this embodiment, as shown in FIG. 5, the operation according to step S6 is performed in parallel with the operation according to step S5, and each pixel 20 is selected in a state where the X image is displayed. Thus, an image signal for Y image drawing can be supplied to the first memory structure 700.

  Here, when the image signal for Y image drawing is written from the first memory structure portion 700 to the second memory structure portion 800 in the operation according to step S11, the pixel electrode 21 has the first potential S1 or the second potential. The potential S2 of 2 cannot be supplied and the Y inverted image cannot be drawn, but the operation of the scanning line driving circuit 60 and the data line driving circuit 70 for supplying the image signal to each pixel 20 is not possible. Is no longer necessary. Therefore, the time length required for writing the image signal for Y image drawing for displaying the Y inverted image after the X inverted image is set to the scanning line driving circuit 60 and the scanning line driving circuit 60 after the X inverted image is displayed as in the comparative example. Compared with the case where the data line driving circuit 70 is driven, it can be drastically shortened.

  Therefore, the time length required for switching from the X reverse image to the Y reverse image can be drastically shortened, and the time for displaying the meaningless X reverse image can be shortened. As a result, it is possible to quickly switch the display from the X image to the Y image. For example, even when a moving image is displayed on the display unit 3, a higher quality display can be performed.

  Next, electronic devices to which the above-described electrophoretic display device is applied will be described with reference to FIGS. Below, the case where the electrophoretic display device described above is applied to electronic paper and an electronic notebook is taken as an example.

  FIG. 7 is a perspective view illustrating a configuration of the electronic paper 1400.

  As illustrated in FIG. 7, the electronic paper 1400 includes the electrophoretic display device according to the above-described embodiment as a display unit 1401. The electronic paper 1400 has flexibility, and includes a main body 1402 formed of a rewritable sheet having the same texture and flexibility as conventional paper.

  FIG. 8 is a perspective view showing the configuration of the electronic notebook 1500.

  As shown in FIG. 8, an electronic notebook 1500 is obtained by bundling a plurality of electronic papers 1400 shown in FIG. 7 and sandwiching them between covers 1501. The cover 1501 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

  Since the above-described electronic paper 1400 and electronic notebook 1500 include the electrophoretic display device according to the above-described embodiment, power consumption is small and high-quality image display can be performed.

  In addition to these, the electrophoretic display device according to the present embodiment described above can be applied to the display unit of an electronic device such as a wristwatch, a mobile phone, or a portable audio device.

  The present invention is not limited to the above-described embodiments, and can be changed as appropriate without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. An electrophoretic display device, a driving method thereof, and an electronic apparatus including the electrophoretic display device are also included in the technical scope of the present invention.

It is a block diagram which shows the whole structure of the electrophoretic display device which concerns on this embodiment. It is an equivalent circuit diagram which shows the electrical structure of a pixel. It is a fragmentary sectional view of the display part of the electrophoretic display device concerning this embodiment. It is a schematic diagram which shows the structure of a microcapsule. It is a flowchart for demonstrating the display operation in an electrophoretic display device. It is an equivalent circuit diagram which shows the electrical structure of the pixel in a comparative example. It is a perspective view which shows the structure of the electronic paper which is an example of the electronic device to which the electrophoretic display apparatus is applied. It is a perspective view which shows the structure of the electronic notebook which is an example of the electronic device to which an electrophoretic display apparatus is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Electrophoretic display apparatus, 3 ... Display part, 20 ... Pixel, 21 ... Pixel electrode, 22 ... Common electrode, 23 ... Electrophoretic element, 24 ... Control switch, 25 ... Second memory circuit, 28 ... Element substrate 29 ... Counter substrate, 80 ... Microcapsule, 82 ... White particles, 83 ... Black particles, 110 ... Switch circuit, 240 ... Driving switch, 250 ... First memory circuit, 700 ... First memory structure, 800 ... Second memory structure

Claims (7)

A pixel circuit that includes each of a plurality of pixels in a display unit of an electrophoretic display device and includes an electrophoretic element that is driven based on a potential difference applied between a pixel electrode and a common electrode facing the pixel electrode. There,
At least two memory structures each having a memory circuit;
A control switch for controlling electrical connection between each of the at least two memory structures,
With respect to the memory circuit included in one memory structure portion of the at least two memory structure portions, electrical connection with the other memory structure portions of the at least two memory structure portions is disconnected by the control switch. An image signal is written during a period in which the pixel is selected in a state where the image signal held in the one memory structure unit is controlled by the control circuit with respect to the memory circuit included in the other memory structure unit. Written through the switch for
The pixel circuit, wherein the potential of the pixel electrode is controlled based on the image signal held in the other memory structure unit.   The pixel circuit according to claim 1, wherein the memory circuit included in the other memory structure unit includes an SRAM.   The other memory structure section supplies a predetermined potential to the pixel electrode by performing switching control of the pixel electrode according to an output based on the image signal from the memory circuit included in the other memory structure section. The pixel circuit according to claim 1, further comprising a switch circuit.   4. The pixel circuit according to claim 1, wherein the memory circuit included in the one memory structure unit includes a storage capacitor. 5.   An electrophoretic display device comprising the pixel circuit according to claim 1. An electrophoretic element driven based on a potential difference applied between a pixel electrode and a common electrode facing the pixel electrode; at least two memory structure units each having a memory circuit; and the at least two memory structure units A driving method of an electrophoretic display device for driving an electrophoretic display device including a display unit including a plurality of pixels each provided with a control switch for controlling electrical connection between each of
The pixel is selected, and the memory circuit included in one of the at least two memory structure units is connected to another memory structure unit of the at least two memory structure units by the control switch. A first step of writing an image signal with the electrical connection disconnected;
A second step of writing the image signal held in the one memory structure section to the memory circuit of the other memory structure section via the control switch;
And a third step of controlling the potential of the pixel electrode based on the image signal held in the other memory structure unit.   An electronic apparatus comprising the electrophoretic display device according to claim 5.

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