JP2001188520A - Opto-electric device, drive circuit of the device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate pulses, having a uniform pulse width to drive data and scanning lines of an optoelectric device. SOLUTION: For example, a data line driving circuit 140 is constituted of a shift register 1410 and a selecting circuit group 1420. The group 1420 has plural selecting circuits S1 to Sn, selects enable signal EN pulses, based on drive pulses T1 to Tn and outputs the pulses as drive pulses T1 to Tn. Thus, an active interval of the pulses T1 to Tn is made constant, the time of writing for each pixel via a sampling circuit 150 becomes constant, and the display quality is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a driving circuit, an electro-optical device, and an electronic apparatus of an electro-optical device capable of performing high-quality display.

[0002]

2. Description of the Related Art As is well known, an active matrix type liquid crystal display, which is an example of an electro-optical device, has a liquid crystal sandwiched between an element substrate and a counter substrate. Here, on the element substrate, a plurality of data lines, a plurality of scanning lines intersecting these data lines, and pixels located at intersections of the respective data lines and the respective scanning lines are formed. Each pixel is composed of a pixel electrode and a switching element. The switching element in each pixel conducts when a selection voltage is output to a scanning line corresponding to the pixel, and plays a role of applying a data signal supplied to a data line corresponding to the pixel to a pixel electrode. A drive circuit is formed on the element substrate in addition to the above-described components. The driving circuit includes a scanning line driving circuit for driving a scanning line and a data line driving circuit for driving a data line.

In such a configuration, for example, a selection voltage is applied to a scanning line by a scanning line driving circuit in each horizontal scanning period within one frame (one vertical scanning) period, and a plurality of scanning lines are applied to one scanning period in one frame period. The selection voltages are sequentially supplied. Then, while the selection voltage is being output to each scanning line, the data line driving circuit sequentially outputs image signals corresponding to the display gradation of each pixel to the plurality of data lines, and are arranged along the scanning line. An image signal is applied to pixel electrodes of a series of pixels.

As described above, during one frame period, an image signal corresponding to the display gradation of each pixel is applied to the pixel electrodes of all the pixels, and pixel display is performed.

FIG. 17 is a block diagram showing a conventional configuration example of a data line driving circuit used in the above-described electro-optical device.

In FIG. 17, a data line driving circuit 140
0 is a latch circuit 1430-k (k = 1 to n + 1);
It is composed of a NAND circuit 1464-k (k = 1 to n) and an inverter 1465-k (k = 1 to n).

The latch circuit 1430-k (k = 1 to n +
1) are cascaded as shown, and n +
This constitutes a one-stage shift register. Each latch circuit 1
Reference numerals 430-k denote circuits for fetching and holding input data with a two-phase clock, respectively, and are supplied with a clock signal CLK and its inverted clock signal CLKINV. The odd-numbered latch circuits 1430-k
(K is an odd number) has a configuration in which input data is output when the clock signal CLK is at a high level and the inverted clock signal CLKINV is at a low level, and an even-numbered stage latch circuit 1430-k (k is an even number) Is the clock signal CLK
Is low level, and the input data is output when the inverted clock signal CLKINV is high level.

The first-stage latch circuit 1430-1 is supplied with a drive start command pulse DX. This drive start command pulse DX is a pulse generated at the start of the horizontal scanning period. First stage latch circuit 1430-1
Shifts the drive start command pulse DX in response to the rising edge of the clock signal CLK and the falling edge of the inverted clock signal CLKINV and outputs it as a pulse E1.
The second-stage latch circuit 1430-2 shifts this pulse E1 and outputs it as a pulse E2 in response to the subsequent fall of the clock signal CLK and the rise of the inverted clock signal CLKINV. The subsequent stages operate in the same manner, whereby a plurality of delay pulses E1 to En + 1, each of which is sequentially shifted in phase by a half cycle of the clock signal CLK (inverted clock signal CLKINV), is composed of n + 1 latch circuits 1430-k ( k = 1 to n + 1). n NAND gates 1464-k (k = 1 to n)
, A pulse Ek output from the latch circuit 1430-k and a pulse Ek + 1 output from the latch circuit 1430- (k + 1) are input. Inverter 14
65-k (k = 1 to n) is a NAND gate 1464-
The selection pulses of k (k = 1 to n) are inverted and output as drive pulses Fk (k = 1 to n).

In the example shown in FIG. 17, n data lines D1 to Dn are arranged on the element substrate of the electro-optical device, and a sampling circuit 1440 is provided. This sampling circuit 1440 includes n switching elements 14
41-k (k = 1 to n). These switching elements 1441-k (k = 1 to n) are n
It is interposed between each data line and a signal line for supplying the image signal VID.

FIG. 18 is a timing chart showing the operation of the data line driving circuit 1400 described above.

A driving start command pulse DX is input at the beginning of the horizontal scanning period, and the clock signal CLX rises (timing clock signal CL) at a timing t1 immediately after the driving start command pulse DX.
XINV falls), whereby the drive start command pulse DX is captured by the first-stage latch circuit 1430-1.
The selection pulse E1 of the first-stage latch circuit 1430-1 becomes high level.

Next, when the clock signal CLX falls at the timing t2 (the inverted clock signal CLXINV
Rises), the second stage latch circuit 1430-2 captures the selection pulse E1 of the first stage latch circuit 1430-1. As a result, the selection pulse E2 of the second-stage latch circuit 1430-2 becomes high level. On the other hand, the first-stage latch circuit 1430-1 does not take in input data depending on the falling of the clock signal CLX (the rising of the inverted clock signal CLXINV), and retains the previously taken data. Still at high level.

Next, when the drive start command pulse DX falls to the low level, and thereafter, when the clock signal CLX rises at the timing t3 (the inverted clock signal CLX).
When INV falls), the first-stage latch circuit 1430-1
Receives the low-level input data and selects the selection pulse E
Output as 1. The second-stage latch circuit 1430-
The second selection pulse E2 maintains the high level. Further, the third-stage latch circuit 1430-3 includes the second-stage latch circuit 1430.
30-2 selection pulse E2 (high level) is taken in,
Output as the selection pulse E3.

Hereinafter, similarly, odd-numbered latch circuits 143
When the clock signal CLX rises (the inverted clock signal CLXINV falls), 0-k (k is an odd number) is the selection pulse E of the preceding latch circuit 1430- (k-1).
The clock signal CLX falls (inverted clock signal CLXINV) at the even-numbered latch circuits 1430-k (k is an even number).
Rises), the preceding latch circuit 1430- (k
-1) is fetched and the selection pulse E
Output as k.

As a result of performing such a shift operation, as shown in FIG. 18, each of the clock signals has a pulse width of one cycle of the clock signal CLX (inverted clock signal CLXINV) and the clock signal CLX (inverted clock signal CLXINV). CLXIN
N) pulses Ek (k = 1 to n + 1) having phases shifted from each other by a half cycle of the latch circuit 1430-k
(K = 1 to n + 1) and output from the NAND gate 14
64-k (k = 1 to n).

Here, the NAND gate 1464-k (k
= 1 to n), two adjacent latch circuits 1
464-k and 1464- (k + 1) selection pulses E
k and Ek + 1 are input. Therefore, as shown in FIG. 18, each pulse has a pulse width corresponding to a half cycle of the clock signal CLX (inverted clock signal CLXINV), and has a phase difference of half a cycle of the clock signal CLX (inverted clock signal CLXINV). N drive pulses Fk (k
= 1 to n) are the respective NAND gates 1464-k (k = 1 to
n) Each subsequent inverter 1464-k (k = 1 to n)
Output from

These drive pulses Fk (k = 1 to n)
Are supplied to the switching elements 1441-k (k = 1 to n), respectively.

The switching elements 1441-k (k = 1 to n) are sequentially turned on by the driving pulse Fk (k = 1 to n). And each switching element 14
The image signal VID is sequentially applied to the data lines Dk (k = 1 to n) via 41-k (k = 1 to n).

[0019]

By the way, the driving circuit of the above-mentioned conventional electro-optical device is constituted by using an active element such as a thin film transistor (hereinafter referred to as "TFT") on an element substrate. I have. Here, in order to perform high-quality display with no display unevenness by the electro-optical device, it is necessary to obtain a drive pulse Fk (k = 1 to n) having a uniform pulse width from a drive circuit. It is desired that each TFT constituting this drive circuit has uniform characteristics. However, it is difficult to form a TFT having uniform characteristics over a wide range on an element substrate, and manufacturing variations occur in the threshold voltage and mutual conductance of the formed TFT depending on the location on the element substrate. For this reason, when a conventional drive circuit as illustrated in FIG. 17 is employed, the pulse width of the drive pulse Fk (k = 1 to n) output from this drive circuit becomes non-uniform.

For example, the drive pulse F1 rises when the selection pulse E2 of the latch circuit 1430-2 rises due to the fall of the clock signal CLX (rise of the inverted clock signal CLXINV), and rises to the clock signal CLX (the inverted clock signal CLXINV). (Fall), the selection pulse E1 of the latch circuit 1430-1 falls.

Accordingly, the pulse width ta of the driving pulse F1 is obtained.
Becomes ta = tw-td1 + td2. Here, tw is the cycle of the clock signal CLX (inverted clock signal CLXINV). Also, td1
Is the falling edge of the clock signal CLX (the rising edge of the inverted clock signal CLXINV) → the latch circuit 1430-2
Is the delay time when signal propagation is performed from the rise of the selection pulse E2 to the rise of the drive pulse F1. Further, td2 is a delay time when signal propagation is performed such as rising of the clock signal CLX (falling of the inverted clock signal CLXINV) → falling of the selection pulse E1 of the latch circuit 1430-1 → falling of the drive pulse F1. is there. The same applies to the other drive pulses F2 to Fn.

Here, each TFT formed on the element substrate
If the threshold voltage or the mutual conductance varies between them, the td1 and td2 vary between the signal propagation paths related to the drive pulses F1 to Fn.

In this case, for example, in a signal propagation path related to the generation of a certain driving pulse Fi, td1 increases, the pulse width ta of the driving pulse Fi decreases, and the signal propagation related to the generation of another driving pulse Fj. In the route t
It is possible that d2 increases and the pulse width ta of the drive pulse Fj increases.

In the case of the conventional driving circuit shown in FIG. 17, the driving pulse Fk (k = 1 to n) is applied to the inverter 14
65-k (k = 1 to n). If the threshold voltages and the mutual conductances of the TFTs constituting these inverters vary, the driving pulse Fk (k = 1 to n) varies.
The pulse width of n) varies.

When the pulse width of the drive pulse Fk varies in this way, the time during which the switching element is turned on differs depending on the data line. For this reason, for example, when the same pixel signal is applied to all data lines, the voltage held in each data line varies due to the variation in the time during which the switching element is turned on, and the display quality of the electro-optical device increases. It may cause deterioration.

The present invention has been made in view of the above circumstances, and can generate a pulse having a uniform pulse width as a pulse for driving a data line or a scanning line of an electro-optical device. An object of the present invention is to provide a driving circuit of an electro-optical device, an electro-optical device, and an electronic apparatus using the electro-optical device for a display portion.

[0027]

In order to solve the above-mentioned problems, the present invention comprises a plurality of scanning lines, a plurality of data lines, and a plurality of pixels driven through the scanning lines and the data lines. A delay circuit for sequentially delaying a pulse-like drive start command signal and outputting a plurality of selection pulses having different phases, and a clock signal common to one of the plurality of selection pulses. Entered,
A plurality of selection circuits for selecting and outputting a pulse within a period in which the selection pulse is input from the clock signal, wherein the plurality of scanning lines or the plurality of scanning lines are selected by a plurality of pulses selected by the plurality of selection circuits. A driving circuit for an electro-optical device, wherein the driving circuit drives the plurality of data lines.

According to such a drive circuit, a plurality of pulses having different phases are extracted from the common clock signal by the plurality of selection circuits and used for driving the scanning line or the data line. Therefore, the width of the pulse used for driving can be made uniform between the scanning lines or between the data lines, and high-quality display without display unevenness can be performed.

In a preferred aspect of the present invention, the driving circuit includes a plurality of switching elements interposed between the image signal supply source and the plurality of data lines, the plurality of switching elements being selected by the plurality of selection circuits. On / off driving is performed by a driving pulse.

In another aspect of the present invention, the driving circuit drives the plurality of scanning lines with a plurality of driving pulses selected by the plurality of selecting circuits.

In the driving circuit according to the present invention, the plurality of selecting circuits include a selecting circuit for selecting a positive pulse from the clock signal and a selecting circuit for selecting a negative pulse from the clock signal. The data line or the scanning line may be driven by the selected positive pulse and negative pulse.

In this configuration, since both the high active pulse and the low active pulse included in the clock signal are used for driving the data line or the scanning line, the data line is driven at a frequency twice the frequency of the clock signal. Alternatively, scanning lines are driven.

In the case where clock signals of the first phase and the second phase which are in opposite phase relation to each other are used as the clock signal, a plurality of selection circuits select a pulse from the clock signal of the first phase. A first selection circuit group, and a second selection circuit group for selecting a pulse having the same polarity as the pulse selected by the first selection circuit group from the second-phase clock signal; The data line or the scanning line may be driven by a plurality of pulses having the same polarity.

Further, in the drive circuit according to the present invention, the transmission circuit includes a P-channel transistor and an N-channel transistor for selecting and outputting a pulse in the clock signal during a period in which the selection pulse is applied. You may comprise by a gate.

According to this configuration, since the pulse included in the clock signal maintains its waveform and is output via the analog switch, the width of the pulse used for driving the data line or the scanning line is extremely large. They can be matched with precision.

The present invention can be embodied not only as a drive circuit of an electro-optical device, but also as an electro-optical device equipped with this drive circuit, and further as an electronic apparatus having such an electro-optical device as a display unit. It is also possible to carry out.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

A. 1. First Embodiment (1) Configuration of Embodiment FIG. 1 is a block diagram showing a configuration of an electro-optical device according to a first embodiment of the present invention. The electro-optical device according to the present embodiment is an active matrix type liquid crystal display device using liquid crystal as an electro-optical material.

As shown in FIG. 1, the liquid crystal display device comprises a liquid crystal panel 100 and a peripheral circuit comprising a semiconductor integrated circuit. FIG. 1 shows a timing generator 200 and an amplifying / inverting circuit 300 as main ones of the peripheral circuits.

Here, the timing generator 200
Is a circuit that outputs various timing signals for performing timing control of each unit. This timing generator 200 includes a clock signal generation circuit 200 shown in FIG.
A is included. FIG. 3 shows the clock signal generation circuit 2
6 is a timing chart showing waveforms of respective parts of 00A.

As shown in FIG. 2, the clock signal generation circuit 200A includes toggle flip-flops 201 and 203 and an inverter 202.

Toggle flip-flops 201 and 20
Reference numeral 3 denotes a flip-flop that inverts the output signal levels of the output terminals Q and / Q every time the input signal level of the trigger terminal T rises. A timing pulse TP having a predetermined frequency is input to a trigger terminal T of the toggle flip-flop 201 among these flip-flops.
When the timing pulse TP is input, the clock signal C having a frequency half the frequency of the timing pulse TP is output.
LX is obtained from the output terminal Q of the toggle flip-flop 201, and a clock signal CLXINV obtained by inverting the level of the clock signal CLX is output from the toggle flip-flop 201.
(See FIG. 3).

A timing pulse TP is supplied to the trigger terminal T of the toggle flip-flop 203 by the inverter 2.
The timing pulse TP 'whose level has been inverted by 02 is input (see FIG. 3). This timing pulse TP '
Is input, 1/1 of the timing pulse TP is input.
A periodic signal having a frequency of 2 and a clock signal CL
The enable signal EN whose phase is delayed by a half cycle of the timing pulse TP from X is supplied to the toggle flip-flop 20.
3 and an enable signal ENINV obtained by inverting the level of the enable signal EN is obtained from the output terminal / Q of the toggle flip-flop 203 (FIG. 3).
reference).

The clock signal generation circuit 200 described above
The clock signal CLX, inverted clock signal CLXINV, and enable signal EN generated by A are used for driving timing control of a data line (described later) on the liquid crystal panel 100.

The timing generator 200 includes a clock signal generation circuit 200A and a clock signal generation circuit (not shown) for generating a clock signal CLY and an inverted clock signal CLYINV used for driving timing control of a scanning line (described later) on the liquid crystal panel 100. Abbreviation).

In addition to the various clock signals described above, the timing gelator 200 generates a signal DY at the start timing of the vertical scanning period, and generates a drive start command pulse DX at the start timing of the horizontal scanning period.

The amplifying / inverting circuit 300 amplifies the image signal to an amplitude suitable for driving the pixel, and converts the image signal to the amplitude center potential so that the voltage applied to each pixel becomes an AC voltage. This is a circuit for alternately inverting the voltage level between positive polarity and negative polarity and outputting the same.

In FIG. 1, the liquid crystal panel 100 has a structure in which an element substrate and a counter substrate are opposed to each other on the electrode forming surface, and liquid crystal is sealed between the two substrates. FIG. 1 shows each circuit formed on the element substrate. As shown in FIG. 1, on the element substrate, a plurality of parallel scanning lines 112 are formed along the X direction, and a plurality of parallel data lines 114 are formed along the Y direction orthogonal thereto. I have.
Each intersection of the scanning line 112 and the data line 114 has a TFT as a switch for controlling each pixel.
116 are arranged. Each TFT 116 disposed at each of these intersections has a gate electrode connected to a scanning line 112 passing through the intersection, a source electrode connected to a data line 114 passing through the intersection, and a drain electrode Are connected to the pixel electrode 118 disposed at the intersection. Each pixel includes a pixel electrode 118 disposed at each intersection, a common electrode (not shown in FIG. 1) on the counter substrate facing the pixel electrode 118, and a liquid crystal sandwiched between the two electrodes. Composed of In addition, a storage capacitor may be connected in parallel to the pixel electrode 118 to suppress a decrease in the applied voltage between the pixel electrode 118 and the common electrode due to leakage.

A drive section 120 is formed on the element substrate. The driving unit 120 includes the scanning line driving circuit 13
0, the data line driving circuit 140, and the sampling circuit 1
50. Each of these circuits is configured using a P-channel TFT and an N-channel TFT formed by a common manufacturing process with the TFT 116 for driving a pixel.

FIG. 4 is a circuit diagram showing a configuration of the data line driving circuit 140 and the sampling circuit 150 according to the present embodiment. As shown in FIG. 4, the data line driving circuit 14
0 is composed of a shift register 1410 and a selection circuit group 1420. The shift register 1410 receives the clock signal CLX from the timing generator 200,
The drive command pulse D is generated by the inverted clock signal CLXINV.
By sequentially shifting X, the selection pulses P1 to Pn
Are sequentially output.

Here, the signal lines to which the clock signal CLX and the inverted clock signal CLXINV are supplied are provided with level shifters (LS) 1451 and 1452, respectively.
The level shifters (LS) 1451 and 1452 convert the low logic amplitude clock signal CLX and the inverted clock signal CLXINV into high logic amplitude signals and output them.

As described above, the level shifters 1451 and 145
The reason for converting to a high logic amplitude by 2 is as follows. First, a timing generator 200 (see FIG. 1) for supplying various timing signals to the liquid crystal panel 100 includes:
In general, the output voltage is about 3 to 5 V because it is constituted by a CMOS circuit. On the other hand, the data line driving circuit 1
The component 40 is a TFT 11 for switching pixels.
The TFT is formed on the element substrate in the same process as that of No. 6, and it is difficult to operate at a low voltage. Therefore, the TFT is operated at a relatively high voltage of about 12V. Therefore, the clock signal CLX and the inverted clock signal CLXINV are converted into high logic amplitudes by the level shifters 1451 and 1452 so that the clock signal CLX and the inverted clock signal CLXINV are accepted as logic signals having appropriate levels, and the data line driving circuit 140 It is supplied to.

Although not shown, the drive start command start pulse DX and the enable signal EN are also converted from a low logic amplitude signal to a high logic amplitude signal by a similar level shifter and supplied to the data line drive circuit 130. Is done.

Next, the shift register 1410 is formed by cascading n latch circuits Rk (k = 1 to n), and outputs a drive start command pulse DX supplied at the beginning of the horizontal scanning period. By the clock signal CLX and the inverted clock signal CLXINV converted to the high logic amplitude,
The configuration is such that the data is sequentially shifted and output from the preceding (left) latch circuit to the subsequent (right) latch circuit.

Of the latch circuits Rk (k = 1 to n), the odd-numbered latch circuits R1, R3,... Operate when the clock signal CLX is at a high level (inverted clock signal C
An input signal is taken in when LXINV is at a low level and output to a latch circuit at a subsequent stage, and when a clock signal CLX is at a low level (inverted clock signal CLXINV).
When the signal goes to a high level). The latch circuits R2, R4,.
Takes the input signal when the clock signal CLX is at a low level (when the inverted clock signal CLXINV is at a high level) and outputs it to the subsequent latch circuit, and when the clock signal CLX becomes high (inverted clock This is a circuit that holds the input signal up to that time (when the signal CLXINV becomes low level).

Each latch circuit Rk (k = 1 to n) is composed of clocked inverters 1411 and 1413 and an inverter 1412. Here, a drive start command pulse DX or an output signal from a previous-stage latch circuit is input to an input terminal of the clocked inverter 1411. The output terminal of the clocked inverter 1411 is connected to the output terminal of the clocked inverter 1413.
Clocked inverter 1413
Is fed back to the input terminal. The output signal of the inverter 1412 becomes an input signal to the subsequent latch circuit.

Each clocked inverter 1411 and 1
A clock signal CLX and an inverted clock signal CLXINV are supplied to 413 as control signals for determining whether to put each in an output state or a high impedance state. How to apply the clock signal CLX and the inverted clock signal CLXINV to the clocked inverters 1411 and 1413 is different between the odd-numbered latch circuit and the even-numbered latch circuit. Hereinafter, this will be described in detail.

As shown in FIGS. 5A and 5B, a clocked inverter in a latch circuit Rk (k = 1 to n) includes two P-channel TFTs between a positive power supply VDD and a negative power supply VSS. And two N-channel TFTs connected in series. Further, a latch circuit Rk (k = 1 to
The inverter in n) has a positive power supply VD as shown in FIG.
One P-channel TFT and one N-channel TFT are connected in series between D and the negative power supply VSS.

As described with reference to FIG. 4, each latch circuit Rk (k = 1 to n) has two clocked inverters 1411 and 1413.

Here, in the odd-numbered latch circuits Rk, as shown in FIG.
The inverted clock signal CLXINV is supplied to the P-channel TFT, and the clock signal CLX is supplied to the N-channel TFT. Further, in the odd-numbered latch circuit Rk, FIG.
As shown in (b), the clock signal CLX is applied to the P-channel TFT of the clocked inverter 1413,
The channel TFT is supplied with the inverted clock signal CLXINV.

Therefore, in the odd-numbered latch circuits Rk, when the clock signal CLX is at the high level and the inverted clock signal CLXINV is at the low level, the clocked inverter 1411 is in the output state and the clocked inverter 1413 is in the high state. It becomes an impedance state. Therefore, the drive start command pulse DX or a signal obtained by inverting the output signal of the preceding latch circuit is output from the clocked inverter 1411.
The signal obtained by inverting the output signal of the inverter 11 is the inverter 14
The signal is output from 12 to the subsequent latch circuit and is also input to the input terminal of the clocked inverter 1413.

Thereafter, when the clock signal CLX goes low and the inverted clock signal CLXINV goes high, the clocked inverter 1411 goes into a high impedance state and the clocked inverter 1413 goes into an output state. Therefore, the output signal of the inverter 1412 at that time, that is, the output signal of the latch circuit Rk is inverted by the clocked inverter 1413 and returned to the input terminal of the inverter 1412. The output signal of the latch circuit Rk is held by the closed loop.

On the other hand, in the latch circuit Rk of the even-numbered stage, as shown in FIG.
The clock signal CLX is supplied to the P-channel TFT 411 and the inverted clock signal CLXINV is supplied to the N-channel TFT.
Is given. In the even-numbered latch circuit Rk, as shown in FIG.
The inverted clock signal CLXINV is supplied to the P-channel TFT, and the clock signal CLX is supplied to the N-channel TFT.

Therefore, in the even-numbered stage latch circuit Rk,
The clock signal CLX is at low level and the inverted clock signal C
The input signal is fetched and output when LXINV is at the high level, and the output signal is held when the clock signal CLX is at the high level and the inverted clock signal CLXINV is at the low level.

Referring to FIG. 4, a selection circuit group 1420 includes selection circuits S1 to Sn corresponding to latch circuits R1 to Rn, and outputs enable signal EN supplied from timing generator 200 to selection pulse P1 output from shift register 1410. To Pn, and outputs this signal as drive pulses T1 to Tn.

Each of the selection circuits S1 to Sn is composed of two analog switches (transmission gates) 1421 and 1422.

Each analog switch is composed of a P-channel TFT and an N-channel TFT as shown in FIG. These P-channel TFT and N-channel T
In the FT, each source electrode is commonly connected, and each drain electrode is commonly connected. These two common connection points form an analog signal input terminal and an analog signal output terminal of the analog switch. I have. When a low-level control signal is applied to the gate electrode of the P-channel TFT and a high-level control signal is applied to the gate electrode of the N-channel TFT, both T
The FT is turned on, and the analog switch is turned on. On the other hand, a high-level control signal is supplied to the gate electrode of the P-channel TFT,
When a low-level control signal is applied to the gate electrode of the FT, both TFTs are turned off, and the analog switch is turned off.

In each selection circuit Sk, an enable signal EN is input to an analog signal input terminal of the analog switch 1421. The output signal of the inverter 1412 of the latch circuit Rk, that is, the output signal Pk of the latch circuit Rk is input to the gate electrode of the N-channel TFT of the analog switch 1421, and the clock signal of the latch circuit Rk is applied to the gate electrode of the P-channel TFT. Inverter 1411
Alternatively, an output signal of 1413, that is, a signal obtained by inverting the level of the output signal Pk is input.

In each selection circuit Sk, an inverted signal of the output signal Pk of the latch circuit Rk is input to the gate electrode of the N-channel TFT of the analog switch 1422, and the latch circuit Rk is input to the gate electrode of the P-channel TFT. Is output. The analog signal output terminal of the analog switch 1422 is commonly connected to the analog signal output terminal of the analog switch 1421. This common connection point forms an output terminal of the selection circuit Sk for outputting the above-described drive pulse Tk.

Therefore, in each selection circuit Sk, while the output signal Pk of the latch circuit Rk is at the high level, the analog switch 1421 is turned on and the analog switch 14
Since the signal 22 is turned off, the enable signal EN passes through the analog switch 1421 and is output from the output terminal. In the present embodiment, the enable signal EN draws one positive pulse waveform during a period when the output signal Pk of the odd-numbered latch circuit Rk is at a high level, and the output signal Pk of the even-numbered latch circuit Rk is at a high level. One negative pulse waveform is drawn in a certain period. Therefore, the odd-numbered selection circuits S
k selects a positive pulse included in the enable signal EN during a period in which the output signal Pk of the latch circuit Rk is at a high level, and outputs the selected pulse as a drive pulse Tk. During the period when the output signal Pk of Rk is at the high level, the negative pulse included in the enable signal EN is selected and output as the drive pulse Tk. Reference is made in more detail.

On the other hand, in each selection circuit Sk, a latch circuit R
During the period when the output signal Pk of k is at the low level, the analog switch 1421 is in the off state and the analog switch 142
2 is turned on, the input voltage to the analog signal input terminal of the analog switch 1422 is selected and output from the output terminal.

Here, the input voltage to the analog signal input terminal of the analog switch 1422 of each selection circuit Sk (k = 1 to n) depends on whether the selection circuit is an odd-numbered stage or an even-numbered stage. Is different.

That is, in the odd-numbered selection circuit Sk, the negative power supply voltage VSS corresponding to the low level is applied to the analog signal input terminal of the analog switch 1422, and in the even-numbered selection circuit Sk, the analog switch 1422 A positive power supply voltage VDD corresponding to a high level is applied to a signal input terminal.

Therefore, in the odd-numbered stage selection circuit Sk, a low level is output from the output terminal while the output signal Pk of the latch circuit Rk is at the low level, whereas in the even-numbered stage selection circuit Sk, the latch circuit While the output signal Pk of Rk is at a low level, a high level is output from the output terminal.

Next, the sampling circuit 150 will be described. As shown in FIG. 4, the sampling circuit 150 includes a switching circuit Uk (k = 1 to n) corresponding to the selection circuit Sk (k = 1 to n).

Each switching circuit Uk (k = 1 to n)
Are provided corresponding to each of the n data lines 114 in FIG. 1, and are configured by an analog switch (transmission gate) 151 and an inverter 152. Each switching circuit Uk (k = 1 to n)
The analog signal input terminal of the analog switch 151 is supplied with the image signal VID. The analog signal output terminal of the analog switch 151 of each switching circuit Uk (k = 1 to n) is connected to the corresponding data line 11.
4 is connected.

How to supply a control signal to the analog switch 151 of each switching circuit Uk (k = 1 to n) is as follows.
It differs depending on whether the switching circuit Uk is of an odd-numbered stage or an even-numbered stage.

That is, in the odd-numbered switching circuits Uk, the output signal Tk of the selection circuit Sk is applied to the analog switch 1
A signal obtained by inputting the output signal Tk to the gate electrode of the N-channel TFT 51 by the inverter 152 is input to the gate electrode of the P-channel TFT of the analog switch 151. On the other hand, in the even-numbered switching circuit Uk, a signal obtained by inverting the level of the output signal Tk of the selection circuit Sk by the inverter 152 is input to the gate electrode of the N-channel TFT of the analog switch 151, and the output signal Tk is output to the analog switch 151. Input to the gate electrode of the P-channel TFT.

Accordingly, when a positive drive pulse Tk is output from the odd-numbered selection circuit Sk, the analog switch 151 of the switching circuit Uk corresponding to the selection circuit Sk is turned on by the positive drive pulse Tk. When a negative drive pulse Tk is output from the even-numbered selection circuit Sk, the analog switch 151 of the switching circuit Uk corresponding to the selection circuit Sk is turned on by the negative drive pulse Tk. .

Next, the scanning line driving circuit 130 shown in FIG.
Will be described. The scanning line driving circuit 130 has a shift register as a main component. The scanning line driving circuit 130 receives a two-phase clock signal CL having a predetermined frequency from the timing generator 200 described above.
Y and CLYINV are input, and a transfer start command pulse DY is supplied at the start timing of the vertical scanning period. The shift register in the scanning line driving circuit 130 transmits the transfer start command pulse DY to the two-phase clock signal C.
LY and CLYINV sequentially shift to the subsequent stage, and a plurality of pulse-like selection signals Yk (k = 1 to m) whose phases are shifted so as not to overlap on the time axis are generated from the output terminals of each stage of the shift register. These selection signals Yk (k
= 1 to m) to each scanning line 112. Here, each pulse width of the selection signal Yk (k = 1 to m) corresponds to a horizontal scanning period. That is, the selection signal Yk (k = 1 to
m) is generated, the drive start command pulse DX described above is supplied to the data line drive circuit 140, and the selection signal Yk maintains the active level.
The data line driving circuit 140 controls all data lines 114
Is performed.

(2) Operation of the Embodiment FIG. 7 is a timing chart showing the waveform of each part in this embodiment. Hereinafter, the operation of the present embodiment will be described with reference to FIG.

First, a driving start command pulse DY is supplied to the scanning line driving circuit 130 at the beginning of the vertical scanning period.
As a result, in the shift register in the scanning line driving circuit 130, the clock signal CLY and its inverted clock signal C
The drive start command pulse DY is sequentially shifted by LYINV, and the scanning signals Y1 to Ym are sequentially output to each scanning line 112.

The scanning signal Yk is applied to each scanning line 112.
Is output and the horizontal scanning period starts, a driving start command pulse DX is supplied to the data line driving circuit 140.

At timing t11 after the input of the drive start command pulse DX, the clock signal CLX rises (the inverted clock signal CLXINV falls).
Then, the first-stage latch circuit R1 in the shift register 1410 of the data line drive circuit 140 shown in FIG. 4 takes in the high-level portion of the drive start command pulse DX and outputs the selection pulse P1.

Next, at timing t12, the clock signal CLX falls (inverted clock signal CLXIN
V rises), the second-stage latch circuit R2 outputs the selection pulse P, which is the output signal of the first-stage latch circuit R1.
1 is taken in and a selection pulse P2 is output. Here, the first-stage latch circuit R1 holds the output signal up to that point when the clock signal CLX falls (the inverted clock signal CLXINV rises).

Next, when the drive start command pulse DX falls and the clock signal CLX rises (the inverted clock signal CLXINV falls) at the subsequent timing t13, the first stage latch circuit R1 causes the drive start command pulse to fall. The low level portion of the pulse DX is captured, and the selection pulse P1, which is the output signal, falls. Here, the second-stage latch circuit R2 outputs the clock signal CLX
Rises (the inverted clock signal CLXINV falls) to hold the output signal up to that point.

Next, at timing t12, the clock signal CLX falls (inverted clock signal CLXIN
When V rises), the second-stage latch circuit R2 takes in the low-level output signal from the first-stage latch circuit R1 and causes the selection pulse P2 to fall. Here, the first
When the clock signal CLX falls (the inverted clock signal CLXINV rises), the latch circuit R1 at the stage holds the output signal up to that point.

The same shift operation as described above is performed in each of the third and subsequent latch circuits. By performing such a shift operation, each has a pulse width of one cycle of the clock signal CLK (inverted clock signal CLKINV), and has a phase difference of half a cycle of the clock signal CLX (inverted clock signal CLXINV). The shifted selection pulse Pk (k = 1
To n) are output from the latch circuits Rk (k = 1 to n), respectively.

Next, the following operation is performed in the selection circuit group 1420. First, in the selection circuit S1 of the first stage, while the selection pulse P1 is at the low level, the analog switch 1421 is turned off and the analog switch 141 is turned off.
22 is turned on, and the low-level signal selected by the analog switch 1422 is output to the switching circuit U1.
Supplied to

When the selection pulse P1 goes high, the first-stage selection circuit S1 selects this selection pulse P1.
While the 1 is at the high level, the analog switch 1421
Is turned on, and the enable signal EN in this period passes through the analog switch 1421. As a result, FIG.
As shown in (1), a positive drive pulse T1 is obtained from the analog switch 1421 and supplied to the switching circuit U1.

Next, in the second-stage selection circuit S2, while the selection pulse P2 is at the low level, the analog switch 1421 is turned off, the analog switch 1422 is turned on, and the high level selected by the analog switch 1422 is set. The level signal is supplied to the switching circuit U1.

When the selection pulse P2 goes high, the second-stage selection circuit S2 outputs the selection pulse P2.
2 is high level, the analog switch 1421
Is turned on, and the enable signal EN in this period passes through the analog switch 1421. As a result, FIG.
As shown in (1), a negative drive pulse T2 is obtained from the analog switch 1421 and supplied to the switching circuit U2.

Thereafter, when the selection pulse P1 goes low, the analog switch 1422 is turned on in the first-stage selection circuit S1, and the analog switch 1422 is turned on.
The low-level signal selected by 22 is supplied to the switching circuit U1.

The same applies to the third and subsequent selection circuits. In the odd-numbered selection circuits Sk, while the selection pulse Pk is at the low level, the positive drive pulse Tk is extracted from the enable signal EN and the switching circuit Uk In the even-numbered selection circuit Sk, the negative drive pulse Tk is extracted from the enable signal EN and supplied to the switching circuit Uk while the selection pulse Pk is at the low level.

In the sampling circuit 150, when the driving pulse T1 becomes high level, the switching circuit U1 samples the image signal VID only during the high-level period tc, and supplies the image signal VID to the corresponding data line 114 as the data signal X1. Is done. Then, the data signal X1 is written to a pixel intersecting the currently selected scanning line 112 via the TFT.

Next, when the drive pulse T1 goes low and the drive pulse T2 goes low, the switching circuit U2 samples the image signal VID only during the active period tc, and as the data signal X2, 114. The data signal X1 is output to the currently selected scanning line 112.
Is written through the TFT 116 to the pixel intersecting with.

The same operation as described above is performed in the third and subsequent switching circuits Uk, and all the data lines 114 are switched.
Is driven.

When the driving of all the data lines 112 is completed and the next scanning line 112 is selected, a driving start command DX is generated, and the same operation as described above is repeated. As described above, in the data line drive circuit 140 according to the present embodiment, each active period tc of the drive pulse Tk (k = 1 to n) is determined by the pulse width of the enable signal EN. Therefore, the driving pulse Tk (k = 1
To n), the sampling period for driving each data line can be made uniform.
A decrease in display quality of the liquid crystal panel 100 can be suppressed.

<Second Embodiment> FIG. 8 is a block diagram showing a configuration of a data line driving circuit according to the second embodiment. In this embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

Data line drive circuit 140 shown in FIG.
However, the difference from the first embodiment shown in FIG. 4 is as follows. a. The enable signal E is supplied to the analog signal input terminal of the analog switch 1421 of the selection circuits S1, S3,.
N, and the inverted enable signal ENINV is supplied to the analog signal input terminals of the even-numbered selection circuits S2, S4,... Here, the inverted enable signal ENINV is a signal obtained by inverting the level of the enable signal EN. For example, the toggle flip-flop 203 in the timing generator 200 (see FIG.
) Can be obtained from the output terminal / Q. b. In each of the selection circuits Sk (k = 1 to n), the input voltage to the analog signal input terminal of the analog switch 1422 is set to the negative power supply voltage VSS regardless of whether the selection circuit is of an odd-numbered stage or an even-numbered stage. (Low level). c. Regarding each switching circuit Uk (k = 1 to n), the output signal Tk from the selection circuit Sk is supplied to the N-channel TFT of the analog switch 151 regardless of whether the switching circuit is of an odd-numbered stage or an even-numbered stage. The output signal Tk is supplied to the gate of the inverter 152.
Is applied to the P-channel TFT.

FIG. 10 is a timing chart showing the operation of this embodiment. In this embodiment, the enable signal EN is supplied to the odd-numbered selection circuits S1, S3,..., And the inverted enable signal ENIN is supplied to the even-numbered selection circuits S2, S4,.
Since V is supplied, positive drive pulses Tk (k = 1 to n) are obtained from all the selection circuits regardless of whether they are odd or even. In the sampling circuit 150, the analog switch 151 is turned on / off by the drive pulse Tk (k = 1 to n).

Also in this embodiment, the driving pulse Tk
Each active period tc (k = 1 to n) is determined by the pulse width of the enable signal EN and the inverted enable signal ENINV. Therefore, similarly to the first embodiment, the sampling period for driving each data line can be made uniform, and a decrease in display quality in the liquid crystal panel 100 can be suppressed.

In the case of the present embodiment, the analog switch 1 is connected to each switching circuit Uk (k = 1 to n).
Since the drive pulse Tk is applied in the same manner to 51, the sampling period for driving each data line can be made more uniform than in the first embodiment. The details are as follows.

First, in the first embodiment, the manner in which the drive pulse Tk is applied to the analog switch 151 differs between the odd-numbered switching circuit Uk and the even-numbered switching circuit Uk as follows.

First, in the case of the odd-numbered switching circuit Uk, the drive pulse Tk from the selection circuit Sk is applied to the gate electrode of the N-channel TFT of the analog switch 151, and the level is inverted by the inverter 152.
The signal is supplied to the gate electrode of the P-channel TFT of the analog switch 151. Therefore, in the analog switch 151 of the switching circuit Uk, when the drive pulse Tk goes high, the N-channel TFT is turned on first, and then the P-channel TFT is turned on with a delay.

On the other hand, in the case of the even-numbered switching circuit Uk, the drive pulse Tk from the selection circuit Sk is applied to the gate electrode of the P-channel TFT of the analog switch 151, and then the level is inverted by the inverter 152.
The signal is supplied to the gate electrode of the N-channel TFT of the analog switch 151. Therefore, in the analog switch 151 of the switching circuit Uk, when the drive pulse Tk goes low, the P-channel TFT is turned on first, and then the N-channel TFT is turned on with a delay.

Here, if the threshold voltage and the mutual conductance of the P-channel TFT and the N-channel TFT constituting the analog switch 151 can be made the same, regardless of whether the stage is an odd-numbered stage or an even-numbered stage, The delay time from the rise or fall of the pulse Tk to the rise or fall of the output level of the analog signal output terminal of the analog switch 151 can be made equal. However, it is difficult to suppress manufacturing variations in threshold voltage and transconductance of the P-channel TFT and the N-channel TFT. For this reason, the delay time from the rising or falling of the drive pulse Tk to the change in the output level of the analog signal output terminal of the analog switch 151 differs between the odd-numbered switching circuit and the even-numbered switching circuit.
Due to this, the sampling period of the image signal VID may be slightly different between the odd-numbered data lines and the even-numbered data lines.

On the other hand, in the present embodiment, in all the switching circuits Uk (k = 1 to n), the driving pulse Tk is applied to the analog switch 151 in the same manner, so that such a problem does not occur. Thus, the sampling periods corresponding to the respective data lines can be made to coincide more strictly than in the first embodiment.

In each of the embodiments described above, the case where the present invention is applied to the data line driving circuit is described as an example.
The application range of the present invention is not limited to this, and the present invention may be applied to a scanning line driving circuit that drives a scanning line to make the scanning period uniform.

In each of the above embodiments, each data line 114 is sequentially sampled one by one without using a so-called phase expansion circuit. However, the present invention is not limited to this. For the data lines 114,
The image signals VID1 to VID6 converted into six systems are simultaneously sampled and supplied, and the image signal VID1
To VID6 may be sequentially applied for each data line group. The number of conversions and the number of data lines to be simultaneously applied are “3”, “12”, “24”, etc., and three, twelve, twenty-four data lines are converted into three systems, It is also possible to adopt a configuration in which image signals supplied in parallel through system conversion, 24 system conversion, etc. are simultaneously supplied. The number of conversions and the number of data lines to be applied at the same time are multiples of 3 in view of the fact that a color image signal is composed of signals related to three primary colors in order to simplify control and circuits. preferable.

<Configuration Example of Liquid Crystal Panel> Next, the overall configuration of the liquid crystal panel 100 having the data line driving circuit 140 according to each of the above-described embodiments will be described with reference to FIGS. Here, FIG.
FIG. 12 is a cross-sectional view taken along line AA ′ in FIG.

As shown in these figures, the liquid crystal panel 100 is made of a glass on which the pixel electrodes 118 and the like are formed, an element substrate 101 of a semiconductor, quartz or the like, and a transparent material such as a glass on which the common electrodes 108 are formed. With the opposite substrate 102
With a certain gap maintained by the sealing material 104 mixed with the spacer 103, the electrodes are bonded so that their electrode forming surfaces face each other, and a liquid crystal 105 as an electro-optical material is sealed in this gap. . In addition,
The sealant 104 is formed along the periphery of the counter substrate 102, and has a partly opened opening for enclosing the liquid crystal 105. Therefore, after the liquid crystal 105 is sealed, the opening is sealed by the sealing material 106.

Here, the data line driving circuit 140 and the sampling circuit 150 described above are formed on the opposite side of the element substrate 101 and one side outside the sealing material 104, and the data line 114 extending in the Y direction is formed. Is driven. Further, a plurality of external circuit connection terminals 107 are formed on one side to input various signals from the timing generator 200 and the image signal processing circuit 300. Two scanning line driving circuits 130 are formed on two sides adjacent to this one side, and are configured to drive the scanning lines 112 extending in the X direction from both sides. If the delay of the scan signal supplied to the scan line 112 does not matter, the scan line drive circuit 130 may be formed only on one side. In addition, in the element substrate 101, the data lines 11
In order to reduce the load of writing an image signal to the data line 4, a precharge circuit for precharging each data line 114 to a predetermined potential at a timing preceding the image signal may be formed.

On the other hand, the common electrode 108 of the opposite substrate 102
Of the four corners of the portion to be bonded to the element substrate 101
By the conductive material provided in at least one place,
Electrical conduction with the element substrate 101 is achieved. In addition, depending on the use of the liquid crystal panel 100, for example, first, a stripe shape, a mosaic shape,
A color filter arranged in a triangle shape or the like is provided. Second, a light-shielding film such as a resin material in which a metal material such as chromium or nickel, or carbon or titanium is dispersed in a photoresist is provided. A backlight for irradiating the liquid crystal panel 100 with light is provided.
In the case of color light modulation, a light-shielding film is provided on the counter substrate 102 without forming a color filter.

In addition, an alignment film (not shown) rubbed in a predetermined direction is provided on each of the opposing surfaces of the element substrate 101 and the opposing substrate 102, and each of the back surfaces thereof has an orientation direction corresponding to the alignment direction. Polarizing plates (not shown) are provided. However, when a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 105, the above-described alignment film and polarizing plate are not required, so that the light use efficiency is increased. This is advantageous in terms of low power consumption and the like.

Instead of forming part or all of the peripheral circuits such as the drive circuit 120 on the element substrate 101, for example, a drive IC chip mounted on a film using TAB (Tape Automated Bonding) technology is used. , Element substrate 1
01 may be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position,
The driving IC chip itself may be electrically and mechanically connected to a predetermined position of the element substrate 101 via an anisotropic conductive film using a COG (Chip On Grass) technique.

<Configuration of Element Substrate> In each embodiment, the element substrate 101 of the liquid crystal panel 100 is formed of a transparent insulating substrate such as glass, and a silicon thin film is formed on the substrate. A source on the thin film,
The switching element (TFT 116) of the pixel and the driving circuit 120 are formed by the TFT in which the drain and the channel are formed.
However, the present invention is not limited to this.

For example, the element substrate 101 is composed of a semiconductor substrate, and the switching element and the driving circuit 1 of the pixel are formed by an insulated gate field effect transistor having a source, a drain and a channel formed on the surface of the semiconductor substrate.
Twenty elements may be configured. Thus, the element substrate 10
When the pixel electrode 1 is composed of a semiconductor substrate, the pixel electrode 1 cannot be used as a transmissive electro-optical device.
18 is formed of aluminum or the like, and is used as a reflection type. Alternatively, the element substrate 101 may simply be a transparent substrate and the pixel electrode 118 may be of a reflection type.

Further, in the above-described embodiment,
Although the switching element of the pixel has been described as a three-terminal element represented by a TFT, it may be configured with a two-terminal element such as a diode. However, when a two-terminal element is used as a switching element of a pixel, the scanning line 112 is formed on one substrate, the data line 114 is formed on the other substrate, and the two-terminal element is connected to the scanning line 112 or the data line. 11
4 and the pixel electrode. In this case, the pixel includes a pixel electrode to which the two-terminal element is connected and a signal line (data line 114
Or, one of the scanning lines 112) and the liquid crystal interposed therebetween.

Further, as the electro-optical material, in addition to the liquid crystal, the present invention can be applied to a display device which uses an electroluminescence element or the like to display by the electro-optical effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to the above-described liquid crystal display device.

<Electronic Equipment> Next, the case where the above-described liquid crystal display device is applied to various electronic equipment will be described.
In this case, as shown in FIG. 13, the electronic device mainly includes a display information output source 1000 and a display information processing circuit 100.
2, power supply circuit 1004, liquid crystal panel 100, drive circuit 1
20 and a timing generator 200. Needless to say, the drive circuit 120 may be built in the liquid crystal panel 100. Among them, the display information output source 1000 is a ROM (Read Only Memory).
, A memory such as a random access memory (RAM), a storage unit such as various disks, a tuning circuit for tuning and outputting an image signal, and the like.
00, based on various clock signals generated by
Display information such as an image signal in a predetermined format is supplied to the display information processing circuit 1002. Next, the display information processing circuit 1002 is connected to the S / P conversion circuit 302 described above.
And a well-known circuit such as a rotation circuit, a gamma correction circuit, and a clamp circuit, in addition to the amplification / inversion circuit 304, executes processing of input display information, and outputs the image signal together with the clock signal CLK to the driving circuit. 120. The power supply circuit 1004 supplies a predetermined power to each component. Note that FIG.
, The clock signal CLK is supplied to the display information processing circuit 1
002, as shown in FIG.
It is needless to say that the display information processing circuit 1002, which is a higher-level configuration of the image processing circuit 300, may operate in synchronization with a clock signal from the timing generator 200.

Next, some examples in which the above-described liquid crystal display device is used in specific electronic devices will be described.

<Part 1: Projector> First, a projector using this liquid crystal panel as a light valve will be described. FIG. 14 is a plan view showing the configuration of this projector. As shown in the figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by three mirrors 1106 and two dichroic mirrors 1108 arranged inside, and a liquid crystal panel as a light valve corresponding to each primary color 100R, 100B and 100G respectively. Here, the light of the B color has a longer optical path compared to the other R and G colors, so that the incident lens 1122, the relay lens 1123, and the output lens 1
It is guided through a relay lens system 1121 consisting of 124.

The configuration of the liquid crystal panels 100R, 100B, and 100G is the same as that of the above-described liquid crystal panel 100, and is driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). Things. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, the R and B lights are refracted at 90 degrees, while the G light travels straight. Therefore, as a result of combining the images of the respective colors, the screen 112 is projected through the projection lens 1114.
A color image is projected on 0.

Here, each of the liquid crystal panels 100R, 100B
Focusing on the display image of the liquid crystal panel 100G, the display image of the liquid crystal panel 100R,
It is necessary that the display image of 100B is horizontally inverted. For this reason, the horizontal scanning direction is
00G and the liquid crystal panels 100R and 100B have a relationship opposite to each other. The liquid crystal panels 100R, 10R
0B and 100G have dichroic mirror 110
8, light corresponding to each of the primary colors of R, G, and B enters, so that it is not necessary to provide a color filter.

<Part 2: Mobile Computer> Next, an example in which the liquid crystal panel is applied to a mobile personal computer will be described. FIG. 15 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1200 includes a keyboard 120
And a liquid crystal display unit 120 provided with
6 is comprised. This liquid crystal display unit 120
6 is configured by adding a backlight to the back surface of the liquid crystal panel 100 described above.

<Part 3: Mobile phone> Further, an example in which this liquid crystal panel is applied to a mobile phone will be described. FIG.
FIG. 6 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 has a plurality of operation buttons 1302
In addition, the liquid crystal panel 100 is provided together with the earpiece 1304 and the mouthpiece 1306. This liquid crystal panel 10
A backlight may be provided on the back of the zero if necessary.

Note that the electronic devices are shown in FIGS.
In addition to those described with reference to the above, a liquid crystal television, a viewfinder type, a video tape recorder of a monitor direct-view type, a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a PO
An S terminal, a device equipped with a touch panel, and the like are included. Needless to say, the liquid crystal panel of each embodiment and the electro-optical device can be applied to these various electronic devices.

[0129]

As described above, according to the present invention,
In a driving circuit of an electro-optical device having a plurality of scanning lines, a plurality of data lines, and a plurality of pixels driven through the scanning lines and the data lines, a pulse-like driving start command signal is sequentially delayed. Delay means for outputting a plurality of selection pulses having different phases from each other, a clock signal common to one of the plurality of selection pulses being inputted, and a pulse in a period during which the selection pulse is inputted from the clock signal. A plurality of selection circuits for selecting and outputting are provided, and the plurality of scan lines or the plurality of data lines are driven by a plurality of pulses selected by the plurality of selection circuits. The period for driving the lines can be made uniform, and the display quality can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device to which a drive circuit according to a first embodiment of the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of a timing generator in the liquid crystal display device.

FIG. 3 is a timing chart showing waveforms of various parts of the timing generator.

FIG. 4 is a block diagram showing a configuration of a data line driving circuit in the liquid crystal display device.

FIGS. 5A and 5B are circuit diagrams each showing a configuration example of a clocked inverter.

FIG. 6 is a circuit diagram illustrating a configuration example of an inverter.

FIG. 7 is a timing chart for explaining the operation of the data line driving circuit.

FIG. 8 is a block diagram illustrating a configuration of a data line driving circuit according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating a configuration example of an analog switch.

FIG. 10 is a timing chart for explaining the operation of the data line drive circuit.

FIG. 11 is a perspective view showing a structure of the liquid crystal panel.

FIG. 12 is a partial cross-sectional view illustrating the structure of the liquid crystal panel.

FIG. 13 is a block diagram illustrating a schematic configuration of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 14 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 15 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 16 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 17 is a block diagram showing a configuration of a data line driving circuit according to a conventional technique.

FIG. 18 is a timing chart for explaining the operation of the data line driving circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 liquid crystal panel 101 element substrate 102 counter substrate 116 TFT 120 driving circuit 130 scanning line driving circuit 140 data line driving circuit 150 sampling circuit 151, 1421, 1422 analog switch 200 timing generator 1410 shift Register 1420 ... Selection circuit group R1-Rn ... Latch circuit S1-Sn ... Selection circuit U1-Uk ... Switching circuit

Continued on the front page F-term (reference) 2H093 NA16 NA42 NC12 NC16 NC21 NC22 NC23 NC34 NC67 ND05 ND09 5C006 AC02 AF52 AF72 BB16 BC03 BC06 BC13 BF07 BF24 BF27 BF33 BF34 EC02 EC05 EC09 EC11 EC13 FA21 5C080 AA10 BB05 DD03 DD30 DD03 DD03 JJ06 KK02 KK07 KK20 KK23 KK27 KK43

Claims (8)

[Claims] A pulse-like driving start command is provided in a driving circuit of an electro-optical device having a plurality of scanning lines, a plurality of data lines, and a plurality of pixels driven through the scanning lines and the data lines. Delay means for sequentially delaying a signal to output a plurality of selection pulses having different phases; a clock signal common to one of the plurality of selection pulses is input, and the selection pulse is input from the clock signal And a plurality of selection circuits for selecting and outputting pulses in a period, wherein the plurality of scanning lines or the plurality of data lines are driven by the plurality of pulses selected by the plurality of selection circuits. Driving circuit of the electro-optical device. 2. A plurality of switching elements interposed between an image signal supply source and the plurality of data lines are turned on / off by a plurality of drive pulses selected by the plurality of selection circuits. The driving circuit for an electro-optical device according to claim 1, wherein: 3. The driving circuit according to claim 1, wherein the plurality of scanning lines are driven by a plurality of driving pulses selected by the plurality of selection circuits. 4. The plurality of selection circuits include a selection circuit that selects a positive pulse from the clock signal, and a selection circuit that selects a negative pulse from the clock signal, and the positive pulse selected from these. 4. The driving circuit according to claim 1, wherein the data line or the scanning line is driven by a negative pulse. 5. The clock signal is a clock signal of a first phase and a clock signal of a second phase having an opposite phase relationship to each other, and the plurality of selection circuits are configured to select a pulse from the clock signal of the first phase. And a pulse having the same polarity as that of the pulse selected by the first selection circuit group.
4. The data line or the scanning line is driven by a plurality of pulses having the same polarity selected from the second selection circuit group selected from the phase clock signals. 5. Drive circuit of the electro-optical device. 6. The selection circuit includes a transmission gate composed of a P-channel transistor and an N-channel transistor for selecting and outputting a pulse in the clock signal during a period in which the selection pulse is supplied. A driving circuit for the electro-optical device according to claim 1. 7. An electro-optical device comprising the driving circuit according to claim 1. 8. An electronic apparatus comprising the electro-optical device according to claim 7 as a display unit.