JP2005149624A - Shift register circuit and display device - Google Patents

Shift register circuit and display device Download PDF

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JP2005149624A
JP2005149624A JP2003386172A JP2003386172A JP2005149624A JP 2005149624 A JP2005149624 A JP 2005149624A JP 2003386172 A JP2003386172 A JP 2003386172A JP 2003386172 A JP2003386172 A JP 2003386172A JP 2005149624 A JP2005149624 A JP 2005149624A
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potential
circuit
transistor
power supply
bootstrap
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JP4686972B2 (en
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Masumitsu Ino
Daisuke Ito
Seiichiro Jinda
大亮 伊藤
益充 猪野
誠一郎 甚田
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Sony Corp
ソニー株式会社
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Abstract

Since a through current flows through a circuit for each transfer operation in each transfer stage, the power consumption of the entire shift register circuit is increased.
In a shift register circuit that performs a transfer operation by setting each output of a previous register and a subsequent register (transfer stage) as inputs IN1 and IN2, an output OUT (n-1) of the previous stage (n-1) is used as an input IN1. ) Is applied, the gate potential of the MOS transistor Qp15 is set to the VDD potential and the gate potential of the MOS transistor Qp16 is set to the VSS potential by the action of the bootstrap state determination circuit 22. Also, in a state other than the bootstrap state, the output (n + 1) of the subsequent stage (n + 1) is given as the input IN2, so that the gate potential of the MOS transistor Qp15 is set to the VSS potential by the action of the initial state determination circuit 21, and the MOS The gate potential of the transistor Qp16 is set to the VDD potential.
[Selection] Figure 3

Description

  The present invention relates to a shift register circuit and a display device, and more particularly, to a shift register circuit formed of a single channel (same conductivity type) transistor on an insulating substrate and the shift register circuit used as a part of a drive circuit. The present invention relates to a display device.

  FIG. 24 shows a conventional example of a shift register circuit constituted by using only a single channel MOS transistor, for example, an N channel MOS transistor. As is apparent from the figure, the shift register circuit according to the conventional example includes an inverter 201 composed of N-channel MOS transistors Qn101 and Qn102, an inverter 202 composed of MOS transistors Qn103 and Qn104, an inverter 203 composed of MOS transistors Qn105 and Qn106, Are connected by a transfer gate 211 composed of an N-channel MOS transistor Qn111, a transfer gate 212 composed of a MOS transistor Qn112, a transfer gate 213 composed of a MOS transistor Qn113, and so on (for example, non-patent literature). 1).

  FIG. 25 is a timing chart for explaining the operation of the conventional shift register circuit. In FIG. 25, φ1 and φ2 indicate two-phase clock pulses, and Vin indicates an input pulse. A is an output pulse of the inverter 201, B is a shift pulse (second input pulse) output from the first transfer stage, C is an output pulse of the inverter 202, and D is from the second transfer stage. The output shift pulse (third stage input pulse), E represents the output pulse of the inverter 203, and F represents the shift pulse (fourth stage input pulse) output from the third transfer stage.

  The first-phase clock pulse φ1 is applied to the odd-numbered transfer stages, and the second-phase clock pulse φ2 is applied to the even-numbered transfer stages. By making these two-phase clock pulses φ1 and φ2 alternately high level (hereinafter referred to as “H” level) every half cycle of the input pulse Vin, each transfer stage is connected in a chain shape. The input pulse Vin propagates sequentially through the circuit chain. Then, it is output from each transfer stage as shift pulses B, D, F,.

Hara, "Basics of MOS Integrated Circuits", Modern Science, p. 82-p. 88

  In the shift register circuit according to the conventional example having the above configuration, in the first transfer stage, when the input pulse Vin is at “H” level and the clock pulse φ1 is at “H” level, the MOS transistors Qn101 and Qn102 are Both are turned on, and a through current flows during this period. In the second transfer stage, both the MOS transistor Qn103 and the MOS transistor Qn104 are turned on when the shift pulse B “H” level output from the first transfer stage and the clock pulse φ2 are “H” level. In this period, a through current flows. Thereafter, the same operation is repeated.

  As described above, in the shift register circuit according to the above-described conventional example, each time a transfer operation is performed in each transfer stage, a through current is supplied in a period in which both the input pulse and clock pulse φ1 / φ2 of each transfer stage are at “H” level. This causes a problem that the power consumption of the entire shift register circuit increases. In particular, in a polysilicon process or an amorphous silicon process of a TFT (Thin Film Transistor) formed on an insulating substrate, variations in transistor characteristics such as threshold voltage Vth and mobility μ are larger than in a single crystal process. In addition, since the off-current Ioff of the MOS transistor cannot be ignored, it is necessary to consider these when designing the circuit.

Incidentally, in a P-channel TFT produced by a polysilicon process or an amorphous silicon process, the threshold voltage Vth is about −1 [V] to −3 [V], and the mobility μ is 10 to 100 [cm 2 / V · sec]. The off-state current Ioff varies by about 1 [pA] to 100 [nA]. Therefore, it is necessary to consider variations in transistor characteristics when designing a circuit.

FIG. 26 is a characteristic diagram showing the relationship (measurement result) of the source-drain current Ids with respect to the gate voltage Vgs of a P-channel MOS TFT produced by a low-temperature polysilicon process. When the gate voltage Vgs is negative and large, the TFT is connected (on) between the source and drain, and when the gate voltage Vgs is positive, the TFT is turned off (off). However, as apparent from FIG. 26, after the TFT is turned off, the leak current is as large as 10 −11 to 10 −9 [A], so that the shift is performed using a P-channel MOS type TFT produced by a low-temperature polysilicon process. When configuring a register circuit, a circuit configuration that is resistant to leakage current is required.

  The present invention has been made in view of the above-described problems, and the object of the present invention is to be less affected by variations in transistor characteristics such as the threshold voltage Vth and mobility μ, and suppresses through current and reduces power consumption. It is an object of the present invention to provide a shift register circuit and a display device that enable electric power.

  The shift register circuit according to the present invention is a shift register circuit configured by a single channel transistor on an insulating substrate, the first transistor having a source connected to a first power source, and the source being the first transistor. A second transistor to which a clock signal is applied to the drain, and the second transistor performs a bootstrap operation; and when the first input signal is applied. The gate potential of the first transistor is set to the potential of the first power supply, and the gate potential of the second transistor is set to the potential of the second power supply to determine the bootstrap state of the output means. When the bootstrap state determining means and the second input signal are given, the gate potential of the first transistor is set to A basic circuit comprising: an initial state determining means for setting the potential of the second power supply and setting the gate potential of the second transistor to the potential of the first power supply to determine the initial state of the output means; Each of the basic circuits has a configuration in which the output signal of the previous basic circuit is used as the first input signal and the output signal of the subsequent basic circuit is used as the second input signal. ing. The shift register circuit includes a pixel array unit in which pixels including display elements are arranged in a matrix on a transparent insulating substrate, and a shift register circuit configured by a single-channel transistor. In a display device including a drive circuit integrated with the pixel array portion on a substrate and driving the pixel array portion, the display device is used as a shift register circuit of the drive circuit.

  In a display device using the shift register circuit having the above configuration or the shift register circuit as a shift register circuit of a driver circuit, when an output signal of a previous basic circuit is given as a first input signal to a basic circuit of a certain stage, The strap state determination means sets the gate potential of the first transistor to the potential of the first power supply and sets the gate potential of the second transistor to the potential of the second power supply. As a result, the potential state for performing the bootstrap operation is determined, and the bootstrap operation is performed. In the state other than the bootstrap state, the output of the subsequent basic circuit is given as the second input signal, so that the initial state determining means sets the gate potential of the first transistor to the potential of the second power supply, and The gate potential is set to the potential of the first power supply. As a result, the second transistor is completely turned off, so that no through current flows through the second transistor.

  According to the present invention, the second transistor is completely turned off in the initial state, and no through current flows through the second transistor, and the first transistor is completely turned off except in the initial state. Thus, since no through current flows through the first transistor, power consumption can be reduced without being affected by variations in transistor characteristics such as threshold voltage Vth and mobility μ.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of a shift register circuit according to the present invention. As shown in FIG. 1, the shift register circuit according to the present invention is constituted by a single channel (same conductivity type) transistor on an insulating substrate (not shown) by a polysilicon process or an amorphous silicon process. A shift register circuit, which has N stages of registers (S / R) 11-1 to 11-N and two transfer gate circuits 12, 13, stores some data in parallel, It has a function of outputting serially in a predetermined order and adding the data stored in each of the registers 11-1 to 11-N bit by bit from the least significant digit.

  The shift register circuit receives an input pulse ST and two-phase clock pulses CK1 and CK2. FIG. 2 shows a timing relationship between the input pulse ST, the clock pulses CK1 and CK2, and the inputs / outputs IN1 (1), IN2 (N), and OUT (1) to OUT (N) of the registers 11-1 to 11-N. . As is clear from FIG. 2, the input pulse ST is activated twice in one field period, specifically, at the start and end parts of one field period. Here, for the sake of convenience, the input pulse ST that is active at the start of one field period is ST1, and the input pulse ST that is active at the end of one field period is ST2.

  The N-stage registers 11-1 to 11-N will be described with reference to a certain n-th register 11-n. The register 11-n outputs the output OUT (n-1) of the previous-stage register 11-n-1. Is the first input IN1, and the output OUT (n + 1) of the subsequent register 11-n + 1 is the second input IN2. Then, a transfer (shift) operation is performed in synchronization with the two-phase clock pulses CK1 and CK2 by the input of the output OUT (n−1) at the previous stage, and initialization is performed by the input of the output OUT (n + 1) at the subsequent stage.

  Assuming that the positive side power supply voltage is VDD and the negative side power supply voltage is VSS, the pulse amplitudes of the input pulse ST and the clock pulses CK1 and CK2 are VDD to VSS, and the transfer gate circuit 12 includes the input pulse ST and the clock pulse CK1. The first input pulse ST1 is selected by becoming active at the falling edge of the signal, and the pulse ST1 is given to the first stage register 11-1 as the first input IN1. The transfer gate circuit 13 becomes active at the falling edge of the input pulse ST and the clock pulse CK2 to select the second input pulse ST2, and the pulse ST2 is input to the final stage register 11-N as the second input IN2. Give as. In order to realize this input / output relationship, the total number of stages N of this shift register circuit needs to be an even number.

  Here, the pulse ST1 generated by the transfer gate circuit 12 is given to the first-stage register 11-1 as the first input IN1, and the pulse ST2 generated by the transfer gate circuit 13 is supplied to the second-stage register 11-N by the second input. However, it is not necessary to provide the transfer gate circuits 12 and 13 when adopting a configuration in which these pulses ST1 and ST2 are given from the outside. Also, the total number N of shift registers need not be an even number.

  As described above, the shift register circuit according to the present invention is characterized in that the transfer operation is performed by setting the outputs of the first and second registers (transfer stages) as the first and second inputs IN1 and IN2. The registers 11-1 to 11-N use bootstrap registers, and the transfer gate circuits 12 and 13 use bootstrap transfer gates. The configuration and operation of the bootstrap register and the bootstrap transfer gate will be specifically described below.

[First Embodiment]
The basic circuit (one register) of the shift register circuit according to the first embodiment of the present invention includes a first transistor whose source is connected to a first power supply, a source connected to the drain of the first transistor, And a second transistor to which a clock signal is applied, and an output means for performing a bootstrap operation of the second transistor, and a gate potential of the first transistor when the first input signal is applied. A bootstrap state determining means for setting the gate potential of the second transistor to the potential of the second power supply to determine the bootstrap state of the output means, and a second input signal When given, the gate potential of the first transistor is set to the potential of the second power supply, and the gate potential of the second transistor is set to the first potential. Source has a configuration that includes an initial state determination means for determining the initial state of the output means is set to a potential used as each of the registers 11-1 to 11-N in FIG.

(Example 1)
FIG. 3 is a circuit diagram showing a configuration of a basic circuit (register) of the shift register circuit according to Example 1 of the first embodiment. The shift register circuit according to the present embodiment is a bootstrap type register circuit configured by only a P-channel MOS transistor on an insulating substrate such as a glass substrate, and a positive power supply VDD (hereinafter referred to as VDD power supply) is used. The first power supply is used, and the negative power supply VSS (hereinafter referred to as VSS power supply) is used as the second power supply.

  As shown in FIG. 3, the basic circuit 20 of the shift register circuit according to this embodiment includes an initial state determination circuit 21, a bootstrap state determination circuit 22, an output circuit 23, a bootstrap circuit 24, and a reset circuit 25. The circuit has two circuit input terminals 26 and 27, a clock terminal 28, a reset terminal 29, and a circuit output terminal 30.

  The initial state determination circuit 21 has a diode-connected P-channel MOS transistor Qp11 whose gate and drain are commonly connected to the circuit input terminal 26, a gate connected to the source of the MOS transistor Qp11, and a source connected to the VDD power supply. P channel MOS transistor Qp12. The bootstrap state determination circuit 22 has a P-channel MOS transistor Qp13 whose source is connected to the VDD power source and whose drain is connected to the source of the MOS transistor Qp11, and a gate and a drain connected to the circuit input terminal 26 together with the gate of the MOS transistor Qp13. The P channel MOS transistor Qp14 is connected in common and the source is connected in common to the drain of the MOS transistor Qp12.

  The output circuit 23 has a source connected to the VDD power source, a gate connected to a common connection node (hereinafter referred to as node N11) of the source of the MOS transistor Qp11, the gate of the MOS transistor Qp12, and the drain of the MOS transistor Qp13, and a drain connected to the circuit output terminal 30. Are connected to a P-channel MOS transistor Qp15, a source connected to the circuit output terminal 30, a gate connected to a common connection node (hereinafter referred to as node N12) of the drain of the MOS transistor Qp12 and the source of the MOS transistor Qp14, and a drain connected to the clock. P channel MOS transistor Qp16 connected to terminal 28, respectively. A clock pulse CK1 or CK2 is applied to the clock terminal 28.

  The bootstrap circuit 24 includes a MOS transistor Qp16 that constitutes a part of the output circuit 23, and a capacitor Cap connected between the gate and drain of the MOS transistor Qp16. The reset circuit 25 includes a P-channel MOS transistor Qp17 having a source connected to the node N11, a drain connected to the VSS power supply, and a gate connected to the reset terminal 29.

  In the basic circuit 20 of the shift register circuit according to the first embodiment having the above configuration, the P-channel MOS transistors Qp11 to Qp17 are TFTs (thin film transistors) formed by a polysilicon process or an amorphous silicon process. The P-channel TFT includes a bottom gate structure in which a gate electrode is disposed under a gate insulating film (oxide film) and a top gate structure in which a gate electrode is disposed on a gate insulating film.

FIG. 4 is a cross-sectional view showing an example of the structure of a bottom gate type P-channel TFT. As shown in FIG. 4, in a TFT having a bottom gate structure, a gate electrode (Mo gate) 32 is formed on an insulating substrate 31 such as a glass substrate, and a polysilicon layer ( Alternatively, an amorphous silicon layer 34 is formed, and interlayer insulating films 35 and 36 are further formed thereon. A source region 37 and a drain region 38 made of a P + diffusion layer are formed on the gate insulating film 33 on the side of the gate electrode 32, and Al (aluminum) electrodes 39 and 40 are formed in these regions 37 and 38. It is connected.

FIG. 5 is a cross-sectional view showing an example of the structure of the top gate type P-channel TFT. As shown in FIG. 5, in a TFT having a top gate structure, a polysilicon layer (or amorphous silicon layer) 42 is formed on an insulating substrate 41 such as a glass substrate, and a gate insulating film 43 is interposed therebetween. A gate electrode (Mo gate) 44 is formed, and an interlayer insulating film 45 is further formed thereon. A source region 46 and a drain region 47 made of a P + diffusion layer are formed on the insulating substrate 41 on the side of the polysilicon layer 42, and Al electrodes 48 and 49 are connected to these regions 46 and 47. ing.

  Next, the circuit operation of the basic circuit 20 according to the first embodiment having the above configuration will be described with reference to the timing chart of FIG. Here, the case where the basic circuit 20 is the n-th register 11-n of the shift register circuit shown in FIG. 1 will be described as an example.

  Prior to the basic circuit 20 starting the circuit operation, when the reset pulse rst becomes the VSS level (hereinafter referred to as “L” level), the MOS transistor Qp17 is turned on in response to this, and the node N11 The potential is reset to “L” level. When this reset operation is completed, the circuit operation of the basic circuit 20 is started. During the period in which the basic circuit 20 is in the operating state, the reset pulse rst is always at the VDD level (hereinafter referred to as “H” level).

  When the circuit operation starts, in the initial state determination circuit 21, when the output (n + 1) of the subsequent stage (n + 1 stage) is at “L” level, the MOS transistor Qp11 is turned on, so that the potential of the node N11 is “ L "level. Further, when the output OUT (n + 1) at the subsequent stage is at “H” level, the MOS transistor Qp11 is turned off. The MOS transistor Qp12 is turned on when the potential of the node N11 is at "L" level, that is, in an initial state. Therefore, in the initial state, the potential of the node N12 is at “H” level.

  Next, in the bootstrap state determination circuit 22, when the output (n-1) of the previous stage (n-1 stage) is at "L" level, the MOS transistors Qp13 and Qp14 are both turned on. The potential of N11 becomes “H” level, and the potential of the node N12 becomes “L” level. On the other hand, when the output OUT (n−1) in the previous stage is at “H” level, both the MOS transistors Qp13 and Qp14 are turned off.

  As apparent from the operations of the initial state determination circuit 21 and the bootstrap state determination circuit 22, the potential of the node N11 and the potential of the node N12 are opposite to each other. As a result, in the output circuit 13, the MOS transistors Qp15 and Qp16 having the gates of the potentials of the nodes N11 and N12 perform a complementary operation in which one is turned on and the other is turned off. Therefore, since the MOS transistor Qp16 (Qp15) is completely turned off when the MOS transistor Qp15 (Qp16) is in the on state, no through current flows through the MOS transistor Qp16 (Qp15).

  When the clock pulse CK2 transits from the “H” level to the “L” level while the potential of the node N12 is “L” level, the bootstrap circuit 24 lowers the potential of the node N12 by capacitive coupling by the capacitor Cap. Is started, and the bootstrap operation lowers the potential of the node N12 further below the VSS potential. As a result, the MOS transistor Qp16 is completely turned on, and the VSS level is extracted as the output OUT (n).

  In the bootstrap circuit 24, the bootstrap operation can be performed only by the gate capacitance of the MOS transistor Qp16. Therefore, the capacitor Cap is not essential, and is an auxiliary capacitance for performing a more stable bootstrap operation.

(Example 2)
FIG. 8 is a circuit diagram showing a configuration of a basic circuit (register) of the shift register circuit according to Example 2 of the first embodiment. The shift register circuit according to the present embodiment is a bootstrap type register circuit configured by only an N-channel MOS transistor on an insulating substrate such as a glass substrate, and a negative power supply VSS (hereinafter referred to as VSS power supply). The first power supply is used, and the positive power supply VDD (hereinafter referred to as VDD power supply) is used as the second power supply.

  As shown in FIG. 8, the basic circuit 50 of the shift register circuit according to this embodiment includes an initial state determination circuit 51, a bootstrap state determination circuit 52, an output circuit 53, a bootstrap circuit 54, and a reset circuit 55. The circuit has two circuit input terminals 56 and 57, a clock terminal 58, a reset terminal 59, and a circuit output terminal 60.

  The initial state determination circuit 51 has a diode-connected N-channel MOS transistor Qn11 whose gate and drain are commonly connected to the circuit input terminal 56, a gate connected to the source of the MOS transistor Qn11, and a source connected to the VSS power supply. N channel MOS transistor Qn12. The bootstrap state determination circuit 52 has an N-channel MOS transistor Qn13 whose source is connected to the VSS power source and whose drain is connected to the source of the MOS transistor Qn11, and a gate and a drain connected to the circuit input terminal 57 together with the gate of the MOS transistor QN13. The N channel MOS transistor Qn14 is connected in common and the source is connected in common to the drain of the MOS transistor Qn12.

  The output circuit 53 has a source connected to the VSS power supply, a gate connected to a common connection node (hereinafter referred to as node N21) of the source of the MOS transistor Qn11, the gate of the MOS transistor Qn12, and the drain of the MOS transistor Qn13, and a drain connected to the circuit output terminal 60. Are connected to the N channel MOS transistor Qn15, the source to the circuit output terminal 60, the gate to the drain of the MOS transistor Qn12 and the source of the MOS transistor Qn14 (hereinafter referred to as node N22), the drain to the clock. N channel MOS transistor Qn16 connected to terminal 58, respectively. A clock pulse CK1 or CK2 is applied to the clock terminal 58.

  The bootstrap circuit 54 includes a MOS transistor Qn16 that forms a part of the output circuit 53, and a capacitor Cap connected between the gate and drain of the MOS transistor Qn16. The reset circuit 55 includes an N-channel MOS transistor Qn17 having a source connected to the node N21, a drain connected to the VDD power supply, and a gate connected to the reset terminal 59.

In the bootstrap register circuit 50 configured as described above, the N channel MOS transistors Qn11 to Qn17 are TFTs formed by a polysilicon process or an amorphous silicon process. Similar to the P-channel TFT, the N-channel TFT includes a bottom-gate structure and a top-gate structure, and basically has the same structure. That is, in FIGS. 4 and 5 showing the structure of the P-channel TFT, the structure of the N-channel TFT is the one in which the P + diffusion layers of the source regions 37 and 46 and the drain regions 38 and 47 are N + diffusion layers.

  The bootstrap-type register circuit 50 according to the second embodiment is different from the bootstrap-type register circuit 20 according to the first embodiment as apparent from the comparison between FIG. 8 and FIG. The only difference is that the polarities of the two power supplies are reversed, basically the same configuration, and the circuit operation and operational effects are basically the same.

  FIG. 9 is a timing chart for explaining the circuit operation of the bootstrap register circuit 50 according to the second embodiment. The output OUT (n−1) of the (n−1) th stage, the clock pulses CK1 / CK2, ( The timing diagram shows the output relationship of the (n + 1) -th stage output OUT (n + 1), the potentials of the nodes N21 and N22, and the n-th stage output OUT (n).

  As described above, in the basic circuit (bootstrap register) 20/50 according to the first embodiment, the shift operation is performed by setting the outputs of the preceding and succeeding registers (transfer stages) as the inputs IN1 and IN2. In the register circuit, when the output (n−1) of the previous stage (n−1) is given as the input IN1, the bootstrap state determination circuit 22/52 uses the gate potential of the MOS transistors Qp15 / Qn15 as the first power supply (VDD / VSS) potential and the gate potential of the MOS transistor Qp16 / Qn16 is set to the potential of the second power supply (VSS / VDD), thereby determining the state of the potential for performing the bootstrap operation. A bootstrap operation is performed in synchronization with CK1 / CK2. By this bootstrap operation, the gate potential of the MOS transistor Qp16 / Qn16 is further lowered / increased from the potential of the second power supply, and the MOS transistor Qp16 / Qn16 is completely turned on, so that the output OUT (n) As a result, the potential of the second power source can be taken out. At this time, since the MOS transistors Qp15 / Qn15 are completely off, no through current flows through the MOS transistors Qp15 / Qn15.

  In a state other than the bootstrap enabled state where the bootstrap operation can be performed, the output (n + 1) of the subsequent stage (n + 1) is given as the input IN2, so that the initial state determination circuit 21/51 has the gate potential of the MOS transistors Qp15 / Qn15. Is set to the potential of the second power supply (VSS / VDD), and the gate potential of the MOS transistors Qp16 / Qn16 is set to the potential of the first power supply (VDD / VSS). Thereby, the MOS transistor Qp16 / Qn16 is completely turned off, so that no through current flows through the MOS transistor Qp16 / Qn16. Since this operation is performed for each basic circuit (one register), the power consumption of the present shift register circuit can be greatly reduced.

  As described above, a circuit configuration that is resistant to variations in threshold voltage Vth and mobility μ can be realized. Further, in the case of the bootstrap type register circuit 50 according to the second embodiment using only the N channel MOS transistor, a configuration in which the hot electron effect is reduced by an LDD (Lightly Doped Drain) structure is adopted. This is not necessary in the bootstrap type register circuit 20 according to the first embodiment using only this, and the number of processes can be reduced accordingly, which is advantageous in terms of productivity and yield.

  In the case of the basic circuit 20/50 of the register circuit according to the first embodiment, as apparent from the timing charts of FIGS. 6 and 9, the output OUT (n−1), OUT (n + 1) “ During periods other than the L ″ level, the potentials of the nodes N11 / N21 and N12 / N22 are in a floating state. When transistor leakage occurs in this floating state, the potentials of the nodes N11 / N21 and N12 / N22 fluctuate and are normal. There is a concern that the operation cannot be guaranteed. In view of this point, a shift register circuit according to a second embodiment described below is made.

[Second Embodiment]
The basic circuit (one register) of the shift register circuit according to the second embodiment of the present invention is in addition to the output means, bootstrap state determining means, and initial state determining means in the basic circuit of the shift register circuit according to the first embodiment. In the bootstrap operation of the output means, the first switch means for separating the gate side of the second transistor from the bootstrap state determination means side, or the gate potential of the second transistor is the potential of the second power supply 1 further includes bootstrap potential determining means for setting the gate potential of the first transistor to the potential of the first power supply, and is used as each of the registers 11-1 to 11-N in FIG.

(Example 1)
FIG. 10 is a circuit diagram showing the configuration of the basic circuit (register) of the shift register circuit according to Example 1 of the second embodiment. In the figure, parts equivalent to those in FIG. Yes.

  As shown in FIG. 10, the basic circuit 70 of the shift register circuit according to this embodiment determines the initial state in order to minimize the period in which the potentials of the nodes N11 and N12 are in a floating state and to ensure normal operation. In addition to the circuit 21, the bootstrap state determination circuit 22, the output circuit 23, the bootstrap circuit 24, and the reset circuit 76, a leak mitigation countermeasure switch circuit 71, a bootstrap potential stabilization circuit 72, a bootstrap performance improvement countermeasure switch circuit 73 and An initial state voltage stabilization circuit 74 is provided, and a clock terminal 75 is provided separately from the clock terminal 28.

  The leakage mitigation switch circuit 71 includes a P-channel MOS transistor Qp18 whose source is connected to a common connection node (hereinafter referred to as node N13) of the drain of the MOS transistor Qp12 and the source of the MOS transistor Qp14 and whose drain is connected to the VSS power source. It is configured. The bootstrap potential stabilization circuit 72 includes a P-channel MOS transistor Qp19 having a source connected to the VDD power supply, a drain connected to the node N11, and a gate connected to the node N13. The bootstrap performance improvement countermeasure switch circuit 73 is configured by a P-channel MOS transistor Qp20 connected between the node N12 and the node N13 and having a gate connected to the VSS power supply.

  The initial state voltage stabilizing circuit 74 has a P channel MOS transistor Qp21 having a drain connected to the node N11 and a gate connected to the clock terminal 75 (CKinB terminal in FIG. 1), and a gate and a drain common to the drain of the MOS transistor Qp16. Connected between the source of the MOS transistor Qp21 and the common connection node (hereinafter referred to as node N14) of the sources of the MOS transistors Qp21 and Qp22 and the VDD power source. The capacitor Cap is formed. The clock pulse CK2 / CK1 is applied to the clock terminal 28 (CKinA terminal in FIG. 1), and the clock pulse CK1 / CK2 is applied to the clock terminal 75 (CKinB terminal in FIG. 1). In addition to the MOS transistor Qp17, the reset circuit 76 includes a P-channel MOS transistor Qp23 connected between the node N14 and the VSS power supply and supplied with a reset pulse rst at the gate.

  Next, the circuit operation of the basic circuit 70 according to the first embodiment having the above configuration will be described with reference to the timing chart of FIG. Here, the case where the basic circuit 70 is the n-th register 11-n of the shift register circuit shown in FIG. 1 will be described as an example.

  Note that the configurations and circuit operations of the initial state determination circuit 21, the bootstrap state determination circuit 22, the output circuit 23, the bootstrap circuit 24, and the reset circuit 76 are the same as those in the first embodiment. Shall be omitted.

  In the bootstrap potential stabilization circuit 72, when the potential of the node N13 is “L” level, the MOS transistor Qp19 is turned on, so that the potential of the node N11 is always “H” level. The potential of the node N11 is in the “H” level for a period from when the output OUT (n−1) at the previous stage is input to when the output OUT (n + 1) at the subsequent stage is input. Therefore, in this period, it is possible to prevent the potential of the node N11 from being in a floating state during a period when the output OUT (n−1) is not at the “L” level (the node N11 is set to “ Therefore, the potential for performing the bootstrap operation can be stabilized.

  MOS transistors Qp13 and Qp19 are both ON when OUT (n-1) is at "L" level, and MOS transistor Qp19 includes the function of MOS transistor Qp13. Therefore, if the MOS transistor Qp19 is present, the MOS transistor Qp13 need not be disposed, but the “L” level of the node N13 (the gate potential of the MOS transistor Qp19) is lower than the VSS potential due to the influence of the threshold voltage Vth of the MOS transistor Qp14. Is higher by Vth and the influence of the on-resistance of the MOS transistor Qp14, the MOS transistor Qp13 should be arranged in terms of circuit operation reliability (minimum drive voltage, etc.) and high-speed operation. good.

  In the bootstrap operation, the MOS transistor Qp20 is turned off when the potential of the node N12 falls below the VSS potential due to the bootstrap operation, and the bootstrap operation is performed mainly on the gate side of the MOS transistor Qp16. The circuit is disconnected from the decision circuit 22 side. As a result, the influence of the parasitic capacitance on the wiring between the gate of the MOS transistor Qp16 and the source of the MOS transistor Qp14 on the bootstrap operation can be minimized, so that the reliability of the bootstrap operation can be improved.

  The MOS transistor Qp18 is turned on when the potential of the node N12 is equal to or lower than VSS, and sets the potential on the bootstrap state determination circuit 22 side, that is, the potential of the node N13 to the VSS potential. The “L” level of the node N13 is at a potential higher by Vth than the VSS potential due to the influence of the threshold voltage Vth of the MOS transistor Qp14. Since the potential difference between the node N13 and the node N12 can be minimized by setting the potential of the node N13 to the VSS potential at the time of bootstrap driving where leakage current in the MOS transistor Qp20 causes a problem, the leakage is reduced. be able to.

  Next, in the initial state voltage stabilization circuit 74, the MOS transistor Qp22 is turned on in synchronization with the clock pulse CK2, that is, when the clock pulse CK2 is at the “L” level, thereby setting the capacitor Cap to “L”. The battery is charged to the “level” potential, that is, the VSS potential. The MOS transistor Qp21 is turned on in synchronization with the clock pulse CK1, that is, when the clock pulse CK1 is at the “L” level, whereby the potential of the capacitor Cap, that is, the potential of the node N14 is changed to the gate potential of the MOS transistor Qp15. That is, the node is N11. Here, the capacitance of the capacitor Cap needs to be set sufficiently larger than the parasitic capacitance at the node N11. In this manner, the capacitor Cap is periodically charged to the “L” level, and the potential of the capacitor Cap is set to the potential of the node N11, thereby stabilizing the state where the potential of the node N11 is at the “L” level. be able to.

(Example 2)
FIG. 12 is a circuit diagram showing the configuration of the basic circuit (register) of the shift register circuit according to Example 2 of the second embodiment. In FIG. 12, the same parts as those in FIG. Yes.

  As shown in FIG. 12, the basic circuit 80 of the shift register circuit according to this embodiment includes an initial state determination circuit 51, a bootstrap state determination circuit 52, an output circuit 53, a bootstrap circuit 54, and a reset circuit 86. A leakage mitigation countermeasure switch circuit 81, a bootstrap potential stabilization circuit 82, a bootstrap performance improvement countermeasure switch circuit 83, and an initial state voltage stabilization circuit 84 are provided, and a clock terminal 85 is provided separately from the clock terminal 58. Yes.

  The leakage mitigation switch circuit 81 includes an N-channel MOS transistor Qn18 having a source connected to a common connection node (hereinafter referred to as a node N23) of the drain of the MOS transistor Qn12 and the source of the MOS transistor Qn14, and a drain connected to the VDD power source. It is configured. The bootstrap potential stabilization circuit 82 includes an N-channel MOS transistor Qn19 having a source connected to the VSS power supply, a drain connected to the node N21, and a gate connected to the node N23. The bootstrap performance improvement countermeasure switch circuit 83 is configured by an N-channel MOS transistor Qn20 connected between the nodes N23 and N22 and having a gate connected to the VDD power supply.

  The initial state voltage stabilization circuit 84 has an N channel MOS transistor Qn21 having a drain connected to the node N21 and a gate connected to the clock terminal 85 (CKinB terminal in FIG. 1), and a gate and a drain common to the drain of the MOS transistor Qn16. N channel MOS transistor Qn22 whose source is connected to the source of MOS transistor Qn21, and a common connection node (hereinafter referred to as node N24) of the sources of MOS transistors Qn21 and Qn22 and a VSS power supply The capacitor Cap is formed. A clock pulse CK2 / CK1 is applied to the clock terminal 58 (CKinA terminal in FIG. 1), and a clock pulse CK1 / CK2 is applied to the clock terminal 85 (CKinB terminal in FIG. 1). In addition to the MOS transistor Qn17, the reset circuit 86 includes an N-channel MOS transistor Qn23 connected between the node N24 and the VDD power supply and supplied with a reset pulse rst at the gate.

  The bootstrap-type register circuit 80 according to the second embodiment is different from the bootstrap-type register circuit 70 according to the first embodiment, as is apparent from the comparison between FIG. 12 and FIG. The only difference is that the polarities of the two power supplies are reversed, basically the same configuration, and the circuit operation and operational effects are basically the same.

  FIG. 13 is a timing chart for explaining the circuit operation of the bootstrap register circuit 80 according to the second embodiment. The output OUT (n−1) of the (n−1) th stage, the clock pulses CK1 and CK2, ( The output OUT (n + 1) of the (n + 1) th stage, the potentials of the nodes N21, N22, N23, and N24 and the output OUT (n) timing relation of the nth stage are shown.

  As described above, in the basic circuit (bootstrap type register) 70/80 according to the second embodiment, in addition to the operational effects of the basic circuit 20/50 according to the first embodiment, the gate potential of the MOS transistors Qp16 / Qn16. By the action of the bootstrap potential stabilization circuit 72/82 for setting the gate potential of the MOS transistor Qp15 / Qn15 to the potential of the first power supply (VDD / VSS) when is the potential of the second power supply (VSS / VDD), Since the potential of the node N11 / N21 does not enter the floating state during the period in which the bootstrap operation is performed, normal operation of the bootstrap can be guaranteed.

  Further, during the bootstrap operation, the action of the bootstrap performance improvement countermeasure switch circuit 73/83, which is the first switch means for circuit-separating the gate side of the MOS transistor Qp16 / Qn16 from other circuit parts, causes the MOS transistor Qp16 to Since the influence of the parasitic capacitance on the wiring between the gate and the source of the MOS transistor Qp14 on the bootstrap operation can be minimized, the reliability of the bootstrap operation can be improved.

  Further, when the gate potential of the MOS transistors Qp16 / Qn16 is equal to or lower than the potential of the second power supply (VSS / VDD), the potential on the bootstrap state determination circuit 22/52 side is set to the potential of the second power supply (VSS / VDD). When the leakage of the MOS transistor Qp20 / Qn20 becomes a problem during the bootstrap operation due to the action of the leakage mitigation countermeasure switch circuit 71/81 which is the second switch means, the nodes N13 / N23 and N12 / N22 Since the potential difference between the two can be minimized, the leakage can be mitigated.

  Furthermore, the capacitor Cap is charged with the potential of the second power supply (VSS / VDD) in synchronization with the clock pulse CK2, and the capacitor Cap is set to the gate potential of the MOS transistors Qp15 / Qn15 in synchronization with the clock pulse CK1. By the action of the state voltage stabilization circuit 74/84, it is possible to stabilize the state where the potential of the node N11 / N21 is at the “L” level / “H” level.

  Subsequently, a transfer gate circuit which is a first input signal generating means for generating the first input IN1 of the first stage register 11-1 based on the input pulse ST1 and the clock pulse CK1 that are active at the start of one field period 12 and a transfer gate which is a second input signal generating means for generating the second input IN2 of the final stage register 11-N based on the input pulse ST2 and the clock pulse CK2 which are active at the end of one field period A specific circuit configuration of the circuit 13 will be described.

[Transfer gate circuit 12]
(Example 1)
FIG. 14 is a circuit diagram illustrating a configuration of the transfer gate circuit 12 according to the first embodiment. The transfer gate circuit according to this embodiment is a bootstrap type transfer gate circuit composed of only P-channel MOS transistors, and includes a bootstrap type transfer gate 91 and a power supply switch 92, and an input pulse ST is The circuit has a circuit input terminal 93 to be applied and a clock terminal 94 to which a clock pulse CK1 is applied.

  The bootstrap type transfer gate 91 has a P-channel MOS transistor Qp24 whose source is connected to the clock terminal 94, a gate connected to the VSS power supply, a drain to the circuit input terminal 93, a gate to the drain of the MOS transistor Qp24, and a source to The P-channel MOS transistor Qp25 is connected to the IN1-side input terminal of the first stage register 11-1. The power supply switch 92 includes a P-channel MOS transistor Qp26 having a source connected to the VDD power supply, a gate connected to the circuit input terminal 93, and a drain connected to the output terminal of the first stage register 11-1.

  Next, the circuit operation of the transfer gate circuit according to the first embodiment having the above configuration will be described with reference to the timing chart of FIG. FIG. 15 shows the timing relationship between the input pulse ST, the clock pulses CK1 and CK2, the drain potential A of the MOS transistor Qp24, the source potential B of the MOS transistor Qp25, and the output OUT (1) of the first stage register 11-1. Further, as shown in FIG. 7, the input pulse ST has a timing relationship delayed by a predetermined delay time d with respect to the clock pulses CK1 / CK2. This delay time d is necessary for performing the bootstrap operation in the MOS transistor Qp25.

  First, the bootstrap type transfer gate 91 becomes active at the falling edge of the input pulse ST and the clock pulse CK1, selects the pulse ST1 at the start of one field period in the input pulse ST, and uses the pulse ST1 as the first stage register 11. Input to -1. The power supply switch 92 supplies the VDD level to the output OUT (1) of the first stage register 11-1 when the MOS transistor Qp26 is turned on in synchronization with the “L” level of the input pulse ST.

  Even when the source potential B of the MOS transistor Qp25 fluctuates due to the leakage of the MOS transistor Qp25 due to the influence of the pulse ST2 at the end of one field period in the input pulse ST by the action of the power supply switch 92, the influence is the first stage. It can be prevented from appearing at the output OUT (1) of the register 11-1. That is, it is possible to mitigate or eliminate the influence caused by variations in the threshold voltage Vth and mobility μ of the transistor, leakage current, and the like. In other words, it is possible to construct a circuit that is resistant to variations in threshold voltage Vth and mobility μ of transistors, leakage current, and the like.

(Example 2)
FIG. 16 is a circuit diagram illustrating a configuration of the transfer gate circuit 12 according to the second embodiment. In the figure, the same components as those in FIG. 14 are denoted by the same reference numerals. The transfer gate circuit according to this embodiment is a bootstrap type transfer gate circuit composed of only N-channel MOS transistors, and includes a bootstrap type transfer gate 95 and a power supply switch 96.

  The bootstrap type transfer gate 95 has an N-channel MOS transistor Qn24 whose source is connected to the clock terminal 94, a gate connected to the VDD power source, a drain to the circuit input terminal 93, a gate to the drain of the MOS transistor Qn24, and a source to The N-channel MOS transistor Qn25 is connected to the input terminal on the IN1 side of the first stage register 11-1. The power supply switch 96 includes an N-channel MOS transistor Qn26 having a source connected to the VSS power supply, a gate connected to the circuit input terminal 93, and a drain connected to the output terminal of the first stage register 11-1.

  The bootstrap type transfer gate circuit according to the second embodiment is different from the bootstrap type transfer gate circuit according to the first example as shown in FIG. 16 and FIG. The only difference is that the polarities of the two power supplies are reversed, basically the same configuration, and the circuit operation and operational effects are basically the same.

  FIG. 17 shows a timing relationship between the input pulse ST, the clock pulses CK1 and CK2, the drain potential A of the MOS transistor Qn24, the source potential B of the MOS transistor Qn25, and the output OUT (1) of the first stage register 11-1.

[Transfer Gate Circuit 13]
(Example 1)
FIG. 18 is a circuit diagram illustrating a configuration of the transfer gate circuit 13 according to the first embodiment. The transfer gate circuit according to this embodiment is a bootstrap type transfer gate circuit composed of only P-channel MOS transistors, and includes a bootstrap type transfer gate 97 and a circuit input terminal 98 to which an input pulse ST is applied. And a clock terminal 99 to which a clock pulse CK2 is applied.

  The bootstrap type transfer gate 97 has a P-channel MOS transistor Qp27 whose source is connected to the clock terminal 99, a gate connected to the VSS power supply, a drain to the circuit input terminal 98, a gate to the drain of the MOS transistor Qp27, and a source to P-channel MOS transistor Qp28 connected to the IN2 side input terminal of final stage register 11-N.

  Next, the circuit operation of the transfer gate circuit according to the first embodiment having the above configuration will be described with reference to the timing chart of FIG. FIG. 19 shows the timing relationship between the input pulse ST, the clock pulses CK1 and CK2, the drain potential A of the MOS transistor Qp27, the source potential B of the MOS transistor Qp28, and the output OUT (N) of the final stage register 11-N. .

  The bootstrap type transfer gate 97 becomes active at the falling edge of the input pulse ST and the clock pulse CK2, selects the pulse ST2 at the end of one field period in the input pulse ST, and uses the pulse ST2 as the final stage register 11- N is input as an initialization signal.

(Example 2)
FIG. 20 is a circuit diagram showing the configuration of the transfer gate circuit 13 according to the second embodiment. In the figure, the same parts as those in FIG. The transfer gate circuit according to the present embodiment is a bootstrap type transfer gate circuit composed of only N-channel MOS transistors, and has a configuration having a bootstrap type transfer gate 100.

  The bootstrap type transfer gate 100 has an N channel MOS transistor Qn27 whose source is connected to the clock terminal 99 and its gate connected to the VDD power source, a drain to the circuit input terminal 98, a gate to the drain of the MOS transistor Qn27, and a source to The N-stage MOS transistor Qn28 is connected to the IN2-side input terminal of the final stage register 11-N.

  The bootstrap type transfer gate circuit according to the second embodiment is different from the bootstrap type transfer gate circuit according to the first example as shown in the comparison between FIG. 20 and FIG. The only difference is that the polarities of the two power supplies are reversed, basically the same configuration, and the circuit operation and operational effects are basically the same.

  FIG. 21 shows the timing relationship between the input pulse ST, the clock pulses CK1 and CK2, the drain potential A of the MOS transistor Qn27, the source potential B of the MOS transistor Qn28, and the output OUT (N) of the final stage register 11-N. .

[Application example]
The shift register circuit according to the first and second embodiments described above is a shift register circuit with a single PMOS transistor configuration when configured in Example 1, and a shift register circuit with a single NMOS transistor configuration when configured in Example 2. Become. This shift register is used in a panel type display device typified by a liquid crystal display device, EL (electroluminescence) or LED (Light Emitting Diode) display device, or an XY address type solid-state imaging device typified by a CMOS image sensor. It can be used as a shift register circuit constituting a vertical drive circuit or a horizontal drive circuit for selecting pixels. However, this application example is only an example, and the shift register circuit according to the present invention is not limited to this application example, and can be widely used as a general shift register circuit.

  FIG. 22 is a block diagram showing a schematic configuration of, for example, an active matrix liquid crystal display device according to an application example of the present invention.

  As shown in FIG. 22, an active matrix liquid crystal display device according to an application example of the present invention includes a pixel array unit 102 in which a large number of pixels 101 are arranged in a matrix, and each pixel 101 of the pixel array unit 102 is arranged in a row. The configuration includes at least a vertical driving circuit 103 that sequentially selects in units, and a horizontal driving circuit 104 that writes a video signal to each pixel in a row selected by the vertical driving circuit 103. The vertical drive circuit 103 and the horizontal drive circuit 104 constitute a drive circuit that is integrated on the display panel 105 together with the pixel array unit 102 to drive the pixel array unit 102.

  A vertical start pulse VST, vertical clock pulses VCK and xVCK, a horizontal start pulse HST, and horizontal clock pulses HCK and xHCK are input to the display panel 105 from the outside of the panel. The vertical start pulse VST and the horizontal start pulse HST are given to the vertical drive circuit 103 and the horizontal drive circuit 104 after passing through the level shift (L / S) circuit group 106 and the inverter circuit group 107.

  The vertical clock pulses VCK and xVCK and the horizontal clock pulses HCK and xHCK pass through the level shift circuit group 106 and the inverter circuit group 107, and then directly pass through the buffer circuits 108 and 109 and the buffer circuits 110 and 111 and the horizontal drive pulse 103 and horizontal. It is given to the drive circuit 104. The level shift circuit group 106 performs level shift (level conversion) on each of the low voltage amplitude vertical start pulse VST, the vertical clock pulses VCK and xVCK, the horizontal start pulse HST, and the horizontal clock pulses HCK and xHCK to a high voltage amplitude pulse signal. )

  In this example, the vertical start pulse VST, the vertical clock pulses VCK and xVCK, the horizontal start pulse HST, and the horizontal clock pulses HCK and xHCK are input from the outside of the display panel 105. The generated timing generator is integrated on the display panel 105, and the vertical start pulse VST and the horizontal start pulse HST are directly supplied from the timing generator to the vertical drive circuit 103 and the horizontal drive circuit 104, and the vertical clock pulses VCK, xVCK and the horizontal The clock pulses HCK and xHCK may be provided to the vertical drive circuit 103 and the horizontal drive circuit 104 via the buffer circuits 108 to 111.

  In the pixel array unit 102, the display panel 105 includes scanning lines 112 (112-1 to 112-112) corresponding to the number m of rows of the pixel array unit 102 on one of two transparent insulating substrates (for example, glass substrates). -M) and signal lines 113 (113-1 to 113-n) corresponding to the number of columns n are wired in a matrix, and a liquid crystal layer is held between the other substrate opposed to each other with a predetermined gap. For example, the backlight is arranged on the back side. Then, the pixel 101 is arranged at the intersection of the scanning line 112 and the signal line 113.

  As is apparent from FIG. 22, the pixel 101 has a pixel transistor TFT composed of a thin film transistor having a gate connected to the scanning line 112 and a source connected to the signal line 113, and a pixel electrode connected to the drain of the pixel transistor TFT. The liquid crystal cell LC and the storage capacitor CS having one electrode connected to the drain of the pixel transistor TFT are provided. Here, the liquid crystal cell LC means a capacitance generated between a pixel electrode formed by the pixel transistor TFT and a counter electrode formed facing the pixel electrode. The counter electrode of the liquid crystal cell LC is connected to the common line 114 together with the other electrode of the storage capacitor CS, for example.

  FIG. 23 is a block diagram illustrating an example of a specific configuration of the vertical drive circuit 103. As is apparent from FIG. 23, the vertical drive circuit 103 includes a shift register 121 and the like. When the vertical start pulse VST is given, the vertical start pulse VST is sequentially shifted in synchronization with the vertical clock pulse VCK, and the pixel array. Vertical scanning pulses φV1 to φVm for sequentially selecting the pixels 101 of the unit 102 in units of rows are output from each stage. The vertical scanning pulses φV1 to φVm are applied to the scanning lines 122-1 to 122-m of the pixel array unit 102 via the buffer circuits 122-1 to 122-m.

  The horizontal drive circuit 104 is also configured to include at least a shift register. In the horizontal drive circuit 104, when the horizontal start pulse HST is given to the shift register, the horizontal start pulse HST is sequentially shifted in synchronization with the horizontal clock pulse HCK, and sampling pulses are sequentially output from each stage. Then, the horizontal drive circuit 104 samples the video signal supplied from the outside of the display panel 105 using this sampling pulse, and dot-sequentially applies to each pixel 101 in the row selected by the vertical drive circuit 103, or An operation of writing in line sequential order is performed.

  In the liquid crystal display device having the above-described configuration, for example, the first and first shift registers 121 described above are used as the shift register 121 that outputs the vertical scanning pulses φV1 to φVm for sequentially selecting the pixels 101 of the pixel array unit 102 in units of rows. The shift register circuit according to the second embodiment is used. As described above, the shift register circuits according to these embodiments are low power consumption shift register circuits that can suppress a through current flowing in the circuit. Therefore, by using the shift register circuit according to the first and second embodiments as the shift register 121 of the vertical drive circuit 103, the scanning lines 112-1 to 112-m can be driven with low power consumption. The power consumption of the liquid crystal display device can be reduced.

  In this application example, the case where the shift register circuit according to the first and second embodiments is used as the shift register 121 constituting the vertical drive circuit 103 has been described as an example. However, this application example is merely an example. It can also be used as a shift register constituting the horizontal drive circuit 104.

  In this application example, the case where the present invention is applied to a liquid crystal display device using a liquid crystal cell as a display element of the pixel 101 has been described as an example. However, the present invention is not limited to this application example. For example, the present invention can be similarly applied to other active matrix display devices such as an EL display device using EL elements.

  A display device typified by a liquid crystal display device using the buffer circuit according to the above-described embodiment as a part of a drive circuit is used as a screen display unit of a mobile phone, a PDA (Personal Digital Assistants), a notebook PC (Personal Computer), etc. It can be mounted and used.

It is a block diagram which shows the structural example of the shift register circuit based on this invention. It is a timing chart which shows the timing relationship of each input / output IN1 (1), IN2 (N), and OUT (1) -OUT (N) of input pulse ST, clock pulses CK1, CK2, and N stage registers. It is a circuit diagram which shows the structure of the basic circuit of the shift register circuit which concerns on Example 1 of 1st Embodiment. It is sectional drawing which shows an example of the structure of bottom gate type P channel TFT. It is sectional drawing which shows an example of the structure of a top gate type P channel TFT. 6 is a timing chart for explaining the circuit operation of the shift register circuit according to Example 1 of the first embodiment; It is a timing chart which shows the timing relationship with respect to clock pulse CK1 / CK2 of the input pulse ST. It is a circuit diagram which shows the structure of the basic circuit of the shift register circuit which concerns on Example 2 of 1st Embodiment. 6 is a timing chart for explaining the circuit operation of the shift register circuit according to Example 2 of the first embodiment; It is a circuit diagram which shows the structure of the basic circuit of the shift register circuit which concerns on Example 1 of 2nd Embodiment. It is a timing chart with which it uses for description of the circuit operation | movement of the shift register circuit which concerns on Example 1 of 2nd Embodiment. It is a circuit diagram which shows the structure of the basic circuit of the shift register circuit which concerns on Example 2 of 2nd Embodiment. It is a timing chart with which it uses for description of the circuit operation | movement of the shift register circuit which concerns on Example 2 of 2nd Embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a first-stage transfer gate circuit according to the first embodiment. 3 is a timing chart for explaining the circuit operation of the first-stage transfer gate circuit according to the first embodiment. FIG. 6 is a circuit diagram illustrating a configuration of a first-stage transfer gate circuit according to a second embodiment. 10 is a timing chart for explaining the circuit operation of the first-stage transfer gate circuit according to the second embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a final-stage transfer gate circuit according to the first embodiment. 6 is a timing chart for explaining the circuit operation of the final-stage transfer gate circuit according to the first embodiment. 6 is a circuit diagram illustrating a configuration of a transfer gate circuit for a final stage according to Embodiment 2. FIG. 12 is a timing chart for explaining the circuit operation of the final-stage transfer gate circuit according to the second embodiment. It is a block diagram which shows the outline of a structure of the active matrix type liquid crystal display device which concerns on the application example of this invention. It is a block diagram which shows an example of a specific structure of a vertical drive circuit. It is a circuit diagram which shows the structure of the shift register circuit based on the prior art example comprised only using the MOS transistor. It is a timing chart with which it uses for description of the circuit operation | movement of the shift register circuit which concerns on a prior art example. FIG. 6 is a characteristic diagram showing a relationship (measurement result) of a source-drain current Ids with respect to a gate voltage Vgs of a P-channel MOS TFT produced by a low-temperature polysilicon process.

Explanation of symbols

  11-1 to 11-N: Register (S / R), 12: First-stage transfer gate circuit, 13: Final-stage transfer gate circuit, 20, 50, 70, 80: Basic circuit, 21, 51: Initial state determination Circuit, 22, 52 ... Bootstrap state determination circuit, 23, 53 ... Output circuit, 24, 54 ... Bootstrap circuit, 25, 55 ... Reset circuit, 71, 81 ... Leak mitigation switch circuit, 72, 82 ... Bootstrap Potential stabilization circuit 73, 83 ... Bootstrap performance improvement countermeasure switch circuit, 74, 84 ... Initial state voltage stabilization circuit

Claims (16)

  1. A shift register circuit comprising a single channel transistor on an insulating substrate,
    A first transistor having a source connected to a first power supply; and a second transistor having a source connected to the drain of the first transistor and a clock signal applied to the drain. An output means for performing a bootstrap operation;
    When the first input signal is applied, the gate potential of the first transistor is set to the potential of the first power supply, and the gate potential of the second transistor is set to the potential of the second power supply. Bootstrap state determination means for determining the bootstrap state of the output means,
    When the second input signal is applied, the gate potential of the first transistor is set to the potential of the second power supply, and the gate potential of the second transistor is set to the potential of the first power supply. And a basic circuit comprising an initial state determining means for determining an initial state of the output means is cascaded in a plurality of stages,
    Each of the basic circuits uses the output signal of the preceding basic circuit as the first input signal and the output signal of the succeeding basic circuit as the second input signal.
  2. The shift register circuit according to claim 1, wherein the transistor constituting the basic circuit is a thin film transistor.
  3. The apparatus further comprises bootstrap potential determination means for setting the gate potential of the first transistor to the potential of the first power supply when the gate potential of the second transistor is the potential of the second power supply. The shift register circuit according to claim 1.
  4. 2. The shift register circuit according to claim 1, further comprising a first switch unit that separates the gate side of the second transistor from the bootstrap state determination unit side during a bootstrap operation of the output unit.
  5. The apparatus further comprises second switch means for setting the potential on the bootstrap state determining means side to the potential of the second power supply when the gate potential of the second transistor is the potential of the second power supply. The shift register circuit according to claim 4.
  6. The first input signal is a signal that becomes active at a start portion and an end portion of one field period,
    The clock signal is a two-phase clock signal;
    First input signal generating means for generating the first input signal of the basic circuit in the first stage based on one of the first input signal and the two-phase clock signal that are active at the start portion;
    Second input signal generation means for generating the second input signal of the basic circuit at the final stage based on the other of the first input signal and the two-phase clock signal that are active at the end portion; The shift register circuit according to claim 1, further comprising:
  7. The first input signal generation means supplies the potential of the first power supply to the output of the basic circuit in the first stage in synchronization with one of the two-phase clock signals. Shift register circuit.
  8. The capacitor is charged with the potential of the second power supply in synchronization with the other of the two-phase clock signals, and the potential of the capacitor is set to the gate potential of the first transistor in synchronization with one of the two-phase clock signals. The shift register circuit according to claim 6, further comprising initial state voltage stabilizing means for performing the operation.
  9. A pixel array unit in which pixels including display elements are arranged in a matrix on a transparent insulating substrate;
    A display device including a shift register circuit configured by a single channel transistor, and a driving circuit integrated with the pixel array unit on the insulating substrate to drive the pixel array unit;
    The shift register circuit includes:
    A first transistor having a source connected to a first power supply; and a second transistor having a source connected to the drain of the first transistor and a clock signal applied to the drain. An output means for performing a bootstrap operation;
    When the first input signal is applied, the gate potential of the first transistor is set to the potential of the first power supply, and the gate potential of the second transistor is set to the potential of the second power supply. Bootstrap state determining means for determining the bootstrap state of the output means,
    When the second input signal is applied, the gate potential of the first transistor is set to the potential of the second power supply, and the gate potential of the second transistor is set to the potential of the first power supply. And a basic circuit comprising an initial state determining means for determining an initial state of the output means is cascaded in a plurality of stages,
    Each of the basic circuits uses the output signal of the preceding basic circuit as the first input signal and the output signal of the succeeding basic circuit as the second input signal.
  10. The display device according to claim 9, wherein the transistor constituting the basic circuit is a thin film transistor.
  11. The apparatus further comprises bootstrap potential determination means for setting the gate potential of the first transistor to the potential of the first power supply when the gate potential of the second transistor is the potential of the second power supply. The display device according to claim 9.
  12. 10. The display device according to claim 9, further comprising a first switch unit that separates the gate side of the second transistor from the bootstrap state determination unit side during a bootstrap operation of the output unit.
  13. The apparatus further comprises second switch means for setting the potential on the bootstrap state determining means side to the potential of the second power supply when the gate potential of the second transistor is the potential of the second power supply. The display device according to claim 12.
  14. The first input signal is a signal that becomes active at a start portion and an end portion of one field period,
    The clock signal is a two-phase clock signal;
    First input signal generating means for generating the first input signal of the basic circuit in the first stage based on one of the first input signal and the two-phase clock signal that are active at the start portion;
    Second input signal generation means for generating the second input signal of the basic circuit at the final stage based on the other of the first input signal and the two-phase clock signal that are active at the end portion; The display device according to claim 9, further comprising:
  15. The first input signal generation means supplies the potential of the first power supply to the output of the basic circuit in the first stage in synchronization with one of the two-phase clock signals. Display device.
  16. The capacitor is charged with the potential of the second power supply in synchronization with the other of the two-phase clock signals, and the potential of the capacitor is set to the gate potential of the first transistor in synchronization with one of the two-phase clock signals. The display device according to claim 14, further comprising an initial state voltage stabilizing unit configured to perform the initial state voltage stabilization.
JP2003386172A 2003-11-17 2003-11-17 Shift register circuit, basic circuit and display device Active JP4686972B2 (en)

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US9024860B2 (en) 2009-03-06 2015-05-05 Japan Display Inc. Scanner, electro-optical panel, electro-optical display device and electronic apparatus
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