KR100830903B1 - Shift resister and liquid crystal display device having the same - Google Patents

Abstract

A shift register and a liquid crystal display having the same are disclosed. The gate driving circuit integrated on the liquid crystal display panel and sequentially applying scan pulses to the plurality of gate lines includes one shift register. The shift register provides a power supply voltage to the output terminal in response to a pull-up part for providing a clock signal to the gate line, a pull-up driver for driving the pull-up part in response to an output signal of a previous stage, and an output signal of a next stage. It consists of a pull-down section for. Therefore, the liquid crystal display device can secure reliability, and can minimize size and power consumption.

Description

SHIFT RESISTER AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME}

1 is a view showing a conventional liquid crystal display device.

2 is a perspective view showing in detail a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 3 is a plan view specifically showing the liquid crystal display panel shown in FIG. 2.

4 is a block diagram illustrating a shift register of the gate driving circuit illustrated in FIG. 3.

FIG. 5 is a circuit diagram illustrating an internal configuration of the shift register shown in FIG. 4.

FIG. 6 is a timing diagram of each part of the shift register shown in FIG. 4.

7 is a plan view specifically showing a liquid crystal display panel according to another exemplary embodiment of the present invention.

8 is a block diagram illustrating a shift register of the gate driving circuit illustrated in FIG. 7.

FIG. 9 is a timing diagram of each part of the shift register shown in FIG. 8.

The present invention relates to a shift register and a liquid crystal display having the same. More particularly, the present invention relates to a shift register for sequentially driving the gate lines by sequentially applying scan pulses to the gate lines and a liquid crystal display having the same. will be.

Recently, information processing devices have been rapidly developed to have various forms, various functions, and faster information processing speed. Information processed in such an information processing device has an electrical signal form. In order for the user to visually check the information processed by the information processing apparatus, a display apparatus serving as an interface is required.

Recently, a liquid crystal display device has a light weight, a small size, high resolution, low power, and environmentally friendly advantages compared to a CRT type display device.

The liquid crystal display is largely divided into a twisted nematic (TN) method and a super-twisted nematic (STN) method, and the switching method and the TN liquid crystal are used as a difference between the driving methods. It is divided into an active matrix (AM) display method and a passive matrix (PM) display method using STN liquid crystals.

The AM display method is used for the TFT-LCD, which drives the LCD using the TFT as a switch, and the PM display method does not require a complicated circuit in this regard since it does not use a transistor.

TFT-LCDs are classified into a-Si thin film transistor liquid crystal display devices (hereinafter referred to as TFT-LCDs) and poly-Si TFT LCDs. The poly-Si TFT LCD has a small power consumption and a low price, but has a disadvantage in that the TFT manufacturing process is complicated compared to a-Si TFT. Thus, the poly-Si TFT LCD is mainly applied to a small display device such as a display of an IMT-2000 phone. On the other hand, the a-Si TFT LCD has a large area and a high yield, and is mainly applied to a large screen display device such as a notebook PC, an LCD monitor, and an HDTV.

1 is a view showing a conventional a-Si TFT LCD.

Referring to FIG. 1, an a-Si TFT LCD forms a data driving chip 34 on a flexible circuit board 32 by a chip on film (hereinafter referred to as COF) method, and the flexible circuit board 32. The data printed circuit board 36 and the data line terminal of the pixel array are connected to each other through the circuit board 36. In addition, the gate driving chip 40 is formed on the flexible circuit board 38 by a COF method, and the gate printed circuit board 42 and the gate line terminal portion of the pixel array are connected through the flexible circuit board 38.

The gate driving chip 40 sequentially selects the gate lines, turns on the TFTs connected to the selected gate lines, and simultaneously applies respective signals.

Since the a-Si TFT LCD performs a process of assembling a plurality of flexible circuit boards on a glass substrate, an outer lead bonding process (OLB) is more complicated than a poly-Si TFT LCD, and thus manufacturing cost is high. In addition, there is a need for a technology for lowering the power consumed in the a-si TFT LCD, specifically, the power consumed in the driving circuit.

Therefore, in recent years, the data driving circuit and the gate driving circuit are simultaneously formed on the glass substrate as well as the pixel array in a-Si TFT LCD, thereby reducing the number of assembly processes and reducing the power consumption of the driving circuit. Minimize.

The gate driving circuit integrated in the liquid crystal display panel by a poly-Si TFT method includes a shift register. In this case, the number of transistors used to configure the shift register and the external connection terminals greatly influence the reliability and power consumption of the liquid crystal display.

Specifically, the large number of transistors used in the shift register not only reduces reliability in the layout process but also increases the area occupied by the transistors, thereby increasing the size of the liquid crystal display device.

In addition, as the number of external connection terminals required to drive the shift register increases, the process becomes more complicated, the reliability decreases, and the size of the liquid crystal display increases.

Accordingly, it is a first object of the present invention to provide a shift register that can ensure reliability and minimize size and power consumption.

It is a second object of the present invention to provide a liquid crystal display device having a shift register integrated in a liquid crystal display panel, which can secure reliability and minimize size and power consumption.

In the shift register according to the present invention for achieving the above-described first object, a plurality of stages are cascaded and each stage includes an input terminal, an output terminal, a control terminal, and a clock signal input terminal. In this case, a first clock signal is provided to odd-numbered stages of the shift register, and a second clock signal inverted in phase with the first clock signal is provided to even-numbered stages.

Each stage of the shift register is connected to an input node of the pull-up unit and a pull-up unit for providing the first clock signal or the second clock signal provided from the clock signal input terminal to the output terminal. The output terminal connected to a pull-up driving unit for turning on the pull-up unit and an input node of the pull-up unit in response to the first output signal of the previous stage provided to the control unit, and in response to a second output signal of the next stage provided to the control terminal; It includes a pull-down unit for providing a power supply voltage.

According to an aspect of the present invention, there is provided a liquid crystal display device including a display cell array circuit, a data driving circuit, and a gate driving circuit formed on a transparent substrate, wherein the display cell array circuit includes a plurality of data lines. And a plurality of gate lines, each display cell circuit being connected to a corresponding data and gate line pair.

In this case, the gate driving circuit is a plurality of stages are cascaded, each stage is composed of a shift register including an input terminal, an output terminal, a control terminal and a clock signal input terminal, the odd stages of the shift register One clock signal is provided, and even-numbered stages are provided with a second clock signal whose phase is inverted from the first clock signal.

Each stage of the shift register is connected to an input node of the pull-up unit and a pull-up unit for providing the first clock signal or the second clock signal provided from the clock signal input terminal to the output terminal. A pull-up driving unit for turning on the pull-up unit in response to a first output signal of a previous stage provided from the input terminal and an input node of the pull-up unit, the output terminal in response to a second output signal of the next stage provided from the control terminal; It includes a pull-down unit for providing a power supply voltage.

According to the present invention, the shift register may include a pull-up part for providing a clock signal to the gate line, a pull-up driver for driving the pull-up part in response to an output signal of a previous stage, and the output terminal in response to an output signal of a next stage. It is composed of a pull-down unit for providing a power supply voltage to the. Therefore, the liquid crystal display device can secure reliability, and can minimize size and power consumption.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

2 is a perspective view specifically showing a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the liquid crystal display 500 may include a display unit 100 for displaying an image and a backlight assembly 200 for providing light to the display unit 100 under the display unit 100. ).

The display unit 100 includes a liquid crystal display panel 110 for displaying an image and a flexible circuit board 190 connected to one side of the liquid crystal display panel 110.

The liquid crystal display panel 110 includes a TFT substrate 120 having a TFT and a pixel electrode, a color filter substrate 130 on which RGB pixels and a common electrode are formed, and the TFT substrate 120 and the color filter substrate 130. It consists of a liquid crystal layer (not shown) interposed in between. A display cell array circuit, a data driver circuit, a gate driver circuit, and external connection terminals are formed on the TFT substrate 120 by an a-Si TFT process, and a plurality of data driver chips are mounted on the TFT substrate 120.

The flexible circuit board 190 supplies a driving signal and an image data signal provided from the outside of the liquid crystal display panel 110 to the liquid crystal display panel 110. The flexible circuit board 190 is connected to a plurality of data driving chips mounted on the liquid crystal display panel 110 to be electrically connected to the circuits of the TFT substrate 120. In detail, the flexible circuit board 190 provides a data signal and a data timing signal to the data driving circuit, and provides a gate timing signal and a gate driving voltage to the gate driving circuit.

The backlight assembly 200 includes a lamp assembly 220 for generating a first light and a light guide plate 240 for guiding the first light toward the liquid crystal display panel 110. In addition, the optical sheets 260 and the light guide plate 240 may be provided on the light guide plate 240 to diffuse the second light guided toward the liquid crystal display panel 110 to improve the uniformity of the second light. A reflection plate 280 is further provided on the lower side to reflect the third light leaked from the light guide plate 240 to increase the amount of the second light.

The backlight assembly 200 and the display unit 100 are accommodated in the mold frame 290. In addition, a chassis 300 coupled to the mold frame 290 and configured to fix the backlight assembly 200 and the display unit 100 to the mold frame 290 is provided.

FIG. 3 is a plan view specifically showing the liquid crystal display panel shown in FIG. 2.

Referring to FIG. 3, the TFT substrate 120 is divided into a display area A for displaying an image and peripheral areas B and C of the display area A. FIG. In the display area A, a display cell array circuit (not shown) is formed by a TFT process. Specifically, TFTs (not shown) are formed in the display area A, m data lines DLm extending in a column direction, and n gate lines GLn extending in a row direction. Is formed. At this time, the source electrodes of the TFTs arranged in the column direction are commonly connected to the data line DLm extending in the column direction, and the gate electrodes of the TFTs arranged in the row direction are the gate lines extending in the row direction. Commonly connected to (GLn). In addition, the drain electrode of the TFT is connected to a pixel electrode (not shown).

The peripheral regions B and C are divided into a first region B formed by extending one end of the data lines DLm and a second region C formed by extending one end of the gate lines GLn. do. A plurality of data driving chips 140 coupled to one end of the data lines DLm are mounted in the first region B. The plurality of data driving chips 140 are also connected to the first external connection terminal 191 connected to the flexible circuit board 190.

The gate driving circuit 150 connected to one end of the gate lines GLn in the second region C and sequentially applying scan pulses to the gate lines GLn is the same as the display cell array circuit. It is formed by the process. In this case, the gate driving circuit 150 is connected to the second external connection terminal 192 connected to the flexible circuit board 190. The second external connection terminal 192 has an input terminal IN to which a start signal ST to be described later is input, a first clock signal input terminal CK, a second clock signal input terminal CKB, and a power supply voltage. It includes a terminal (VSS).

4 is a block diagram specifically illustrating a shift register constituting the gate driving circuit illustrated in FIG. 3.

Referring to FIG. 4, the gate driving circuit 150 includes one shift register. In this case, the shift register is composed of n + 1 stages SRC1 to SRCn + 1 including n cascaded SRC1 to SRCn and one dummy stage SRCn + 1. That is, the output terminal OUT of each stage SRC is connected to the input terminal IN of the next stage, and also to the control terminal CT of the previous stage. The output terminals OUT of the n stages SRC1 to SRCn correspond to the n gate lines GLn, respectively.

Specifically, each stage has an input terminal IN, an output terminal OUT, a control terminal CT, a clock signal input terminal CK, and a power supply voltage terminal VSS.

The first clock signal CK is provided to the odd-numbered stages SRC2i-1 of the shift register, and the second clock signal CKB is provided to the even-numbered stages SRC2i. In this case, the first clock signal CK and the second clock signal CKB have phases opposite to each other.

The output signal of the next stage is input as a control signal to each control terminal CT of each stage. Therefore, the control signal input to the control terminal CT is delayed by the duty period of its output signal.

Therefore, since output signals of each stage are sequentially generated with an active period (high state), corresponding gate lines are enabled in the active period of each output signal.

The input terminal IN of the first stage SRC1 is provided with the start signal ST instead of the output signal of the previous stage. In addition, the dummy stage SRCn + 1 provides a control signal to the control terminal CT of the previous stage SRCn.

FIG. 5 is a detailed internal configuration circuit diagram of each stage of the shift register shown in FIG. 4. FIG. 6 is an output waveform diagram of each stage of the shift register shown in FIG. 4.

Referring to FIG. 5, each stage of the shift register includes a pull up unit 151, a pull up driver 152, and a pull down unit 153.

The pull-up unit 151 includes a first NMOS transistor NT11 having a drain connected to a clock signal input terminal CK, a gate connected to a node N, and a source connected to an output terminal OUT.                     

The pull-up driving unit 152 has a source and a gate connected to an input terminal IN, and a second NMOS transistor NT2 having a source connected to the node N, and between the node N and the output terminal OUT. It includes a connected capacitor (C).

The pull-down unit 153 includes a third NMOS transistor NT3 having a source connected to the node N, a gate connected to the control terminal CT, and a drain connected to the power supply voltage VSS.

As shown in FIG. 6, when the first and second clock signals CK and CKB and the start signal ST are supplied to the shift register, the first stage SRC1 is provided at the leading end of the start signal ST. In response, a high level section of the first clock signal CK is generated as an output signal OUT1 at the output terminal OUT.

At this time, the active section of the start signal ST has a phase about 1/2 cycles ahead of the high level section of the first clock signal CK. The tip of the output signal OUT1 is delayed by a predetermined time from the start of the start signal ST.

This delay characteristic is such that the capacitor C of the pull-up driving unit 152 begins to be charged through the second NMOS transistor NT2 at the front end of the start signal ST, and the charging voltage of the capacitor C is increased. After the first NMOS transistor NT1 is charged above the gate-to-gate threshold voltage of the first NMOS transistor NT1, the first NMOS transistor NT1 is turned on, and the high level section of the first clock signal CK becomes the output terminal OUT. Because it appears.

When the high level section of the clock signal starts to appear on the output terminal OUT, the output voltage is bootstraped to the capacitor C so that the gate voltage of the first NMOS transistor NT1 rises above the turn-on voltage. Done. Accordingly, the first NMOS transistor NT1 maintains a full conduction state.

Subsequently, when the output signal of the next stage provided to the control terminal CT rises to the turn-on voltage, the third NMOS transistor NT3 is turned on. In this case, the first NMOS transistor NT1 is turned off by the potential at the node N being lowered to the power supply voltage VSS. Therefore, the output terminal OUT goes down from the turn-on voltage to the power supply voltage VSS.

Even when the output signal of the next stage applied to the control terminal CT is lowered to the low level and the transistor NT3 is turned off, the first NMOS transistor NT1 until the turn-on voltage is applied to the input terminal IN. ) Will always be turned off.

As shown in FIG. 6, the stages are operated by the above-described operation, so that output signals OUT1 to OUT4 are stably generated sequentially.

As described above, in the embodiment of the present invention, the number of transistors used in each stage of the shift register is minimized, and the number of the second external connection terminals 192 connected to the gate driving circuit 150 is reduced. As a result, an area occupied by the shift register in the liquid crystal display panel 110 may be reduced, and reliability may be increased.

7 is a plan view specifically showing a liquid crystal display panel according to another exemplary embodiment of the present invention. However, in describing FIG. 7, the same reference numerals are given to the same components as in FIG. 3, and the description of the components is omitted.

Referring to FIG. 7, the liquid crystal display panel 110 includes a display area A for displaying an image and peripheral areas B, C, and D of the display area A. FIG. The display area A is an area where the display cell array circuit is formed by a TFT process. The peripheral regions B, C, and D may include a first region B in which one end of m data lines DLm extends, a second region B in which one end of n gate lines extends, and the n pieces of data lines DLm. The other ends of the gate lines are divided into a third region D extending. Here, 'n' is an even number.

The data driving chip 140 and the first external connection terminal 191 are formed in the first region B, and one end of the flexible circuit board 190 is attached to the first external connection terminal 191. The other end of the flexible circuit board 190 is attached to the integrated printed circuit board (not shown).

In the second region C, a first gate driving circuit 160 for sequentially driving odd-numbered gate lines GLn-1 among the n gate lines is formed by a TFT process, and the third In the region D, a second gate driving circuit 170 for sequentially driving even-numbered gate lines GLn among the n gate lines is formed by a TFT process. That is, the first and second gate driving circuits 160 and 170 are symmetrically disposed on the left and right sides of the liquid crystal display panel 110, respectively. The first gate driving circuit 160 is connected to the second external connection terminal 193 connected to the flexible circuit board 190, and the second gate driving circuit 170 is connected to the flexible circuit board 190. It is connected to the third external connection terminal 194.

8 is a diagram illustrating in detail the first and second gate driving circuits illustrated in FIG. 7, and FIG. 9 is a timing diagram of each stage of the shift register illustrated in FIG. 8.

Referring to FIG. 8. The first gate driving circuit 160 includes one first shift register, and the second gate driving circuit 170 includes one second shift register.

The first gate driving circuit 160 includes three terminals of a start signal input terminal ST, a first clock signal input terminal CK, and a power supply voltage terminal VSS. The second gate driving circuit 170 includes two terminals of a second clock signal input terminal CKB and a power supply voltage terminal VSS.

The first gate driving circuit 160 is disposed in the left peripheral area of the display area A, in which the odd-numbered gate lines GLn-1 extend, that is, the second area C, and each of the output terminals OUT. Is composed of a plurality of shift registers SRC1 to SRCn + 1 connected thereto. The second gate driving circuit 170 is disposed in the right peripheral area of the display area A, in which the even-numbered gate lines GLn extend, that is, the third area D, and each of the output terminals OUT is provided. Consists of a plurality of connected shift registers SRC2 to SRCn.

The output of the odd-numbered shift register SRCn-1 is disposed across the display area A via the odd-numbered gate line GLn-1, and then is input to the input terminal IN of the even-numbered shift resist SRCn. At the same time, a control signal is provided to the control terminal CT of the previous even shift register SRCn. Similarly, the output signal of the even-numbered shift register SRCn is provided as an input signal to the input terminal IN of the next odd-numbered shift register SRCn + 1, and at the same time, the control of the previous odd-numbered shift register SRCn-1 is performed. It is provided as a control signal to the terminal CT.

The last odd shift register SRCn + 1 is a dummy register and is added to provide a control signal to the control terminal CT of the last even shift register SRCn.

Referring to FIG. 9, the odd-numbered gate lines GLn-1 and the even-numbered gate lines GLn are sequentially shifted by the start signal ST, and thus the first and second clock signals CK and CKB. It can be seen that they are scanned while being alternately active in synchronization with each other.

The odd-numbered pixels of the plurality of pixels forming one horizontal line are driven by the corresponding odd-numbered gate line GLn-1, and the even-numbered pixels are driven by the corresponding even-numbered gate line GLn.

According to the present invention, a gate driving circuit integrated on a liquid crystal display panel and sequentially applying scan pulses to a plurality of gate lines includes one shift register. The shift register provides a power supply voltage to the output terminal in response to a pull-up part for providing a clock signal to the gate line, a pull-up driver for driving the pull-up part in response to an output signal of a previous stage, and an output signal of a next stage. It consists of a pull-down section for.

Accordingly, the liquid crystal display device can secure reliability by minimizing the number of transistors used in the shift register and reducing the number of external connection terminals, thereby minimizing size and power consumption.

In the liquid crystal display according to the present invention, first and second gate driving circuits are formed in left and right peripheral regions of the liquid crystal display panel. In this case, the first gate driving circuit drives odd-numbered gate lines, and the second gate driving circuit drives even-numbered gate lines. Therefore, the liquid crystal display device may be formed symmetrically.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

Claims (9)

In the shift register comprising a plurality of stages are cascaded, each stage includes an input terminal, an output terminal, a control terminal and a clock signal input terminal, The odd-numbered stages of the shift register are provided with a first clock signal, and the even-numbered stages are provided with a second clock signal whose phase is inverted from the first clock signal. Each stage Pull-up means for providing said first clock signal or said second clock signal provided from said clock signal input terminal to said output terminal; A pull-up driving means connected to an input node of the pull-up means and turning on the pull-up means in response to a first output signal of a previous stage provided to the input terminal; And And a pull-down means connected to an input node of the pull-up means for providing a power supply voltage to the output terminal in response to a second output signal of a next stage provided to the control terminal. According to claim 1, wherein the pull-up driving means, A first transistor having a drain and a gate connected to the input terminal and a source connected to an input node of the pull-up means; And And a capacitor connected between the input node and the output terminal. The method of claim 1, wherein the pull-down means, And a second transistor connected to an input node of the pull-up means, a gate connected to the control terminal, and a source connected to a power supply voltage terminal. The shift register according to claim 1, wherein a start signal is provided to an input terminal of the first stage. The method of claim 1, wherein the shift register, And a dummy stage for providing a second output signal of the next stage to the control terminal of the last stage. And a display cell array circuit, a data driving circuit, and a gate driving circuit formed on the transparent substrate, wherein the display cell array circuit includes a plurality of data lines and a plurality of gate lines, and each display cell circuit includes corresponding data and In a liquid crystal display device connected to a pair of gate lines, The gate driving circuit includes a plurality of stages in which a plurality of stages are cascade-connected, each stage includes a shift register including an input terminal, an output terminal, a control terminal, and a clock signal input terminal, and a first stage of odd numbered stages of the shift register. A clock signal is provided, and even-numbered stages are provided with a second clock signal whose phase is inverted from the first clock signal. Each stage Pull-up means for providing said first clock signal or said second clock signal provided from said clock signal input terminal to said output terminal; A pull-up driving means connected to an input node of the pull-up means and for turning on the pull-up means in response to a first output signal of a previous stage provided from the input terminal; And And pull-down means connected to an input node of the pull-up means for providing a power supply voltage to the output terminal in response to a second output signal of a next stage provided from the control terminal. The terminal of claim 6, wherein the external connection terminal connected to the gate driving circuit comprises four terminals of a first clock signal input terminal, a second clock signal input terminal, a start signal input terminal, and a power supply voltage input terminal. LCD display device. 7. The liquid crystal display device according to claim 6, wherein the transistors of the display cell array circuit, the data driving circuit, and the gate driving circuit are composed of a-Si NMOS TFTs. The gate driving circuit of claim 6, wherein the gate driving circuit is disposed in a left peripheral region of the display cell array circuit to drive odd-numbered gate lines among the plurality of gate lines by the first clock signal. And a second gate driving circuit disposed in a right peripheral region of the display cell array circuit to drive even-numbered gate lines of the plurality of gate lines by the second clock signal.

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