KR20000026582A - Shift register circuit - Google Patents

Abstract

PURPOSE: A shift register circuit to drive the liquid crystal cell in a single type driving circuit to drive a pixel row is provided to prevent circuit characteristics from being changed by a variation of threshold voltage and being degraded by over current. CONSTITUTION: A first NMOS transistor(T1) is connected among an input scanning pulse supply line(gi-1), a first node(P1) and a fourth node(P4). A second NMOS transistor(T2) is connected among the first node(P1), the second node(P2) and a base voltage line(VSS). A third NMOS transistor(T3) is connected among a supply voltage line(VDD), a third clock signal line(C3) and the second node(P2). A fourth NMOS transistor(T4) is connected among the second node(P2), the fourth node(P4) and the base voltage line(VSS). A capacitor(CAP) is connected among the third node(P3) and an output line(14i). A fifth NMOS transistor(T5) is connected among the third node(P3), a first clock signal line(C1) and the output line(14i). A sixth NMOS transistor(T6) is connected among the second node(P2), the output line(14i) and the base voltage line(VSS).

Description

A shift register circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for an active matrix display device, and more particularly to a shift register for driving a liquid crystal cell in a built-in driving circuit for driving a pixel row of a liquid crystal display device.

Conventional liquid crystal display devices used as display devices of televisions and computers have a liquid crystal matrix in which liquid crystal cells are arranged at intersections of data lines and select lines, respectively. These select lines are selected by the shift register as horizontal lines (row lines) of the liquid crystal matrix. A typical shift register is shown in Fig. The shift registers are connected in a dependent manner and n stages (2 ₁ to 2 _n ) connected respectively to n row lines (ROW ₁ to ROW _n ) via respective output lines (4 ₁ to 4 _n ) Respectively. A first stage _(21), the scanning pulse (SP) are input to the second to n-th stages (2 ₂ to 2 _n) I am the output signal (g ₁ to g _n-1) of the previous stage, and three clock signals The row lines ROWi connected to the pixel column are selected by two of the clock signals C1 to C3. Each stage 2 ₁ to 2 _n includes a fifth NMOS transistor T5 for supplying a voltage signal of high logic to the output line 4i as shown in Fig. 2, And a sixth NMOS transistor T6 for supplying a voltage signal of the second NMOS transistor T6. If from the preceding stage (2 _i-1) applied to the i-1 first row line input signal (g _i-1) at a high level, the first NMOS transistor 4 and the (T1, T4) are turned on. 3, the high-level third clock signal C3 is supplied to the third NMOS transistor T3 in synchronization with the ( _i-1 ) -th row line input signal _gi-1 , The transistor T3 is turned on. The third and fourth NMOS transistors T3 and T4 are ratioed logic and when the voltage on the second node P2 is low level when the third and fourth NMOS transistors T3 and T4 are turned on simultaneously So that the resistance ratio of the third and fourth NMOS transistors T3 and T4 is set. Therefore, when the ( _i-1 ) th row line input signal g _i-1 is applied, the voltage on the second node P2 becomes low. At this time, the second and sixth NMOS transistors T2 and T6 are turned off as the voltage on the second node P2 becomes low level. The supply voltage VDD is charged to a high level because the first NMOS transistor T1 is turned on and the second NMOS transistor T2 is turned off. When the voltage on the first node P1 is charged to a high level, the fifth NMOS transistor T5 is turned on since a voltage equal to or higher than the threshold voltage is supplied to its gate. At this time, since the first clock signal C1 maintains the low level, the low level voltage is supplied to the output line 4i.

With the voltage on the first node P1 at the high level, the first clock signal C1 is supplied to the drain of the fifth NMOS transistor T5 to the high level. Then, since the fifth NMOS transistor T5 is kept turned on, the voltage Vout on the output line 4i starts to be charged to a high level. At this time, the voltage on the first node P1 is equal to the gate-to-source capacitance Cgs of the fifth NMOS transistor T5 connected between the output line 4i and the first node P1, To be charged to a higher level. Thus, the high-level voltage of the first clock signal C1 can be supplied to the output line 4i with little loss. Such a bootstrap method is used to compensate for a voltage loss due to a threshold voltage in a circuit including an NMOS transistor.

When the first clock signal C1 changes to the low level, the fifth NMOS transistor T5 maintains the turned-on state, so that the voltage Vout on the output line 4i changes to the low level.

When the ( _i-1 ) -th row line input signal _gi-1 is applied to the gates of the first and fourth NMOS transistors T1 and T4 as a low level, the first and fourth NMOS transistors T1 and T4 turn So that the voltage on the first node P1 is changed to the low level. At this time, the third clock signal C3 is applied at the high level to the gate of the third NMOS transistor T3 to turn on the third NMOS transistor T3. Then, the supply voltage VDD is applied to the second node P2, so that the second node P2 starts to be charged to a high level. When a voltage equal to or higher than the threshold voltage is applied to the gate of the sixth NMOS transistor T6 via the second node P2 The sixth NMOS transistor T6 is turned on. The sixth NMOS transistor T6 is turned on so that the voltage charged on the output line 4i is discharged to the ground voltage VSS so that the voltage on the low line ROWi maintains the low level.

However, in the conventional shift register circuit, the resistance ratio of the third and fourth NMOS transistors T3 and T4 used as the reticle logic must be set accurately in order for the shift register to operate normally. In other words, when the third clock signal C3 and the ( _i-1 ) -th row line input signal _gi-1 are simultaneously high level and applied to the third and fourth NMOS transistors T3 and T4, The channel width of the fourth NMOS transistor T4 must be approximately 10 times larger than that of the third NMOS transistor T3 in order to make the voltage on the second node P2 low level. Here, if the device characteristics are uneven, the current ratio of the third and fourth NMOS transistors T3 and T4 changes. In this case, the shift register can not operate normally. When the third and fourth NMOS transistors T3 and T4 are simultaneously turned on by the third clock signal C3 and the ( _i-1 ) th row line input signal _gi-1 , the third and fourth NMOS transistors T3, and T4, the characteristics of the device due to the overcurrent of the direct current (DC) tend to deteriorate. When the voltage of the first node P1 is at a high level and the first clock signal C1 is changed to a high level, the potential on the first node P1, which is a floating node, The degree of the rise is given by the following equation (1), so that the potential on the first node P1 changes according to the change of the parasitic capacitance, which makes it difficult to accurately design the circuit characteristics.

Here,? Vp1 and? Vout represent a voltage variation amount on the first node P1 and a voltage variation amount on the output line 4i, respectively, and C _L and C _OX are respectively the parasitic capacitance on the first node P1 )_____to be.

In addition to these problems, another problem of the conventional shift register circuit is that when the potential on the output line 4i is changed to the high level, the capacitance coupling by the gate and the drain capacitance component in the sixth NMOS transistor T6 The potential on the second node P2 rises and the output voltage Vout (i.e., the voltage on the low line) can be distorted.

It is therefore an object of the present invention to provide a shift register circuit which prevents variations in circuit characteristics due to variations in threshold voltage and the like.

It is another object of the present invention to provide a shift register circuit which prevents deterioration of circuit characteristics due to an overcurrent.

It is still another object of the present invention to provide a shift register circuit which minimizes a potential change on a bootstrap node due to a threshold voltage change.

1 schematically shows a conventional shift register.

2 is a detailed circuit diagram of the stage shown in Fig.

3 is an input / output waveform diagram of the stage shown in Fig.

4 is a circuit diagram showing in detail an output portion of the stage shown in Fig.

5 illustrates a shift register according to a first embodiment of the present invention.

FIG. 6 is a detailed circuit diagram of the stage shown in FIG. 5; FIG.

7 is an input / output waveform diagram of the stage shown in Fig.

8 is a diagram showing a stage of a shift register according to a second embodiment of the present invention;

9 is a view showing a stage of a shift register according to a third embodiment of the present invention;

10 is a voltage waveform diagram showing that the polling time of the output voltage becomes longer.

Fig. 11 is a voltage waveform diagram showing voltage changes on the first and second nodes with and without the capacitor C _L 2 shown in Fig. 6; Fig.

DESCRIPTION OF THE EMBODIMENTS

2 ₂ to 2 _n , 12 ₂ to 12 _n :

4 ₁ to 4 _n , 4 _i , 14 ₁ to 14 _n , 14 _i : output lines

T1 to T7: NMOS transistors

In order to achieve the above objects, a stage of a shift register circuit according to the present invention includes a first input electrode to which a first clock signal delayed in phase from an input signal is input, a first output electrode connected to a row line, Down transistor having a second input electrode to which a low potential voltage is supplied, a second output electrode connected to a low line, and a second control electrode, and a pull- An input circuit for generating a first control signal supplied to one control electrode and generating a second control signal supplied to the second control electrode in response to a second clock signal delayed in phase with respect to the first clock signal, And a boosting means for boosting the first control signal.

The stages of the shift register circuit according to the present invention include a pull-up transistor having a first input electrode to which a first clock signal delayed in phase than an input signal is input, a first output electrode connected to the row line, and a first control electrode, An output circuit part including a pull-down transistor having a second input electrode to which a potential voltage is supplied, a second output electrode connected to the row line, and a second control electrode; An input circuit for generating a first control signal and generating a second control signal to be supplied to a second control electrode in response to a second clock signal delayed in phase with respect to the first clock signal; And discharging means for discharging the second control signal during a period in which the first control signal is enabled.

The stages of the shift register circuit according to the present invention include a pull-up transistor having a first input electrode to which a first clock signal delayed in phase than an input signal is input, a first output electrode connected to the row line, and a first control electrode, An output circuit part including a pull-down transistor having a second input electrode to which a potential voltage is supplied, a second output electrode connected to the row line, and a second control electrode; and an output circuit part supplied to the first control electrode in response to the input signal An input circuit for generating a first control signal to generate a first control signal and a second control signal to be supplied to a second control electrode in response to a second clock signal delayed in phase with respect to the first clock signal, Step-up means for step-up, and acceleration means for accelerating the discharge speed of the row line.

Other objects and advantages of the present invention will become apparent from the following detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 5 to 10.

5 shows a shift register according to the first embodiment of the present invention.

Referring to FIG. 5, the shift register of the present invention has n stages 12 ₁ to 12 _n that are cascade-connected to a scanning pulse input line to drive an m × n pixel array. Output lines 14 ₁ to 14 _{n of} these n stages 12 ₁ to 12 _n are connected to n row lines ROW 1 to ROWn included in the pixel array, respectively. A first stage (12 _1), the scanning pulse (Sp) is supplied and the output signal (g ₁ to g _n-1) of the first to the first n-1 stages (12 ₁ to 12 _n-1) are respectively the rear end of the And are supplied as scanning pulses to the stages. The input signals of the shift register circuit, that is, the scanning pulse SP, the first to fourth clock signals C1 and C4, the supply voltage VDD and the ground voltage VSS, . Each of the stages 12 ₁ to 12 _n includes a first NMOS transistor 12 connected between an input scanning pulse supply line g _i-1 , a first node P 1 and a fourth node P 4, A second NMOS transistor T2 connected between the first node P1 and the second node P2 and the base voltage line VSS and a second NMOS transistor T2 connected between the supply voltage line VDD, A third NMOS transistor T3 connected between the third node C3 and the second node P2 and a fourth NMOS transistor T3 connected between the second node P2 and the fourth node P4 and the base- A capacitor CAP connected between the third node P3 and the output line 14i and a capacitor CAP connected between the third node P3 and the first clock signal line C1 and the output line 14i, And a sixth NMOS transistor T6 connected between the second node P2, the output line 14i and the base low voltage line VSS.

The first and fourth NMOS transistors T1 and T4 are turned on when a high level i-1 th row line input signal g _i-1 is applied from the previous stage 12 _i-1 . The voltage on the first node P1 is changed to the high level by the supply voltage VDD supplied as the first NMOS transistor T1 is turned on and the voltage on the second node P2 is changed to the high level by the fourth NMOS transistor T4 are turned on and discharged to the base low voltage VSS to be low level. 7, the third clock signal C3 maintains a low level in a period in which the ( _i-1 ) -th row line input signal _gi-1 maintains a high level. Thus, the i-1 th row line input signal g _i-1 and the third clock signal C3 are supplied to the fourth NMOS transistor T4 and the third NMOS transistor T3, respectively, The voltage level on the second node P2 is determined regardless of the resistance ratio of the third and fourth NMOS transistors T3 and T4. Therefore, even when the device characteristics of the third and fourth NMOS transistors T3 and T4 are not uniform, changes in circuit characteristics are not so large as to make normal operation impossible, and the third and fourth NMOS transistors T3 and T4 The current flows only during a period of time during which the signal changes, so that deterioration of device characteristics can be prevented by the overcurrent caused by the direct current.

When the voltage on the first node P1 becomes a high level, the fifth NMOS transistor T5 is turned on. At this time, the first clock signal C1 is supplied to the drain of the fifth NMOS transistor T5 as a high level, and the voltage on the output line 14i starts to be charged to a high level. The capacitor CAP boosts the voltage on the first node P1 by the voltage level of the first clock signal C1 when the high level first clock signal C1 is supplied to the output line 14i. As the gate voltage is increased by the capacitor CAP, the fifth NMOS transistor T5 quickly transfers the first clock signal C1 of high level to the output line 14i without attenuation. Thus, the voltage loss due to the threshold voltage of the fifth NMOS transistor T5 is minimized. Meanwhile, the capacitor CAP may be replaced by a parasitic capacitor existing in the fifth NMOS transistor T5.

When the first clock signal C1 changes to the low level, the fifth NMOS transistor T5 maintains the turned-on state, so that the voltage Vout on the output line 14i changes to the low level.

Since the third clock signal C3 is supplied at the high level to the gate of the third NMOS transistor T3, the third NMOS transistor T3 is turned on and the potential on the second node P2 is changed to the high level. The second and sixth NMOS transistors T2 and T6 are turned on because a high level voltage is supplied to their gates through the second node P2 so that the voltage on the first node P1 is set to the low voltage VSS and keeps the voltage on the output line 14i at a low level. On the other hand, when the voltage on the first node P1 is at a high level and the first clock signal C1 is input to the gate of the fifth NMOS transistor T5 at a high level, the voltage on the first node P1 further rises A capacitor C _L 1 is provided between the first node P 1 and the base voltage source VSS and a capacitor C _L2 is provided between the second node P 2 and the base voltage source VSS. It is possible to accurately design the voltage change amount? Vp1 on the first node P1 as can be seen from the equation (2).

Here, it is preferable that the three capacitors (CAP, C _L 1, C _L 2) are about 0.1 pF to 10 pF.

In addition, by providing a capacitor C _L 2 between the second node P 2 and the base voltage source VSS, the change of the voltage on the second node is minimized when the output voltage Vout changes, Thereby suppressing the voltage change on the second node P2. This is the first and the first and the voltage on the second node when the first did 2 be a voltage waveform (P1, P2) and the capacitor (C _L 2) on the node installation of when Fig. 11 is a capacitor (C _L 2) installed in Can be known through the waveforms P1 'and P2'.

8 shows a stage of a shift register according to a second embodiment of the present invention. In Fig. 8, the waveforms of the input / output signals are the same as in Fig.

8, an i-th stage 12i includes a first NMOS transistor T1 connected between an input scanning pulse supply line _gi-1 and a first node P1, A second NMOS transistor T2 connected between the second node P2 and the base low voltage line VSS and a second NMOS transistor T2 connected between the supply voltage line VDD, A fourth NMOS transistor T4 connected between the first node P1, the second node P2 and the base low voltage line VSS, and a third NMOS transistor T3 connected to the third node P3 And a fifth NMOS transistor T5 connected between the third node P3, the first clock signal line C1, and the output line 24i, and a third node P3 connected between the third node P3 and the output line 24i. And a sixth NMOS transistor T6 connected between the second node P2, the output line 24i and the base low voltage line VSS.

When the high-level i-1 th row line input signal g _i-1 is applied from the previous stage 22 _i-1 , the first NMOS transistor T 1 is turned on and the voltage on the first node P 1 is at the high level . When the voltage on the first node P1 is charged to a high level equal to or higher than the threshold voltage, the fourth NMOS transistors T1 and T4 are turned on to discharge the voltage on the second node P2 to the ground voltage VSS. Accordingly, during the period in which the voltage on the first node P1 maintains the high level (i.e., when the (i-1) th row line input signal maintains the high level), the fourth NMOS transistor T4 is turned on It becomes possible to suppress the voltage fluctuation on the two nodes P2. The second and sixth NMOS transistors T2 and T6 are turned off because the voltage on the second node P2 is at the low level. The third clock signal C3 maintains a low level during a period in which the ( _i-1 ) -th row line input signal _gi-1 is maintained at the high level, so that the third and fourth NMOS transistors T3 and T4 The voltage level on the second node P2 is determined regardless of the resistance ratio. The first clock signal C1 is supplied to the drain of the fifth NMOS transistor T5 as a high level, and the output line 24i is charged to a high level. The capacitor CAP boosts the voltage on the first node P1 by the voltage level of the first clock signal C1 when the high level first clock signal C1 is supplied to the output line 14i.

When the first clock signal C1 changes to the low level, the fifth NMOS transistor T5 maintains the turned-on state, so that the voltage on the output line 14i changes to the low level. Then, since the third clock signal C3 is supplied to the gate of the third NMOS transistor T3 as a high level, the third NMOS transistor T3 is turned on to charge the potential on the second node P2 to a high level, 2 and the sixth NMOS transistors T2 and T6 are turned on. The voltage on the output line 24i is maintained at a low level by turning on the second and sixth NMOS transistors T2 and T6.

9 shows a stage of a shift register according to a third embodiment of the present invention. In Fig. 9, the waveform of the input / output signals is the same as in Fig.

9, the i-th stage 32i includes a first NMOS transistor T1 connected between an input scanning pulse supply line gi _-1 and a first node P1, A second NMOS transistor T2 connected between the second node P2 and the base low voltage line VSS and a second NMOS transistor T2 connected between the supply voltage line VDD, A fourth NMOS transistor T4 connected between the first NMOS transistor T1 and the second node P2 and the base voltage line VSS and a third NMOS transistor T3 connected to the third node And a fifth NMOS transistor T5 connected between the third node P3, the first clock signal line C1 and the output line 34i, and a capacitor CAP connected between the third node P3 and the output line 24i. A sixth NMOS transistor T6 connected between the second node P2, the output line 34i and the base low voltage line VSS, and a sixth NMOS transistor T6 connected between the output line 34i and the base low voltage line VSS. The seventh NMOS transistor (T7) And a.

A high level from the preceding stage _{(32 i-1) i-} 1 first row line input signal (g _i-1) is applied when the first NMOS transistor (T1) is turned on first at a high level the voltage on node (P1) . When the voltage on the first node P1 is charged to a high level equal to or higher than the threshold voltage, the fourth NMOS transistors T1 and T4 are turned on to discharge the voltage on the second node P2 to the ground voltage VSS. Thus, during a period in which the voltage on the first node P1 maintains the high level, the fourth NMOS transistor T4 is turned on, thereby suppressing the voltage fluctuation on the second node P2. The second and sixth NMOS transistors T2 and T6 are turned off because the voltage on the second node P2 is at the low level. The third clock signal C3 maintains a low level during a period in which the ( _i-1 ) -th row line input signal _gi-1 is maintained at the high level, so that the third and fourth NMOS transistors T3 and T4 The voltage level on the second node P2 is determined regardless of the resistance ratio. The first clock signal C1 is supplied to the drain of the fifth NMOS transistor T5 as a high level, and the output line 24i is charged to a high level. The capacitor CAP boosts the voltage on the first node P1 by the voltage level of the first clock signal C1 when the high level first clock signal C1 is supplied to the output line 14i.

When the first clock signal C1 changes to the low level, the fifth NMOS transistor T5 maintains the turned-on state, so that the voltage on the output line 14i changes to the low level. At this time, the gate of the seventh NMOS transistor T7 is supplied with the high-level feedback voltage Vf from the next stage 32i + 1. As a result, the voltage Vout on the output line 34i quickly discharges to the ground voltage VSS. In this case, as shown in FIG. 10, when the falling time of the voltage Vout on the output line 34i becomes longer, the feedback voltage Vf higher than the voltage level on the first node P1 The poling time can be reduced by the seventh NMOS transistor T7 turned on. The voltage V _T5 applied to the gate of the fifth NMOS transistor T5 is lowered when the voltage on the first node P1 is lowered due to the increase of the leakage current of the transistor? The voltage on the output line 34i can be quickly discharged to the ground voltage when the falling time of the voltage Vout on the output line 34i becomes long.

As described above, in the present invention, the circuit configuration is made ratoless with the clock signal of four phases, so that a change in the circuit characteristics due to variations in the device mobility threshold voltage and the like is minimized. Accordingly, current flows only during a signal transition period, so that power consumption is reduced and deterioration of the device characteristics due to the overcurrent of the DC current is prevented. Further, in the present invention, a separate capacitor is provided between the output node and the bootstrap node, and a capacitor is provided between the DC power supply and the bootstrap node, thereby stabilizing the operation of the circuit by reducing the potential change of the bootstrap node.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

Claims (15)

A high potential voltage supply, a low potential voltage supply, and means for generating phase delayed clock signals, and connected to one row line, respectively, so that the output signal of the previous stage as a scanning signal is supplied as an input signal, In a shift register composed of a plurality of stages, Wherein the stages include a pull-up transistor having a first input electrode to which a first clock signal delayed in phase with the input signal is input, a first output electrode connected to the row line, and a first control electrode, An output circuit part including a pull-down transistor having a second input electrode, a second output electrode connected to the row line, and a second control electrode; And a second control signal which is supplied to the second control electrode in response to a second clock signal delayed in phase with respect to the first clock signal, An input circuit for generating two control signals, And a boosting means for boosting the first control signal. The method according to claim 1, Wherein the input circuit section comprises: A first transistor having a third input electrode to which the input signal is supplied, a third output electrode connected to the first control electrode, and a third control electrode connected to the third input electrode, And a second transistor having a fourth input electrode connected to the low potential voltage supply source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode Shift register circuit. The method according to claim 1, Wherein the input circuit section comprises: A third transistor having a fifth input electrode connected to the high potential voltage supply source, a fifth output electrode connected to the second control electrode, and a fifth control electrode receiving the second clock signal, And a fourth transistor having a sixth input electrode connected to the low potential voltage supply source, a sixth output electrode connected to the second control electrode, and a sixth control electrode supplied with the input signal. Shift register circuit. The method according to claim 1, And the boosting means includes a first capacitor connected to the row line and the second control electrode. The method according to claim 1, A second capacitor connected between the first control electrode and the low potential voltage supply source, And a third capacitor connected between the second control electrode and the low potential voltage supply source. A high potential voltage supply, a low potential voltage supply, and means for generating phase delayed clock signals, and connected to one row line, respectively, so that the output signal of the previous stage as a scanning signal is supplied as an input signal, In a shift register composed of a plurality of stages, Wherein the stages include a pull-up transistor having a first input electrode to which a first clock signal delayed in phase with the input signal is input, a first output electrode connected to the row line, and a first control electrode, An output circuit part including a pull-down transistor having a second input electrode, a second output electrode connected to the row line, and a second control electrode; And a second control signal which is supplied to the second control electrode in response to a second clock signal delayed in phase with respect to the first clock signal, An input circuit for generating two control signals, A boosting means for boosting the first control signal, And a discharging means for discharging the second control signal during a period in which the first control signal is enabled. The method according to claim 6, Wherein the input circuit section comprises: A first transistor having a third input electrode to which the input signal is supplied, a third output electrode connected to the first control electrode, and a third control electrode connected to the third input electrode, And a second transistor having a fourth input electrode connected to the low potential voltage supply source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode Shift register circuit. The method according to claim 6, Wherein the input circuit section comprises: And a third transistor having a fifth input electrode connected to the high potential voltage supply source, a fifth output electrode connected to the second control electrode, and a fifth control electrode receiving the second clock signal . The method according to claim 6, Wherein said voltage step-up means comprises a capacitor connected to said row line and said second control electrode. The method according to claim 6, The discharging means includes a transistor having a sixth input electrode connected to the low potential voltage supply source, a sixth output electrode connected to the second control electrode, and a sixth control electrode connected to the first control electrode . A high potential voltage supply, a low potential voltage supply, and means for generating phase delayed clock signals, and connected to one row line, respectively, so that the output signal of the previous stage as a scanning signal is supplied as an input signal, In a shift register composed of a plurality of stages, Wherein the stages include a pull-up transistor having a first input electrode to which a first clock signal delayed in phase with the input signal is input, a first output electrode connected to the row line, and a first control electrode, An output circuit part including a pull-down transistor having a second input electrode, a second output electrode connected to the row line, and a second control electrode; And a second control signal which is supplied to the second control electrode in response to a second clock signal delayed in phase with respect to the first clock signal, An input circuit for generating two control signals, A boosting means for boosting the first control signal, Further comprising an acceleration means for accelerating a discharge speed of the row line. 12. The method of claim 11, Wherein the input circuit section comprises: A first transistor having a third input electrode to which the input signal is supplied, a third output electrode connected to the first control electrode, and a third control electrode connected to the third input electrode, And a second transistor having a fourth input electrode connected to the low potential voltage supply source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode Shift register circuit. 12. The method of claim 11, Wherein the input circuit section comprises: A third transistor having a fifth input electrode connected to the high potential voltage supply source, a fifth output electrode connected to the second control electrode, and a fifth control electrode receiving the second clock signal, And a fourth transistor having a sixth input electrode connected to the low potential voltage supply source, a sixth output electrode connected to the second control electrode, and a sixth control electrode supplied with the input signal. Shift register circuit. 12. The method of claim 11, Wherein said voltage step-up means comprises a capacitor connected to said row line and said second control electrode. 12. The method of claim 11, The acceleration means includes a transistor having a seventh input electrode connected to the low potential voltage supply source, an output electrode connected to the low line, and a seventh control electrode connected to the output line of the next stage, Register circuit.