KR100973821B1 - Driving apparatus for display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a display device, and more particularly, to a driving device of a display device capable of reducing power consumption by reducing a through current using a bootstrapping method. A driving device of a display device according to an aspect of the present invention includes a gate driver including a plurality of pixels including a switching element and a plurality of shift registers arranged in a row, each shift register having a phase. Two of the first to fourth clock signals which are different from each other are input, and each of the shift registers includes transistors for charging and discharging and first to fourth switching elements connected thereto. The transistor may include a first terminal selectively connected to a first voltage or a second voltage, a second terminal selectively connected to the first clock signal, and a third terminal connected to the second terminal by wiring. Include.

In this way, the use of five transistors of the same type not only reduces the through current, but also simplifies the circuit, reducing manufacturing costs and increasing process yield.

Gate Driver, Shift Register, Clock Signal, Transistor, PMOS, NMOS, Charge, Discharge

Description

Drive device for display device {DRIVING APPARATUS FOR DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

4 is a detailed circuit diagram of a shift register of a gate driver according to an exemplary embodiment of the present invention.

FIG. 5 is a timing diagram of a clock signal having an duty ratio of 25% and an input and output signal shown in FIG. 4.

FIG. 6 is a timing diagram of a clock signal having an duty ratio of 50% and an input and output signal shown in FIG.

The present invention relates to a driving device of a display device.

A liquid crystal display, an EL (electro luminescence) display, or the like includes a plurality of pixels arranged in a matrix form. Each pixel includes a switching element that selectively receives an image signal, and a three-terminal element such as a MOS transistor is mainly used as the switching element. The display device also includes a plurality of gate lines and a plurality of data lines connected to the switching elements, each gate line delivering a gate-on voltage for turning on the switching elements, respectively, and each data line through each turned-on switching element for each pixel. Pass the image signal on.

The display device also includes a gate driver for applying a gate-on voltage to the gate line, a data driver for applying an image signal to the data line, and a signal controller for controlling the gate driver.

The gate driver starts outputting the gate-on voltage according to the vertical synchronization start signal from the signal controller, and sequentially applies the gate-on voltage to the gate lines arranged in a row. In order to output the gate-on voltage in this manner, the conventional gate driver includes a plurality of shift registers connected to the gate lines, respectively. The first shift register starts the output of the gate-on voltage in synchronization with the vertical synchronization start signal and the clock signal, and the second shift register starts the output of the gate-on voltage in synchronization with the clock signal and the output voltage of the front end shift register.

Thin film transistors that form shift registers often use only N-type or P-type instead of complementary to reduce process cost and improve yield. At this time, since the shift register is basically composed of an inverter, a through current flows between the positive driving voltage and the negative driving voltage, so that power consumption is very high.

Accordingly, an object of the present invention is to provide a driving device of a display device capable of reducing power consumption.

According to an aspect of the present invention, a driving device of a display device includes a gate driver including a plurality of pixels including a switching element and a plurality of shift registers arranged in a row. Each shift register receives two of the first to fourth clock signals having different phases, and each shift register includes a transistor for charging and discharging and first to fourth switching elements connected thereto. The transistor includes a first terminal selectively connected to a first voltage or a second voltage, a second terminal selectively connected to the first clock signal, and a third terminal wired to the second terminal. do.

In this case, the first switching device includes first and second terminals connected to the first voltage, and a third terminal connected to the first terminal of the transistor, wherein the second switching device includes the first terminal. And a third terminal connected to the second clock signal, a second terminal connected to the first terminal of the transistor, and a third terminal connected to the second voltage, wherein the third switching device comprises a first terminal of the transistor. A first terminal connected to a first terminal, a second terminal connected to the first clock signal, and a third terminal connected to a second terminal of the transistor, wherein the fourth switching device includes the second switching The display device may include a first terminal connected to a first terminal of the device, a second terminal connected to a third terminal of the transistor, and a third terminal connected to the second voltage.

In addition, the duty ratio of the first to second clock signals is preferably 50% or less.

Meanwhile, the first and third switching devices are turned on at a first time point, the first switching device is turned off at a second time point, and the second and fourth switching devices are turned on at a third time point. desirable. In addition, the transistor starts charging at the first time point, enters a floating state at the second time point, and starts discharging at the third time point.

The shift register may further include an output terminal connected between the third terminal of the transistor and the second terminal of the fourth switching element, and the output terminal may be connected to the first clock signal at the first and second time points. And may be connected to the second voltage at the third time point.

In this case, the first to fourth clock signals have a voltage range equal to a ground voltage and a voltage range lower than the ground voltage, and the second voltage is equal to the ground voltage. The first to fourth switching elements may be PMOS transistors.

The transistors and the first to fourth switching elements when the first to fourth clock signals have a voltage range equal to a ground voltage and a voltage range higher than the ground voltage, and the second voltage is lower than the ground voltage. May be an NMOS transistor.

On the other hand, it is preferable that the two clock signals input to the shift register among the first to fourth clock signals have a phase difference of 90 ° to each other.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver And a gray voltage generator 800 connected to the signal 500 and a signal controller 600 for controlling the gray voltage generator 800.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. It includes the line (D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , a liquid crystal capacitor C _LC , and a storage capacitor C _S t connected thereto. ). The storage capacitor (C _S t) may be omitted, if necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. and an output terminal is connected to the LC capacitor (C _LC) and the storage capacitor (C _S t).

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. Functions as a genetic material The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _S t is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and the predetermined signal line such as the common voltage V _com is provided on the separate signal line. Is applied. However, the storage capacitor C _S t may be formed by the pixel electrode 190 overlapping the front gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n and consists of a plurality of shift registers.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. It consists of a circuit.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 generates a gate control signal CONt1, a data control signal CONt2, and the like based on the input control signal, and adjusts the image signals R, G, and B to match the operating conditions of the liquid crystal panel assembly 300. After appropriately processing, the gate control signal CONt1 is sent to the gate driver 400, and the data control signal CONt2 and the processed image signals R ', G', and B 'are sent to the data driver 500.

The gate control signal CONt1 includes a vertical synchronization start signal StV indicating the start of the output of the gate on pulse (gate on voltage section), a gate clock signal CPV controlling the output timing of the gate on pulse, and a gate on pulse. An output enable signal OE or the like that defines a width.

The data control signal CONt2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal StH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives and shifts image data R ', G', and B 'corresponding to one row of pixels according to the data control signal CONt2 from the signal controller 600, and generates a gray voltage. The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the unit 800. Then, it is applied to the corresponding data line D ₁ -D _m .

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONt1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. When the switching element Q connected to the () is turned on, the data voltage applied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q. The operation of the shift register constituting the gate driver 400 will be described later in detail.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The liquid crystal molecules vary in arrangement depending on the magnitude of the pixel voltage. As a result, the polarization of light passing through the liquid crystal layer 3 changes. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

After one horizontal period (or “1H”) (one period of the horizontal sync signal H _sync , the data enable signal DE, and the gate clock CPV), the data driver 500 and the gate driver 400 are next. The same operation is repeated for the pixels in the row. In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels.

Next, the structure and operation of the gate driver 400 will be described in more detail with reference to FIGS. 3 to 6.

3 is a block diagram of a gate driver 400 according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the gate driver 400 includes a plurality of shift registers 410 arranged in a line, and the shift registers 410 are formed in the same process as the switching elements of the pixel and integrated on the same substrate. Can be.                     

Each shift register 410 generates a gate output Gout (N) based on the front gate output Gout (N-1) and the clock signals Clk1-Clk4. The neighboring shift registers 410 receive clock signals with the same phase and clock signals 180 degrees out of phase, respectively. Each clock signal Clk1-Clk4 has a period of 4H and a duty ratio (ratio of low periods to the entire period) can be 25% or 50%. Here, when the switching element is polysilicon, the high value of the clock signals Clk1-Clk4 may be 0V and the low value may be -10V.

4 is a detailed circuit diagram of a shift register of a gate driver according to an exemplary embodiment of the present invention, and FIGS. 5 and 6 are timing diagrams of a clock signal and an input and output signal shown in FIG. 4. In FIG. 5, the duty ratio of the clock signal is 25%, and in FIG. 6, the duty ratio of the clock signal is 50%.

The shift register 410 shown in FIG. 4 is the (N + 1) th shift register, and the front gate output Gout (N) and the clock signals Clk2 and Clk3 are input.

The shift register 410 according to the embodiment of the present invention includes a plurality of PMOS transistors M1-M5.

The first and second transistors M1 and M2 are connected between the front gate output Gout (N) and the driving voltage V _DD .

The gate and the drain of the first transistor M1 are connected to each other, and the source thereof is connected to the drain of the second transistor M2. The gate of the second transistor M2 is connected to the clock signal Clk3 and the source is connected to the driving voltage V _DD . Here, as is known, the drain and the source are determined by relative voltage magnitudes. In the case of the PMOS transistor, the smaller side is the drain and the larger side is the source.

Third to fifth transistors are connected between the clock signal Clk2 and the driving voltage V _DD .

The drain of the third transistor M3 is connected to the clock signal Clk2 and the gate is connected to the gate of the fourth transistor M4 and is also connected between the first transistor M1 and the second transistor M2. It is. The source of the third transistor is connected to the drain of the fourth transistor M4. The gate of the fifth transistor M5 is connected to the gate of the second transistor M2 and simultaneously receives the clock signal Clk3, and the source is connected to the driving voltage V _DD .

Here, the fourth transistor M4 serves as a capacitor. The conductive layer is formed under the oxide film (insulating film) by connecting the source and the drain of the fourth transistor with the same wiring as the metal layer. Then, a kind of capacitor is formed between the gate and the conductive layer of the fourth transistor M4. The remaining transistors M1-M3 and M5 serve as ordinary switching elements.

The operation of the shift register 410 will now be described.

The values of the clock signals Clk1-Clk4 and the preceding and current gate output signals Gout (N, Gout (N + 1) are all the same, and the value of the driving voltage V _DD is equal to the high value of the aforementioned signals. Corresponding.

As shown in FIG. 5, the front gate output signal Gout (N) is input at a time t ₁ . Then, since the first transistor M1 is turned on and the second transistor M2 is turned off, a predetermined voltage is transmitted to the third and fourth transistors M3 and M4. Of course, the value transferred is obtained by subtracting the threshold voltage Vth of the first transistor M1. In the above example, if the gate voltage is -10V and the threshold voltage is -1V, the output voltage becomes -9V minus the threshold voltage -1V from the input value -10V, and this value is transferred to the node A.

In this case, the third transistor M3 is turned on to transfer the clock signal Clk2 to the fourth transistor M4. Therefore, the gate output voltage Gout (N + 1) becomes high at time t ₁ .

On the other hand, since the fourth transistor M4 serves as the capacitor described above, the fourth transistor M4 starts to charge a value corresponding to the voltage difference between the signal input to the gate of the fourth transistor M4 and the clock signal Clk2 transferred to the conductive layer. do. This is because the fourth transistor M4 acts as a capacitor while the source and drain are short circuited by wiring.

Subsequently, at a time t ₂ , the gate output voltage Gout (N) is turned high, and the first transistor M1 is turned off. In addition, since the clock signal Clk3 is still high, the second transistor M2 is also turned off. The fourth transistor M4 is then in a floating state to maintain the previously charged voltage. Accordingly, the voltage of the node A is still -9V, the voltage of the conductive layer is 0V, and the potential difference is maintained at 9V so that the third transistor M3 is kept turned on.

Meanwhile, as the clock signal Clk2 becomes low at time t ₂ , the low value is transmitted to the output terminal through the conductive layers of the third transistor M3 and the fourth transistor M4 that are turned on, which is low as shown. Is generated as the gate output voltage Gout (N + 1). At this time, since -10V, which is a low value, is input to the fourth transistor M4, the voltage of the node A drops to -19V. As such, the phenomenon in which the fourth transistor M4 in the floating state falls as much as a new voltage is input is referred to as bootstrapping.

Next, when the clock signal Clk3 becomes low at a time t ₃ , the second and fifth transistors M2 and M5 are turned on. Then, the driving voltage V _DD is transmitted to the node A through the second transistor M2 and to the output terminal through the fifth transistor M5, so that the gate output signal Gout (N + 1) is shown. ] Becomes high. Since the voltage of the node A is also high, the third transistor M3 is turned off.

At this time, the gate voltage of the fourth transistor M4 is the same as that of the conductive layer transferred through the fifth transistor M5. As a result, the fourth transistor M4 starts to discharge and the operation of the shift register 410 is completed.

The next stage shift register 410 generates a gate output voltage [Gout (N + 2)] by repeating the above-described operation while the output Gout (N + 1) of the previous shift register is input at time t ₂ . .

The clock signals Clk1-Clk4 have four different phases with a phase difference of 90 ° and each has a duty ratio of 25% as described above. In contrast, Fig. 6 shows an example in which the duty ratio of the clock signals Clk1-Clk4 is 50%.

Next, an operation in the case where the duty ratio of the clock signal is 50% according to another embodiment of the present invention will be briefly described.

Referring to FIG. 4, the shift register 410 is also an (N + 1) th shift register.

When the gate output voltage Gout (N) of the front end shift register 410 is input at a time t ₁ , the first transistor M1 is turned on to transmit a corresponding signal to the node A. Then, the third transistor M3 is turned on and the fourth transistor M4 starts to charge a voltage corresponding to the voltage difference between the gate voltage and the conductive layer, which is the voltage of the node A. The clock signal Clk2 is transmitted to the output terminal through the third and fourth transistors M3 and M4 so that the gate output voltage [Gout (N + 1)] is kept high.

Then, the clock signal Clk2 becomes low at time t ₂ , and is transferred to the output side through the conductive layers of the third transistor M3 and the fourth transistor M4, so that the gate output voltage [Gout (N + 1)] is obtained. It will go low.

At this time, since the first and second transistors M1 and M2 are turned off, the fourth transistor M4 is in a floating state.

When the clock signal Clk3 becomes low at a time t ₃ , the second and fifth transistors M2 and M5 are turned on to transfer the driving voltage V _DD to the node A and the output side, respectively. At this time, the gate output voltage Gout (N + 1) is turned high and the third transistor M3 is turned off. The fourth transistor M4 starts to discharge while the gate voltage and the conductive layer have the same voltage.

The next stage shift register 410 generates a gate output voltage [Gout (N + 2)] by repeating the above-described operation while the output Gout (N + 1) of the previous shift register is input at time t ₂ . .

On the other hand, the duty ratio of the clock signals Clk1-Clk4 is preferably within 50%.

For example, when the duty ratio is 75%, since the clock signal Clk3 is low at time t ₁ , not only the first, third and fourth transistors M1, M3, and M4 but also the second and fifth transistors ( M2 and M5) are also turned on so that the entire circuit is short-circuited. In this case, the signal line or the power line formed on the glass substrate may be overloaded and the wiring may be broken. Therefore, the duty ratio is preferably within 50%. In other words, less than 50% can have any duty ratio in between.

On the other hand, since the gate and the drain of the first transistor M1 of the input terminal are connected to each other, the number of wirings can be reduced as compared with a method in which the drain is applied with a separate driving voltage.

In addition, by using a 4-phase clock signal having four different phases, the number of transistors constituting the shift register 410 can be reduced even if the number of clock signals increases, thereby simplifying the circuit. have. In addition, the use of one type of MOS transistor can contribute to simplifying the process and improving yield.

Furthermore, since no through current flows except for racing caused by signal delay, power consumption can be reduced.

Here, racing is a kind of short-circuit phenomenon. For example, it may occur when the clock signal Clk2 is delayed at time t ₃ in the circuit shown in FIG. 4 and is still low.

Since the voltage of the fourth transistor M4 does not change instantaneously, it maintains the value before the time t ₃ . As a result, the third transistor M3 remains turned on. When the clock signal Clk3 goes low at a time t ₃ without a delay, a short circuit occurs because the fifth transistor M5 is also turned on and the third transistor M3 is turned on. That is, a through current flows instantaneously from the high driving voltage V _DD side to the low clock signal Clk2 side. At this time, the output is unstable, so that it cannot be driven properly, and power consumption is increased.

However, such a racing phenomenon belongs to an unusual phenomenon, so that the through current hardly flows.

On the other hand, although the above-described embodiment has been described using a PMOS transistor as an example, it will be appreciated by those skilled in the art that the present invention can be implemented using an NMOS transistor. In other words, when the NMOS transistor is used, the phase of the clock signals Clk1-Clk4 may be inverted and the driving voltage may be replaced with low rather than high.

In this way, the use of bootstrapping cuts through the flow of through current to reduce power consumption while using one form of MOS transistor to reduce process costs and simplify circuitry.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (10)

An apparatus for driving a display device including a plurality of pixels including a switching element, A gate driver including a plurality of shift registers arranged in a line, Each of the shift registers receives two of the first to fourth clock signals having different phases. Each of the shift registers includes a transistor for charging and discharging and first to fourth switching elements connected thereto. The transistor may include a first terminal selectively connected to a first voltage or a second voltage, a second terminal selectively connected to the first clock signal, and a third terminal connected to the second terminal by wiring. Containing Drive device for display device. In claim 1, The first switching device includes first and second terminals connected to each other and connected to the first voltage, and a third terminal connected to a first terminal of the transistor. The second switching element includes a first terminal connected to the second clock signal, a second terminal connected to the first terminal of the transistor, and a third terminal connected to the second voltage, The third switching device includes a first terminal connected to the first terminal of the transistor, a second terminal connected to the first clock signal, and a third terminal connected to the second terminal of the transistor, The fourth switching device includes a first terminal connected to a first terminal of the second switching device, a second terminal connected to a third terminal of the transistor, and a third terminal connected to the second voltage. doing Drive device for display device. In claim 2, The duty ratio of the first to second clock signals is 50% or less. In claim 2, At a first time point, the first and third switching devices are turned on. At a second time point, the first switching device is turned off. At a third time point, the second and fourth switching devices are turned on. Drive device for display device. In claim 4, The transistor is Starting charging at the first time point, entering a floating state at the second time point, and starting discharge at the third time point. Drive device for display device. In claim 5, The shift register further includes an output terminal connected between a third terminal of the transistor and a second terminal of the fourth switching element, The output terminal is connected to the first clock signal at the first and second time points, and is connected to the second voltage at the third time point. Drive device for display device. In claim 6, The first to fourth clock signals have a voltage equal to the ground voltage and a voltage range lower than the ground voltage. The second voltage is the same voltage as the ground voltage and the transistors and the first to fourth switching elements are PMOS transistors. Drive device for display device. In claim 6, The first to fourth clock signals have a voltage equal to the ground voltage and a voltage range higher than the ground voltage. The second voltage is lower than the ground voltage and the transistors and the first to fourth switching elements are NMOS transistors. Drive device for display device. In claim 7 or 8, 2. The driving apparatus of the display device, wherein the two clock signals input to the shift register among the first to fourth clock signals have a phase difference of 90 ° from each other. The method of claim 9, The transistor and the first to fourth switching elements are formed in the same process as the switching elements of the pixel.

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