KR100857495B1 - Method for driving shift resister for driving amorphous-silicon thin film transistor gate - Google Patents

Abstract

The present invention relates to a gate shift register driving method of a large-screen a-Si TFT LCD. The gate shift register driving method of the present invention provides the TFT gate shift register with a voltage source (Vona) that is larger than the voltage source (Von) provided to the clock generator providing the clock signal to the gate shift register. As a result, the slope of the curve rising from the low level to the high level of the output voltage of the inverter for pull-down driving among the gate shift register circuits is increased so that the gate line driving signal falls quickly from the high level to the low level. As a result, it is possible to implement a high-resolution large screen display in which the screen display defect of the TFT LCD does not occur.

Description

Amorphous Silicon Thin Film Transistor Gate Drive Shift Resistor Drive Method {METHOD FOR DRIVING SHIFT RESISTER FOR DRIVING AMORPHOUS-SILICON THIN FILM TRANSISTOR GATE}

1 is a schematic view showing the configuration of a TFT substrate of a conventional a-Si LCD.

2 is an exploded perspective view of a liquid crystal display of an a-Si TFT LCD according to the present invention;

3 is a view showing the configuration of a TFT substrate of an a-Si TFT LCD of the present invention.

4 is a block diagram of a shift register constituting a gate driving circuit of the a-Si TFT LCD of FIG.

5 is a detailed circuit diagram of each stage of the shift register of FIG.

6 is a timing diagram of each part of FIG. 5.

FIG. 7 is a block diagram illustrating a power generator and a clock generator for driving the shift register of FIG. 4. FIG.

FIG. 8 is a simulation output waveform diagram of a gate line driving voltage which is an output voltage of a shift register when a voltage source identical to the voltage source provided to the clock generator as shown in FIG. 7 is provided to the shift register.

9 is a block diagram illustrating a power generator and a clock generator for driving a shift register according to an exemplary embodiment of the present invention.                 

10 is an example of an internal circuit configuration of a DC / DC converter for generating a shift register driving power supply according to an embodiment of the present invention.

FIG. 11 is a simulation output waveform diagram of a gate line driving voltage which is an output voltage of a shift register when a voltage source different from the voltage source provided to the clock generator is applied to the shift register as in FIG. 9; FIG.

12 is a simulation output waveform diagram showing a gate line driving voltage which is an output voltage of a shift register when the shift register driving power of FIGS. 4 and 9 is applied.

<Description of the symbols for the main parts of the drawings>

170: TFT gate driving shift register (gate driving circuit)

710: DC / DC converter 720: clock generator

The present invention relates to an amorphous silicon thin film transistor (a-Si TFT LCD) gate drive shift register for large screens.

Recently, a liquid crystal display device has a light weight, a small size, high resolution, low power, and an environment-friendly advantage, compared to a typical CRT display device, and is capable of full color and is emerging as a next-generation display device.                         

The liquid crystal display is divided into TN (Twisted Nematic) and STN (Super-Twisted Nematic) methods, and the difference between the driving method is the active matrix display method using the switching element and the TN liquid crystal and the passive matrix using the STN liquid crystal. There is a passive matrix display method.

The big difference between these two methods is that the active matrix display method is used for TFT-LCD, which drives the LCD using the TFT as a switch, and the passive matrix display method does not use transistors, thus requiring a complicated circuit. Do not

TFT-LCD is divided into a-Si TFT LCD and poly-Si TFT LCD. Poly-Si TFT LCD has low power consumption and low price, but has a disadvantage of complicated TFT manufacturing process compared to a-Si TFT. Thus, poly-Si TFT LCDs are mainly applied to small display devices such as those of IMT-2000 phones. The a-Si TFT LCD has large area and high yield, and is mainly applied to large screen display devices such as notebook PCs, LCD monitors, and HDTVs.

1 is a schematic view showing the configuration of a TFT substrate of a conventional a-Si LCD.

As shown in FIG. 1, a typical a-Si TFT LCD forms a data driving chip 34 on a flexible printed circuit board 32 by a COF (CHIP ON FLIM) method, and forms the flexible printed circuit board 32. The data printed circuit board 36 is connected to the data line terminal of the pixel array. In addition, the gate driving chip 40 is formed on the flexible printed circuit board 38 by a COF method, and the gate printed circuit board 42 and the gate line terminal portion of the pixel array are connected through the flexible printed circuit board 40. .                         

When implementing an a-Si TFT LCD for a high-resolution large screen, there is a need for a gate driving circuit capable of quickly discharging a charge charged in a capacitive load present in a gate line of a pixel. However, when a conventional gate driving circuit is used, it is difficult to implement a high resolution large screen display in which display failure does not occur.

A first object of the present invention is to provide a gate driving circuit used to implement a high resolution large screen display in which a display failure does not occur in order to solve the problems of the prior art.

In order to achieve the first object of the present invention, the method of driving the thin film transistor gate shift register according to the present invention includes a first in each of the plurality of shift registers cascaded to provide a gate line driving signal to the plurality of gate lines of the thin film transistor. And alternately input a second clock signal to drive each shift register. In the thin film transistor gate shift register driving method, first, a clock generator driven by a first power supply voltage having a first high level in each shift register is used. A first or second clock signal having the first high level is received from the input signal. Next, a second power supply voltage having a second high level greater than the first high level by a predetermined magnitude is generated and provided to the respective shift registers, and the respective shift is performed during a duty period of the first or second clock signal. A gate line driving signal is generated to pull up the gate line coupled to the output terminal of the register. In response to an output signal of a shift register immediately after the gate line driving signal, the gate line driving signal is pulled down from a high level to a low level to initiate pull-down of the gate line, and a pull-down driving driven by the second power voltage after the pull-down of the gate line starts. As the output signal of the switching element rises from the low level to the high level, the gate line driving signal is lowered to maintain the pull-down of the gate line.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention through an embodiment of the present invention.

2 is an exploded perspective view of a liquid crystal display of an a-Si TFT LCD according to the present invention.

Referring to FIG. 2, the liquid crystal display device 100 includes a liquid crystal display panel assembly 110, a backlight assembly 120, a chassis 130, and a cover 140.

The liquid crystal display panel assembly 110 includes a liquid crystal display panel 112, a flexible printed circuit board 116, an integrated control and data driving chip 118. The liquid crystal display panel 112 includes a TFT substrate 112a and a color filter substrate 112b. In the TFT substrate 112a, a display cell array circuit, a data driving circuit, a gate driving circuit, and external connection terminals are formed by an a-Si TFT process. Color filters and transparent common electrodes are formed on the color filter substrate 112b. The TFT substrate 112a and the color filter substrate 112b are opposed to each other and liquid crystal is injected therebetween and then encapsulated.                     

The integrated control and data driver chip 118 and the circuits of the TFT substrate 112a provided in the flexible printed circuit board 116 are electrically connected by the flexible printed circuit board 116. The flexible printed circuit board 116 provides data signals, data timing signals, gate timing signals, and gate driving voltages to the data driving circuit and gate driving circuit of the TFT substrate 112a.

The backlight assembly 120 includes a lamp assembly 122, a light guide plate 124, optical sheets 126, a reflector plate 128, and a mold frame 129.

3 shows the configuration of a TFT substrate of an a-Si TFT LCD of the present invention.

Referring to FIG. 3, the display cell array circuit 150, the data driving circuit 160, the gate driving circuit 170, the data driving circuit external connection terminals 162 and 163, and the gate are disposed on the TFT substrate 112a of the present invention. The driving circuit external connection terminal portion 172 is formed together in the TFT process.

The display cell array circuit 150 includes m data lines DL1 to DLm extending in a column direction and n gate lines GL1 to GLn extending in a row direction.

At each intersection of the data lines and the gate lines, a switching transistor ST is formed. The drain of the switching transistor STi is connected to the data line DLi, and the gate is connected to the gate line GLi. The source of the switching transistor STi is connected to the transparent pixel electrode PE. The liquid crystal LC is positioned between the transparent pixel electrode PE and the transparent common electrode CE formed on the color filter substrate 112b.                     

Therefore, the liquid crystal array is controlled by the voltage applied between the transparent pixel electrode PE and the transparent common electrode CE, thereby controlling the amount of light passing through to display the gray level of each pixel.

The data driving circuit 160 includes a shift register 164 and a plurality of switching transistors SWT. The plurality of switching transistors SWT may form a plurality of data line blocks, for example, BL1 to BL8.

The plurality of data lines are divided into eight blocks, for example, as described above, and each block is sequentially selected by eight block selection signals of the shift register 164.

FIG. 4 shows a block diagram of a shift register constituting the gate driving circuit 170 of the a-Si TFT LCD of FIG.

Referring to FIG. 4, the gate driving circuit 170 is cascaded with a plurality of stages (shift registers) SR1, SR2,... SRN.

That is, the output Gout terminal of each stage is connected to the input terminal of the next stage. For example, when the number of gate lines is 192, the stages may include 192 stages SR1 to SR192 and one dummy stage SR193 corresponding to the gate lines.

Each stage has an input terminal IN, an output terminal OUT, a control terminal CT, a clock signal CKV, CKVB input terminal, a first power supply voltage Voff terminal, and a second power supply voltage Von terminal. .

The start signal STV is input to the input terminal of the first stage SR1. The start signal STV is a pulse signal synchronized with the vertical synchronizing signal.                     

The output signals Gout (1), Gout (2), Gout (3), Gout (4), ... of each stage are gate line driving signals for driving each gate line, and are connected to respective corresponding gate lines. . The odd clock stages SR1, SRC3,... Are provided with a first clock signal CKV, and the even stages SR2, SR4, ... are provided with a second clock signal CKVB. The first clock signal CKV and the second clock signal CKVB have phases opposite to each other.

Each control terminal of stages SR1, SR2, SR3, ... is controlled by the output signals Gout (2), Gout (3), Gout (4), ... of the next stages SR2, SR3, SRC4, ... It is input as a signal. That is, the control signal input to the control terminal is a signal delayed by the duty period of its output signal.

Therefore, since output signals of each stage are sequentially generated with an active period (high state), corresponding gate lines (horizontal lines) are selected in the active period of each output signal.

FIG. 5 shows a concrete circuit diagram of each stage of the a-Si TFT gate drive shift register circuit of FIG. 4.

Referring to FIG. 5, each stage (shift register) includes pull-up driving transistors 502, 504, and 506, pull-down driving transistor 508, and gate output drivers 510 and 512.

In the gate output driving units 510 and 512, the drains of the pull-up transistors NT2 and 510 are connected to the clock signal input terminal CK, the gate is connected to the first node N1, and the output signal Gout (N) is output. It is a pull-up NMOS transistor whose source is connected to the output terminal OUT.

In the gate output drivers 510 and 512, the drains of the pull-down transistors NT3 and 512 are connected to the output terminal OUT, the gate is connected to the second node N2, and the source is connected to the first power voltage Voff. Connected pull-down NMOS transistors.

The pull-up NMOS transistor NT2 is driven by the capacitor C1 and the NMOS transistors NT1, NT4, and NT7. The capacitor C1 is connected between the first node N1 and the output terminal OUT. In the first pull-up driving transistor NT1, a drain is connected to the second power supply voltage Von terminal, a gate is connected to an input terminal IN that receives the output signal Gout (N-1), and the first The source is connected to node N1. In the second pull-up driving transistor NT4, a drain is connected to the first node N1, a gate is connected to the control terminal CT that receives the next output signal Gout (N + 1), and a source is formed. 1 It is connected to the power supply voltage (Voff) terminal. The transistor NT7 has a drain connected to the first node N1, a gate connected to the second node N2, and a source connected to the first power supply voltage Voff terminal. At this time, the size of the first pull-up driving transistor NT1 is preferably formed to be about twice as large as that of the transistor NT7.

The pull-down driving transistor (inverter) 508 drives the pull-down NMOS transistor NT3 of the gate output driver 510 and 512, and preferably consists of two NMOS transistors NT5 and NT6, and an inverter Has the function of That is, the pull-down driving transistor 508 functions to control the pull-down transistor NT3 to be turned off when the pull-up transistor NT2 is turned on, and to control the pull-down transistor NT3 to be turned on when the pull-up transistor NT2 is turned off. In the transistor NT5, a drain and a gate are commonly coupled to the second power supply voltage Von terminal, and a source is connected to the second node N2. The transistor NT6 has a drain connected to the second node N2, a gate connected to the first node N1, and a source connected to the first power supply voltage Voff terminal. At this time, the size of the transistor NT5 is preferably formed about 16 times larger than the size of the transistor NT6.

FIG. 6 shows each sub timing diagram of FIG. 5. Hereinafter, the operation of the a-Si TFT gate driving shift register circuit of FIG. 5 will be described with reference to FIG. 6.

Referring to FIG. 6, after the capacitor C1 is charged by the output signal of the immediately preceding stage, the clock signal connected to the pull-up transistors NT2 and 510 is output to the output terminal, and the gate of the stage immediately after this stage is output by the output voltage. Immediately after the line driving signal is generated, the output signal of the shift register drives the second pull-up driving transistor NT4 to discharge the capacitor C1 voltage to end one cycle of each stage.

Hereinafter, the operation of the a-Si TFT gate driving shift register circuit of FIG. 5 will be described in more detail.

The output stage Gout (N-1) of the preceding stage sets the current stage by charging the capacitor C1 of the current stage, and the output stage Gout (N + 1) of the next stage sets the current stage by discharging the capacitor C1 of the current stage. To reset. Here, the first clock signal CKV and the second clock signal CKVB have opposite phases.                     

First, when the first and second clock signals CKV and CKVB and the scan start signal STV are supplied to the first stage, the first clock signal CKV is high in response to the rising edge of the scan start signal STV. After the level section is delayed for a predetermined time, the output signal Gout (1) is generated at the output terminal.

The capacitor C1 of the gate output drivers 510 and 512 begins to be charged at the rising edge of the start signal STV input to the gate of the first pull-up driving transistor NT1 through the input terminal IN. After the charging voltage Vc1 of the capacitor C1 is charged above the threshold voltage between the pull-up transistor NT2 gate sources, the pull-up transistor NT2 is turned on and the high voltage of the first clock signal CKV is turned on. The level section appears on the output terminal. As a result, such a delay characteristic appears.

When the high level section of the clock signal begins to appear at the output terminal OUT, the output voltage is bootstraped to the capacitor C1 so that the gate voltage of the pull-up transistor NT2 rises above the turn-on voltage Von. do. Accordingly, the pull-up transistor NT2, which is an NMOS transistor, is maintained in a full conduction state. At this time, since the size of the first pull-up driving transistor NT1 is about twice as large as that of the transistor NT7, the pull-up transistor NT2 is turned on even if the transistor NT7 is turned on by the start signal STV. Let's transition.

On the other hand, before the start signal is input, the pull-down driving transistor 508 raises the second node N2 to the second power supply voltage Von by the transistor NT5, and the pull-down transistor NT3 is turned on. Therefore, the voltage of the output signal of the output terminal OUT is in the state of the first power supply voltage Voff. When the start signal STV is input, the transistor NT6 is turned on so that the potential of the second node N2 is lowered to the first power supply voltage Voff. Thereafter, even when the transistor N5 is turned on, since the size of the transistor N6 is about 16 times larger than the size of the transistor N5, the second node N2 is continuously maintained at the first power supply voltage Voff. Accordingly, the pull-down transistor NT3 transitions from the turned on state to the turned off state.

That is, when the start signal is input, the pull-up transistor NT2 of the gate driving shift register circuit of FIG. 5 is turned on, the pull-down transistor NT3 is turned off, and the first clock signal CKV is applied to the output terminal. The delay appears by the duty period of (CKV).

When the voltage of the output signal of the output terminal OUT drops to the turn-off voltage (VOFF = VSS), the transistor NT6 is turned off. At this time, since only the second power supply voltage Von is supplied to the second node N2 through the transistor NT5, the potential of the second node N2 is changed from the first power supply voltage Voff to the second power supply voltage Von. Starts to rise. When the potential of the second node N2 starts to rise, the transistor NT7 starts to turn on, and thus the charging voltage of the capacitor C1 begins to discharge through the transistor NT7. Therefore, pull-up transistor NT2 also starts to be turned off.

Subsequently, since the output signal Gout (N + 1) of the next stage provided to the control terminal CT is increased to the turn-on voltage, the second pull-up driving transistor NT4 is turned on. In this case, since the size of the second pull-up driving transistor NT4 is about twice as large as that of the transistor NT7, the potential of the first node N1 is faster than the transistor NT7 is turned on faster than the first power supply voltage Voff. Will be down.

In addition, when the potential of the second node N2 rises to the second power supply voltage Von, the pull-down transistor NT3 is turned on so that the output terminal OUT is turned down from the turn-on voltage VON to the turn-off voltage VOFF. do.

Even when the second pull-up driving transistor NT4 is turned off because the output signal Gout (N + 1) of the next stage applied to the control terminal CT is lowered to the low level, the second node N2 passes through the transistor NT5. The biased state of the second power supply voltage Von is maintained. Therefore, even when the output signal Gout (N + 1) of the next stage applied to the control terminal CT is lowered to the low level and the second pull-up driving transistor NT4 is turned off, the potential of the second node N2 is set to the second level. Since the voltage is maintained at the power supply voltage Von, stable operation is secured without fear of a malfunction in which the pull-down transistor NT3 is turned off.

Each stage is operated by the above-described operation so that the output signals GOUT (1), GOUT (2), GOUT (3), Gout (4), ... are sequentially generated.

FIG. 7 is a block diagram illustrating a power generator and a clock generator 720 for driving the shift register 170 of FIG. 4.

Referring to FIG. 7, a DC / DC converter 710 is used as the power generator for driving the shift register 170 of FIG. 4, and the output voltage Von of the DC / DC converter 710 is a clock generator. 720 and a TFT gate shift register 170. The clock generator 720 receives the Von voltage and the Voff voltage to generate clock signals CKV and CKVB and provide them to the TFT gate shift register 170.

That is, the same voltage source Von is used as a power source for driving the clock generator 720 and the TFT gate shift register 170.

FIG. 8 shows a simulation output waveform diagram of the gate line driving voltage which is the output voltage of the shift register when the same voltage source as that provided to the clock generator is provided to the shift register as shown in FIG. 7.

Referring to FIG. 8, when the same voltage source Von as the voltage source provided to the clock generator is provided to the shift register, the first according to the change in the output voltage of the inverter 508 of the first shift register, that is, the pull-down driving switching elements NT5 and NT6. The gate line driving voltage V [Gout (2) of the first stage shift register according to the change of the gate line driving voltage V [Gout (1) '] of the shift register and the output voltage of the inverter 508 of the second stage shift register. ) '], You can see the waveform change.

When the same voltage source Von as the voltage source provided to the clock generator is provided to the shift register as described above, the highest potential value of the clock signal becomes equal to the high level value of the Von voltage.

As shown in FIG. 7, when a voltage source is applied to the TFT gate shift register 170 and applied to a high resolution large screen TFT LCD, an abnormality occurs in the screen display of the TFT LCD according to an increase in the capacitive load of the gate line. .

As shown in the graph of FIG. 8, V [Gout (1) '] has a pulse width of 1H or more for a clock pulse width of 1H. In general, since the minimum value of the gradation voltage is 0 V, the pulse width of the effective gate line driving signal V [Gout (n)] which becomes 0 V or more is preferably 1 clock pulse width or less. In particular, in order to reduce display defects, the gate line driving signal is quickly changed from the high level to the low level in response to a section in which the output voltage of the inverter 508, that is, the pull-down driving switching elements NT5 and NT6 changes from a low level to a high level. It is preferable to make the pulse width of the effective gate line drive signal V [Gout (n)] less than one clock pulse width by making it fall.

The reason why the pulse width of V [Gout (1) '] becomes 1H or more is because the operation of the inverter 508 for driving the pull-down transistor NT3, that is, the pull-down driving switching elements NT5 and NT6 is slow as shown in the graph. to be. In particular, as shown in portions A1 'and A2' of FIG. 8, an operation in which the output voltage of the inverter 508 rises from a low level to a high level is gradually performed. Accordingly, V [Gout ( 1) '] and V [Gout (2)'] fail to fall quickly to the low level at falling edge portions A1 'and A2', resulting in V [Gout (1) '] and V [Gout (2) The effective pulse width of '] becomes 1H or more.

When the effective pulse width of V [Gout (n) '] is larger than 1H by a predetermined value or more, the pixel width connected to each shift register through the gate line is 1H since the pulse width of the gradation voltage provided from the data driving circuit 160 is 1H. The display voltage is likely to be affected by the gray voltage corresponding to the next gate line.

 Thus, one of the ways to ensure that the effective pulse width of V [Gout (n) '] is as close to 1H or not as high as possible, above 1H, is one of the ways in which the output voltage of inverter 508 is high at low Ascending to the level is to be done quickly. That is, the slope of the curve in which the output voltage of the inverter 508 rises from the low level to the high level is increased. One way to increase the slope of the rising curve of the output voltage of the inverter 508 is to increase the magnitude of the output voltage of the inverter as a whole so that the output voltage of the inverter 508 is at a low level for the same time. To rise to a higher level with a further increased value.

9 is a block diagram illustrating a power generator and a clock generator for driving a shift register according to an exemplary embodiment of the present invention.

Referring to FIG. 9, the output voltage Von is generated by the DC / DC converter 710 and applied to the clock generator 720 to drive the clock generator 720, and generates a separate voltage source Vona different from the Von voltage. The TFT gate shift register 170 is applied to the TFT gate shift register 170 to drive the TFT gate shift register 170. That is, the TFT gate shift register 170 is driven using a separate voltage source Vona that is different from the voltage source Von provided to the clock generator 720.

In order for the maximum value of the output voltage of the inverter 508 to be larger than that of FIG. 8, the magnitude of the Vona voltage is preferably larger than the magnitude of the Von voltage. For example, FIG. 10 shows an example of a power supply circuit for generating Vona larger than the magnitude of the Von voltage.

10 illustrates an example of an internal circuit configuration of a DC / DC converter for generating a shift register driving power source according to an exemplary embodiment of the present invention.

Referring to FIG. 10, a current pump including a plurality of diodes D1, D2, D3, and D4 and capacitors C2, C3, C4, and C5, as illustrated in FIG. 10, receives a DC voltage source VDD. The circuit generates VDD + ΔV at the Von voltage and VDD + 2ΔV at the Vona voltage.

The Von voltage receives the DC voltage of VDD through the anode of the diode D1, receives the voltage of ΔV through the capacitor C2, and generates a voltage of Von = VDD + ΔV at the cathode of the diode D2 via the diode D2. Similarly, the Von voltage is input through the anode of diode D3, the voltage of ΔV is input through capacitor C4, and Vona = VDD + 2ΔV of which V is increased to Von voltage at the cathode of diode D4 via diode D4. Generate voltage. That is, two voltages, Vona and Von, of which Vona> Von may be generated using the current pump circuit as described above.

In addition, the Von voltage may be adjusted using a conventionally known voltage shift circuit, and the Vona voltage may be adjusted independently of the Von voltage to be Vona> Von.

When a Vona voltage source with Vona> Von is applied to the TFT gate shift register 170, the inverter 508 is driven by the voltage source Vona through the drain of the transistor NT5, as can be seen in Figs. As a result, the output voltage of the inverter 508 becomes larger than when driven by the Von voltage, and the output voltage waveform of the inverter 508 rises with a larger slope from low level to high level. Therefore, it is possible to prevent the screen display defect from occurring by making the effective pulse width of V [Gout (n)] as close to 1H or as large as possible without exceeding 1H.                     

 FIG. 11 is a simulation output waveform diagram of a gate line driving voltage that is an output voltage of a shift register when a voltage source Vona larger than the voltage source Von provided to the clock generator is applied to the TFT gate shift register 170.

In FIG. 8, a Von voltage of about 25 V is applied to the inverter 508 so that the maximum value of the output voltage of the inverter 508 is about 15 V. In FIG. 11, a Vona voltage of about 45 V is applied to the inverter 508. When applied, the maximum value of the output voltage of the inverter 508 is about 35V. As a result, when the output voltage of the inverter 508 rises from the low level to the high level, the effective pulse widths of the gate line driving signals V [Gout (1)] and V [Gout (2)] are determined. It can be seen that the narrower than in the case of FIG.

12 illustrates a case in which the same voltage source as the voltage source Von provided to the clock generator is applied to the shift register 170, and a voltage source Vona larger than the voltage source Von provided to the clock generator is applied to the shift register 170. The simulation output waveform diagram which shows the gate line drive voltage in the case.

Referring to FIG. 12, the gate line driving signal when the same voltage source as the voltage source Von provided to the clock generator is applied to the shift register 170 is represented by V [Gout '], and the voltage source Von provided to the clock generator is shown. The gate line driving signal when a larger voltage source Vona is applied to the shift register 170 is represented by V [Gout]. Comparing the A portion and the A 'portion of the falling edge portion of the gate line driving signal at the portion where the output voltage of the inverter 508 rises from the low level to the high level, the effective pulse width of the gate line driving signal V [Gout] is compared. It can be seen that the pulse width becomes narrower than the effective pulse width of the gate line driving signal V [Gout ']. Therefore, the gate line driving signal falls quickly from the high level to the low level, and as a result, the screen display defect of the TFT LCD can be prevented from occurring.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

As described above, in the present invention, by applying a larger voltage source (Vona) separate from the voltage source (Von) provided to the clock generator to the TFT gate driving shift register, it is possible to prevent display defects from occurring even when implementing a high-resolution large screen display. .

Claims (5)

In the method for driving each shift register by receiving the first and second clock signal alternately input from each of the plurality of shift registers cascaded to provide a gate line driving signal to the plurality of gate lines of the thin film transistor, Receiving a first or second clock signal having the first high level from a clock generator driven by a first power supply voltage having a first high level in each shift register; Generating and supplying a second power supply voltage having a second high level greater than the first high level to each shift register; Generating a gate line driving signal for pulling up a gate line coupled to an output terminal of each shift register during a duty period of the first or second clock signal; Initiating pull-down of the gate line by lowering the gate line driving signal from a high level to a low level in response to an output signal of a immediately following shift register; And After the pull-down of the gate line is started, the output signal of the pull-down driving switching element driven by the second power voltage rises from the low level to the high level so as to lower the gate line driving signal to the low level to thereby pull down the gate line. Steps to maintain Thin film transistor gate shift register driving method comprising a. The method of claim 1, wherein the second power supply voltage having the second high level is generated by boosting the first power supply voltage. The method of claim 2, wherein the first power supply voltage of the first high level is adjusted to be variable, and the second power supply voltage having the second high level is provided to be adjusted to be independent of the first power supply voltage. A thin film transistor gate shift resistor driving method. The thin film transistor gate shift register driving method of claim 1, wherein a maximum value of the pull-down driving switching element output signal is smaller than the second high level and larger than the first high level. A plurality of cascaded circuits alternately receiving the first and second clock signals having the first high level from a clock generator driven by a first power supply voltage having a first high level and providing them as gate line driving signals of a thin film transistor; A first pull-up driving switching element configured to turn on the pull-up switching element in response to a leading end of the start signal or the gate line driving signal of the immediately preceding shift register; A second pull-up driving switching element which turns off the pull-up switching element in response to a leading end of a gate line driving signal of a immediately following shift register; A pull-up switching element which receives a corresponding clock signal among the first and second clock signals when the power is turned on by the first pull-up driving switching element and provides the output terminal as a gate line driving signal; A pull-down switching device that is turned on when the pull-up switching device is turned off to provide a third power supply voltage to the output terminal; A gate shift performed in a thin film transistor gate shift register of a thin film transistor liquid crystal display device including a pull-down driving switching element which turns off the pull-down switching element in response to a leading end of the start signal or a gate line driving signal of the immediately preceding shift register; In the register driving method, Receiving a first or second clock signal having a first high level in each shift register; Generating and supplying a second power supply voltage having a second high level greater than the first high level to each shift register; Generating a gate line driving signal for pulling up a gate line coupled to an output terminal of each shift register during a duty period of the first or second clock signal; Initiating pull-down of the gate line by lowering the gate line driving signal from a high level to a low level in response to an output signal of a immediately following shift register; And After the pull-down of the gate line is started, the output signal of the pull-down driving switching element driven by the second power voltage rises from the low level to the high level so as to lower the gate line driving signal to the low level to thereby pull down the gate line. Steps to maintain Thin film transistor gate shift register driving method comprising a.

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