JPH11308856A - Charge pump circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a charge pump circuit large in doubling rate by separating a boosting transistor into plural groups, and gradually raising the back gate potential. SOLUTION: A unit boosting circuit is composed of an N-type MOS transistors T1-T7 having short-circuited a gain and a drain, and a capacitors C1-C7 connected to the short circuit point, and these unit boosting circuits are connected in large numbers in a column to constitute a charge pump, and also plural unit boosting circuits are separated into plural groups, and each group is given different back gate biases. The voltage boosted in the preceding group is applied as a back gate bias at least to the group including an output stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit for generating a high voltage from a low power supply voltage, and more particularly to a charge pump circuit device which boosts a low power supply voltage to a considerably high potential and has a high driving capability at the boosted potential. About.

[0002]

2. Description of the Related Art For example, an electrically erasable programmable ROM in which a memory cell comprises a single transistor.
(EEPROM: Electricaly Erasable Programmable ROM)
In the case of writing / erasing information,
A high potential of about V is required. The power supply potential of an ordinary electronic device has been reduced to about 3 V, and supplying the high potential from the outside leads to an increase in the cost of the electronic device. Therefore, a charge pump circuit is built in the semiconductor chip to generate a necessary high potential from the power supply potential Vcc (for example, Japanese Patent Application Laid-Open No. 62-190746). In addition, in recent system LSI concepts, a high-power element for driving an external load is also integrated in the same chip, and a high-voltage power supply dedicated to this high-power element is used. There has been a demand for generating a high potential.

FIG. 3A shows an example of a conventional charge pump circuit. In this charge pump circuit, N-channel MOS transistors M1 to M7 (arbitrary in number) having a gate and a drain short-circuited are connected in series by connecting a source and a drain, and a capacitance C is connected to a connection point between the source and the drain.
1 to C7 are connected. Each capacitance element C1 to C7
Is connected to a clock signal C as shown in FIG.
LK and a complementary clock signal * CLK are applied thereto, and a power supply potential VDD is applied to the connection point between the source of the N-type MOS transistor M1 and the capacitor C1 via the N-type MOS transistor M0. Power supply potential VDD as the output voltage Vout at the source of the p-type MOS transistor M7.
This is to obtain a more boosted potential.

FIG. 3C is a circuit diagram of a first stage of the charge pump circuit (a portion corresponding to the N-type MOS transistor T1). Hereinafter, the circuit operation of the charge pump circuit will be described.

In the initial state, when the clock CLK is at L level (0 V), the potential of the node C rises due to the current i1 and takes into account (VDD−Vth−) in consideration of the threshold Vth of the N-type MOS transistor T0. ΔVth). Here, ΔVth represents a fluctuation range of the threshold value due to the back gate bias effect of the N-type MOS transistor T0.

Thereafter, when the clock signal CLK changes to the H level (3 V), the potential of the node C is pushed up and rises. The rising potential Vup at this time is determined by the capacitance C
When the capacitance value of 1 is Cp1 and the parasitic capacitance at the node C is Cnode, it can be expressed by equation (1). Vup = VDD · (Cp1 / (Cp1 + Cnode)) (1) At this time, the potential of the node A is Va, and the potential of the node C is V
If (Vc−Va> Vth + △ Vth) holds as c, the source of the N-type MOS transistor T1
The potential Va of the node A is changed by the drain current i2 to (2)
It is charged to the potential according to the formula. Va = Vc−Vth− △ Vth (2) As described above, for each stage of the charge pump circuit, only the potential Vup according to the equation (1) is obtained. The output potential Vout is increased, and the output potential Vout is obtained by increasing the voltage.

[0007]

The N-type MOS transistors T1 to T7 at each stage of the charge pump circuit form N-type source / drain regions on the surface of the P-type semiconductor region, and have one source region adjacent to the other. Is configured to be shared with the drain region. At this time, since the ground potential (GND) is applied to the P-type semiconductor region as the back gate bias of the N-type MOS transistors T1 to T7, the potential difference (−Vbs) between the source potential and the back gate potential becomes closer to the output stage. ) Opens, and the fluctuation width ΔVth of the threshold increases due to the back gate bias effect.
When the fluctuation width ΔVth becomes equal to or more than a certain value, the current i2 according to the equation (2) does not flow, and the boosted voltage is limited. That is, the voltage cannot be boosted beyond a certain number of stages even if the number of transistor stages is increased.

As described above, the conventional charge pump circuit has a drawback that the boosted voltage is limited. In addition, since the influence of the back gate bias effect is greatest in the last transistor, the source / drain current of this transistor is also reduced, and there is a drawback that its driving capability is low.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and a plurality of transistors constituting a charge pump circuit are divided into at least two groups, and the transistors included in the group including an output stage are provided. The present invention provides a charge pump circuit which can eliminate the limit of the boosted voltage by applying a voltage applied to the first stage of the group and boosted by another group as a back gate bias.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below.
This will be described in detail with reference to FIG. This charge pump circuit includes N-channel MOS transistors M1 to M7 (arbitrary in number) diode-connected by short-circuiting the gate and the source, and capacitors C1 to C7 connected to a connection point between the gate and the drain. In addition, one N-type MOS transistor T1 to T7 and one capacitor C1 to C7 are used as a unit booster circuit, and are cascade-connected so as to connect the source of one transistor and the drain of the adjacent transistor. A clock signal CLK and a complementary clock signal * CLK as shown in FIG. 3B are applied to the other ends of the capacitors C1 to C7, and a connection point between the source of the N-type MOS transistor M1 and the capacitor C1. N-type MOS transistor M
0, the power supply potential VDD is applied through the N-type M
The output of the source of the OS transistor M7 is a potential boosted from the power supply potential VDD as the output voltage Vout.

The unit booster circuit connected in cascade is an N-type MO.
It is divided into a first group 10 of S transistors T1 to T4 (arbitrary number) and a second group 11 of N-type MOS transistors T5 to T7 (arbitrary number). The divided N-type MOS transistors T1 to T4 of the first group 10 output boosted voltages according to the number of stages of the unit booster circuit to the source (connection point 12) of the N-type MOS transistor T4, and N type M of group 11
The signal is transmitted to the OS transistor T5. Second group 11
Further boosts the voltage transmitted to the connection point 12 and outputs an output voltage Vout.

A ground potential (GND) is applied as a back gate bias to the divided first group of N-type MOS transistors T1 to T4, and a booster output to the connection point 12 is applied to the second group 11. The applied voltage is applied as a back gate bias. For example, the power supply potential V
DD (3V) is boosted by the first group 10 and the connection point 1
When a potential of 6 V is output to the second group 2 and the second group 11 further boosts to obtain an output voltage Vout of 12 V, a voltage of 6 V is applied to the second group 11 as a back gate bias.

FIG. 2 is a sectional view showing an example of a semiconductor integrated circuit embodying the above charge pump circuit. In order to apply a different back gate potential to each group, a double well structure was adopted.

That is, N + type source / drain regions 22 and a gate electrode 23 are formed on the surface of a P type semiconductor substrate 21 to form N type MOS transistors T1 to T4.
A P-type well region 25 is formed on the surface of the substrate 21 so as to overlap with the N-type well region 24 and is electrically independent. The N-type source / drain region 22 and the gate electrode are formed on the surface of the P-type well region 25. 23 to form N-type MOS transistors T5 to T7. Sources and drains of adjacent transistors are formed using one source / drain region 22 as a common region, and electrical connection between the transistors is made by aluminum electrode wiring according to the circuit diagram. The ground potential (GND) is applied to the P-type substrate 21 by the N + region 26, and the first group 1 is applied to the P-type well region 25 by the N + region 27.
A potential at a connection point 12 between 0 and the second group 11 is applied. This is to maintain a reverse bias condition between the back gate potential and the source potential. In order to make the P-type well region 25 electrically independent, the N-type well region 2
4 is also applied with the potential of the connection point 12. 28 is a LOCOS oxide film for element isolation. In addition, the capacity C1
C7 to C7 were constituted by MOS capacitance elements in which the source and drain were short-circuited and one electrode was used, and the gate was used as the other electrode.

FIG. 1B shows still another embodiment. FIG. 1A shows a clock signal CL applied to each of the capacitors C1 to C7.
While K and * CLK are applied, in this example, a ring oscillator circuit is used. That is, the inverter 40 is connected between the capacitors C1 to C7, and the NAND
The output of the gate 41 is connected to the capacitor C7, and the capacitor C1 is connected to the NA.
It is connected to one of the inputs of the ND gate 41, and the clock signal CLK is applied to the other of the inputs of the NAND gate 41. By making the number of the inverters 40 odd, self-oscillation is performed, and a signal similar to the complementary clock signal in FIG. 3B can be applied to each unit booster circuit.

As described above, by electrically isolating the region serving as the back gate for each group, it becomes possible to apply a different back gate bias to each group. Then, the boosted potential at the connection point 12 is set as the back gate bias for the transistor near the last stage, so that the difference between the back gate potential and the source potential of the N-type MOS transistors T5 to T7 of the second group 11 is determined. (−Vbs) can be made smaller than before. Therefore, the back gate bias effect that occurs in the transistors of the second group 11 can be reduced, and the amount of change in the threshold voltage △
Vth can be reduced. This reduces the number of groups to three.
By increasing the number to four, it means that the potential can be increased to an extremely high potential. Further, since the amount of change ΔVth of the threshold value due to the back gate bias effect of the transistor T7 in the final output stage can be suppressed to a small value, the output voltage Vo
It becomes possible to take out a large current as ut. Furthermore,
Since the potential difference between the back gate potential and the source potential does not need to be increased, all transistors can be manufactured with the same design withstand voltage.

Although the description has been made on the assumption that the number of groups is two, the number of groups may be increased according to a desired output voltage, and the number of transistors included in one group is arbitrary. Further, instead of the N-channel type, P
It is also possible to use a channel-type transistor.

[0018]

As described above, according to the present invention, by applying a back gate bias with a boosted potential, the back gate bias effect can be suppressed and a charge pump circuit having a large doubling rate can be provided. Have. At this time, the potential (boosted potential) applied to the back gate can be almost arbitrarily selected, so that the back gate bias effect generated in the final transistor can be suppressed, and the driving capability as an output transistor can be doubled. Thus, even a low power supply voltage LSI having a power supply potential Vdd of about 2 V, for example, can generate a high voltage of 12 to 20 V inside.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the present invention.

FIG. 3 is a diagram for explaining a conventional example.

[Explanation of symbols]

 T0 to T7 N-type MOS transistors C1 to C7 Capacitance element 10 First group 11 Second group 12 Connection point

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/115 H01L 27/10 434 27/10 481

Claims (2)

[Claims] An insulated gate transistor element and a capacitive element are combined to form a single unit booster circuit, a plurality of the unit booster circuits are connected in cascade, and synchronous signals having opposite phases are supplied to adjacent unit booster circuits. A charge pump circuit device that inputs, inputs a predetermined potential to an input terminal of a first-stage unit booster circuit, and outputs a boosted output voltage from an output terminal of the last-stage unit booster circuit. It is divided into at least two groups, a ground potential is applied as a back gate bias to one group, and a potential boosted by the first group is applied as a back gate bias to another group. Charge pump circuit device. 2. An insulated gate transistor element and a capacitive element are combined into one unit booster circuit, a plurality of the unit booster circuits are connected, and synchronous signals having opposite phases are input to adjacent unit booster circuits. A charge pump circuit device that inputs a predetermined potential to an input terminal of a first-stage unit booster circuit and outputs a boosted output voltage from an output terminal of the last-stage unit booster circuit, wherein the insulated gate transistor element is of one conductivity type. At least two of a first group formed on the surface of the first region of the first region and a second group formed on the surface of the second region of one conductivity type electrically separated from the first region. Ground potential is applied to the first region as a back gate bias of the first group, and a final boosted potential of the first group is applied to the second group. A charge pump circuit device, wherein one of the potentials boosted by the first group is applied to the second region as a back gate bias while being input to the first stage insulated gate transistor.