JP2019092303A - Negative voltage boosting charge pump - Google Patents

Abstract

To provide a negative voltage boosting charge pump with high operation stability.SOLUTION: A negative voltage boosting charge pump 1 includes: negative voltage boosting units 10 to 50 respectively including charge transfer transistors M11 to M15; low potential holding circuits 110 to 150 each of which switches a connection destination of a back gate of each of the charge transfer transistors M11 to M15 to a low potential side of either one of a drain and a source; and hold auxiliary transistors M41 to M45 that are connected between the respective back gates and the drains (or the sources) of the charge transfer transistors M11 to M15 and are turned on/off with the charge transfer transistors M11 to M15, and generates a negative output voltage VN lower than a ground voltage VSS. The negative voltage boosting units 10 to 50 are serially connected between an input terminal of the ground voltage VSS and an output terminal of the output voltage VN, and are driven by using four-phase clock signals CLK1 to CLK4 having different phases.SELECTED DRAWING: Figure 7

Description

  The invention disclosed herein relates to a negative boost charge pump.

  Conventionally, negative boost charge pumps that produce negative output voltages below ground are used in a variety of applications.

  In addition, patent document 1 and patent document 2 can be mentioned as an example of the prior art relevant to the above.

Patent No. 4775844 (FIG. 12, FIG. 16) Patent No. 4445395 (FIGS. 5, 13 and 16 to 18)

  However, the conventional negative boost charge pump has room for further improvement with respect to the improvement of its operation stability (= operation suppression of parasitic npn transistor of which quantitative prediction is difficult).

  SUMMARY OF THE INVENTION In view of the above problems found by the inventor of the present application, the invention disclosed in the present specification aims to provide a negative boost charge pump with high operation stability.

  The negative boosting charge pump disclosed in the present specification includes a negative boosting unit including a charge transfer transistor, and a low potential hold switching the connection destination of the back gate of the charge transfer transistor to either the drain or the source. A negative auxiliary output voltage lower than the ground voltage, comprising: a circuit; and a hold assist transistor connected between the back gate and the drain or source of the charge transfer transistor and turned on / off together with the charge transfer transistor. It is set as the structure (1st structure) to produce | generate.

  In the negative booster charge pump having the first configuration, the negative booster unit is connected in series between the input terminal of the ground voltage and the output terminal of the output voltage in a plurality of stages, and has four phases different in phase. It is preferable to use a configuration (second configuration) driven using a clock signal of

  In the negative boosting charge pump having the first or second configuration, the negative boosting unit has a gate connected to the charge transfer transistor having a drain connected to a unit input end and a source connected to a unit output end. A discharge transistor connected to the unit input end, a drain connected to the gate of the charge transfer transistor, a source and a back gate connected to the unit output end, and a first end connected to the unit output end; A flying capacitor having two ends connected to a first clock input end, and a gate capacitor having a first end connected to the gate of the charge transfer transistor and a second end connected to a second clock input end It is good to set it as (3rd structure).

  In the negative boosted charge pump having the third configuration, the low potential hold circuit has a drain connected to the drain of the charge transfer transistor and a gate connected to the source of the charge transfer transistor to provide a source and a back gate. A first transistor connected to the back gate of the charge transfer transistor, a drain connected to the source of the charge transfer transistor, a gate connected to the drain of the charge transfer transistor, and a source and a back gate for the charge transfer transistor And a second transistor connected to the back gate of the transistor (4).

  Further, in the negative booster charge pump having the fourth configuration, the charge transfer transistor, the discharge transistor, the first transistor, and the second transistor are all N-channel type (fifth Configuration).

  In the negative boosting charge pump of the second configuration, the negative boosting unit at the last stage has an N-channel type in which the drain is connected to the unit input end and the gate, source and back gate are connected to the unit output end. The charge transfer transistor may be configured (sixth configuration).

  In the negative boosting charge pump of the second configuration, the negative boosting unit at the first stage has an N-channel type in which the drain is connected to the unit input end and the gate, source and back gate are connected to the unit output end. The charge transfer transistor may have a configuration (seventh configuration) including a charge transfer transistor, and a flying capacitor having a first end connected to the unit output end and a second end connected to a clock input end.

  In the negative boosting charge pump of the second configuration, the negative boosting unit at the first stage is a P-channel type in which the source and the back gate are connected to the unit input end and the gate and the drain are connected to the unit output end. The charge transfer transistor may have a configuration (eighth configuration) including a charge transfer transistor, and a flying capacitor having a first end connected to the unit output end and a second end connected to a clock input end.

  The semiconductor device disclosed in the present specification is an integrated P-type semiconductor substrate and an N-type well formed in the P-type semiconductor substrate, which is formed by integrating the negative boost charge pump having the fifth configuration. And a plurality of P-type wells formed in the N-type well, wherein the charge transfer transistor, the hold assist transistor, the first transistor, and the second transistor are configured to have the plurality of P-type wells. Each back gate is configured (ninth configuration).

  Further, the nonvolatile semiconductor memory device disclosed in the present specification has a configuration (tenth configuration) including the negative boost charge pump having any one of the first to eighth configurations.

  According to the invention disclosed in the present specification, it is possible to provide a negative boost charge pump with high operation stability.

A circuit diagram showing a comparative example of a negative boost charge pump Timing chart showing 4-phase clock drive A circuit diagram showing how a charge transfer transistor is accompanied by a parasitic element A longitudinal sectional view showing how a charge transfer transistor is accompanied by a parasitic element A circuit diagram showing how all the negative boost units are accompanied by parasitic elements Waveform diagram showing low potential hold operation A circuit diagram showing a first embodiment of a negative boost charge pump Longitudinal section of negative boost charge pump Circuit diagram of negative boost charge pump with parasitic diode attached to substrate Waveform diagram showing the hold assist operation A circuit diagram showing a second embodiment of a negative boost charge pump A circuit diagram showing a third embodiment of a negative boost charge pump A circuit diagram showing a fourth embodiment of a negative boost charge pump A circuit diagram showing a fifth embodiment of a negative boost charge pump

Comparative Example
Prior to describing the novel embodiment of the negative boost charge pump, first, a comparative example to be compared with this will be briefly described. FIG. 1 is a circuit diagram showing a comparative example of a negative boost charge pump. The negative booster charge pump 1 of the present comparative example has a plurality of (for example, five) negative booster units 10 to 50, low potential hold circuits 110 to 150, and an output capacitor Co, and has a ground voltage VSS (= Generate a negative output voltage VN lower than 0 V). The number of stages of the negative boost unit may be adjusted arbitrarily according to the target value of the output voltage VN.

<Negative boost unit>
Subsequently, the circuit configuration of each of the negative boost units 10 to 50 will be individually and specifically described with reference to FIG. 1.

  The negative booster unit 10 includes a charge transfer transistor M11 (NMOSFET), a discharge transistor M21 (NMOSFET), a flying capacitor C11, and a gate capacitor C21.

  The drain of the charge transfer transistor M11 is connected to the input end of the ground voltage VSS as a unit input end a (= the input end of the negative boosting unit 10). The source of the charge transfer transistor M11 is connected to the input end of the negative boost unit 20 as a unit output end b (= the output end of the negative boost unit 10).

  The gate of the discharge transistor M21 is connected to the drain (= unit input terminal a) of the charge transfer transistor M11. The drain of the discharge transistor M21 is connected to the gate of the charge transfer transistor M11. The source and the back gate of the discharge transistor M21 are both connected to the source (= unit output terminal b) of the charge transfer transistor M11.

  The first end of the flying capacitor C11 is connected to the source (= unit output terminal b) of the charge transfer transistor M11. The second end of the flying capacitor C11 is connected to the input end of the clock signal CLK3 as the first clock input end c.

  The first end of the gate capacitor C21 is connected to the gate of the charge transfer transistor M11. The second end of the gate capacitor C21 is connected to the input end of the clock signal CLK1 as a second clock input end d.

  The negative booster unit 20 includes a charge transfer transistor M12 (NMOSFET), a discharge transistor M22 (NMOSFET), a flying capacitor C12, and a gate capacitor C22.

  The drain of the charge transfer transistor M12 is connected to the output end of the negative boosting unit 10 as the input end of the negative boosting unit 20. The source of the charge transfer transistor M12 is connected to the input end of the negative boosting unit 30 as the output end of the negative boosting unit 20.

  The gate of the discharge transistor M22 is connected to the drain of the charge transfer transistor M12. The drain of the discharge transistor M22 is connected to the gate of the charge transfer transistor M12. The source and back gate of the discharge transistor M22 are both connected to the source of the charge transfer transistor M12.

  The first end of the flying capacitor C12 is connected to the source of the charge transfer transistor M12. The second end of the flying capacitor C12 is connected to the input end of the clock signal CLK4 as a first clock input end.

  The first end of the gate capacitor C22 is connected to the gate of the charge transfer transistor M12. The second end of the gate capacitor C22 is connected to the input end of the clock signal CLK2 as a second clock input end.

  Negative boosting unit 30 includes a charge transfer transistor M13 (NMOSFET), a discharge transistor M23 (NMOSFET), a flying capacitor C13, and a gate capacitor C23.

  The drain of the charge transfer transistor M13 is connected to the output end of the negative boost unit 20 as the input end of the negative boost unit 30. The source of the charge transfer transistor M 13 is connected to the input end of the negative boosting unit 40 as the output end of the negative boosting unit 30.

  The gate of the discharge transistor M23 is connected to the drain of the charge transfer transistor M13. The drain of the discharge transistor M23 is connected to the gate of the charge transfer transistor M13. The source and back gate of the discharge transistor M23 are both connected to the source of the charge transfer transistor M13.

  The first end of the flying capacitor C13 is connected to the source of the charge transfer transistor M13. The second end of the flying capacitor C13 is connected to the input end of the clock signal CLK3 as a first clock input end.

  The first end of the gate capacitor C23 is connected to the gate of the charge transfer transistor M13. The second end of the gate capacitor C23 is connected to the input end of the clock signal CLK1 as a second clock input end.

  Negative boost unit 40 includes charge transfer transistor M14 (NMOSFET), discharge transistor M24 (NMOSFET), flying capacitor C14, and gate capacitor C24.

  The drain of the charge transfer transistor M <b> 14 is connected to the output end of the negative boost unit 30 as the input end of the negative boost unit 40. The source of the charge transfer transistor M14 is connected to the input end of the negative boosting unit 50 as the output end of the negative boosting unit 40.

  The gate of the discharge transistor M24 is connected to the drain of the charge transfer transistor M14. The drain of the discharge transistor M24 is connected to the gate of the charge transfer transistor M14. The source and back gate of the discharge transistor M24 are both connected to the source of the charge transfer transistor M14.

  The first end of the flying capacitor C14 is connected to the source of the charge transfer transistor M14. The second end of the flying capacitor C14 is connected to the input end of the clock signal CLK4 as a first clock input end.

  The first end of the gate capacitor C24 is connected to the gate of the charge transfer transistor M14. The second end of the gate capacitor C24 is connected to the input end of the clock signal CLK2 as a second clock input end.

  The negative booster unit 50 includes a charge transfer transistor M15 (NMOSFET), a discharge transistor M25 (NMOSFET), and a gate capacitor C25.

  The drain of the charge transfer transistor M15 is connected to the output end of the negative boost unit 40 as the input end of the negative boost unit 50. The source of the charge transfer transistor M15 is connected as the output end of the negative boosting unit 50 to the output end of the output voltage VN.

  The gate of the discharge transistor M25 is connected to the drain of the charge transfer transistor M15. The drain of the discharge transistor M25 is connected to the gate of the charge transfer transistor M15. The source and back gate of the discharge transistor M25 are both connected to the source of the charge transfer transistor M15.

  The first end of the gate capacitor C25 is connected to the gate of the charge transfer transistor M15. The second end of the gate capacitor C25 is connected as the clock input end to the input end of the clock signal CLK1.

  The first end of the output capacitor Co is connected to the output end of the output voltage VN. The second end of the output capacitor Co is connected to the application end of the ground voltage VSS.

  Thus, negative boosting units 10 to 50 are connected in series between the input end of ground voltage VSS and the output end of output voltage VN, and are driven using four-phase clock signals CLK1 to CLK4 different in phase. Be done.

<4 phase clock drive>
FIG. 2 is a timing chart showing four-phase clock driving, in which the clock signals CLK1 to CLK4 are depicted in order from the top. The clock signals CLK1 to CLK4 are all pulsed between a high level (for example, the power supply voltage VCC) and a low level (for example, the ground voltage VSS).

  In the example of this figure, the clock signal CLK1 rises to high level at time t4, and falls to low level at time t5. The clock signal CLK2 falls to low level at time t1, rises to high level at time t8, and falls to low level at time t9. The clock signal CLK3 rises to high level at time t2 and falls to low level at time t7. The clock signal CLK4 falls to low level at time t3 and rises to high level at time t6.

  In the period T1 (= time t1 to t2), the clock signals CLK1 to CLK3 are at low level, and the clock signal CLK4 is at high level. Since the gate-source voltage of the charge transfer transistor M12 decreases via the gate capacitor C22 with the falling of the clock signal CLK2 at time t1, the charge transfer transistor M12 is turned off. The same applies to the charge transfer transistor M14.

  In the period T2 (= time t2 to t3), the clock signals CLK1 and CLK2 become low level, and the clock signals CLK3 and CLK4 become high level. Since the gate-source voltage of the discharge transistor M22 rises via the flying capacitor C11 with the rise of the clock signal CLK3 at time t2, the discharge transistor M22 is turned on. The same applies to the discharge transistor M24. On the other hand, when the clock signal CLK3 rises to the high level, the voltage between the gate and the source of the discharge transistor M21 decreases via the flying capacitor C11, and the discharge transistor M21 turns off.

  In the period T3 (= time t3 to t4), the clock signals CLK1, CLK2 and CLK4 are at low level, and the clock signal CLK3 is at high level. Since the voltage between the gate and the source of the discharge transistor M23 decreases via the flying capacitor C12 with the falling of the clock signal CLK4 at time t3, the discharge transistor M23 is turned off. The same applies to the discharge transistor M25.

  In the period T4 (= time t4 to t5), the clock signals CLK2 and CLK4 become low level, and the clock signals CLK1 and CLK3 become high level. Since the gate-source voltage of the charge transfer transistor M11 rises via the gate capacitor C21 with the rise of the clock signal CLK1 at time t4, the charge transfer transistor M11 is turned on. The same applies to the charge transfer transistors M13 and M15.

  In the period T5 (= time t5 to t6), the clock signals CLK1, CLK2 and CLK4 are at low level, and the clock signal CLK3 is at high level. Since the gate-source voltage of the charge transfer transistor M11 decreases via the gate capacitor C21 with the falling of the clock signal CLK1 at time t5, the charge transfer transistor M11 is turned off. The same applies to the charge transfer transistors M13 and M15.

  In the period T6 (= time t6 to t7), the clock signals CLK1 and CLK2 become low level, and the clock signals CLK3 and CLK4 become high level. Since the gate-source voltage of the discharge transistor M23 rises via the flying capacitor C12 with the rise of the clock signal CLK4 at time t6, the discharge transistor M23 turns on. The same applies to the discharge transistor M25.

  In the period T7 (= time t7 to t8), the clock signals CLK1 to CLK3 are at low level, and the clock signal CLK4 is at high level. Since the voltage between the gate and the source of the discharge transistor M22 is lowered via the flying capacitor C11 with the fall of the clock signal CLK3 at time t7, the discharge transistor M22 is turned off. The same applies to the discharge transistor M24. On the other hand, when the clock signal CLK3 falls to a low level, the voltage between the gate and the source of the discharge transistor M21 rises via the flying capacitor C11, and the discharge transistor M21 turns on.

  In the period T8 (= time t8 to t9), the clock signals CLK1 and CLK3 are at low level, and the clock signals CLK2 and CLK4 are at high level. Since the voltage between the gate and the source of the charge transfer transistor M12 rises via the gate capacitor C22 with the rise of the clock signal CLK2 at time t8, the charge transfer transistor M12 is turned on. The same applies to the charge transfer transistor M14.

  As described above, by repeating the periods T1 to T8 in synchronization with the four phase clock signals CLK1 to CLK4 different in phase, the negative output voltage VN lower than the ground voltage VSS (= 0 V) is generated. .

<Low potential hold circuit>
Returning to FIG. 1, the circuit configuration of each of the low potential hold circuits 110 to 150 will be individually and specifically described.

  Low potential hold circuit 110 includes transistors M30 and M31 (both are NMOSFETs). The drain of the transistor M30 and the gate of the transistor M31 are both connected to the drain of the charge transfer transistor M11. The gate of the transistor M30 and the drain of the transistor M31 are both connected to the source of the charge transfer transistor M11. The source and back gate of each of the transistors M30 and M31 are both connected to the back gate of the charge transfer transistor M11.

  Low potential hold circuit 120 includes transistors M32 and M33 (both are NMOSFETs). The drain of the transistor M32 and the gate of the transistor M33 are both connected to the drain of the charge transfer transistor M12. The gate of the transistor M32 and the drain of the transistor M33 are both connected to the source of the charge transfer transistor M12. The source and back gate of each of the transistors M32 and M33 are both connected to the back gate of the charge transfer transistor M12.

  Low potential hold circuit 130 includes transistors M34 and M35 (both are NMOSFETs). The drain of the transistor M34 and the gate of the transistor M35 are both connected to the drain of the charge transfer transistor M13. The gate of the transistor M34 and the drain of the transistor M35 are both connected to the source of the charge transfer transistor M13. The source and back gate of each of the transistors M34 and M35 are both connected to the back gate of the charge transfer transistor M13.

  Low potential hold circuit 140 includes transistors M36 and M37 (both are NMOSFETs). The drain of the transistor M36 and the gate of the transistor M37 are both connected to the drain of the charge transfer transistor M14. The gate of the transistor M36 and the drain of the transistor M37 are both connected to the source of the charge transfer transistor M14. The source and back gate of each of the transistors M36 and M37 are both connected to the back gate of the charge transfer transistor M14.

  Low potential hold circuit 150 includes transistors M38 and M39 (both are NMOSFETs). The drain of the transistor M38 and the gate of the transistor M39 are both connected to the drain of the charge transfer transistor M15. The gate of the transistor M38 and the drain of the transistor M39 are both connected to the source of the charge transfer transistor M15. The source and back gate of each of the transistors M38 and M39 are both connected to the back gate of the charge transfer transistor M15.

  For example, when the voltage of the source of the charge transfer transistor M11 is lower than that of the drain, the transistor M30 is turned off and the transistor M31 is turned on. Therefore, the back gate of the charge transfer transistor M11 is connected to the source of the charge transfer transistor M11 via the transistor M31. On the contrary, when the drain of the charge transfer transistor M11 has a voltage lower than that of the source, the transistor M30 is turned on and the transistor M31 is turned off. Therefore, the back gate of the charge transfer transistor M11 is connected to the drain of the charge transfer transistor M11 via the transistor M30.

  That is, the low potential hold circuit 110 switches the connection destination of the back gate of the charge transfer transistor M11 to either the drain or the source on the low potential side. The same applies to the low potential hold circuits 120-150.

  Next, the significance of introducing the low potential hold circuits 110 to 150 will be described in detail with reference to FIGS.

  3 and 4, under the assumption that the low potential hold circuit 110 to 150 is not introduced into the negative boost charge pump 1, respectively, and the back gate and the source of the charge transfer transistor M15 are shorted. FIG. 18A is a circuit diagram and a vertical cross-sectional view showing how a parasitic element is attached to the charge transfer transistor M15.

  As shown in both figures, when the low potential hold circuit 150 is not introduced, the charge transfer transistor M15 is accompanied by a parasitic diode D1 and an npn type parasitic transistor Q1.

  The parasitic diode D1 uses the P-type well 204 (or P-type impurity diffusion layer 221) corresponding to the back gate BG of the charge transfer transistor M15 as an anode and an N-type impurity diffusion layer corresponding to the drain D of the charge transfer transistor M15. It is attached to make 215 a cathode.

  On the other hand, parasitic transistor Q1 is based on P-type well 204 (or P-type impurity diffusion layer 221), N-type impurity diffusion layer 215 as an emitter, and N-type well 201 including P-type well 204 as a collector. It is attached to.

  Here, a predetermined substrate voltage (for example, ground voltage VSS) is applied to P-type semiconductor substrate 200, and a constant voltage (for example, ground voltage VSS or power supply voltage VDD) higher than the substrate voltage is applied to N-type well 201. Is applied.

  Basically, since the source voltage VS (= output voltage VN) of the charge transfer transistor M15 is lower than the drain voltage VD, the PN junction between the P-type well 204 and the N-type impurity diffusion layer 205 is forward biased. Absent.

  However, if the back gate potential of the charge transfer transistor M15 rises due to any factor and the PN junction becomes forward biased, latchup of the parasitic diode D1 and the parasitic transistor Q1 occurs.

  When such latchup occurs, the collector current of the parasitic transistor Q1 charges the node voltage (= the drain voltage VD of the charge transfer transistor M15) appearing at the first end of the flying capacitor C14. As a result, the amount of charge transfer transferred from the drain D to the source S of the charge transfer transistor M15 decreases, so the efficiency of the negative boost charge pump 1 decreases.

  In FIGS. 3 and 4, although only the charge transfer transistor M15 of the last stage is focused on, in the negative charge pump charge pump 1 provided with a plurality of negative boost units 10 to 50, as shown in FIG. Since the charge transfer transistors M11 to M15 are accompanied by the parasitic diode D1 and the parasitic transistor Q1, each has the same problem as described above.

  Therefore, in the negative booster charge pump 1, as described above, the low potential hold circuit 110 switches the connection destination of the back gate of each of the charge transfer transistors M11 to 15 to either the drain or the source of the respective low potential side. ~ 150 has been introduced.

  FIG. 6 is a waveform diagram showing low potential hold operation in low potential hold circuit 150, and from the top, clock signals CLK1 to CLK4, gate voltage VG (solid line) of charge transfer transistor M15, drain voltage VD (small The dashed line), the source voltage VS (large dashed line), and the back gate voltage VBG (thick solid line) are depicted. The times t1 to t9 in this figure correspond to those in FIG. 2, respectively.

  As shown in the figure, the introduction of the low potential hold circuit 150 lowers the back gate voltage VBG of the charge transfer transistor M15 by either the drain voltage VD or the source voltage VS (more precisely, this corresponds to the transistor M38). Alternatively, the voltage can be switched to the voltage further lowered by the drain-source voltage of M39) (see particularly time t3 to t4). The low potential hold circuits 110 to 140 may be understood in the same manner as described above.

  As described above, in the case of the negative boosted charge pump 1 of the comparative example in which the low potential hold circuits 110 to 150 are introduced, latchup of the parasitic diode D1 and the parasitic transistor Q1 can be suppressed. Is possible.

  However, since the drain and source of each of the charge transfer transistors M11 to M15 are short-circuited during the on period, the voltage difference between the drain voltage VD and the source voltage VS decreases. As a result, in the low potential hold circuit 110 to 150, the back gate voltage VBG of each of the charge transfer transistors M11 to M15 can not be held at low impedance, so it is difficult to ensure the stable operation of the negative boost charge pump 1 Become. Hereinafter, an embodiment capable of solving the above-mentioned problems will be described.

First Embodiment
FIG. 7 is a circuit diagram showing a first embodiment of the negative boost charge pump 1. The negative boosting charge pump 1 of the present embodiment is based on the above-described comparative example (FIG. 1), and additional hold assist transistors M41 to M45 (NMOSFETs) are added. Therefore, the same components as in the comparative example will be assigned the same reference numerals as in FIG. 1 to omit duplicate descriptions, and the following description will be focused on the features of the first embodiment.

  As shown in the drawing, the drains of the hold assist transistors M41 to M45 are connected to the drains of the charge transfer transistors M11 to M15, respectively. The source and back gate of each of the hold assist transistors M41 to M45 are connected to the back gate of each of the charge transfer transistors M11 to M15.

  The gates of the hold assist transistors M41 to M45 are connected to the gates of the charge transfer transistors M11 to M15. By such connection, the hold assist transistors M41 to M45 are turned on / off in synchronization with the charge transfer transistors M11 to M15, respectively.

  FIG. 8 is a longitudinal sectional view of the negative boost charge pump 1 (in particular, the charge transfer transistor M15 of the final stage, the transistors M38 and M39 connected thereto, and the hold assist transistor M45).

  As shown in the figure, the P-type semiconductor substrate 200 (P-sub) of the semiconductor device in which the negative boost charge pump 1 is integrated includes N corresponding to an N-type buried layer (B / L [buried layer]). A mold well 201 is formed. A predetermined substrate voltage (for example, ground voltage VSS) is applied to P-type semiconductor substrate 200, and a constant voltage (for example, ground voltage VSS or power supply voltage VDD) higher than the substrate voltage is applied to N-type well 201. It is applied.

  In the N-type well 201, four P-type wells 202 to 205 are formed. The P-type wells 202 to 205 correspond to the back gates of the hold assist transistor M45, the transistor M38, the charge transfer transistor M15, and the transistor M39, respectively.

  In the N-type well 201, N-type impurity diffusion layers 206 to 210 are formed around the P-type wells 202 to 205, respectively. Each of the N-type impurity diffusion layers 206 to 210 corresponds to a contact of the N-type buried layer.

  N-type impurity diffusion layers 211 and 212, N-type impurity diffusion layers 213 and 214, N-type impurity diffusion layers 215 and 216, and N-type impurity diffusion layers 217 and 218 are formed in the P-type wells 202 to 205, respectively. It is done.

  The N-type impurity diffusion layers 211 and 212, the N-type impurity diffusion layers 213 and 214, and the N-type impurity diffusion layers 215 and 216, and the N-type impurity diffusion layers 217 and 218 are the hold assist transistor M45 and the transistor, respectively. It corresponds to the drain and source of M38, charge transfer transistor M15, and transistor M39, respectively.

  In addition, P-type impurity diffusion layers 219 to 222 are formed in the P-type wells 202 to 205, respectively. The P-type impurity diffusion layers 219 to 222 correspond to the contacts of the P-type wells 202 to 205, respectively.

  Further, on the channel region of each of the P-type wells 202 to 205, the hold auxiliary transistor M45, the transistor M38, the charge transfer transistor M15, and the gates 223 to 226 of the transistor M39 are formed.

  The drains (N-type impurity diffusion layers 211, 213, and 215) of the hold assist transistor M45, the transistor M38, and the charge transfer transistor M15, and the gate 226 of the transistor M39 are all connected to the application end of the drain voltage VD. ing.

  The gate 224 of the transistor M38, the source (N-type impurity diffusion layer 216) of the charge transfer transistor M15, and the drain (N-type impurity diffusion layer 217) of the transistor M39 all apply a source voltage VS (= output voltage VN). Connected to the end.

  The gate 223 of the hold assist transistor M45 and the gate 225 of the charge transfer transistor M15 are both connected to the application end of the gate voltage VG.

  Source and back gate (N-type impurity diffusion layer 212, P-type impurity diffusion layer 219) of hold auxiliary transistor M45, source and back gate (N-type impurity diffusion layer 214, P-type impurity diffusion layer 220) of transistor M38, charge transfer The back gate (P-type impurity diffusion layer 221) of the transistor 15 and the source and back gate (N-type impurity diffusion layer 218 and P-type impurity diffusion layer 222) of the transistor M39 are both application ends of the back gate voltage VBG. It is connected to the.

  The charge transfer transistor M15 is accompanied by parasitic diodes D1 and D2. More specifically, the parasitic diode D1 is attached such that the P-type well 204 is an anode and the N-type impurity diffusion layer 215 is a cathode. On the other hand, the parasitic diode D2 is attached such that the P-type well 204 is an anode and the N-type impurity diffusion layer 216 is a cathode.

  In addition, parasitic diodes D11 and D12 are additionally provided between the P-type wells 202 to 205 and the N-type well 201 and between the P-type semiconductor substrate 201 and the N-type well 201, respectively. More specifically, the parasitic diode D11 is attached such that each of the P-wells 202 to 205 is an anode and the N-well 201 is a cathode. On the other hand, the parasitic diode D12 is attached such that the P-type semiconductor substrate 200 is an anode and the N-type well 201 is a cathode.

  In view of the existence of such a parasitic element, FIG. 7 described above can be rewritten as shown in FIG. However, the N-type well 201 and the P-type wells 202 to 205 may be omitted, and the P-type semiconductor substrate 200 itself may be used as a back gate of the hold assist transistor M45, the transistor M38, the charge transfer transistor M15, and the transistor M39.

  As described above, in the negative boost charge pump 1 of this embodiment, a hold connected between the back gate and the drain of each of the charge transfer transistors M11 to M15 and turned on / off together with the charge transfer transistors M11 to M15 Auxiliary transistors M41 to M45 are added. Hereinafter, the operation and effects of the hold assist operation of the hold assist transistor M45 will be described as an example.

  FIG. 10 is a waveform diagram showing the hold assist operation of the hold assist transistor M45. Clock signals CLK1 to CLK4 are depicted in the upper part of the figure. Also, in the middle and lower parts of the figure, the gate voltage VG (solid line) and the drain voltage VD (small broken line) of the charge transfer transistor M15 are shown as the behavior of the voltage of each part when the hold assist transistor M45 is introduced / not introduced, respectively. , Source voltage VS (large dashed line) and back gate voltage VBG (thick solid line) are depicted. Times t1 to t8 in this figure correspond to those in FIG. 2 or FIG. 6, respectively.

  As shown in the lower part of the figure, when the hold assist transistor M45 is not introduced, the back gate of the charge transfer transistor M15 has a high impedance during the on period (= time t4 to t5) of the charge transfer transistor M15, and the back gate voltage VBG. Becomes indeterminate.

  On the other hand, as shown in the middle part of the figure, when the hold assist transistor M45 is introduced, the hold assist transistor M45 is turned on during the on period (= time t4 to t5) of the charge transfer transistor M15. The gate is shorted to the drain. As a result, the back gate voltage VBG is fixed to the drain voltage VD.

  Although the hold assist operation of the hold assist transistor M45 is illustrated in the drawing, the same function and effect as those described above can be obtained in the hold assist transistors M41 to M44.

  Thus, by introducing the hold assist transistors M41 to M45, the hold assist transistors M41 to M45 are turned on during the on period of each of the charge transfer transistors M11 to M15, and thus the back gates of the charge transfer transistors M11 to M15 are It can be maintained at low impedance. As a result, since the operation of parasitic transistor Q1 (see FIG. 3 or FIG. 5) which is difficult to quantitatively predict can be effectively suppressed, the operation stability of negative boost charge pump 1 can be improved. .

  The transistor M1 of Patent Document 1 is only turned on immediately before start-up to prevent latch-up, and is turned off during charge pump operation. Therefore, the transistor M1 corresponds to the above-described hold assist transistors M41 to M45. Absent.

  Further, the gate voltage setting MOS of Patent Document 2 only plays a role of a connection circuit connecting the "gate potential" of the transfer MOS to the drain, and does not correspond to the above-described hold assist transistors M41 to M45. .

Second Embodiment
FIG. 11 is a circuit diagram showing a second embodiment of the negative boost charge pump 1. As shown in the present embodiment, the drains of the hold assist transistors M41 to M45 may be connected to the sources of the charge transfer transistors M11 to M15.

Third Embodiment
FIG. 12 is a circuit diagram showing a third embodiment of the negative boost charge pump 1. As shown in the present embodiment, in the negative boosting unit 50 of the final stage, the drain is connected as the unit input end a to the output end of the negative boosting unit 140, and the gate, the source and the back gate are output voltages as the unit output end b. Only the N-channel charge transfer transistor M15 connected to the output terminal of VN may be included. The charge transfer transistor M15 thus connected functions as a charge transfer switch equivalent to a diode in which the cathode is connected to the unit input end a and the anode is connected to the unit output end b.

Fourth Embodiment
FIG. 13 is a circuit diagram showing a fourth embodiment of the negative boost charge pump 1. As shown in this embodiment, in the first stage negative boosting unit 60, the drain is connected as the unit input end a to the input end of the ground voltage VSS, and the gate, the source and the back gate are the negative boosting unit as the unit output end b. 10, a charge transfer transistor M16 (NMOSFET) connected to the input end, and a flying capacitor whose first end is connected to the unit output end b and whose second end is connected as the clock input end c to the input end of the clock signal CLK4 And C16 may be included. The charge transfer transistor M16 connected as described above functions as a charge transfer switch equivalent to a diode in which the cathode is connected to the unit input end a and the anode is connected to the unit output end b.

Fifth Embodiment
FIG. 14 is a circuit diagram showing a fifth embodiment of the negative boost charge pump 1. As shown in the present embodiment, in the first stage negative boosting unit 60, the source and the back gate are connected as the unit input end a to the input end of the ground voltage VSS, and the gate and the drain as the unit output end b 10, the charge transfer transistor M16P (PMOSFET) connected to the input end, and the flying having the first end connected to the unit output end b and the second end connected to the input end of the clock signal CLK4 as the clock input end c. A capacitor C16 may be included. The charge transfer transistor M16P connected as described above functions as a charge transfer switch equivalent to a diode in which the cathode is connected to the unit input terminal a and the anode is connected to the unit output terminal b.

<Nonvolatile Semiconductor Memory Device>
The above-mentioned negative boost charge pump 1 can be incorporated in a nonvolatile semiconductor memory device. For example, a flash memory that can electrically rewrite data requires high and negative voltages at the time of writing data. Therefore, by incorporating the negative boost charge pump 1 as negative voltage generation means of the flash memory, it is possible to generate a desired negative voltage inside the device by negatively boosting the power supply voltage supplied from the outside of the device. Become.

<Other Modifications>
In addition to the embodiments described above, various technical features disclosed in the present specification can be modified in various ways without departing from the scope of the technical creation. That is, the above embodiment should be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is not limited to the above embodiment, and claims It is to be understood that the scope and equivalent meaning and all modifications that fall within the scope are included.

  The negative boost charge pump disclosed in the present specification can be used, for example, as a negative voltage generation means of a nonvolatile semiconductor memory device.

1 negative boost charge pump 10 to 60 negative boost unit 110 to 150 low potential hold circuit M11 to M16 charge transfer transistor (NMOSFET)
M16P charge transfer transistor (PMOSFET)
M21 to M25 Discharge transistor (NMOSFET)
M30 to M39 First transistor, second transistor (NMOSFET)
M41 to M45 Hold assist transistor (NMOSFET)
C11 to C14, C16 Flying capacitor C21 to C25 Gate capacitor Co Output capacitor D1, D2, D11, D12 Parasitic diode Q1 Parasitic transistor (npn type)
a unit input end b unit output end c first clock input end d second clock input end 200 P type semiconductor substrate 201 N type well (N type buried layer)
202-205 P type well (back gate)
206 to 210 N-type impurity diffusion layer (contact of N-type buried layer)
211 to 218 N-type impurity diffusion layers (source, drain)
219 to 222 P-type impurity diffusion layer (contact of back gate)
223-226 gates

Claims (10)

A negative boost unit including a charge transfer transistor;
A low potential hold circuit that switches the connection destination of the back gate of the charge transfer transistor to either the drain or the source, whichever is lower;
A hold assist transistor connected between the back gate and the drain or source of the charge transfer transistor and turned on / off with the charge transfer transistor;
Have
A negative boost charge pump characterized by producing a negative output voltage lower than the ground voltage.   The negative boosting unit is connected in series between a plurality of stages between the input end of the ground voltage and the output end of the output voltage, and is driven using four-phase clock signals different in phase. The negative boost charge pump according to claim 1. The negative boost unit is
The charge transfer transistor having a drain connected to the unit input end and a source connected to the unit output end;
A discharge transistor having a gate connected to the unit input end, a drain connected to the gate of the charge transfer transistor, and a source and a back gate connected to the unit output end;
A flying capacitor whose first end is connected to the unit output end and whose second end is connected to the first clock input end;
A gate capacitor having a first end connected to the gate of the charge transfer transistor and a second end connected to a second clock input end;
The negative boost charge pump according to claim 1 or 2, comprising The low potential hold circuit
A first transistor having a drain connected to the drain of the charge transfer transistor, a gate connected to the source of the charge transfer transistor, and a source and a back gate connected to the back gate of the charge transfer transistor;
A second transistor having a drain connected to the source of the charge transfer transistor, a gate connected to the drain of the charge transfer transistor, and a source and a back gate connected to the back gate of the charge transfer transistor;
The negative boost charge pump according to claim 3, comprising   5. The negative boost charge pump according to claim 4, wherein the charge transfer transistor, the discharge transistor, the first transistor, and the second transistor are all N-channel type.   3. The negative boosting unit according to claim 2, wherein the negative boosting unit includes an N-channel charge transfer transistor having a drain connected to the unit input end and a gate, a source and a back gate connected to the unit output end. Negative boost charge pump.   The first negative boosting unit has an N channel charge transfer transistor whose drain is connected to the unit input end and whose gate, source and back gate are connected to the unit output end, and whose first end is connected to the unit output end 3. The negative boost charge pump of claim 2, further comprising: a flying capacitor having a second end connected to the clock input.   The first negative boosting unit has a source and a back gate connected to the unit input end and a gate and a drain connected to the unit output end, and a first end connected to the unit output end. 3. The negative boost charge pump of claim 2, further comprising: a flying capacitor having a second end connected to the clock input. A semiconductor device formed by integrating the negative boost charge pump according to claim 5;
P-type semiconductor substrate,
An N-type well formed on the P-type semiconductor substrate;
A plurality of P-type wells formed in the N-type well;
Have
A semiconductor device characterized in that the charge transfer transistor, the hold auxiliary transistor, the first transistor, and the second transistor use the plurality of P-type wells as back gates, respectively.   A non-volatile semiconductor memory device comprising the negative boost charge pump according to any one of claims 1 to 8.

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