JP3040885B2 - Voltage booster circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage boosting circuit, and more particularly, to a voltage boosting circuit (a so-called charge pump circuit) which boosts a power supply voltage on a chip to generate a desired high voltage. Generally, an EEPROM (electrically erasable
programmable read only memory) and LCD (liquid cr
A semiconductor integrated device that requires a voltage higher than the power supply voltage, such as a ystal display driver, includes a voltage booster circuit (a so-called charge pump circuit) inside the chip, thereby realizing a single power supply operation. ing.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram of a conventional voltage boosting circuit.
You. T₁~ T_FourIs a MOS transistor connected in series
And the MOS transistor T located at the right end₁Game
Is the power supply V_CCConnected to another MOS transistor T
_Two~ T_FourThe gate of the transistor T_n(N is 2
4; the same applies hereinafter) and the preceding MOS transistor
T _n-1N to the source of_n-1Connected to
You. Each node N₁~ N_FourHas a capacitor C₁
~ C_FourOf the capacitor C₁~ C _Four
Is connected to a two-phase clock signal that does not overlap each other.
Source φ₁, Φ_TwoAre connected alternately.

According to such a configuration, φ₁= H level
(V_CC), Φ_Two= L level (0V)
And node N₁To N_TwoTo, N_ThreeTo N_FourTo, ..., to
And the current flows, N_m(M is an arbitrary odd number)_{m + 1}
More about V_TH(MOS transistor threshold voltage) high
Potential. Next, φ₁Falls to the L level,
N ₁, N_Three, N_m, ……, is φ₁Amplitude
(V_CC) Only, due to the capacitance coupling
However, because current is supplied from the left side,
To φ₁Is higher than when L is at the L level. Next
And φ_TwoBecomes H level, then N_m-1To N_mWhat
Current is supplied, and φ_TwoReturns to L level and N
_m-2To N_m-1Is supplied with current, so that N_m-1No electricity
The position rises from the previous cycle. Thus from the left
When a current flows to the right and the steady state is reached, the potential per stage
Rises according to the following equation:

ΑV _OSC −V _TH (1) where α: Coupling ratio of C ₁ , C ₂ ,... (Ratio to capacitance including other stray capacitances) V _OSC : clock voltage φ ₁ , φ ₂ of the amplitude (= V _CC) V _TH: threshold voltage of the MOS transistor

[0005]

SUMMARY OF THE INVENTION
In a conventional voltage boosting circuit, the rise per stage is V
_THOnly this V_THIs due to the substrate bias effect
The larger the number of stages, the larger the number of stages.
Accordingly, there is a problem that the boosting efficiency is deteriorated. [Objective] Accordingly, the present invention has been made in view of such problems.
The boost efficiency is not deteriorated even if it is connected in multiple stages.
The purpose of the present invention is to provide a voltage booster circuit.

[0006]

According to the present invention, a plurality of MOs are provided as shown in FIG.
A first transistor array A including S transistors T _1A and T _2A and a second transistor array B including the same number of MOS transistors T _1B and T _{2B as} the first transistor array A; Each node N _1A ,
Capacitors C _1A , N _2A , N _1B , N _2B and non-overlapping two-phase clock power supplies φ ₁ , φ ₂ respectively.
C _2A , C _1B and C _2B are connected, and the gates of the MOS transistors T _1A and T _2A constituting the first transistor row A are connected to the nodes N _1B and N _2B of the second transistor row B. In addition, the gate of each of the MOS transistors T _1B and T _2B constituting the second transistor row B is connected to each of the nodes N _1A and N _2A of the first transistor row A. Note that _Vin1A and _Vin1B are the input voltages,
_{out1 A,} V _out1B is boosted output voltage.

[0007]

According to the present invention, the two transistor arrays A and B perform a complementary chain operation, and the respective transistor arrays A and
The MOS transistors T _1A , T _2A , T _1B ,
Since the node potential of the other transistor row is given to the gate of T _2B , even if V _TH increases due to the substrate bias effect, it does not affect the boosting operation and avoids the deterioration of boosting efficiency due to the increase in the number of stages. Is done.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.
I do. 2 to 8 show one embodiment of a voltage booster circuit according to the present invention.
It is a figure showing an example. First, the configuration will be described. Figure 2
A_TenIs three MOS transistors T_{Ten A}, T_11A,
T_12AFirst transistor configured by connecting in series
Column, B_TenIs also the three MOS transistors T_10B, T
_11B, T_12BConnected in series to form a second transistor
It is a star row. Note that these six MOS transistors
T_iA, T_iB(I is 10, 11, 12) is n channels
And each gate is a transistor row on the other side.
Connected to the node. That is, the first transition
Star row A_TenT_10A, T_11A, T_12AEach gate of the
2 transistor row B _TenNode N_10B, N_11B, N
_12BAnd the second transistor row B_Tenof
T_10B, T_11B, T_12BGates of the first transistor
Star row A_TenNode N_10A, N_11A, N_12AConnected to
ing. Here, each transistor row A_Ten, B_TenBelow
(Bottom of drawing)_in10A, V_in10BGive
Output voltage V boosted from the upper side_out10A, V_out10BTo
If it is taken out, the potential relation of six nodes (however,
And the steady state) is as follows.

[0009] _{N 10A = N 10B <N 11A} = N 11B <N 12A = N 12B ...... (1) each node N _iA, the N _iB, capacitor C _10A, C _{11A,
C 12A, C 10B, C 11} B, one end of the C _12B are connected respectively, the capacitor C _iA, the other end of the C _iB are two-phase clock power phi ₁ of the non-overlap, connected to each alternately phi ₂ Have been. Specifically, C _10A , C _12A and C _11B are connected to φ ₂ , and the remaining C _11A , C _10B and C _12B
There has been connected to the φ _1. It is also possible to the phi ₁ and phi ₂ in opposite.

Next, the operation will be described. In this embodiment, each node N _iA transistors column A _10, B _10, the potential of the N _iB is, the capacitor C _iA, the capacitance coupling by C _iB, predetermined amplitude (phi _1, phi ₂ of the amplitude, preferably the _V in10A, V in10B the same amplitude; conveniently changed alternately V _CC), for example, N _10A and N _10B, N _12A and N
_{When 12B} is at L level (or H level), N _11A and N
_11B becomes H level (or L level). When an arbitrary node (for example, N _10B ) changes to L level,
Two MOS transistors T connected to the node N _10B
Of the _10B and _T11B , the input side _T10B is turned on, and the output side _T11B is turned off. This node of the transistor rows A ₁₀ on the other side of the gate potential of T _10B N
Supplied from _10A, since the gate potential of T _11B has given from the node N _11A of the transistor column A _10.

Therefore, the potential of N _10B becomes V _in10B (V _CC ) through T _10B when φ ₁ becomes L level.
Then, when φ ₁ = H level,
φ ₁ change (ie, V _CC ) + V _in10B (ie, V
_CC ), the potential of the node N _{10B in} the first stage changes between V _CC (φ ₁ = L level) and 2 × V _CC (φ ₁ = H level), and the boost amount is “ V _CC ".

Also, a second-stage node (for example, N_11B)of
The potential is φ_TwoBecomes low level, T_11BThrough
And N_10BPotential (at this time φ₁= H level,
N_{Ten B}= 2 × V_CC), Then φ_Two= H level
When it becomes_Two(Ie, V_CC) + N
_10BPotential (ie, 2 × V_CC)
Stage N_11BIs 2 × V_CC(Φ_Two= L level
3) V_CC(Φ _Two= H level).
The boost amount of “V” is the same as in the first stage._CC".

A third node (for example, N_12B)of
The potential is φ₁Becomes low level, T_12BThrough
And N_11BPotential (at this time φ_Two= H level,
N_{11 B}= 3 × V_CC), Then φ₁= H level
When it becomes₁(Ie, V_CC) + N
_11BPotential (ie, 3 × V_CC), So 3
Stage N_12BIs 3 × V_CC(Φ₁= L level
4) V_CC(Φ ₁= H level).
The boosted voltage of “V” is the same as in the first and second stages._CC".

As described above, in this embodiment, the boosted voltage of each stage can be set to “V _CC ”. For example, if the booster is constituted by three stages as shown in FIG. 2, the nodes N _12A , N _12B
From the above, the input voltages _Vin10A and _VinB are increased up to 4 times
Output voltage _{V ou} t10A which has been boosted to _CC ", it is possible to take out the _V out10B. Moreover, since the boosted voltage of each stage is " _Vcc " and is not affected by _VTH as in the conventional example at the beginning, even if _VTH increases due to the substrate bias effect,
The boosting efficiency does not deteriorate.

Further, in this embodiment, since the boosted voltage per stage is larger than that of the conventional example (at least there is a difference of V _TH ), a desired boosted voltage can be generated with a small number of stages, and viewed from the load side. The impedance of the boosted voltage circuit (so-called power supply impedance) can be reduced according to the difference in the number of stages. This means that a large current can be supplied to the load, which can be suitable for various semiconductor integrated devices.

Note that, as shown in FIG.
A MOS for load is provided on the input side of the voltage booster circuit (the circuit of FIG. 2).
Transistor T_13A, T_13BConnect this Transis
T _13A, T_13BInput voltage V_in10A, V_in10B
Or as shown in FIG.
As described above, the input of the voltage booster circuit (the circuit of FIG.
MOS transistor T_14A, T_15A, T_16Aas well as
Capacitor C_14A, C _15AFirst charge pong consisting of
Circuit A_{twenty one}And the MOS transistor T_14B, T _15B, T
_16BAnd capacitor C_14B, C_15BThe second cha consisting of
Charge pump circuit B_{twenty one}May be connected. This
For example, charge pump circuit A_{twenty one}, B_{twenty one}And the voltage of the above embodiment
The input voltage V_in10A, V_in10BTwo steps
Can be boosted by holding, and a larger output voltage V_out10A, V
_out10BCan be obtained.

As shown in FIG. 5, the voltage booster circuit of the above embodiment (the circuit of FIG. 2, the circuit of FIG. 3, or the circuit of FIG. 4)
MOS transistors T _17A , T _18A , T
_An output circuit comprising _17B , T _18B and capacitors C _16A , C _16B may be provided. According to _{this, φ 1 = (V out10B =} 4 × V CC) T 17B when the H level is turned on, _{also, (V out10A = 4 × V} CC) when phi ₂ = H level T
Since _17A is turned on, phi _1, phi ₂ of the H level in synchronization with V _Out10A onto a single output line, V _Out10B can be taken out alternately, the output voltage V with a 4 × V _CC constant potential
_{out10A + 10B} can be generated.

FIG. 6 shows the configuration of FIGS. 2, 3 and 5.
FIG. 4 is an overall circuit diagram including an n-channel MOS transistor.
This is an example in which the configuration is made up of data. That is, A₃₁Is four MOS
Transistor T_21A~ T_24AFirst Transist consisting of
Row, B₃₁Is also the four MOS transistors T_21B~
T_24BAnd a second transistor row composed of
Jista row A₃₁, B₃₁Node N_20A~ N_24A, N_20B~
_24BAnd non-overlapping two-phase clock φ₁, Φ_TwoBetween
Has a capacitor C_20A~ C_24A, C_20B~ C_{twenty four B}Is connected
Have been. Also, the first and second transistor rows
A₃₁, B₃₁The input side of the load transistor T_25A, T
_25BInput voltage (V_CC) Is given
From the power side, the MOS transistor T_26A, T_27A, T
_26B, T_27BAnd capacitor C_25A, C_25BOut of
Through the power circuit 20, the final node N _24A, N_24Bof
The potential is alternately taken out. Note that C
_LAnd R _LRepresents the equivalent capacitance and equivalent resistance of the load, respectively.
ing.

FIG. 7 is similar to FIG. 2, FIG. 3 and FIG.
FIG. 13 is an overall circuit diagram including the configuration of FIG.
This is an example in which a transistor is used. That is, A₄₁Is three
MOS transistor T_31A~ T_33AThe first tiger consisting of
Transistor row, B₄₁Is also the three MOS transistors T
_31B~ T_33BAnd a second transistor row consisting of
Transistor row A₄₁, B₄₁Node N_30A~ N_33A, N
_30B~_33BAnd non-overlapping two-phase clock φ₁, Φ
_TwoCapacitor C between_30A~ C_33A, C_30B~ C_33B
Is connected. A first and a second transistor
Row A₄₁, B₄₁The input side of the load transistor T_34A,
T_34BInput voltage (V_SS), And
From the output side, a MOS transistor T_35A, T_36A, T
_35B, T _36BAnd capacitor C_34A, C_34BOut of
Node N of the last stage_33A, N_33Bof
The potential is alternately taken out.

FIG. 8 is a structural diagram of any two p-channel MOS transistors shown in FIG.
Is a p-type semiconductor substrate, 23 is an n-well, and 24-26 are n ⁺
A diffusion region, 27 to 30 are p diffusion regions, and 31 and 32 are gate electrodes. Two adjacent p diffusion regions (27 and 2
8 and 29 and 30) and thereby forming two p-channel type MOS transistor with a gate electrode 31, 32 on its top, and well contact are connected to n ⁺ diffusion regions 24 to 26 to V _SS.

[0021]

According to the present invention, with the above configuration, the boosting voltage per stage can be set to " _Vcc ".
By eliminating the influence of V _TH be connected in multiple stages can be provided exacerbated not the voltage boosting circuit boosting efficiency.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of one embodiment.

FIG. 3 is a configuration diagram of an input circuit which is preferable in addition to one embodiment.

FIG. 4 is a configuration diagram of a charge pump circuit which is preferable in addition to one embodiment.

FIG. 5 is a configuration diagram of an output circuit which is preferable in addition to one embodiment.

FIG. 6 is an overall circuit diagram of one embodiment constituted by n-channel MOS transistors.

FIG. 7 is an overall circuit diagram of one embodiment constituted by p-channel MOS transistors.

FIG. 8 is a structural diagram of a p-channel MOS transistor.

FIG. 9 is a circuit diagram of a conventional example.

[Explanation of symbols]

A: The first transistor rows B: second transistor rows C _iA, C _iB: capacitor N _iA, N _iB: node T _iA, T _iB: MOS transistors phi _1, phi _2: 2-phase clock source

Claims (1)

(57) [Claims] A plurality of MOS transistors (T)_1A, T_2A)
A first transistor row (A) composed of
MOS transistors (T_1B,
T_2B), Each node (N) of the transistor rows (A, B)._1A,
N_2A, N_1B, N_2B) And non-overlapping two-phase clock
Power supply (φ₁, Φ_Two) And a capacitor (C
_1A, C_2A, C_1B, C_2B), And each MOS transistor constituting the first transistor row (A) is connected.
Lanista (T_1A, T _2A) Gate to the second transistor
Node (N)_1B, N_2B)
Each MOS transistor constituting the second transistor row (B)
Lanista (T_1B, T _2B) Gate to the first transistor
Node (N)_1A, N_2A)
A voltage boosting circuit characterized by: