KR20160069046A - Method of driving display device - Google Patents

Abstract

The present invention relates to a gate driving circuit of a GIP structure located in the non-display region of a display panel. A method of driving a display device which includes a gate driving circuit comprising stages includes: a step of applying the blank reset signal of a high state and applying a gate high voltage to the low power line, when the display device is powered off. The stages are connected to gate lines, has: a pullup transistor; a pulldown transistor; and an auxiliary transistor connected to the pulldown transistor in parallel where a drain terminal is connected to a low power line, a source terminal is connected to a gate output terminal, and a gate terminal receives blank-reset signal. So, image quality can be improved.

Description

[0001] The present invention relates to a method of driving a display device,

[0001] The present invention relates to a display device, and more particularly, to a display device having a GIP (gate in panel) structure and capable of discharging a charge in a pixel by using a device inside a GIP circuit when power- And a method of driving the same.

2. Description of the Related Art [0002] As an information society develops, there has been a growing demand for display devices for displaying images. Recently, liquid crystal display devices (LCDs), plasma display panels (PDPs) Various flat display devices such as an organic light emitting diode (OLED) have been utilized.

Of these flat panel display devices, liquid crystal display devices are widely used because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

As a liquid crystal display device, an active matrix type liquid crystal display device in which a switching transistor is formed in each of pixels arranged in a matrix form is widely used.

In general, an active matrix type liquid crystal display device uses a display panel constituted of a gate wiring and a data wiring, a gate driving circuit connected to the display panel and outputting a gate signal, and a data driving circuit outputting a data signal.

On the other hand, recently, a liquid crystal display of a GIP (gate in panel) structure in which a gate driver circuit is directly formed on an array substrate of a display panel is used.

A conventional GIP structure liquid crystal display device uses a separate discharge circuit so that the screen can be turned off at a time when power is off. Referring to FIGS. 1 and 2, a separate discharge circuit will be described.

FIG. 1 is a view schematically showing a part of a liquid crystal display device of a conventional GIP structure, and FIG. 2 is a graph showing a waveform of a voltage applied to a gate wiring and a signal applied to a discharge circuit of a conventional liquid crystal display Timing diagram.

Referring to FIG. 1, in a liquid crystal display device of a conventional GIP structure, a pixel P provided with a switching transistor Ts is formed in a display area AA of a display panel 10. A gate drive circuit 20, which is a shift register circuit, is directly formed in the non-display area NA. The gate drive circuit 20 is composed of a stage SR connected to each of the gate lines GL and outputting a gate signal.

Outside the gate drive circuit 20, a signal wiring area SA is formed in which signal wirings for transmitting various signals to be applied to the gate drive circuit 20 and the discharge circuit DSC are formed.

On the other hand, a discharge circuit (DSC) connected to each of the gate lines GL is formed inside the gate drive circuit 20.

The source terminal S is connected to the gate line GL and the gate terminal and the drain terminal G and D are connected to the discharge gate signal and the discharge drain signal DSC_G and DSC_D, .

A common wiring region CA in which a common wiring for transmitting a common voltage is formed is located inside the discharge circuit DSC.

Referring to FIG. 2, when the display panel 10 displays an image as a power-on state, the stage SR normally operates to sequentially output the gate high voltage VGH. Thus, the pixel P is turned on by the gate high voltage VGH and is supplied with the data voltage transmitted through the data line DL.

The discharge circuit DSC does not operate at the time of power-on and is turned off. That is, the discharge gate signal and the discharge drain signal (DSC_G, DSC_D) in the state of the low power supply voltage (Vss) are applied to the gate terminal and the drain terminal (G, D).

When the display panel 10 is turned off, the operation of the stage SR is turned off and no voltage is outputted to the gate line GL.

On the other hand, the discharging circuit (DSC) operates simultaneously at the time of power-off. That is, the discharge gate signal and the discharge drain signals DSC_G and SC_D in the state of a high voltage, that is, the gate high voltage (VGH) state, are applied to the gate terminal and the drain terminal G and D, respectively. Thus, the discharge circuit DSC outputs the gate high voltage VGH to the gate wiring GL through the source terminal S, whereby the switching transistor Ts of the pixel P is turned on, The electric charge charged in the electric field P is discharged.

As described above, in the conventional case, a separate discharge circuit (DSC) is formed in the non-display area (NA) for the purpose of charge discharge at the time of power-off, and further a separate signal for driving the discharge circuit The wiring is formed in the non-display area NA. As a result, the width of the non-display area NA increases, and it is difficult to realize a narrow bezel which is a current trend.

Since the driving IC for outputting the signal for driving the display panel 10 requires a separate signal output pin for outputting the corresponding signal to the signal wiring for driving the discharging circuit DSC, As the signal output pin increases, the component cost increases.

In addition, since the common wiring region CA is relatively reduced by the formation of the discharge circuit (DSC), the resistance of the common wiring increases. This causes a common voltage deviation in the display panel 10, which causes a common voltage ripple to occur and a smear phenomenon, resulting in a problem of deterioration of image quality.

On the other hand, the above-described problems can occur not only in liquid crystal display devices but also in other types of display devices using a GIP structure.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention It is an object of the present invention to provide a method for reducing the width of a non-display area, reducing component cost, and improving picture quality in a display device of a GIP structure.

According to an aspect of the present invention, there is provided a gate driving circuit of a GIP structure located in a non-display region of a display panel, the gate driving circuit being connected to a plurality of gate wirings and including a pull-up transistor and a pull- And a gate driving circuit including a plurality of stages connected to the drain power supply line, a source terminal connected to the gate output terminal, and a gate terminal connected to the auxiliary reset transistor for receiving a blank reset signal, The method comprising: applying the blank reset signal in a high state during power-off of the display device; and applying a gate high voltage to the row power supply wiring.

Here, in the power-on state of the display device, the blank reset signal in a low state is applied for every frame, the blank reset signal in a high state is applied to a blank section between neighboring frames, And applying a power supply voltage.

The stage may include a reset transistor having a gate terminal applied with the blank reset signal, a drain terminal connected to the row power supply line, and a source terminal connected to the pull-down transistor.

The stage may include a flip-flop circuit having a Q output terminal connected to the gate terminal of the pull-up transistor and a Qb output terminal connected to the gate terminal of the pull-down transistor.

The display panel may be a liquid crystal panel or an organic light emitting device panel.

In the present invention, the auxiliary transistor provided in the gate driving circuit of the GIP structure is operated to perform the function of the discharging circuit upon power-off. As a result, it is not necessary to provide a separate discharge circuit and a separate signal wiring for driving the discharge circuit as in the prior art.

Therefore, the width of the non-display region where the gate driving circuit is formed can be reduced, and the low-speed bezel can be easily implemented.

Further, it is not necessary to provide the signal output pin for driving the discharge circuit to the drive IC, and the component cost can be reduced.

Further, the width of the common wiring region can be increased, and the resistance of the common wiring can be reduced, thereby preventing the common voltage ripple and the smear phenomenon and improving the image quality.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view schematically showing a part of a liquid crystal display device of a conventional GIP structure; Fig.
2 is a timing chart of signals applied to the discharge circuit of the conventional liquid crystal display device of the GIP structure and the voltage applied to the gate wiring.
3 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention.
4 is a view schematically showing a part of a non-display area and a display area of a liquid crystal display device according to an embodiment of the present invention;
5 is a view schematically showing a configuration of a stage of a gate drive circuit according to an embodiment of the present invention;
6 is a timing chart showing waveforms of signals applied to an auxiliary transistor of a stage and a voltage applied to a gate wiring according to an embodiment of the present invention;

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

As the display device according to the embodiment of the present invention, for example, a liquid crystal display device, an organic light emitting element display device, a plasma display device, or the like can be used as all kinds of display devices having a GIP structure. Hereinafter, for convenience of explanation, a liquid crystal display device will be described as an example.

FIG. 3 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention, and FIG. 4 is a view schematically showing a part of a non-display area and a display area of a liquid crystal display device according to an embodiment of the present invention .

3 and 4, a liquid crystal display 100 according to an embodiment of the present invention is a liquid crystal display of a GIP structure, which includes a display panel 110, a driving IC 200, a driving board 300, . ≪ / RTI >

A plurality of pixels P are arranged in a matrix form on the display panel 200 to constitute a display area AA for displaying an image and a non-display area NA formed around the display area AA.

The display panel 200 includes two substrates facing each other, for example, an array substrate, a counter substrate facing the array substrate, and a liquid crystal layer disposed between the two substrates.

On the array substrate of the display panel 200, a plurality of gate lines GL extending in the row direction as a first direction and a plurality of data lines DL extending in the column direction in the second direction are formed. As described above, a plurality of pixels P arranged in a matrix form are defined by gate lines and data lines GL and DL intersecting with each other.

In each pixel P, a switching transistor Ts connected to a gate wiring and data lines GL and DL is formed.

On the other hand, although not specifically shown, the switching transistor Ts is connected to the pixel electrode. A common electrode is formed corresponding to the pixel electrode. When a voltage is applied to the pixel electrode and the common electrode, an electric field is formed therebetween to drive the liquid crystal.

The pixel electrode, the common electrode, and the liquid crystal located between these electrodes constitute a liquid crystal capacitor. Each pixel P further includes a storage capacitor, which serves to store the data signal applied to the pixel electrode until the next frame.

Although not specifically shown, the liquid crystal display 100 may include a backlight unit as a light source for supplying light to the display panel 200. The backlight unit may be a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode (LED), or the like.

A gate drive circuit 120, which is a GIP circuit, may be formed in the non-display area NA of one side of the array substrate. On the other hand, the gate drive circuit 120 may be formed on both sides of the array substrate facing each other. In the embodiment of the present invention, for convenience of explanation, a case where the gate drive circuit 120 is formed on one side of the array substrate will be described as an example.

A signal for transmitting signals for driving the gate driving circuit 120 is provided outside the first area A1 which is the GIP area where the gate driving circuit 120 is formed in the non-display area NA where the gate driving circuit 120 is formed And a second region A2, which is a signal wiring region where wirings are formed, can be located. A third region A3, which is a common wiring region in which a common wiring for transmitting a common voltage to the inside of the display panel 110 is formed, may be located inside the first region A1.

The gate driving circuit 120 formed in the first area A1 is formed with a plurality of stages SR connected to each of the plurality of gate lines GL to output a gate signal.

In the power-on state of the liquid crystal display device 100, the plurality of stages SR sequentially output gate signals in units of row lines for every frame. That is, each stage SR outputs the gate high voltage during the horizontal period of the corresponding row line, and outputs the gate low voltage during the remaining time.

The switching transistor Ts of the pixel P connected to the gate line GL is turned on and the data signal transmitted through the data line GL in synchronization with the turn- And charged.

On the other hand, the blank reset signal BRST is applied to all of the plurality of stages SR at the blank time (see BT in FIG. 6) between adjacent frames, and accordingly, all of the stages SR are simultaneously reset (reset).

When the liquid crystal display device 100 is powered off, the gate driving circuit 120 performs a discharging operation in response to the power-off. That is, all of the plurality of stages SR simultaneously output the gate high voltage. As a result, charges charged in all the pixels P constituting the display panel 110 are discharged at the same time.

Particularly, the discharging operation of the gate driving circuit 120 at the time of power-off is performed by using an auxiliary transistor (also referred to as " discharging circuit ") that receives the blank reset signal BRST as an element constituted in the stage SR, 5 < / RTI > T7N).

Accordingly, it is not necessary to provide a separate discharge circuit and a separate signal wiring for driving the discharge circuit as in the prior art.

Accordingly, the width of the non-display area NA where the gate driving circuit 120 is formed can be reduced, and the inner bezel can be easily implemented. Further, it is not necessary to provide a signal output pin for driving the discharge IC of the driving IC 300, and thus the cost of parts can be reduced. In addition, it is possible to increase the width of the third region A3, which is the common wiring region, thereby reducing the resistance of the common wiring, thereby preventing the common voltage ripple and the smear phenomenon and improving the picture quality .

The gate drive circuit 120 that performs such a function will be described in more detail below.

A plurality of clock signals CLK and gate start signals CLK having different phases are provided as signals for driving the gate driving circuit 120 in the second area A2 located outside the first area A1, A gate control signal including a reset signal Vst and a blank reset signal BRST and signal lines for transmitting a power supply voltage such as a low power supply voltage Vss and a high power supply voltage Vdd may be formed. Furthermore, a ground line may be formed in the second area A2.

The driving IC 200 may be connected to the other side of the array substrate adjacent to one side of the array substrate on which the gate driving circuit 120 is formed.

The driving IC 200 corresponds to a data driving circuit for outputting a data signal to the data line DL. At least one driving IC 200 may be used for driving the display panel 200. For convenience of explanation, three driving ICs 200 are provided.

The driving IC 200 may be mounted on the flexible circuit film 210 on which the wiring pattern is formed and may be connected to the display panel 110 while being mounted on the flexible circuit film 210. As another example, the driving IC 200 may be configured to be mounted directly on the array substrate of the display panel 110 in a COG manner. In the embodiment of the present invention, for convenience of explanation, a case where the driver IC 200 is mounted on the flexible circuit film 210 is taken as an example.

The driving IC 200 positioned near the gate driving circuit 120 may be configured to output signals for driving the gate driving circuit 120 and may have a signal output pin for outputting these signals have.

As described above, according to the embodiment of the present invention, since the separate discharge circuit is not used, the drive IC 200 does not need to have the signal output pin for outputting the signal for driving the discharge circuit .

The driving IC 200 is connected to the driving board 300 through the flexible circuit film 310. A plurality of driving circuits for driving the display panel 200 are mounted on the driving board 300. For example, a timing controller 310, a power supply circuit 320, and the like may be mounted on the driving board 300.

The timing controller 310 receives image data and a timing signal from an external system, and aligns the image data and outputs the image data to the driving IC 200.

The power supply circuit 320 is capable of generating the common voltage Vcom, the high power supply voltage Vdd, and the low power supply voltage Vss, and generates the driving power for driving the liquid crystal display device 100.

Meanwhile, the power supply circuit 420 may be configured with a level shifter. The level shifter level-shifts the clock signal input from the timing controller 210, for example.

Hereinafter, the gate drive circuit 120 and its operation according to the embodiment of the present invention will be described in more detail with reference to FIGS. 5 and 6. FIG.

FIG. 5 is a view schematically showing a structure of a stage of a gate driving circuit according to an embodiment of the present invention, and FIG. 6 is a cross-sectional view of a gate driving circuit according to an embodiment of the present invention, Fig. 5 is a timing chart showing a waveform of voltage. Fig. Here, in FIG. 6, waveforms of voltages applied to the nth and (n + 1) th gate lines GLn and GLn + 1 are shown for convenience of explanation.

5, the stage SR of the gate driving circuit 120 according to the embodiment of the present invention includes a flip-flop circuit FF, a pull-up transistor Tpu, a pull-down transistor Tpd, And an auxiliary transistor T7N.

The flip-flop circuit FF is configured to include a plurality of transistors, and may have a Q output terminal connected to the pull-up transistor Tpu and a Qb output terminal connected to the pull-down transistor Tpd.

The Q output terminal and the Qb output terminal may be configured to output a signal having phases opposite to each other. For example, when the Q output terminal outputs a Q signal in a high state, the Qb output terminal outputs a Qb signal in a low state.

The pull-up transistor Tpu and the pull-down transistor Tpd operate in such a manner that the ON / OFF states of the pull-up transistor Tpu and the pull-down transistor Tpd are opposite to each other by the signal output of the flip-flop circuit FF.

That is, when the pull-up transistor Tpu is turned on, the pull-down transistor Tpd is turned off, and when the pull-up transistor Tpu is turned off, the pull-down transistor Tpd is turned on.

The corresponding clock signal CLK is applied to the source terminal of the pull-up transistor Tpu and the drain terminal is connected to the gate output terminal Vout which outputs the gate signal to the gate line GL.

The gate terminal of the pull-down transistor Tpd is connected to the Qb output terminal of the flip-flop circuit FF. The source terminal of the pull-down transistor Tpd is connected to the row power supply line VssL, and the drain terminal is connected to the gate output terminal Vout.

Here, referring to FIG. 6, when the liquid crystal display 100 is in the power-on state, the row power supply voltage Vss is continuously applied to the row power supply line VssL. On the other hand, when the liquid crystal display 100 is powered off, the gate high voltage VGH is applied to the row power supply line VssL.

In the power-on state of the liquid crystal display device 100, the stage SR operates normally. In a horizontal period corresponding to each frame Fi and Fi + 1, the pull-up transistor Tpu responds to the high- And the pull-down transistor Tpd is turned off in response to the low Qb signal so that the clock signal CLK in the state of the gate high voltage VGH through the pull-up transistor Tpu is applied to the gate output terminal Vout, . As a result, the gate high voltage VGH is applied to the corresponding gate wiring GL.

Alternatively, before and after the horizontal period of each frame Fi, Fi + 1, the pull-up transistor Tpu is turned off in response to the low Q signal and the pull-down transistor Tpd responds to the high Qb signal And the low power supply voltage Vss is output to the gate output terminal Vout through the pull-down transistor Tpd. That is, since the row power supply voltage Vss is applied to the row power supply line VssL, the row power supply voltage Vss is output to the gate output terminal Vout in the turn-on state of the pull-down transistor Tpd. As a result, a low power supply voltage Vss corresponding to a gate low voltage is applied to the corresponding gate wiring GL.

The auxiliary transistor T7N is arranged in parallel connection with the pull-down transistor Tpd. That is, the source terminal of the auxiliary transistor T7N is connected to the gate output terminal Vout, and the drain terminal is connected to the row power supply line VssL. The gate terminal of the auxiliary transistor T7N receives the blank reset signal BRST.

The auxiliary transistor T7N corresponds to a device which functions to mitigate the positive bias stress of the pull-down transistor Tpd. That is, the pull-down transistor Tpd continuously receives the high voltage during the time except for the horizontal period and outputs the low power supply voltage Vss, which causes a positive (+) bias stress. T7N are formed in the stage SR.

The auxiliary transistor T7N receives the blank reset signal BRST in the low state during each frame Fi and Fi + 1, thereby maintaining the turn-off state.

On the other hand, the blank reset signal BRST is applied in the blank interval BT between the neighboring frames Fi and Fi + 1, and the low power supply voltage Vss is applied to the gate output terminal Vout in response to the blank reset signal BRST. .

At this time, the pull-down transistor Tpd maintains the turn-off state and does not output a signal to the gate output terminal Vout.

To this end, the reset transistor Tre for turning off the pull-down transistor Tpd during the blank interval BT may be configured on the stage SR.

In such a reset transistor Tre, the gate terminal is supplied with the blank reset signal BRST, the drain terminal is connected to the row power supply line VssL, and the source terminal is connected to the gate terminal of the pull- .

Accordingly, the reset transistor Tre outputs the low power supply voltage Vss to the gate terminal of the pulled-down transistor Tpd by the blank reset signal BRST in the high-state in the blank section BT, Tpd) is turned off.

As described above, in the blank section BT, the auxiliary transistor T7N is operated to output the low power supply voltage Vss to the gate output terminal Vout in place of the pull-down transistor Tpd, thereby suppressing the stress of the pull- It can be mitigated.

Particularly, in the embodiment of the present invention, the auxiliary transistor T7N operates so as to function as a discharging circuit when the liquid crystal display device 100 is powered off.

That is, all of the stages SR configured in the gate driving circuit 120 are turned on when the power is turned off, the blank reset signal BRST is in a high state and the gate high voltage VGH is applied to the row power supply line VssL, (VGH) at the same time. Thus, the switching transistor Ts of all the pixels P in the display panel 110 is turned on, and the charge in the pixel P can be discharged.

The operation of the gate driving circuit 120 having the above-described configuration in the power on / off state will be described with reference to FIG.

First, in the power-on state of the liquid crystal display device 100, the row power supply voltage Vss is continuously applied to the row power supply line VssL. The blank reset signal BRST maintains the low state during each frame Fi and Fi + 1 and maintains the high state during the blank interval BT between the frames Fi and Fi + 1.

At this time, the pull-up transistor Tpu is turned on in the stage SR for every frame Fi and Fi + 1 to output the clock signal CLK, so that the gate high voltage VGH is And is output to the gate lines GLn and GLn + 1 of the corresponding row line.

The pull-down transistor Tpd is turned on and outputs the low power supply voltage Vss in a period other than the horizontal period of each frame Fi and Fi + 1, And outputted to the wiring lines GLn and GLn + 1.

Next, when the liquid crystal display 100 is powered off, the gate high voltage VGH is applied to the row power supply line VssL. Then, the blank reset signal BRST has a high state.

 At this time, the auxiliary transistor T7N is turned on in response to the blank reset signal BRST in a high state. Thus, the gate high voltage VGH applied to the row power supply line VssL through the auxiliary transistor T7N is output to the gate lines GLn and GLn + 1. That is, all the stages SR of the gate driving circuit 120 simultaneously output the gate high voltage VGH to the corresponding gate wiring GL.

As a result, the switching transistor Ts of all the pixels P in the display panel 110 is turned on, so that the electric charge in the pixel P is discharged through the data line DL.

In the foregoing description, the GIP type liquid crystal display device has been described. On the other hand, it is apparent that the above-described embodiment of the present invention can be applied to a display device such as an organic light emitting diode display device or a plasma display device which can directly form a driving circuit on a panel by the GIP method.

As described above, according to the embodiment of the present invention, the auxiliary transistor provided in the gate driving circuit of the GIP structure is operated to perform the function of the discharging circuit at the time of power-off. As a result, it is not necessary to provide a separate discharge circuit and a separate signal wiring for driving the discharge circuit as in the prior art.

Therefore, the width of the non-display region where the gate driving circuit is formed can be reduced, and the low-speed bezel can be easily implemented.

Further, it is not necessary to provide the signal output pin for driving the discharge circuit to the drive IC, and the component cost can be reduced.

Further, the width of the common wiring region can be increased, and the resistance of the common wiring can be reduced, thereby preventing the common voltage ripple and the smear phenomenon and improving the image quality.

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

100: liquid crystal display device 110: display panel
120: gate driving circuit 200: driving IC
210: flexible circuit film 300: driving board
310: timing controller 320: power supply circuit
Tpu: pull-up transistor
Tpd: pull-down transistor
T7N: auxiliary transistor
Tre: Reset transistor
BRST: blank reset signal
Vss: Low Supply Voltage
VGH: Gate high voltage
BT: Blank section

Claims (5)

A gate driving circuit of a GIP structure located in a non-display area of a display panel, the gate driving circuit being connected to a plurality of gate wirings, the pull-up transistor being connected in parallel with the pull-down transistor, The gate terminal of which is connected to the gate output terminal, and the gate terminal of which is provided with a plurality of stages including an auxiliary transistor receiving a blank reset signal,
Applying the blank reset signal in a high state when the display device is powered off and applying a gate high voltage to the row power supply wiring
And driving the display device.
The method according to claim 1,
In the power-on state of the display device,
Applying the blank reset signal in a low state during each frame, applying the blank reset signal in a high state to a blank section between neighboring frames, and applying a low power supply voltage to the row power supply wiring
And driving the display device.
The method according to claim 1,
The stage includes a reset transistor having a gate terminal applied with the blank reset signal, a drain terminal connected to the row power supply line, and a source terminal connected to the pull-down transistor
A method of driving a display device.
The method according to claim 1,
The stage includes a flip-flop circuit having a Q output terminal connected to the gate terminal of the pull-up transistor and a Qb output terminal connected to the gate terminal of the pull-down transistor
A method of driving a display device.
The method according to claim 1,
The display panel may be a liquid crystal panel or an organic light emitting device panel
A method of driving a display device.

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