KR102296787B1 - Method of driving display device - Google Patents

Abstract

The present invention is a gate driving circuit of a GIP structure positioned in a non-display area of a display panel, each connected to a plurality of gate wirings, a pull-up transistor, a pull-down transistor, and the pull-down transistor connected in parallel with the pull-down transistor, and a drain terminal is connected to a low power wiring and A method of driving a display device comprising: a gate driving circuit configured with a plurality of stages connected to each other, a source terminal connected to a gate output terminal, and a gate terminal including an auxiliary transistor to which a blank reset signal is applied, wherein the display device is powered off , and applying the blank reset signal in a high state and applying a gate high voltage to the low power wiring.

Description

Method of driving display device

The present invention relates to a display device, and more particularly, to a display device capable of discharging electric charges in a pixel by using an element inside a GIP circuit when power is turned off in a display device having a gate in panel (GIP) structure. It relates to the driving method of

As the information society develops, the demand for a display device for displaying an image is increasing in various forms, and in recent years, a liquid crystal display device (LCD), a plasma display panel (PDP), an organic Various flat display devices such as an organic light emitting diode (OLED) are being used.

Among these flat panel display devices, the liquid crystal display device is widely used because it has the advantages of miniaturization, light weight, thinness, and low power driving.

As a liquid crystal display device, an active matrix type liquid crystal display device in which switching transistors are formed in each pixel arranged in a matrix form is currently commonly used.

In general, an active matrix type liquid crystal display device uses a display panel including gate wirings and data wirings, a gate driving circuit connected to the display panel for outputting a gate signal, and a data driving circuit for outputting a data signal.

Meanwhile, recently, a liquid crystal display device having a gate in panel (GIP) structure in which a gate driving circuit is directly formed on an array substrate of a display panel has been used.

The conventional GIP-structured liquid crystal display uses a separate discharge circuit so that the screen can be switched to the off state in a short time when the power is turned off, which will be described with reference to FIGS. 1 and 2 .

1 is a diagram schematically showing a part of a liquid crystal display having a conventional GIP structure, and FIG. 2 is a diagram showing waveforms of a signal applied to a discharge circuit and a voltage applied to a gate wiring of a liquid crystal display of a conventional GIP structure. It's a timing diagram.

Referring to FIG. 1 , in a conventional liquid crystal display having a GIP structure, a pixel P having a switching transistor Ts is formed in the display area AA of the display panel 10 . In addition, the gate driving circuit 20 which is a shift register circuit is directly formed in the non-display area NA. The gate driving circuit 20 includes a stage SR that is connected to each of the gate lines GL and outputs a gate signal.

A signal wiring area SA in which signal wirings for transmitting various signals applied to the gate driving circuit 20 and the discharge circuit DSC are formed is located outside the gate driving circuit 20 .

Meanwhile, a discharge circuit DSC connected to each of the gate lines GL is formed inside the gate driving circuit 20 .

The discharge circuit DSC is composed of a transistor, the source terminal S is connected to the gate wiring GL, and the gate and drain terminals G and D are respectively a discharge gate signal and a discharge drain signal DSC_G and DSC_D. will be authorized

A common wiring area CA in which a common wiring transmitting a common voltage is formed is positioned inside the discharge circuit DSC.

Referring to FIG. 2 , when the display panel 10 displays an image in a power-on state, the stage SR operates normally to sequentially output the gate-high voltage VGH. Accordingly, the pixel P is turned on by the gate high voltage VGH to receive the data voltage transmitted through the data line DL.

The discharge circuit DSC does not operate when the power is turned on and is turned off. That is, the discharge gate signal and the discharge drain signals DSC_G and DSC_D in the low power supply voltage Vss state are applied to the gate and drain terminals G and D.

When the display panel 10 is powered off, the operation of the stage SR is turned off so that a voltage is not output to the gate line GL.

On the other hand, the discharge circuits DSC are all operated at the same time when the power is off. That is, the high voltage, that is, the discharge gate signal and the discharge drain signals DSC_G and SC_D in the state of the gate high voltage VGH are applied to the gate and drain terminals G and D. Accordingly, the discharge circuit DSC outputs the gate high voltage VGH to the gate wiring GL through the source terminal S, and accordingly, the switching transistor Ts of the pixel P is turned on, and the pixel The charge inside (P) is discharged.

As described above, in the conventional case, a separate discharge circuit (DSC) is formed in the non-display area (NA) for the purpose of discharging charges during power-off, and further, a separate signal for driving the discharge circuit (DSC) is formed. A wiring is formed in the non-display area NA. Accordingly, the width of the non-display area NA increases, so that it is difficult to implement a narrow bezel, which is a current trend.

In addition, since the driving IC for outputting a signal for driving the display panel 10 requires a separate signal output pin for outputting a corresponding signal to a signal line for driving the discharge circuit DSC, such a As the signal output pin increases, the component cost increases.

In addition, since the common wiring area CA is relatively decreased according to the formation of the discharge circuit DSC, the resistance of the common wiring is increased. Accordingly, a common voltage deviation occurs within the display panel 10 , and thus a common voltage ripple occurs and a smear phenomenon is induced, resulting in a problem of deterioration of image quality.

On the other hand, the above problem may occur not only in the liquid crystal display device but also in other types of display devices using the GIP structure.

An object of the present invention is to provide a method capable of reducing the width of a non-display area, reducing component cost, and improving image quality in a display device having a GIP structure.

In order to achieve the above object, the present invention provides a gate driving circuit of a GIP structure located in a non-display area of a display panel, each connected to a plurality of gate wirings, and a pull-up transistor, a pull-down transistor, and the pull-down transistor are parallel to each other. driving a display device including a gate driving circuit configured with a plurality of stages including auxiliary transistors connected to the In the method, when the display device is powered off, the method includes applying the blank reset signal in a high state and applying a gate high voltage to the low power supply line.

Here, in the power-on state of the display device, the blank reset signal in a low state is applied for every frame, the blank reset signal in a high state is applied to a blank section between adjacent frames, and a low state is applied to the low power wiring. It may include the step of applying a power voltage.

The stage may include a reset transistor having a gate terminal to which the blank reset signal is applied, a drain terminal connected to the low power line, and a source terminal connected to the pull-down transistor.

The stage may include a flip-flop circuit having a Q output terminal connected to a gate terminal of the pull-up transistor and a Qb output terminal connected to a gate terminal of the pull-down transistor.

The display panel may be a liquid crystal panel or an organic light emitting device panel.

In the present invention, the auxiliary transistor provided in the gate driving circuit of the GIP structure is operated to perform the function of the discharge circuit when the power is turned off. Accordingly, there is no need to provide a separate discharge circuit and a separate signal line for driving the discharge circuit as in the prior art.

Accordingly, the width of the non-display area in which the gate driving circuit is formed can be reduced, so that a narrow bezel can be easily implemented.

In addition, since the driving IC does not need to include a signal output pin for driving a separate discharge circuit, component costs can be reduced.

In addition, the width of the common wiring region can be increased, and thus the resistance of the common wiring can be reduced, thereby preventing common voltage ripple and smearing, thereby improving image quality.

1 is a diagram schematically showing a part of a conventional liquid crystal display having a GIP structure.
2 is a timing diagram of a signal applied to a discharge circuit and a voltage applied to a gate wiring of a conventional liquid crystal display having a GIP structure;
3 is a diagram schematically illustrating a liquid crystal display device according to an embodiment of the present invention.
4 is a diagram schematically illustrating a non-display area and a part of a display area of a liquid crystal display according to an embodiment of the present invention.
5 is a diagram schematically showing the configuration of a stage of a gate driving circuit according to an embodiment of the present invention.
6 is a timing diagram illustrating waveforms of signals applied to an auxiliary transistor of a stage and a voltage applied to a gate line according to an embodiment of the present invention;

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

As the display device according to the embodiment of the present invention, any type of display device having a GIP structure, for example, a liquid crystal display device, an organic light emitting device display device, a plasma display device, and the like may be used. However, hereinafter, for convenience of description, a liquid crystal display device will be described as an example.

3 is a diagram schematically illustrating a liquid crystal display according to an embodiment of the present invention, and FIG. 4 is a diagram schematically illustrating a non-display area and a part of a display area of the liquid crystal display according to an embodiment of the present invention .

3 and 4 , the liquid crystal display 100 according to the embodiment of the present invention is a liquid crystal display having a GIP structure, which includes a display panel 110 , a driving IC 200 , and a driving board 300 . may include.

The display panel 200 includes a display area AA in which a plurality of pixels P are arranged in a matrix to display an image, and a non-display area NA formed around the display area AA.

The display panel 200 includes two substrates facing each other, for example, an array substrate, an opposing substrate facing the same, and a liquid crystal layer positioned between the two substrates.

A plurality of gate lines GL extending along a row direction as a first direction and a plurality of data lines DL extending along a column direction in a second direction are formed on the array substrate of the display panel 200 . A plurality of pixels P arranged in a matrix form are defined by the gate and data lines GL and DL crossing each other as described above.

In each pixel P, a switching transistor Ts connected to the gate line and the data line GL and DL is formed.

Meanwhile, although not specifically illustrated, the switching transistor Ts is connected to the pixel electrode. A common electrode is formed corresponding to the pixel electrode, and when a voltage is applied to the pixel electrode and the common electrode, an electric field is formed between them to drive the liquid crystal.

In addition, the pixel electrode, the common electrode, and the liquid crystal positioned between these electrodes constitute the liquid crystal capacitor. Meanwhile, in each pixel P, a storage capacitor is further configured, which serves to store the data signal applied to the pixel electrode until the next frame.

Meanwhile, although not specifically illustrated, the liquid crystal display 100 may include a backlight unit as a light source for supplying light to the display panel 200 . The backlight unit may use a cold cathode fluorescent lamp (CCFL), an external electrode fluorescent lamp (EEFL), a light emitting diode (LED), or the like.

A gate driving circuit 120 , which is a GIP circuit, may be formed in the non-display area NA of one side of the array substrate. Meanwhile, in some cases, the gate driving circuit 120 may be formed on both sides of the array substrate facing each other. In the embodiment of the present invention, for convenience of description, a case in which the gate driving circuit 120 is formed on one side of the array substrate is taken as an example.

In the non-display area NA in which the gate driving circuit 120 is formed, signals for driving the gate driving circuit 120 are transmitted outside the first area A1 which is the GIP area in which the gate driving circuit 120 is formed. A second area A2 that is a signal wiring area in which wirings are formed may be located. In addition, a third area A3 , which is a common wiring area in which a common wiring for transmitting a common voltage to the inside of the display panel 110 is formed, may be located inside the first area A1 .

The gate driving circuit 120 formed in the first region A1 includes a plurality of stages SR connected to each of the plurality of gate lines GL and outputting gate signals.

The plurality of stages SR sequentially output gate signals in row-line units in every frame in the power-on state of the liquid crystal display 100 . That is, each stage SR outputs the gate high voltage during the horizontal period of the corresponding row line, and outputs the gate low voltage during the remaining time.

When the gate high voltage is output, the switching transistor Ts of the pixel P connected to the corresponding gate line GL is turned on, and in synchronization with this, the data signal transmitted through the data line GL is transmitted to the corresponding pixel P. approved and charged.

Meanwhile, in a blank period (see BT of FIG. 6 ) between neighboring frames, the blank reset signal BRST is applied to all of the plurality of stages SR, and accordingly, all of the stages SR are reset at the same time. (reset)

And, when the liquid crystal display device 100 is powered off, the gate driving circuit 120 performs a discharging operation in response thereto. That is, all of the plurality of stages SR simultaneously output the gate high voltage. Accordingly, the charges charged in all the pixels P configured in the display panel 110 are simultaneously discharged.

In particular, the discharging operation of the gate driving circuit 120 when the power is turned off does not use a separate discharging circuit as in the prior art, but an auxiliary transistor (Fig. 5) using T7N).

Accordingly, there is no need to provide a separate discharge circuit and a separate signal line for driving the same as in the related art.

Accordingly, the width of the non-display area NA in which the gate driving circuit 120 is formed can be reduced, so that a narrow bezel can be easily implemented. In addition, since the driving IC 300 does not need to include a signal output pin for driving a separate discharge circuit, component costs can be reduced. In addition, it is possible to increase the width of the third region A3, which is the common wiring region, and accordingly, the resistance of the common wiring can be reduced, thereby preventing common voltage ripple and smearing, thereby improving image quality. .

The gate driving circuit 120 performing such a function will be described in more detail below.

Signals for driving the gate driving circuit 120 are provided in the second region A2 located outside the first region A1, for example, a plurality of clock signals CLK and gate start signals having different phases. Signal lines for transmitting a gate control signal including Vst and a blank reset signal BRST and a power supply voltage such as a low power voltage Vss and a high power voltage Vdd may be formed. Furthermore, a ground wiring may be formed in the second area A2 .

The driving IC 200 may be connected to the other side of the array substrate adjacent to one side of the array substrate on which the gate driving circuit 120 is formed.

The driving IC 200 corresponds to a data driving circuit that outputs a data signal to the data line DL. At least one driving IC 200 may be used to drive the display panel 200 . For convenience of description, a case in which three driving ICs 200 are provided is exemplified.

The driving IC 200 may be mounted on, for example, the flexible circuit film 210 on which the wiring pattern is formed, and may be connected to the display panel 110 while being mounted on the flexible circuit film 210 . As another example, the driving IC 200 may be configured to be directly mounted on the array substrate of the display panel 110 in a COG method. In the embodiment of the present invention, for convenience of description, a case in which the driving IC 200 is mounted on the flexible circuit film 210 is taken as an example.

On the other hand, the driving IC 200 located close to the gate driving circuit 120 may be configured to output signals for driving the gate driving circuit 120 , and may have a signal output pin for outputting these signals. have.

At this time, as described above, according to the embodiment of the present invention, since a separate discharge circuit is not used, the driving IC 200 does not need to have a signal output pin for outputting a signal for driving the discharge circuit. .

The driving IC 200 is connected to the driving board 300 through the flexible circuit film 310 . A plurality of driving circuits for driving the display panel 200 are mounted on the driving board 300 . For example, the timing controller 310 and the power circuit 320 may be mounted on the driving board 300 .

The timing controller 310 may receive image data and a timing signal from an external system, align the image data, and output the image data to the driving IC 200 .

The power circuit 320 is a component that generates driving power for driving the liquid crystal display device 100 , and may generate a common voltage Vcom, a high power voltage Vdd, a low power supply voltage Vss, and the like.

Meanwhile, a level shifter may be configured in the power circuit 420 . The level shifter, for example, level-shifts the clock signal input from the timing controller 210 and outputs it.

Hereinafter, with further reference to FIGS. 5 and 6 , the gate driving circuit 120 and its operation according to an embodiment of the present invention will be described in more detail.

5 is a diagram schematically illustrating the configuration of a stage of a gate driving circuit according to an embodiment of the present invention, and FIG. 6 is a view showing signals applied to the auxiliary transistor of the stage and the gate wiring according to the embodiment of the present invention. It is a timing diagram showing the waveform of the voltage. Here, in FIG. 6 , waveforms of voltages applied to the n-th and n+1-th gate lines GLn and GLn+1 are shown for convenience of explanation.

Referring to FIG. 5 , the stage SR of the gate driving circuit 120 according to the embodiment of the present invention includes a flip-flop circuit FF, a flip-up transistor Tpu, and a pull-down transistor Tpd. It may include an auxiliary transistor (T7N).

The flip-flop circuit FF is configured to include a plurality of transistors, and may include a Q output terminal connected to the pull-up transistor Tpu and a Qb output terminal connected to the pull-down transistor Tpd.

The Q output terminal and the Qb output terminal may be configured to output signals of opposite phases to each other. For example, when the Q output terminal outputs a high-state Q signal, the Qb output terminal outputs a low-state Qb signal.

By the above signal output of the flip-flop circuit FF, the pull-up transistor Tpu and the pull-down transistor Tpd operate so that their on/off states are opposite to each other.

That is, when the pull-up transistor Tpu is turned on, the pull-down transistor Tpd is turned off, and when the pull-up transistor Tpu is turned off, the pull-down transistor Tpd is turned on.

A corresponding clock signal CLK is applied to a source terminal of the pull-up transistor Tpu, and a drain terminal is connected to a gate output terminal Vout for outputting a gate signal to the gate line GL.

The gate terminal of the pull-down transistor Tpd is connected to the Qb output terminal of the flip-flop circuit FF. The source terminal of the pull-down transistor Tpd is connected to the low power line VssL, and the drain terminal is connected to the gate output terminal Vout.

Here, referring to FIG. 6 , the low power supply voltage Vss is continuously applied to the low power supply line VssL when the liquid crystal display 100 is in a power-on state. On the other hand, when the liquid crystal display 100 is powered off, the gate high voltage VGH is applied to the low power wiring VssL.

In the power-on state of the liquid crystal display 100 , the stage SR operates normally, and the pull-up transistor Tpu responds to the high-state Q signal in a horizontal period corresponding to every frame Fi and Fi+1. is turned on and the pull-down transistor Tpd is turned off in response to the low-state Qb signal, and accordingly, the clock signal CLK of the gate-high voltage VGH state is transferred to the gate output terminal Vout through the pull-up transistor Tpu. is output as Accordingly, the gate high voltage VGH is applied to the corresponding gate line GL.

On the other hand, before and after the horizontal period of each frame (Fi, Fi+1), the pull-up transistor Tpu is turned off in response to the low-state Q signal, and the pull-down transistor Tpd responds to the high-state Qb signal. is turned on, and accordingly, the low power voltage Vss is output to the gate output terminal Vout through the pull-down transistor Tpd. That is, since the low power voltage Vss is applied to the low power wiring VssL, the low power voltage Vss is output to the gate output terminal Vout in the turn-on state of the pull-down transistor Tpd. Accordingly, the low power voltage Vss corresponding to the gate low voltage is applied to the corresponding gate line GL.

The auxiliary transistor T7N is arranged in parallel with the pull-down transistor Tpd. That is, the source terminal of the auxiliary transistor T7N is connected to the gate output terminal Vout, and the drain terminal is connected to the low power supply line VssL. Then, the gate terminal of the auxiliary transistor T7N receives the blank reset signal BRST.

The auxiliary transistor T7N corresponds to a device having a function of alleviating positive bias stress of the pull-down transistor Tpd. That is, the pull-down transistor Tpd continuously receives a high-state voltage for a period of time except for the horizontal period and outputs a low power supply voltage Vss to induce positive (+) bias stress. In order to alleviate this, the auxiliary transistor ( T7N) is configured in the stage SR.

The auxiliary transistor T7N receives the blank reset signal BRST in a low state during each frame Fi and Fi+1, and thus maintains a turned-off state.

Meanwhile, in the blank period BT between the neighboring frames Fi and Fi+1, the high-state blank reset signal BRST is applied, and in response, the low power supply voltage Vss is applied to the gate output terminal Vout. will be output to

At this time, the pull-down transistor Tpd maintains a turned-off state and does not output a signal to the gate output terminal Vout.

To this end, a reset transistor Tre for turning off the pull-down transistor Tpd during the blank period BT may be configured in the stage SR.

The reset transistor Tre is configured such that the gate terminal receives the blank reset signal BRST, the drain terminal is connected to the low power line VssL, and the source terminal is connected to the gate terminal of the pull-down transistor Tpd. can be

Accordingly, by the blank reset signal BRST in the high state in the blank section BT, the reset transistor Tre outputs the low power voltage Vss to the gate terminal of the pull-down transistor Tpd, and the pull-down transistor ( Tpd) is turned off.

As such, in the blank section BT, the auxiliary transistor T7N operates to output the low power voltage Vss to the gate output terminal Vout instead of the pull-down transistor Tpd, thereby reducing the stress of the pull-down transistor Tpd. can be alleviated.

In particular, in the embodiment of the present invention, the auxiliary transistor T7N operates to function as a discharge circuit when the liquid crystal display 100 is powered off.

That is, when the power is turned off, the blank reset signal BRST is in a high state and the gate high voltage VGH is applied to the low power wiring VssL, so that all stages SR configured in the gate driving circuit 120 are is driven to output the gate high voltage VGH at the same time. Accordingly, the switching transistors Ts of all the pixels P in the display panel 110 are turned on, so that the charges in the pixels P can be discharged.

An operation in the power on/off state of the gate driving circuit 120 having the above-described configuration will be described with reference to FIG. 6 .

First, in the power-on state of the liquid crystal display 100 , the low power voltage Vss is continuously applied to the low power wiring VssL. In addition, the blank reset signal BRST maintains a low state during every frame Fi and Fi+1, and maintains a high state in the blank period BT between the frames Fi and Fi+1.

At this time, in the stage SR for every frame Fi, Fi+1, the pull-up transistor Tpu is turned on during the corresponding horizontal period to output the clock signal CLK, and accordingly, the gate high voltage VGH is It is output to the gate wirings GLn and GLn+1 of the corresponding row line.

And, in a section other than the horizontal period of every frame (Fi, Fi+1), the pull-down transistor Tpd is turned on to output the low power voltage Vss, and accordingly, the gate-low voltage is applied to the gate of the corresponding row line. It is output to the wirings GLn and GLn+1.

Next, when the liquid crystal display 100 is powered off, the gate high voltage VGH is applied to the low power wiring VssL. And, the blank reset signal BRST has a high state.

At this time, the auxiliary transistor T7N is turned on in response to the high-state blank reset signal BRST. Accordingly, the gate high voltage VGH applied to the low power line VssL through the auxiliary transistor T7N is output to the gate lines GLn and GLn+1. That is, all stages SR of the gate driving circuit 120 simultaneously output the gate high voltage VGH to the corresponding gate line GL.

Accordingly, the switching transistors Ts of all the pixels P in the display panel 110 are turned on, and accordingly, electric charges in the pixels P are discharged through the data line DL.

In the above bar, the GIP type liquid crystal display has been described. Meanwhile, it is obvious that the above-described embodiment of the present invention can be applied to a display device such as an organic light emitting diode display device or a plasma display device as a display device in which a driving circuit can be directly formed on a panel in the GIP method.

As described above, according to the embodiment of the present invention, the auxiliary transistor provided in the gate driving circuit of the GIP structure is operated to perform the function of the discharge circuit when the power is turned off. Accordingly, there is no need to provide a separate discharge circuit and a separate signal line for driving the discharge circuit as in the prior art.

Accordingly, the width of the non-display area in which the gate driving circuit is formed can be reduced, so that a narrow bezel can be easily implemented.

In addition, since the driving IC does not need to include a signal output pin for driving a separate discharge circuit, component costs can be reduced.

In addition, the width of the common wiring region can be increased, and thus the resistance of the common wiring can be reduced, thereby preventing common voltage ripple and smearing, thereby improving image quality.

The above-described embodiment of the present invention is an example of the present invention, and free modifications are possible within the scope included in the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention provided they come within the scope of the appended claims and their equivalents.

100: liquid crystal display 110: display panel
120: gate driving circuit 200: driving IC
210: flexible circuit film 300: driving board
310: timing controller 320: power circuit
TPU: Pull-up transistor
Tpd: pull-down transistor
T7N: auxiliary transistor
Tre: reset transistor
BRST: Blank reset signal
Vss: Low power voltage
VGH: gate high voltage
BT: blank section

Claims (6)

A gate driving circuit having a GIP structure located in a non-display area of the display panel, each connected to a plurality of gate wirings, respectively connected to a pull-up transistor, a pull-down transistor, and the pull-down transistor in parallel, and a drain terminal connected to a low power wiring A method of driving a display device comprising a gate driving circuit comprising a plurality of stages comprising auxiliary transistors to which a source terminal is connected to a gate output terminal and a gate terminal is applied with a blank reset signal, the method comprising:
applying the blank reset signal in a high state and applying a gate high voltage to the low power wiring when the display device is powered off;
In the power-on state of the display device, the blank reset signal in a low state is applied during every frame, the blank reset signal in a high state is applied during a blank period between adjacent frames, and a low power supply voltage is applied to the low power wiring. step to authorize
including,
During the blank period between neighboring frames, the auxiliary transistor is turned on by the blank reset signal in the high state, and the low power supply voltage of the low power wiring is applied to the plurality of auxiliary transistors through the auxiliary transistor in the turned-on state. A method of driving a display device that is output to a gate output terminal of each of the stages.
delete The method of claim 1,
The stage includes a reset transistor having a gate terminal to which the blank reset signal is applied, a drain terminal connected to the low power wiring, and a source terminal connected to a gate terminal of the pull-down transistor.
Display device driving method.
The method of claim 1,
wherein the stage includes a flip-flop circuit having a Q output terminal connected to a gate terminal of the pull-up transistor and a Qb output terminal connected to a gate terminal of the pull-down transistor.
Display device driving method.
The method of claim 1,
The display panel is a liquid crystal panel or an organic light emitting device panel.
Display device driving method. 4. The method of claim 3,
During the blank period between neighboring frames, the reset transistor is turned on by the blank reset signal in the high state, and the low power voltage of the low power wiring is pulled down through the reset transistor in the turned-on state. is applied to the gate terminal of the transistor, and the pull-down transistor is turned off by the low power supply voltage of the low power wiring.
Display device driving method.

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