KR102004912B1

KR102004912B1 - Shift register and flat panel display device including the same

Info

Publication number: KR102004912B1
Application number: KR1020120131522A
Authority: KR
Inventors: 강해윤; 박기수
Original assignee: 엘지디스플레이 주식회사
Priority date: 2012-11-20
Filing date: 2012-11-20
Publication date: 2019-10-01
Also published as: KR20140064319A

Abstract

The present invention relates to a shift register capable of outputting a normal gate pulse by preventing a leakage current of an oxide transistor and a flat panel display device including the shift register. The shift register according to the present invention includes a plurality of clock signals supplied with a plurality of clock signals. A shift register comprising a plurality of stages selectively connected to a supply line and driven dependently in accordance with a gate start signal, each of the plurality of stages being a gate electrode connected to a first node and a plurality of clock signal supply lines. A pull-up transistor having a first electrode connected to one clock signal supply line and a second electrode connected to an output node; A pull-down having a first gate electrode connected to a second node, a first electrode connected to the output node, a second electrode connected to a low potential voltage supply line, and a second gate electrode connected to a bias voltage supply line transistor; And a node control circuit for controlling a voltage of each of the first and second nodes according to the gate start signal, wherein each of the pull-up transistor and the pull-down transistor includes a semiconductor layer made of an oxide. Can be.

Description

SHIFT REGISTER AND FLAT PANEL DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a shift register and a flat panel display including the same.

Recently, the importance of the display device has increased with the development of multimedia. In response to this, flat panel displays such as liquid crystal displays, plasma displays, and organic light emitting displays have been commercialized.

The gate driving circuit of such a flat panel display includes a shift register for sequentially supplying gate pulses to a plurality of gate lines. The shift register includes a plurality of stages including a plurality of transistors, and the stages are cascaded to sequentially output the gate pulses.

Recently, in the case of a liquid crystal display and / or an organic light emitting display, a gate in panel (GIP) structure in which a transistor constituting the shift register of the gate driving circuit is embedded in a substrate of a display panel in the form of a thin film transistor has been applied. .

The transistor constituting the shift register of the GIP structure serves to supply a gate pulse to the transistor of each pixel formed in the display panel, and thus not only basic transistor characteristics such as mobility and leakage current, but also durability to maintain a long lifespan. And electrical reliability is very important. At this time, the semiconductor layer of the transistor is formed of amorphous silicon or polycrystalline silicon, amorphous silicon has the advantage of simple film formation process and low production cost, but there is a problem that the electrical reliability is not secured. In addition, polycrystalline silicon is very difficult to apply a large area due to high process temperature, there is a problem that the uniformity according to the crystallization method is not secured. In order to solve this problem, researches using an oxide semiconductor as a semiconductor layer of a transistor have been recently conducted.

Oxide semiconductors are evaluated as amorphous and stable materials, and when these oxide semiconductors are used as transistor semiconductor layers, transistors can be manufactured at low temperatures using existing process equipment without additional process equipment. In addition, the ion implantation process is omitted, there are various advantages.

1 is a graph showing transfer characteristics of a general oxide thin film transistor.

As can be seen in FIG. 1, since most of the oxide transistors have a negative threshold voltage, a leakage current occurs in a state where the gate voltage Vg is zero, which causes the leakage current. There is a problem that the normal gate pulse is not output from the shift register. This problem can be solved by shifting the threshold voltage of the oxide transistor positively through a change in the manufacturing process of the oxide transistor, but in this case, the transistor formed in the display area of the display panel also has a positive threshold voltage. Therefore, there is a disadvantage that the driving power increases.

Therefore, a method for preventing leakage current of the oxide transistors constituting the shift resistor is required.

Disclosure of Invention The present invention has been made in view of the above-described problems, and it is an object of the present invention to provide a shift register capable of preventing a leakage current of an oxide transistor and outputting a normal gate pulse, and a flat panel display device including the same.

According to an aspect of the present invention, a shift register includes a plurality of stages selectively connected to a plurality of clock signal supply lines supplied with a plurality of clock signals and driven in dependence on a gate start signal. In the plurality of stages, each of the plurality of stages having a gate electrode connected to the first node, a first electrode connected to the first clock signal supply line of the plurality of clock signal supply lines, and a second electrode connected to the output node -Up transistors; A pull-down having a first gate electrode connected to a second node, a first electrode connected to the output node, a second electrode connected to a low potential voltage supply line, and a second gate electrode connected to a bias voltage supply line transistor; And a node control circuit for controlling a voltage of each of the first and second nodes according to the gate start signal, wherein each of the pull-up transistor and the pull-down transistor includes a semiconductor layer made of an oxide. Can be.

According to an aspect of the present invention, a flat panel display device is defined as a display area including a plurality of pixels formed for each pixel area defined by an intersection of a plurality of gate lines and a plurality of data lines, and a periphery of the display area. A display panel including a non-display area; A plurality of data drivers for converting input pixel data into a plurality of data lines by converting a data signal; And a gate driver formed in a non-display area of the display panel so as to be connected to the plurality of gate lines, the gate driver configured to sequentially supply gate pulses to the plurality of gate lines. It can be configured to include registers.

The flat panel display converts input image data into the pixel data to supply the data driver to the data driver, and supplies a gate control signal including the gate start signal, the plurality of clock signals, and a bias voltage to the gate driver circuit. The electronic device may further include a timing controller, and the bias voltage may have a negative voltage level.

According to the means for solving the above problems, the shift register and the flat panel display including the same according to the present invention has the following advantages.

First, a leakage voltage of the pull-down transistor can be prevented by applying a bias voltage to the second gate electrode formed in the pull-down transistor of each stage to change the threshold voltage of the pull-down transistor to a positive voltage level. Through this, a normal gate pulse can be output.

Second, by driving each pixel normally through the gate pulse normally output from the shift register, a desired image may be displayed on the display panel.

1 is a graph showing transfer characteristics of a general oxide thin film transistor.
2 is a block diagram schematically illustrating a configuration of a shift register according to an exemplary embodiment of the present invention.
FIG. 3 is a circuit diagram for describing the structure of each stage illustrated in FIG. 2.
FIG. 4 is a waveform diagram illustrating the operation of the stage in FIG. 3.
FIG. 5 is a cross-sectional view illustrating a structure of the pull-down transistor shown in FIG. 3.
6 is a graph showing a threshold voltage according to a bias voltage of a pull-down transistor according to the present invention.
7 is a graph illustrating transfer characteristics of a pull-down transistor according to the present invention.
FIG. 8 is a circuit diagram for describing a deformation structure of each stage illustrated in FIG. 2.
9 is a plan view schematically illustrating a flat panel display device according to an exemplary embodiment of the present invention.
FIG. 10 is a waveform diagram illustrating a gate control signal generated by the timing controller illustrated in FIG. 9.

In the present specification, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same number as much as possible even though they are displayed on different drawings.

On the other hand, the meaning of the terms described in this specification should be understood as follows.

Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and the terms “first”, “second”, and the like are intended to distinguish one component from another. The scope of the rights shall not be limited by these terms.

It is to be understood that the term "comprises" or "having" does not preclude the existence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

The term "at least one" should be understood to include all combinations which can be presented from one or more related items. For example, the meaning of "at least one of the first item, the second item, and the third item" means two items of the first item, the second item, or the third item, as well as two of the first item, the second item, and the third item, respectively. A combination of all items that can be presented from more than one.

Hereinafter, exemplary embodiments of a shift register and a flat panel display device including the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating a configuration of a shift register according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the shift register according to an exemplary embodiment of the present invention is selectively connected to a plurality of clock signal supply lines to which a plurality of clock signals CLK1 to CLK5 are supplied, and dependently according to a gate start signal Vst. M stages ST1 to STm to be driven are included.

The gate start signal Vst is supplied to the first stage ST1. Each of the second to m th stages ST2 to STm receives an output signal of the previous stages ST1 to STm-1 as a gate start signal Vst.

Each of the m stages ST1 to STm receives only three clock signals of the five-phase clock signals CLK1 to CLK5 in which the phases are sequentially delayed by 1/2 clock. For example, when the first, third, and fifth clock signals CLK1, CLK3, and CLK5 are input to the first stage ST1, the phase delayed by three phases is sequentially delayed by 1/2 clock in the second stage ST2. Clock signals CLK1, CLK2, CLK4 are input, and three clock signals sequentially phase-delayed by 1/2 clock are sequentially input to the third to m-th stages ST3 to STm.

Each of the m stages ST1 to STm is connected to a high potential voltage Vdd supply line, a low potential voltage Vss supply line, and a bias voltage Vtg supply line, respectively. The output lines of each of the m stages ST1 to STm are connected to m gate lines GL1 to GLm formed in the display area of the flat panel display panel (not shown).

As described above, each of the m stages ST1 to STm is driven by the gate start signal Vst, and the phase of the gate-on voltage level is 1 in accordance with three clock signals among the five-phase clock signals CLK1 to CLK5. Output signals Vout1 to Vout_m sequentially delayed by the horizontal period are output and sequentially supplied to the plurality of gate lines GL1 to GLm. Accordingly, the gate pulses having the gate on voltage level are supplied to each of the gate lines GL1 to GLm for one horizontal period, and the low potential voltage Vss at the gate off voltage level is supplied after the one horizontal period.

FIG. 3 is a circuit diagram for describing the structure of each stage illustrated in FIG. 2.

Referring to FIG. 3, the stage ST according to the present invention includes a pull-up transistor Tu, a pull-down transistor Td, and a node control circuit NCC.

The pull-up transistor Tu may include a gate electrode connected to a first node Q, a first electrode connected to a first clock signal CLK1 supply line, and a second electrode connected to an output node No. Include. The pull-up transistor Tu is turned on according to the voltage of the first node Q to supply the first clock signal CLK1 having a gate-on voltage level to the output node No. Here, the first clock signal CLK1 has a form in which a gate-on voltage level corresponding to two horizontal periods and a gate-off voltage level corresponding to three horizontal periods are repeated, and the first clock signal CLK1 is 1 / second from the gate start signal Vst. The phase is delayed by two horizontal periods.

The pull-up transistor Tu includes an N-type semiconductor layer made of oxide. Although the pull-up transistor Tu is formed of an N-type transistor, the pull-up transistor Tu has a negative threshold voltage due to the characteristics of the oxide semiconductor layer.

The first capacitor C1 may be connected between the gate electrode and the second electrode of the pull-up transistor Tu. When the first clock signal CLK1 of the gate-on voltage level is supplied to the output node No, the first capacitor C1 may be connected to the first node Q by the voltage level of the first clock signal CLK1. Raise the voltage. Accordingly, the pull-up transistor Tu is completely turned on as the gate voltage is increased by the first capacitor C1, so that the first clock signal having the gate-on voltage level without the voltage loss caused by the threshold voltage is applied to the pull-up transistor Tu. CLK1 is quickly supplied to the output node (No). As such, the first capacitor C1 may be a parasitic capacitor formed in an overlapping region between the gate electrode and the second electrode of the pull-up transistor Tu.

The pull-down transistor Td may include a first gate electrode connected to a second node QB, a first electrode connected to the output node No, and a second electrode connected to a low potential voltage Vss supply line. And a second gate electrode connected to the bias voltage Vtg supply line. The pull-down transistor Td is turned on in response to the voltage on the second node QB connected to the first gate electrode, and thus the low-voltage voltage Vss of the gate-off voltage level is output to the output node No. Supplies).

The pull-down transistor Td includes an N-type semiconductor layer made of oxide. Although the pull-down transistor Td has a negative threshold voltage due to the characteristics of the oxide semiconductor layer even though it is formed as an N-type transistor, the pull-down transistor Td is negative supplied to the second gate electrode. It has a positive threshold voltage shifted (or changed) by the bias voltage Vtg having a voltage level. Accordingly, the pull-down transistor Td is turned off completely when the low potential voltage Vss of the gate-off voltage level is supplied to the second node QB, so that the pull-up transistor Tu is turned off. No leakage current is generated while supplying the first clock signal CLK1 of the gate-on voltage level to the output node No. The threshold voltage of the pull-down transistor Td will be described later.

The node control circuit NCC includes the gate start signal Vst, the second and third clock signals CLK1 and CLK3, the high potential voltage Vdd, the low potential voltage Vss, and the bias voltage Vtg. First to fifth switching units 10, 20, 30, 40, and 50, a second capacitor C2, and a third capacitor C3 for controlling the voltage of each of the first and second nodes Q and QB. ).

The first switching unit 10 includes a first transistor T1 that is selectively turned on according to an input gate start signal Vst to output the gate start signal Vst. The first transistor T1 includes a semiconductor layer made of oxide, and has a negative threshold voltage. The first transistor T1 is turned on only when the gate start signal Vst of the gate-on voltage level is supplied, and outputs the gate start signal Vst of the gate-on voltage level.

The second switching unit 20 is selectively turned on according to the second clock signal CLK2 to supply the high potential voltage Vdd to the second node QB. The second switching unit 20 may be composed of one second transistor including an N-type semiconductor layer formed of an oxide, but a multi-gate structure to prevent leakage current during a turn-off period. It is preferable that it is composed of a pair of second transistors T2a and T2b.

The pair of second transistors T2a and T2b include an N-type semiconductor layer made of oxide, and as described above, has a negative threshold voltage. The pair of second transistors T2a and T2b are connected in series between the high potential voltage Vdd supply line and the second node QB to supply the second clock signal CLK2 having the gate-on voltage level. It is turned on only when the high potential voltage Vdd is supplied to the second node QB. At this time, the second clock signal CLK2 has a phase delayed by two horizontal periods from the first clock signal CLK1.

The third switching unit 30 is selectively turned on according to the third clock signal CLK3 to output a gate start signal of the gate-on voltage level output from the first transistor T1 to the first node Q. The third transistor T3 is supplied. The third transistor T3 includes an N-type semiconductor layer made of oxide, and has a negative threshold voltage as described above. The third transistor T3 is turned on only when the third clock signal CLK3 of the gate-on voltage level is supplied to supply the gate start signal to the first node Q. In this case, the third clock signal CLK3 has a phase that is earlier in phase than the first clock signal CLK1 by a half horizontal period. That is, the phase of the first clock signal CLK1 is delayed by a half horizontal period than the third clock signal CLK3. Meanwhile, the third switching unit 30 may also be configured with a pair of third transistors (not shown) having a multi-gate structure to prevent leakage current during the turn-off period.

The fourth switching unit 40 is selectively turned on according to the gate start signal Vst to supply the low potential voltage Vss to the second node QB. The fourth switching unit 40 may be composed of one fourth transistor including an N-type semiconductor layer made of oxide, but has a multi-gate structure to prevent leakage current during a turn-off period. It is preferable that it is composed of a pair of fourth transistors T4a and T4b having a.

The pair of fourth transistors T4a and T4b includes an N-type semiconductor layer made of oxide, and has a negative threshold voltage as described above. The pair of fourth transistors T2a and T2b are connected in series between the second node QB and the low potential voltage Vss supply line to supply the gate start signal Vst having the gate-on voltage level. Only turned on to supply the low potential voltage Vss to the second node QB.

The fifth switching unit 50 is selectively turned on according to the voltage of the second node QB to supply the low potential voltage Vss to the first node Q. The fifth switching unit 50 may be composed of one fifth transistor including an N-type semiconductor layer made of oxide, but a multi-gate structure to prevent leakage current during a turn-off period. It is preferable that it is formed to have a pair of fifth transistors T5a and T5b which are formed to have and connected in series between the first node Q and the low potential voltage Vss supply line.

The first fifth transistor T5a of the pair of fifth transistors T5a and T5b includes a first gate electrode connected to the second node QB and a first electrode connected to the first node Q. A second electrode connected to the fifth fifth transistor T5b, and a second gate electrode connected to the bias voltage Vtg supply line. The second fifth transistor T5b of the pair of fifth transistors T5a and T5b is connected to the first gate electrode connected to the second node QB and the second electrode of the first fifth transistor T5b. A first electrode, a second electrode connected to a low potential voltage Vss supply line, and a second gate electrode connected to a bias voltage Vtg supply line.

The pair of fifth transistors T5a and T5b includes an N-type semiconductor layer made of an oxide, and as described above, the second transistor QB has a negative threshold voltage. ), A leakage current may be generated when the low potential voltage Vss of the gate-off voltage level is supplied. However, since the pair of fifth transistors T5a and T5b have a positive threshold voltage by the bias voltage Vtg supplied to the second gate electrode, the gate-off voltage level is applied to the second node QB. When the low potential voltage of Vss is supplied, the above-mentioned leakage current is not generated because it is completely turned off. In this case, the bias voltage Vtg has a negative voltage level, and may be, for example, in a range of −10 V to −0.1 V, and is constant at the negative voltage level while the shift register is operating. Can be maintained.

As such, the pair of fifth transistors T5a and T5b are turned on only when the low potential voltage Vss is supplied to the second node QB, so that the low potential voltage (1) is applied to the first node Q. Supply Vss). Meanwhile, since the pair of fifth transistors T5a and T5b have a positive threshold voltage due to the bias voltage Vtg, the pull-up transistor Tu has the first gate-level voltage level. The complete turn-off state is supplied while supplying the clock signal CLK1 to the output node No.

The second capacitor C2 is connected between the first node Q and the low potential voltage Vss supply line to control the voltage on the first node Q together with the first capacitor C1.

The third capacitor C3 is connected between the second node QB and the low potential voltage Vss supply line to minimize the voltage change on the second node QB when the voltage of the output node No changes. do.

Meanwhile, in the stage ST described above, the pair of fourth transistors 4Ta and 4Tb may include the same structure as that of the pair of fifth transistors T5a and T5b, that is, the second gate electrode. Even though the pair of fifth transistors T5a and T5b have a negative threshold voltage, the pair of fifth transistors T5a and T5b can prevent the leakage current through the control of the gate start signal Vst and the low potential voltage Vss. The fourth transistors 4Ta and 4Tb need not be formed in the same structure as the pair of fifth transistors T5a and T5b.

Specifically, when each of the pull-down transistor Td and the pair of fifth transistors T5a and T5b has a zero or a negative voltage level, a problem due to their leakage current may occur. On the other hand, leakage current does not occur even when the pair of fourth transistors 4Ta and 4Tb are zero or have a negative voltage level. That is, when the pull-down transistor Td and the pair of fifth transistors T5a and T5b are each turned off by the voltage on the second node QB, the first gate electrode and the source electrode (ie, The voltage of each of the second electrodes is equal to the low potential voltage Vss so that the voltage Vgs between the gate and the source becomes zero. Accordingly, when the pair of fourth transistors 4Ta and 4Tb are zero or have a negative voltage level, a leakage current is generated by the gate-source voltage Vgs of zero. Done.

On the other hand, the gate start signal Vst is supplied to the gate electrodes of the pair of fourth transistors 4Ta and 4Tb, and the low potential voltage Vss is supplied to the source electrode (ie, the second electrode). Even though each of the pair of fourth transistors T4a and T4b has a zero voltage level or a negative voltage level, the pair of fourth transistors 4Ta through the gate start signal Vst and the low potential voltage Vss. Since it is possible to control the voltage Vgs between the gate and the source of 4Tb to a negative voltage level, there is no problem due to leakage currents such as the pair of fifth transistors T5a and T5b. .

FIG. 4 is a waveform diagram illustrating the operation of the stage in FIG. 3.

An operation of the stage will be described with reference to FIGS. 3 and 4 as follows.

First, in a period t1, the gate start signal Vst having the gate on voltage level is supplied to the gate electrode and the first electrode of the first transistor T1, and at the same time, the third clock signal CLK3 having the gate on voltage level is provided with the third clock signal CLK3. It is supplied to the transistor T3. At this time, each of the first and second clock signals CLK1 and CLK2 is maintained at the gate-off voltage level. In this case, the first transistor T1 is turned on by the gate start signal Vst of the gate-on voltage level and the third transistor T3 is turned on by the third clock signal CLK3 of the gate-on voltage level. By being turned on, the voltage VQ on the first node Q is charged to the gate-on voltage level by the gate start signals Vst supplied through the turned-on first and third transistors T1 and T3. Accordingly, the pull-up transistor Tu is turned on by the voltage charged in the first node Q so that the first clock signal CLK1 having the gate-off voltage level is supplied to the output node No. The voltage Vout of the level is supplied. At the same time, each of the pair of fourth transistors T4a and T4b is turned on by the gate start signal Vst of the gate-on voltage level, so that the low potential voltage Vss of the gate-off voltage level is turned to the second node. The pull-down having a positive threshold voltage by the bias voltage Vtg by being supplied to QB and simultaneously applying a bias voltage Vtg to the second gate electrode of the pull-down transistor Td. The transistor Td is turned off completely by the low potential voltage Vss supplied to the second node Q. Therefore, the gate-off voltage level supplied to the output node No is kept constant due to the complete turn-off state of the pull-down transistor Td.

Subsequently, in a period t2, while the gate start signal Vst and the third clock signal CLK3 are maintained at the gate-on voltage level, the first clock signal CLK1 of the gate-on voltage level is pulled up. It is supplied to the first electrode of the transistor Tu. In this case, the gate-on voltage level of the first clock signal CLK1 is output to the output node No through the pull-up transistor Tu which is turned on by the t1 period. At this time, the voltage VQ on the first node Q is raised to a higher voltage level by booststrapping by the first capacitor C1, which causes the pull-up transistor Tu to rise. Since the complete turn-on state, the first clock signal CLK1 having the gate-on voltage level is quickly supplied to the output node No without loss.

Next, in the period t3, the gate start signal Vst and the third clock signal CLK3 are changed to the gate-off voltage level and the first clock signal CLK1 is maintained at the gate-on voltage level. In this case, the pair of fourth transistors T4a and T4b are turned off by the gate start signal Vst of the gate off voltage level and the third clock signal CLK3 of the gate off voltage level is turned off. The three transistors T3 are turned off. At this time, even when the pair of fourth transistors T4a and T4b are turned off, the voltage VQB on the second node QB is maintained at the previous state, so that the turn-on state of the pull-up transistor Tu is maintained. maintain. Accordingly, since the first clock signal CLK1 is maintained at the gate-on voltage level and the turn-on state of the pull-up transistor Tu is maintained, the voltage Vout on the output node No is gate-on. It is maintained at the voltage level.

Subsequently, in the period t4, the gate start signal Vst and the third clock signal CLK3 are maintained at the gate-off voltage level, the first clock signal CLK1 is changed to the gate-off voltage level, and gate-on is performed. The second clock signal CLK2 of the voltage level is supplied to the gate electrodes of the pair of second transistors T2a and T2b. In this case, since the high potential voltage Vdd is supplied to the second node QB through the pair of second transistors T2a and T2b turned on by the second clock signal CLK2, the second node ( The voltage on QB) is charged to the high potential voltage Vdd. Accordingly, the pull-down transistor Td is turned on by the voltage on the second node QB and the pair of fifth transistors T5a and T5b are turned off, thereby reducing the gate-off voltage level. The low potential voltage Vss is supplied to the output node No through the turned-on pull-down transistor Td and at the same time the first node Q through the pair of fifth transistors T5a and T5b that are turned on. Is supplied. Accordingly, the voltage VQ on the first node Q is changed to a gate-off voltage level so that the pull-up transistor Tu is turned off, and the voltage of the output node No is the low potential voltage Vss. Is changed to the gate-off voltage level.

The shift register according to the present invention including the stage as described above sequentially performs a gate pulse, which is a clock signal of a gate-on voltage level, whose phase is delayed by 1/2 horizontal period according to the operation of the stage as described above. Will be supplied.

As described above, in the shift register according to the present invention, a second gate electrode is added to the pull-down transistor Td of each stage ST, and a bias voltage Vtg is applied to the second gate electrode to allow the pull register. By allowing the -down transistor Td to have a positive threshold voltage, a leakage current of the turned off pull-down transistor Td can be prevented to output a normal gate pulse.

Meanwhile, in the shift register according to the present invention described above, the phases of the five-phase clock signals CLK1 to CLK5 are sequentially delayed by 1/2 horizontal period, but the present invention is not limited thereto. This delay may be sequentially, and the phase delay of each of the five-phase clock signals CLK1 to CLK5 may be set to correspond to the driving method of each pixel of the display panel.

FIG. 5 is a cross-sectional view illustrating a structure of the pull-down transistor shown in FIG. 3.

Referring to FIG. 5, the pull-down transistor Td may include a first gate electrode 111 formed on the first substrate 110 of the flat panel display panel and a gate insulating layer 112 covering the first gate electrode 110. And a channel region of the semiconductor layer 113 formed of an oxide formed on the gate insulating layer 112 so as to overlap the first gate electrode 111 and the semiconductor layer 113 overlapping the first gate electrode 110. The first and second electrodes 114 and 115 described above, the protective layer 116 covering the semiconductor layer 113 and the first and second electrodes 114 and 115, and the first gate electrode 111. ) And a second gate electrode 117 formed on the protective layer 116.

The first gate electrode 111 may be the aforementioned second node QB or may be connected to the second node QB line.

The semiconductor layer 113 may be formed of an oxide such as zinc oxide, tin oxide, ga-in-zn oxide, in-zn oxide, or in-sn oxide, or may include Al, Ni, Cu, Ta, Mo, Ions of Zr, V, Hf or Ti materials may be made of oxides doped. The semiconductor layer 113 includes a channel region, a source region, and a drain region, and the channel region overlaps the first gate electrode 110.

The second gate electrode 117 may be formed on the passivation layer 116 so as to partially or completely overlap the first gate electrode 111. The second gate electrode 117 is connected to the aforementioned bias voltage Vtg supply line and is supplied with a bias voltage Vtg. In this case, the bias voltage Vtg has a negative voltage level and may be, for example, in a range of -10V to -0.1V.

Since the bias voltage Vtg having a negative voltage level is applied to the second gate electrode 117, the negative threshold voltage of the pull-down transistor Td is positive. Is shifted in the direction to have a positive threshold voltage.

In FIG. 5, although the second gate electrode 117 and the first and second electrodes 114 and 115 of the pull-down transistor Td are formed on different layers, the present invention is not limited thereto. Each of the second gate electrode 117 and the first and second electrodes 114 and 115 of the pull-down transistor Td may be formed on the same layer so as to overlap different areas on the semiconductor layer 113. . In this case, each of the first and second electrodes 114 and 115 of the pull-down transistor Td is connected to the semiconductor layer 113 through a contact hole (not shown).

On the other hand, since each of the pair of fifth transistors T5a and T5b described above is formed in the same structure as the pull-down transistor Td shown in FIG. 5, a description thereof will be replaced with the description of FIG. 5. Shall be. Each of the remaining transistors T1, T2a, T2b, T3, T4a, and T4b except for each of the pull-down transistor Td and the pair of fifth transistors T5a and T5b is the second shown in FIG. 5. Since the gate electrode is omitted, a description thereof will be omitted.

6 is a graph showing a threshold voltage according to a bias voltage of a pull-down transistor according to the present invention.

As can be seen in FIG. 6, the threshold voltage Vth of the pull-down transistor Td has a positive threshold voltage that gradually increases as the negative bias voltage Vtg is low. can see. Accordingly, the bias voltage Vtg is preferably set in the range of -10V to -0.1V so that the pull-down transistor Td has a positive threshold voltage.

7 is a graph showing a transfer characteristic of a pull-down transistor according to the present invention, which is applied to a first gate voltage Vg when a bias voltage Vtg of −10V is applied to a second gate electrode of the pull-down transistor. The drain current Id is shown.

As shown in FIG. 7, a transistor of a comparative example having one gate electrode has a negative threshold voltage, whereas a pull-down transistor according to an embodiment of the present invention having first and second gate electrodes It can be seen that it has a positive threshold voltage by a bias voltage Vtg of -10V applied to the second gate electrode.

Accordingly, the pull-down transistor Td according to the present invention has a positive threshold voltage by the bias voltage Vtg supplied to the second gate electrode 117 so that the pull-up transistor Tu ) Is completely turned off while supplying the first clock signal CLK1 at the gate-on voltage level to the output node No.

As a result, the shift register according to the present invention can prevent the leakage current of the pull-down transistor Td, thereby outputting a normal gate pulse.

FIG. 8 is a circuit diagram for describing a deformation structure of each stage illustrated in FIG. 2.

Referring to FIG. 8, a stage ST according to a modified example of the present invention includes a pull-up transistor Tu, a pull-down transistor Td, a node control circuit NCC, and a bias voltage transistor Tb. In this case, the bias voltage transistor Tb is added at the stage shown in FIG. 3. Accordingly, hereinafter, only the bias voltage transistor Tb will be described.

The bias voltage transistor Tb is paired with a gate electrode connected to a bias control signal BCS supply line, a first electrode connected to a bias voltage Vtg supply line, and the pull-down transistor Td described above. And a second electrode commonly connected to the second gate electrodes of the fifth transistors T5a and T5b. In this case, the bias control signal BCS maintains a high state only during the turn-on period of the pull-up transistor Tu, while maintaining a low state during the turn-off period of the pull-up transistor Tu. . Accordingly, the bias control signal BCS may be a first clock signal CLK1 supplied to the pull-up transistor Tu or a gate pulse output to an output node through the pull-up transistor Tu. have.

The bias voltage transistor Tb is turned on at the same time as the pull-up transistor Tu is turned on in response to the bias control signal BCS to apply a negative bias voltage Vtg to the pull-up voltage. Threshold voltages of each of the pull-down transistor Td and the pair of fifth transistors T5a and T5b are supplied to the second gate electrode of the down transistor Td and the pair of fifth transistors T5a and T5b, respectively. Is shifted to a positive threshold voltage to prevent leakage current as described above. In addition, the bias voltage transistor Tb is turned off at the same time as the pull-up transistor Tu is turned off according to the bias control signal BCS to be paired with the pull-down transistor Td. The pull-down transistor Td and the pair of fifth transistors T5a and T5b are blocked by blocking the negative bias voltage Vtg supplied to each of the second gate electrodes of the fifth transistors T5a and T5b. Each operates according to a negative threshold voltage.

As described above, the stage ST according to a modified example of the present invention turns on the bias voltage transistor Tb only during the turn-on period of the pull-up transistor Tu so that the pull-down transistor Td is turned on. And a pair of the pull-down transistor Td generated during the turn-on period of the pull-up transistor Tu by supplying a bias voltage Vtg to each of the pair of fifth transistors T5a and T5b. The leakage current of each of the fifth transistors T5a and T5b can be prevented and power consumption due to the bias voltage Vtg can be reduced.

9 is a plan view schematically illustrating a flat panel display device according to an exemplary embodiment of the present invention.

Referring to FIG. 9, a flat panel display device according to an exemplary embodiment of the present invention may include a display panel 100, a plurality of data drivers 200, a gate driver 300, a printed circuit board 400, and a timing controller 500. It is configured to include.

The display panel 100 includes first and second substrates that are opposed to each other.

The first substrate has a display area AA having a plurality of pixels P formed in a pixel area defined by the intersection of a plurality of gate lines GL and a plurality of data lines DL, and a display area AA. It includes a non-display area (IA) provided in the vicinity of the.

Each of the plurality of pixels P includes a pixel cell displaying an image according to a gate pulse supplied from an adjacent gate line GL and a data signal supplied from an adjacent data line DL. In this case, the pixel cell includes at least one thin film transistor and at least one capacitor, and is a liquid crystal cell displaying an image by controlling the light transmittance of the liquid crystal according to the data signal, or a current corresponding to the data signal. It may be a light emitting cell that emits light in proportion to display an image.

The second substrate covers the entire first substrate except for a portion of the non-display area IA. In this case, when each pixel P is formed of a liquid crystal cell, a color filter layer overlapping each pixel P may be formed on the second substrate.

The plurality of data drivers 200 are attached to the first substrate of the display panel 100 to supply data signals to the plurality of data lines DL. To this end, each of the plurality of data drivers 200 includes a data flexible circuit film 210 and a data driver integrated circuit 220.

The data flexible circuit film 210 is attached to a data pad part formed in an upper non-display area of the first substrate so as to be connected to the data line DL. Each of the data flexible circuit films 210 may be made of a Tape Carrier Package (TCP) or a Chip On Flexible Board or Chip On Film (COF) and attached to a data pad part by a tape automated bonding (TAB) process.

The data driving integrated circuit 220 is mounted on the data flexible circuit film 210. The data driving integrated circuit 220 may analogize the pixel data by using the pixel data, a data control signal, and a plurality of reference gamma voltages input from an external printed circuit board 400 through the data flexible circuit film 210. The data signal is converted into a data signal, and the converted data signal is supplied to the corresponding data line DL through the data flexible circuit film 210 and the data pad part.

The gate driver 300 is formed in each of the left and right non-display regions of the first substrate, and sequentially supplies first and second gate driving circuits 300a and 300b to the plurality of gate lines GL. It includes.

Each of the first and second gate driving circuits 300a and 300b may include a shift register including the plurality of stages ST1 to STm illustrated in FIG. 2, and each of the stages ST1 to STm. ) May be formed in a structure as shown in FIG. 3 or FIG. 8 described above. Therefore, the description of each of the first and second gate driving circuits 300a and 300b will be replaced with the above description of the shift register.

The printed circuit board 400 is commonly attached to the data flexible circuit film 210 of each of the data drivers 200. The printed circuit board 400 includes a timing controller 500, a user connector (not shown), a power generator (not shown) that generates a common gamma voltage, a common voltage, and various power supply voltages.

The timing controller 500 generates pixel data by aligning the image data input through the user connector to be suitable for driving the display panel 100 and based on the timing synchronization signal input through the user connector (not shown). Generates a data control signal. The pixel data and the data control signal are supplied to each data driver integrated circuit 220 through the printed circuit board 400 and the data flexible circuit film 210.

In addition, as illustrated in FIG. 10, the timing controller 500 controls the gate start signal Vst, the 5-phase clock signals CLK1 to CLK5, and the bias voltage Vtg based on the timing synchronization signal. To generate a gate control signal comprising. The gate control signals are respectively provided to the first and second gate driving circuits 300a and 300b through the printed circuit board 400, the first and last data flexible circuit films 220, and upper edge portions of the first substrate. Supplied to.

The timing controller 500 may not be mounted on the printed circuit board 400, but may be mounted on a separate control board (not shown) connected to the printed circuit board 400. In addition, the gate driver 300 may include only one gate driving circuit of the first and second gate driving circuits 300a and 300b.

As described above, the flat panel display according to the exemplary embodiment of the present invention includes the shift registers of the present invention embedded in the left and right non-display areas of the display panel 100, and as described above, Each pixel is normally driven according to a gate pulse normally output from the stage, thereby displaying a desired image on the display panel 100.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical matters of the present invention. It will be evident to those who have knowledge of.

10: first switching unit 20: second switching unit
30: third switch 40: fourth switch
50: fifth switching unit 100: display panel
110: first substrate 111: first gate electrode
113: semiconductor layer 114: first electrode
115: second electrode 117: second gate electrode
200: data driver 300: gate driver
400: printed circuit board 500: timing control unit

Claims

A shift register comprising a plurality of stages selectively connected to a plurality of clock signal supply lines supplied with a plurality of clock signals and driven dependently according to a gate start signal,
Each of the plurality of stages,
A pull-up transistor having a gate electrode connected to the first node, a first electrode connected to the first clock signal supply line among the plurality of clock signal supply lines, and a second electrode connected to the output node;
A pull-down having a first gate electrode connected to a second node, a first electrode connected to the output node, a second electrode connected to a low potential voltage supply line, and a second gate electrode connected to a bias voltage supply line transistor; And
A node control circuit for controlling a voltage of each of the first and second nodes according to the gate start signal,
And the pull-up transistor and the pull-down transistor each comprise a semiconductor layer made of an oxide.

The method of claim 1,
The node control circuit,
A first switching unit configured to output the gate start signal;
A second switching unit configured to supply a high potential voltage to the second node according to a second clock signal supplied to a second clock signal supply line among the plurality of clock signal supply lines;
A third switching unit configured to supply the gate start signal output from the first switching unit to the first node according to a third clock signal supplied to a third clock signal supply line among the plurality of clock signal supply lines;
A fourth switching unit configured to connect the second node to the low potential voltage supply line according to the gate start signal; And
And a fifth switching unit for connecting the first node to the low potential voltage supply line according to the voltage of the second node.

The method of claim 2,
And each of the first to fifth switching units comprises at least one transistor including a semiconductor layer made of an oxide.

The method of claim 3, wherein
And the pull-down transistor has a positive threshold voltage according to a bias voltage supplied from the bias voltage supply line to the second gate electrode.

The method of claim 3, wherein
The fifth switching unit includes a first gate electrode commonly connected to the second node, a first electrode and a second electrode connected in series between the first node and the low potential voltage supply line, and the bias voltage supply line. A pair of transistors including a second gate electrode connected in common,
Each of the pair of transistors has a positive threshold voltage in accordance with a bias voltage supplied from the bias voltage supply line to the second gate electrode.

The method of claim 5,
Each of the plurality of stages further comprises a bias voltage transistor for selectively supplying the bias voltage to a second gate electrode of each of the pull-down transistor and the pair of transistors in accordance with a bias control signal.

The method according to claim 4 or 5,
The bias voltage has a negative voltage level.

A display panel including a display area including a plurality of pixels formed for each pixel area defined by intersections of the plurality of gate lines and the plurality of data lines, and a non-display area defined around the display area;
A plurality of data drivers for converting input pixel data into data signals and supplying the data signals to the plurality of data lines; And
A gate driver formed in a non-display area of the display panel to be connected to the plurality of gate lines, the gate driver configured to sequentially supply gate pulses to the plurality of gate lines;
The said gate drive circuit contains the shift register of any one of Claims 1-6, The flat panel display apparatus.

The method of claim 8,
And a timing controller for converting input image data into the pixel data and supplying the data to the data driver, and supplying a gate control signal including the gate start signal, the plurality of clock signals, and a bias voltage to the gate driving circuit. Flat display device.

The method of claim 9,
And the bias voltage has a negative voltage level.