KR102041872B1

KR102041872B1 - Shift register and flat panel display device using the same

Info

Publication number: KR102041872B1
Application number: KR1020130050103A
Authority: KR
Inventors: 양정열
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-05-03
Filing date: 2013-05-03
Publication date: 2019-11-07
Also published as: KR20140131137A

Abstract

The present invention relates to a flat panel display device, and more particularly, to provide a shift register and a flat panel display device using the same, in which a pull-up transistor is formed in a double gate structure. To this end, the shift register according to the present invention includes a plurality of stages, each of which is separated from each other by a first electrode connected to a clock signal supply line and a second electrode connected to an output node. A pull-up transistor comprising two gate electrodes commonly connected to the first node; A pull-down transistor comprising a gate electrode connected to a second node, a first electrode connected to the output node, and a second electrode connected to a voltage supply line; And a node control circuit for controlling a voltage supplied to the first node and the second node according to a gate start signal.

Description

SHIFT REGISTER AND FLAT PANEL DISPLAY DEVICE USING THE SAME}

The present invention relates to a shift register and a flat panel display including the same.

Flat panel displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and more recently, an electrophoretic display. (EPD: ELECTROPHORETIC DISPLAY) is also widely used.

The gate driver of the flat panel display device as described above includes a shift register for sequentially supplying gate pulses (pull-up signals) to the plurality of gate lines. The shift register includes a plurality of stages including a plurality of transistors, and the stages are cascaded to sequentially output the gate pulses.

Recently, a GIP (gate in panel) type in which a thin film transistor constituting the shift register of the gate driver is incorporated in a panel of the flat panel display device is widely used.

In each of the stages constituting the shift register of the GIP type, a pull-up transistor (PU) for outputting an output signal capable of turning on a switching transistor formed in each pixel of the panel and the switching transistor may be turned off. It may be configured to include a pull-down transistor (PD) for outputting an output signal.

That is, the output signal output from the one stage is transmitted to one gate line to turn on or off the switching transistor connected to the gate line, also referred to as a scan signal.

The scan signal further includes a pull-up signal for turning on the switching transistor and a pull-down signal for turning off the switching transistor.

The pull-up signal is output only during one horizontal period during which the data voltage is applied to the panel during one vertical period, and the pull-down signal is transmitted to the gate line during most of the one vertical period.

In each stage of a general gate driver, one pull-down transistor PD is used to transfer the pull-down signal to the gate line.

In this case, since the pull-down signal is output only for most of one vertical period, when the pull-down transistor is used for a long time, the pull-down transistor PD may deteriorate, thereby reducing the reliability of the circuit. Can be.

Therefore, recently, a gate driver in which two pull-down transistors are alternately driven has been developed.

On the other hand, in the conventional shift register as described above, the size of the pull-up transistor is large so that the pull-up transistor can produce a sufficient output. That is, the pull-up transistor for generating the pull-up signal is formed several times to several tens of times larger than other transistors formed in the shift register of the GIP type and operated.

For example, when the size of the pull-down transistor is 12/10 (W / L, μm), the size of the pull-up transistor is 300/10 (W / L, μm), and the size of the pull-up transistor is the pull-down transistor. It is about 25 times larger than the size of.

In other words, the pull-up transistor occupies a large area in the shift register. This increases the size of the entire circuit of the shift register of the GIP type.

The gate driver including the shift registers of the GIP type is formed in a non-display area (Bezel area) of the panel. Therefore, increasing the size of the gate driver means that the non-display area becomes large.

That is, as the size of the pull-up transistor formed in the shift register of the GIP type increases, the size of the non-display area increases. This phenomenon may impede the development of a design to minimize the size of the non-display area.

In particular, the size of the non-display area in which the shift register in which two pull-down transistors are formed is larger than the size of the non-display area in which the shift resistor in which one pull-down transistor is formed. Therefore, it is more difficult to reduce the size of the non-display area in a flat panel display using a shift register in which two pull-down transistors are formed.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and it is a technical object of the present invention to provide a shift register and a flat panel display device using the same, in which a pull-up transistor has a double gate structure.

The shift register according to the present invention for achieving the above-described technical problem includes a plurality of stages, each of the plurality of stages, the first electrode connected to the clock signal supply line, and the second electrode connected to the output node A pull-up transistor comprising an electrode and two gate electrodes separated from each other and commonly connected to the first node; A pull-down transistor comprising a gate electrode connected to a second node, a first electrode connected to the output node, and a second electrode connected to a voltage supply line; And a node control circuit for controlling a voltage supplied to the first node and the second node according to a gate start signal.

According to an aspect of the present invention, there is provided a flat panel display including: a panel in which pixels are formed at intersections of data lines and gate lines; A data driver for supplying a data voltage to the data lines; A timing controller driving the data driver; And a pull-up transistor embedded in a non-display area of the panel and driven by a clock signal input from the timing controller to sequentially supply a pull-up signal to the gate lines and to output the pull-up signal to the gate line. Includes a panel embedded gate driver formed of a double gate structure.

According to the present invention, since the pull-up transistor has a double gate structure, the power of the pull-up transistor can be increased.

Since the power of the pull-up transistor can be increased, the size of the pull-up transistor can be reduced, and the size of the pull-up transistor can be reduced, so that the size of the shift register including the pull-up transistor can be reduced. Since the size of the shift register can be reduced, the size of the non-display area in which the shift register is formed can be reduced.

In addition, since the size of the non-display area can be reduced, it is possible to implement a narrow bezel.

That is, according to the present invention, since the size of the pull-up transistor is reduced, the size of the non-display area (bezel) can be reduced, and power consumption can also be reduced.

1 is a view schematically showing a flat panel display device according to the present invention.
2 is an exemplary view showing a configuration of a shift register of a panel embedded gate driver applied to a flat panel display device according to the present invention;
3 is a circuit diagram of an embodiment of a stage applied to a shift register according to the present invention;
4 is a cross-sectional view of one embodiment of a pull-up transistor applied to the stage shown in FIG.
5 is an exemplary view showing waveforms of signals supplied to a pull-up transistor shown in FIG.
6 is an exemplary view for explaining the effect of the shift register according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a view schematically showing a flat panel display device according to the present invention.

In the flat panel display device according to the present invention, as shown in FIG. 1, a panel 100 in which pixels are formed at intersections of data lines DL1 to DLd and gate lines GL1 to GLg, and the data A data driver 300 for supplying data voltages to the lines DL1 to DLd, a timing controller 400 for driving the data driver 300, and a non-display area of the panel 100. And a panel embedded gate driver 200 which is driven by a clock signal input from the controller 400 and sequentially supplies scan signals to the gate lines GL1 to GLg.

First, the panel 100 includes pixels P formed in regions defined by intersections of the gate lines GL1 to GLg and the data lines DL1 to DLd formed in the display area 110. The panel 100 may be a panel applied to a liquid crystal display (LCD), a panel applied to an organic light emitting display (OLED), or a panel applied to an electrophoretic display (EPD). In addition to the flat panel display devices described above, the panel 100 may be a panel applied to various types of flat panel display devices driven by a pull-up signal (scan signal).

The panel 100 includes a first substrate and a second substrate that are opposed to each other.

The first substrate includes a display area 110 and a display area having a plurality of pixels P formed in a pixel area defined by an intersection of a plurality of gate lines GL and a plurality of data lines DL. It includes a non-display area 120 provided around the 110.

Each of the plurality of pixels P displays an image according to a pull-up signal supplied from an adjacent gate line GL and a data voltage supplied from an adjacent data line DL.

The pixel P may include at least one thin film transistor and at least one capacitor. The pixel P may be a liquid crystal cell that displays an image by controlling the light transmittance of the liquid crystal according to the data voltage, or may be a light emitting cell that displays an image by emitting light in proportion to the current according to the data voltage. In addition to the liquid crystal cell or the light emitting cell, the pixel P may be formed in various shapes according to the type of the panel 100.

The second substrate covers the entirety of the first substrate except for a portion of the non-display area 120. When the pixel P is formed of a liquid crystal cell, a color filter layer may be formed on the second substrate. When the pixel P is formed of a light emitting cell, the second substrate may function as an encapsulation substrate (encap) that seals the first substrate 110. The second substrate may also be formed in various forms according to the type of the panel 100.

The thin film transistor TFT formed in each of the pixels P is turned on by a pull-up signal supplied from the gate line, and the data voltage supplied from the data line is formed in the pixel P. The organic light emitting diode OLED formed in the pixel P or supplied to the pixel electrode is emitted.

That is, the panel 100 displays an image by the pull-up signal supplied through the gate line GL and the data voltage supplied through the data line DL, and may be formed in various forms. Can be. In addition, the flat panel display device according to the present invention may be a liquid crystal display device, an organic light emitting display device, or an electrophoretic display device (EPD) according to the type of the panel 100. Hereinafter, for convenience of description, the present invention will be described with an example in which the flat panel display is a liquid crystal display and the panel 100 is a liquid crystal panel.

Next, the data driver 300 converts the digital image data transmitted from the timing controller 400 into a data voltage to convert the data voltage of one horizontal line for every one horizontal period during which a pull-up signal is supplied to the gate line. Supply to the data lines.

As illustrated in FIG. 1, the data driver 300 may be a source driver IC connected to the panel 100 in a chip on film (COF) form or a tape carrier package (TCP) method. In this case, at least one data driver 300 may be connected to the panel 100. In addition, the at least one data driver 300 formed of the source drive IC may be directly disposed in the non-display area 120 of the panel 100.

The data driver 300 converts the image data into the data voltage using the gamma voltages supplied from a gamma voltage generator (not shown), and then outputs the image data to the data line. To this end, the data driver 300 includes a shift register unit, a latch unit, a digital analog converter (DAC), and an output buffer.

The shift register unit outputs a sampling signal by using data control signals SSC and SSP received from the timing controller 400.

The latch unit latches the digital image data Data sequentially received from the timing controller 400, and simultaneously outputs the digital image data to the digital analog converter DAC.

The digital-to-analog converter converts the image data transmitted from the latch unit into a positive or negative data voltage at the same time and outputs the data voltage. That is, the digital-to-analog converter determines the image data according to the polarity control signal POL transmitted from the timing controller 400 by using the gamma voltage supplied from the gamma voltage generator (not shown). The data voltage is converted into a polarity or a negative data voltage and output to the data lines.

The output buffer is a data line DL of the panel according to the source output enable signal SOE transmitted from the timing controller 400 to the positive or negative data voltage transmitted from the digital analog converter. Output to

Next, the timing controller 400 uses the timing signal input from the external system 600, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE. The gate control signal GCS for controlling the operation timing of the panel embedded gate driver 200 and the data control signal DCS for controlling the operation timing of the data driver 300 are generated, and the data driver 300 is generated. Create image data to be transmitted to.

To this end, the timing controller 400 may include a receiver for receiving input image data and timing signals from the external system 600, a control signal generator for generating various control signals, and the input image data. Rearranging the data, the data aligning unit for outputting the rearranged image data, and an output unit for outputting the control signals and the image data.

In other words, the timing controller 400 rearranges the input image data input from the external system 600 according to the structure and characteristics of the panel 100 and realigns the rearranged image data with the data driver. Send to 300. This function may be executed in the data alignment unit.

The timing controller 400 uses the timing signals transmitted from the external system 600, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE. A data control signal DCS for controlling a driver and a gate control signal GCS for controlling the panel embedded gate driver 200 are generated, and the control signals are generated by the data driver and the panel embedded gate driver 200. Perform the function of sending to. Such a function may be executed in the control signal generator.

The gate control signals GCS generated by the control signal generator include a gate output enable signal GOE, a gate start signal VST, a clock signal CLK, and the like.

The data control signals generated by the control signal generator include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like.

Finally, the panel embedded gate driver 200 sequentially supplies a pull-up signal to each of the gate lines GL1 to GLg by using the gate control signals GCS generated by the timing controller 400. .

Here, the pull-up signal refers to a voltage capable of turning on the switching thin film transistors connected to the gate lines. The voltage capable of turning off the switching thin film transistor is called a pull-down signal, and the pull-up signal and the pull-down signal are collectively called a scan signal.

When the thin film transistor is N type, the pull-up signal is a high level voltage and the pull-down signal is a low level voltage. When the thin film transistor is a P type, the pull-up signal is a low level voltage, and the pull-down signal is a high level voltage.

The panel embedded gate driver 200 receives the gate control signal generated by the timing controller and sequentially outputs the pull-up signal to the gate lines using the gate control signal.

A detailed internal configuration of the panel embedded gate driver 200 will be described below with reference to FIGS. 2 to 4.

FIG. 2 is an exemplary diagram illustrating a configuration of a shift register of a panel embedded gate driver applied to a flat panel display device according to the present invention.

In the panel-type gate driver 200 applied to the flat panel display device according to the present invention, as illustrated in FIG. 2, the shift register according to the present invention includes a plurality of stages 230 connected to each gate line. 210.

The stages are embedded in a non-display area of the panel. That is, the stages are formed in the non-display area through the manufacturing process of the elements formed in the display area.

The number of the stages 230 may be variously set according to the structure and size of the panel, the number of gate lines, and the like. 2 shows a shift register 210 applied to the panel 100 having 1080 gate lines as an example of the present invention. In this case, each of the 1080 stages 230 constituting the shift register 210 is connected one-to-one with 1082 gate lines.

Referring to the basic operation of the shift register 210 according to the present invention.

When the gate start signal VST is input from the timing controller 400 to the first stage Stage1 of the stages 230, the first stage Stage1 starts driving. The first stage Vstage1 generates a first pull-up signal VGOUT1 using the clock signal CLK and the gate start signal VST transmitted from the timing controller 400 to generate a first gate line V1. While outputting to GL1), the first pull-up signal is transmitted to the second stage Stgae. The second stage Stage2 starts driving by the first pull-up signal VGOUT1 and then generates a second pull-up signal VGOUT2 using the clock signal CLK and the gate start signal VST. Output to the second gate line GL2.

The operation as described above is similarly repeated from the third stage (Stage3) to the 1080th stage (Stage1080).

That is, the stages sequentially output the scan signal VGOUT to each gate line using the clock signal CLK and the gate start signal VST.

The method of driving the stages may be variously formed according to the number of clock signals input to the stages and the shape of a clock signal. That is, in the above description, only one clock signal is input to each of the stages, but the present invention is not limited thereto. Thus, two or more clock signals may be input to the stages to drive the stages.

3 is an exemplary circuit diagram of a stage applied to a shift register according to the present invention, FIG. 4 is a cross-sectional view of an embodiment of a pull-up transistor applied to the stage illustrated in FIG. 3, and FIG. 5 is a pull-up illustrated in FIG. 3. 6 is an exemplary diagram illustrating waveforms of signals supplied to a transistor, and FIG. 6 is an exemplary diagram illustrating an effect of a shift register according to the present invention.

Each stage 230 constituting the shift register according to the present invention includes a pull-up transistor Tu for outputting a pull-up signal, a pull-down transistor Td for outputting a pull-down signal, and a node control circuit as shown in FIG. 3. (NCC).

In the following, a shift register including the stage shown in FIG. 3 is described as an example of the present invention. That is, the shift register according to the present invention is not limited to the configuration shown in FIG.

In addition, although the pull-up transistor Tu, the pull-down transistor Td and other transistors constituting the stage 230 shown in FIG. 3 are configured as N type, the present invention is not limited thereto.

In addition, although the stage 230 illustrated in FIG. 3 uses two pull-down transistors Td1 and Td2, the present invention is not limited thereto. That is, each stage applied to the shift register according to the present invention may use only one pull-down transistor.

First, the pull-up transistor Tu includes a first electrode connected to a clock signal supply line, a second electrode connected to an output node, and two gate electrodes commonly connected to the first node in a separated state. Include. Among the two gate electrodes, the first gate electrode 111 is connected to the first node Q. The second gate electrode 117 of the two gate electrodes is connected to the first node Q, and is separated from the first gate electrode, and the first electrode and the second electrode have an insulating layer therebetween. It is arranged on the electrode.

The pull-up transistor Tu is turned on according to the voltage of the first node Q to supply the clock signal CLK of the pull-up signal level to the output node No.

In particular, when a turn-on voltage capable of turning on the pull-up transistor Tu is supplied to the first node Q, the turn-on voltage is applied to the first gate electrode 111 and the second gate electrode 117. By being supplied at the same time, the power of the pull-up signal output to the output node No through the pull-up transistor Tu may be increased.

That is, the pull-up transistor Tu has a double gate structure including a bottom gate electrode (first gate electrode) 111 and a top gate electrode (second gate electrode) 117. The first gate electrode 111 and the second gate electrode 117 are both connected to the first node Q. Therefore, when the first node Q is charged and a high voltage is supplied to the first gate electrode 111 so that the pull-up transistor Tu is turned on, the first node Q is turned on. The high voltage is applied to the second gate electrode 117 at the same time.

As a result, a wider path through which electrons (or holes) may move is formed in an active layer constituting the pull-up transistor Tu, and is output through the pull-up transistor Tu. The power of the pull up signal may be increased.

When the first node Q is discharged and a low voltage is supplied to the first gate electrode 111, a low voltage is also supplied to the second gate electrode 117, so that the pull-up transistor Tu is applied. Is turned on. As a result, the output of the pull-up signal is stopped.

The configuration of the pull-up transistor Tu will be described with reference to FIG. 4 as follows.

The pull-up transistor Tu may include the first gate electrode 111 formed on the first substrate 110 of the panel 100, the gate insulating layer 112 covering the first gate electrode 111, and the first gate electrode 111. The semiconductor layer (active layer, ACT) 113 formed on the gate insulating layer 112 so as to overlap one gate electrode 111, and the channel of the semiconductor layer 113 overlapping the first gate electrode 111. A protective layer covering the first electrode 114, the second electrode 115, the semiconductor layer 113, the first electrode 114, and the second electrode 115 formed side by side with an area therebetween. 116 and the second gate electrode 117 formed on the protective layer 116 so as to overlap the first gate electrode 111. Although not illustrated, the first electrode 114 and the second electrode 115 may be formed on the semiconductor layer 113 with an ohmic contact layer therebetween.

First, the first gate electrode 111 is connected to the first node Q.

Second, the insulating layer 112 insulates the first gate electrode 111 from the first electrode 114, the second electrode 115, and the semiconductor layer 113.

The set material and the semiconductor layer 113 may be formed of an oxide such as zinc oxide, tin oxide, ga-in-zn oxide, in-zn oxide, or in-sn oxide, or may include Al, Ni, Cu, Ta, Ions of Mo, Zr, V, Hf or Ti materials can be made of oxides doped. The semiconductor layer 113 includes a channel region, a source region, and a drain region, and the channel region overlaps the first gate electrode 110. The semiconductor layer 113 forms a path through which electrons or holes move.

Fourth, the first electrode 114 and the second electrode 115 perform the functions of the source terminal and the drain terminal of the pull-up transistor Tu.

Fifth, the protective layer 116 protects the first electrode 114, the second electrode 115, and the semiconductor layer 113, while the protective layer 116 protects the first electrode 114. The second electrode 115 and the semiconductor layer 113 are insulated from the second gate electrode 117.

Sixth, the second gate electrode 117 may be formed in the passivation layer 116 so as to partially or completely overlap the first gate electrode 111. The second gate electrode 117 is connected to the first node Q like the first gate electrode 111.

Meanwhile, in FIG. 3, although the second gate electrode 117, the first electrode 114, and the second electrode 115 of the pull-up transistor Tu are illustrated in different layers, The invention is not limited thereto. That is, each of the second gate electrode 117, the first electrode 114, and the second electrode 115 of the pull-up transistor Tu may be overlapped with each other on the semiconductor layer 113. It may be formed in the layer. In this case, each of the first electrode 114 and the second electrode 115 of the pull-up transistor Tu may be connected to the semiconductor layer 113 through a contact hole (not shown).

As described above, in the pull-up transistor Tu, since the turn-on voltage is simultaneously supplied to the first gate electrode 111 and the second gate electrode 117, the output through the pull-up transistor Tu. The power of the pull-up signal output to the node No may be increased.

That is, in the present invention, as shown in FIG. 5, the voltage of the first node Q supplied to the first gate electrode 111 is also supplied to the second gate electrode 117, thereby providing the same timing. The same voltage is applied to the first gate electrode 111 and the second gate electrode 117. As a result, a path of the semiconductor layer 113 is extended, and a large amount of current flows along the semiconductor layer 113. As a result, the power of the pull-up signal Vout output from the pull-up transistor Tu is increased. Will increase.

Features of the present invention as described above, can be confirmed through FIG. That is, as shown in FIG. 6, at the same gate source voltage Vgs, the voltage supplied to the second gate electrode 117 is increased so that the voltage supplied to the second gate electrode 117 is the second voltage. As it becomes equal to the voltage applied to the one-gate electrode 117 (arrow direction), the current Id flowing through the pull-up transistor Tu increases. Accordingly, when the voltage of the first node Q is simultaneously supplied to the first gate electrode 111 and the second gate electrode 117, the pull-up signal Vout output from the pull-up transistor Tu may be used. The output is increased.

Next, the pull-down transistor Td includes a gate electrode connected to a second node QB, a first electrode connected to the output node No, and a second electrode connected to a low potential voltage Vss supply line. do.

The pull-down transistor Td is turned on according to the voltage on the second node QB connected to the gate electrode to supply the low potential voltage Vss of the pull-down signal level to the output node No.

3 shows a stage in which two pull-down transistors Td are formed. In this case, the two pull-down transistors Td1 and Td2 may be operated alternately every frame or at least two frames. That is, the two pull-down transistors are alternately operated every predetermined period.

However, as mentioned above, the present invention is not limited to a stage having two pull-down transistors.

Finally, the node control circuit NCC uses the gate start signal VST, the high potential voltage Vdd, and the low potential voltage Vss to form the first node Q and the second node QB. Control each voltage.

The node control circuit NCC is driven by the gate start signal VST to drive the high potential voltage Vdd to the first gate electrode 111 and the second gate electrode of the pull-up transistor Tu. 117). That is, a turn-on voltage (high potential voltage Vdd) for turning on the pull-up transistor is supplied to the first node Q. When the pull-up transistor Tu is turned on by the high potential voltage Vdd, the clock signal CLK is output to the output node No through the pull-up transistor Tu. The clock signal CLK output through the output node No is supplied to the gate line connected to the output node No as the pull-up signal.

The node control circuit NCC may turn off the pull-down transistor to the second node QB while the high-potential voltage Vdd is supplied to the pull-up transistor Tu, namely, The low potential voltage Vss is supplied to turn off the pull-down transistor Td, thereby preventing the low potential voltage Vss from being output to the output node No to which the pull-up signal is being output.

Meanwhile, the stage illustrated in FIG. 3 is an n-th stage, and in the n-th stage, the n-second pull-up signal Vout (outputted from the n-th -2th stage as the gate start signal VST) is output. n-2) is used.

That is, when the first transistor T1 is turned on by the n-th second pull-up signal Vout (n-2), the high potential voltage Vdd becomes the first transistor T1 through the first transistor T1. Supplied to node Q.

The high potential voltage Vdd supplied to the first node Q is supplied to the first gate electrode 111 and the second gate electrode 117 of the pull-up transistor Tu. When the pull-up transistor Tu is turned on by the high potential voltage Vdd, the pull-up signal is output through the pull-up transistor Tu, and the pull-up signal is supplied to the gate line through the output node No. do.

In this case, a turn-off voltage for turning off the two pull-down transistors Td1 and Td2 is input to the gate electrodes of the two pull-down transistors Td1 and Td2. Thus, no signal is output from the two pull-down transistors.

When the output of the n-th second pull-up signal is stopped and the n + 2-th pull-up signal is output, the first transistor T1 is turned off and the second transistor T2 is turned on.

Therefore, the low potential voltage Vss is supplied to the first node Q instead of the high potential voltage Vdd. The low potential voltage is an x turn-off transition that turns off the pull-up transistor. Accordingly, the pull-up transistor Tu is turned off so that the pull-up signal is not output from the pull-up transistor.

As an example, in the stage shown in FIG. 3, the first pull-down transistor Td1 is driven in an odd frame and the second pull-down transistor Td2 is driven in an even frame.

In this case, when the output of the pull-up signal is stopped from the n-th stage shown in FIG. 3 after the odd-numbered frame starts, by the combination of the odd-numbered driving voltage Vdd_o and the even-numbered driving voltage Vdd_e, The first pull-down transistor Td1 is turned on. That is, a turn-on voltage capable of turning on the first pull-down transistor is supplied to the gate electrode of the first pull-down transistor by the combination of the odd-numbered driving voltage and the even-numbered driving voltage.

When the first pull-down transistor Td1 is turned on, the low potential voltage Vss is output to the gate line through the output node No through the first pull-down transistor Td1.

When the output of the pull-up signal is stopped from the n-th stage shown in FIG. 3 after the even-numbered frame starts, by the combination of the odd-numbered driving voltage Vdd_o and the even-numbered driving voltage Vdd_e, The first pull-down transistor Td2 is turned on.

When the second pull-down transistor Td2 is turned on, the low potential voltage Vss is output to the gate line through the output node No through the second pull-down transistor Td2.

For the operation as described above, the third transistor T3 to the tenth transistor T10 connected to the first pull-down transistor Td1 and the second pull-down transistor Td2 may be configured in various forms. have.

That is, the node control circuit NCC is not limited to the configuration shown in FIG. 3, and is configured in various forms and may be driven in various ways.

The present invention as described above is summarized as follows.

First, the second gate electrode (Top Gate) is formed in the pull-up transistor Tu together with the first gate electrode, so that the pull-up transistor Tu is formed in a double gate structure. The two gate electrodes are connected to the first node Q of the node control circuit NCC.

When the first node Q is charged and the turn-on voltage is simultaneously applied to the first gate electrode and the second gate electrode of the pull-up transistor Tu, a wider path to the semiconductor layer 113 of the pull-up transistor ( Path) is formed to increase the power of the pull-up signal output from the pull-up transistor.

Second, the double gate structure may be applied to all the transistors formed in the pull-down transistor Td and the node control circuit NCC, in addition to the pull-up transistor Tu. That is, the double gate structure can be applied to all transistors generating an output.

Third, the present invention can be applied to shift registers of various types (DAC, DC, SLC etc.) regardless of the type of the node control circuit (NCC).

Fourth, according to the present invention, the size of the pull-up transistor can be reduced, and even if the size of the pull-up transistor is reduced, the power of the pull-up signal output through the pull-up transistor can be increased.

Fifth, according to the present invention, since the size of the pull-up transistor is reduced, the size of the non-display area in which the shift register is formed can be reduced, thereby enabling the narrow bezel to be implemented.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: panel 200: gate driver
300: data driver 400: timing controller
600: external system Tu: pull-up transistor
Td: pull-down transistor NCC: node control circuit

Claims

Including a plurality of stages,
Each of the plurality of stages,
A pull-up transistor comprising a first electrode connected to a clock signal supply line, a second electrode connected to an output node, and two gate electrodes separated from each other and commonly connected to the first node;
A pull-down transistor comprising a gate electrode connected to a second node, a first electrode connected to the output node, and a second electrode connected to a voltage supply line; And
A node control circuit for controlling a voltage supplied to the first node and the second node according to a gate start signal,
A first gate electrode of the two gate electrodes is connected to the first node,
A second gate electrode of the two gate electrodes is connected to the first node, is separated from the first gate electrode, overlaps with the first gate electrode,
And the pull-up transistor is turned on by a voltage supplied from the first node to output a clock signal supplied through the clock signal supply line to a gate line through the output node.

delete

The method of claim 1,
The pull-up transistor,
A first gate electrode formed on the substrate;
A gate insulating layer covering the first gate electrode;
A semiconductor layer formed on the gate insulating layer so as to overlap the first gate electrode;
The first electrode and the second electrode formed to be parallel to each other with the channel region of the semiconductor layer overlapping the first gate electrode;
A protective layer covering the semiconductor layer, the first electrode, and the second electrode; And
And a second gate electrode formed on the passivation layer so as to overlap the first gate electrode.

The method of claim 1,
And the pull-down transistor is turned on by a voltage supplied from the second node to output a voltage supplied through the voltage supply line to the gate line through the output node.

The method of claim 4, wherein
The clock signal is a pull-up signal for turning on a switching transistor formed in the gate line,
And the voltage supplied through the voltage supply line and output to the gate line through the output node is a pull-down signal for turning off the switching transistor.

The method of claim 4, wherein
The node control circuit,
Supplying a turn-off voltage for turning off the pull-down transistor to the second node while a turn-on voltage for turning on the pull-up transistor is supplied to the first node,
And a turn-on voltage for turning on the pull-down transistor to the second node while a turn-off voltage for turning off the pull-up transistor is supplied to the first node.

The method of claim 1,
The pull-down transistor,
A first pull-down transistor and a second pull-down transistor,
The node control circuit,
And the first pull-down transistor and the second pull-down transistor are alternated every predetermined period.

The method of claim 1,
And the stages are embedded in a non-display area of the panel.

A panel in which pixels are formed at intersections of the data lines and the gate lines;
A data driver for supplying a data voltage to the data lines;
A timing controller driving the data driver; And
A pull-up transistor embedded in a non-display area of the panel and driven by a clock signal input from the timing controller to sequentially supply a pull-up signal to the gate lines and to output the pull-up signal to the gate line; Including a panel built-in gate driver formed of a double gate structure,
The pull-up transistor includes a first electrode connected to a clock signal supply line, a second electrode connected to an output node, and two gate electrodes separated from each other and commonly connected to the first node,
A first gate electrode of the two gate electrodes is connected to the first node,
A second gate electrode of the two gate electrodes is connected to the first node, is separated from the first gate electrode, overlaps with the first gate electrode,
And the pull-up transistor is turned on by a voltage supplied from the first node and outputs a clock signal supplied through the clock signal supply line to a gate line through the output node.

The method of claim 9,
The panel embedded gate driver includes a plurality of stages,
Each of the plurality of stages,
The pull-up transistor;
A pull-down transistor comprising a gate electrode connected to a second node, a first electrode connected to the output node, and a second electrode connected to a voltage supply line; And
And a node control circuit for controlling a voltage supplied to the first node and the second node according to a gate start signal.