KR20140131137A

KR20140131137A - Shift register and flat panel display device using the same

Info

Publication number: KR20140131137A
Application number: KR1020130050103A
Authority: KR
Inventors: 양정열
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-05-03
Filing date: 2013-05-03
Publication date: 2014-11-12
Also published as: KR102041872B1

Abstract

The present invention relates to a flat panel display, and more particularly, to a shift register in which a pull-up transistor is formed in a double gate structure and a flat panel display using the same. To this end, a shift register according to the present invention includes a plurality of stages, each of the plurality of stages including a first electrode connected to a clock signal supply line, a second electrode connected to the output node, A pull-up transistor including two gate electrodes commonly connected to a first node; A pull-down transistor including a gate electrode connected to a second node, a first electrode connected to the output node, and a second electrode connected to a voltage supply line; And a node control circuit for controlling a voltage supplied to the first node and the second node in accordance with the gate start signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a shift register and a flat panel display using the shift register,

The present invention relates to a shift register and a flat panel display including the same.

Flat panel displays (FPDs) are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. Examples of flat panel display devices include a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) (EPD: ELECTROPHORETIC DISPLAY) are also widely used.

The gate driver of the flat panel display device as described above includes a shift register for sequentially supplying gate pulses (pull-up signals) to a plurality of gate lines. The shift register includes a plurality of stages including a plurality of transistors, and the stages are cascade-connected to sequentially output the gate pulses.

In recent years, a GIP (gate in panel) type in which a thin film transistor constituting a shift register of the gate driver is embedded in a panel of the flat panel display device is widely used.

Each of the stages constituting the GIP type shift register includes a pull-up transistor (PU) for outputting an output signal capable of turning on a switching transistor formed in each pixel of the panel, and a pull- And a pull-down transistor PD for outputting an output signal.

That is, the output signal output from one stage is transferred to one gate line, turning on or off the switching transistor connected to the gate line, and is also referred to as a scan signal.

The scan signal again includes a pull-up signal for turning on the switching transistor and a pull-down signal for turning off the switching transistor.

The pull-up signal is output during one horizontal period during which the data voltage is applied to the panel during one vertical period, and the pull-down signal is transmitted to the gate line during most of the remaining vertical periods.

In each stage of a general gate driver, the pull-down signal is transmitted to the gate line using one pull-down transistor PD.

In this case, since the pull-down signal is outputted only during most of the time of one vertical period, if the pull-down transistor is used for a long time, the pull-down transistor PD may be deteriorated, .

Therefore, in recent years, a gate driver in which two pull-down transistors are alternately driven has been developed.

On the other hand, in the conventional shift register as described above, the size of the pull-up transistor is formed so that the pull-up transistor can output a sufficient output. That is, the pull-up transistor for generating the pull-up signal is formed several times to several tens times larger than other transistors formed and operated in the shift register of the GIP type.

For example, when the size of the pull-down transistor is 12/10 (W / L, 탆), the size of the pull-up transistor is 300/10 (W / L, Which is about 25 times larger than the size of the "

That is, the pull-up transistor occupies a large area in the shift register. As a result, the size of the entire circuit of the GIP type shift register becomes large.

The gate driver including the GIP type shift registers is formed in a non-display area (Bezel area) of the panel. Therefore, the larger the size of the gate driver means that the non-display area is larger.

That is, as the size of the pull-up transistor formed in the GIP type shift register increases, the size of the non-display region becomes larger. This phenomenon may hinder the development of a design that minimizes the size of the non-display area.

In particular, the size of the non-display area where the shift register in which two pull-down transistors are formed is larger than the size of the non-display area in which the shift register in which one pull-down transistor is formed is formed. Therefore, in a flat panel display device using a shift register in which two pulldown transistors are formed, it is further difficult to reduce the size of the non-display region.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above problems, and it is a technical object to provide a shift register and a flat panel display using the shift register, in which the pull-up transistor is formed in a double gate structure.

According to an aspect of the present invention, there is provided a shift register including a plurality of stages, each of the plurality of stages including a first electrode connected to a clock signal supply line, a second electrode connected to the output node, A pull-up transistor including an electrode, two gate electrodes separated from each other and commonly connected to a first node, A pull-down transistor including a gate electrode connected to a second node, a first electrode connected to the output node, and a second electrode connected to a voltage supply line; And a node control circuit for controlling a voltage supplied to the first node and the second node in accordance with the gate start signal.

According to an aspect of the present invention, there is provided a flat panel display comprising: a panel having pixels formed at intersections of data lines and gate lines; A data driver for supplying a data voltage to the data lines; A timing controller for driving the data driver; And a pull-up transistor which is built in a non-display area of the panel and is driven by a clock signal inputted from the timing controller to sequentially supply a pull-up signal to the gate lines, And a panel built-in gate driver having a double gate structure.

According to the present invention, since the pull-up transistor is formed in the double gate structure, the power of the pull-up transistor can be increased.

Since the size of the pull-up transistor can be reduced and the size of the pull-up transistor can be reduced since the power of the pull-up transistor can be increased, the size of the shift register including the pull-up transistor can be reduced, Since the size of the shift register can be reduced, the size of the non-display area where the shift register is formed can be reduced.

In addition, since the size of the non-display region can be reduced, Narrow Bezel can be implemented.

That is, according to the present invention, since the size of the pull-up transistor is reduced, the size of the non-display region (bezel) can be reduced and the power consumption can also be reduced.

1 is a view schematically showing a flat panel display according to the present invention.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a flat panel display device, and more particularly,
3 is a circuit diagram of an embodiment of a stage applied to a shift register according to the present invention.
4 is a sectional view of one embodiment of a pull-up transistor applied to the stage shown in FIG.
5 is an exemplary view showing a waveform of signals supplied to the pull-up transistor shown in FIG.
6 is an exemplary diagram for explaining the effect of the shift register according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view schematically showing a flat panel display device according to the present invention.

1, the flat panel display according to the present invention includes a panel 100 in which pixels are formed at intersecting regions of data lines DL1 to DLd and gate lines GL1 to GLg, A data driver 300 for supplying a data voltage to the lines DL1 to DLd, a timing controller 400 for driving the data driver 300, And a panel built-in gate driver 200 driven by a clock signal input from the controller 400 to sequentially supply a scan signal to the gate lines GL1 to GLg.

The panel 100 includes pixels P formed in each of the regions defined by intersections of the gate lines GL1 to GLg formed in the display region 110 and the data lines DL1 to DLd. The panel 100 may be a panel applied to a liquid crystal display (LCD), a panel applied to an organic light emitting diode (OLED), or a panel applied to an electrophoretic display (EPD). In addition, the panel 100 may be a panel applied to various types of flat panel display devices driven by a pull-up signal (scan signal) in addition to the flat panel display devices.

The panel 100 includes a first substrate and a second substrate facing each other.

The first substrate includes a display region 110 having a plurality of pixels P formed in a pixel region defined by the intersection of a plurality of gate lines GL and a plurality of data lines DL, And a non-display area 120 provided in the periphery of the display area 110.

Each of the plurality of pixels P displays an image according to a data voltage supplied from a data line DL adjacent to a pull-up signal supplied from an adjacent gate line GL.

The pixel P may include at least one thin film transistor and at least one capacitor. The pixel P may be a liquid crystal cell that displays an image by controlling the light transmittance of the liquid crystal according to the data voltage, or may be a light emitting cell that displays an image by emitting light in proportion to a current according to the data voltage. In addition to the liquid crystal cell or the light emitting cell, the pixel P may be formed in various shapes according to the type of the panel 100.

The second substrate covers the whole of the first substrate excluding the part of the non-display region (120). When the pixel P is a liquid crystal cell, a color filter layer may be formed on the second substrate. If the pixel P is a light emitting cell, the second substrate may serve as an encapsulating substrate for sealing the first substrate 110. The second substrate may also be formed in various shapes depending on the type of the panel 100.

The thin film transistor (TFT) formed in each of the pixels P is turned on by a pull-up signal supplied from the gate line, and a data voltage supplied from the data line is formed in the pixel P And supplies the organic light emitting diode OLED formed on the pixel P to the pixel electrode.

That is, the panel 100 displays an image by the pull-up signal supplied through the gate line GL and the data voltage supplied through the data line DL, and may be formed in various forms . The flat panel display device according to the present invention may be a liquid crystal display device, an organic light emitting display device, or an electrophoretic display device (EPD) according to the type of the panel 100. Hereinafter, for convenience of explanation, the present invention will be described by taking the case where the flat panel display device is a liquid crystal display device and the panel 100 is a liquid crystal panel.

Next, the data driver 300 converts the digital image data transmitted from the timing controller 400 into a data voltage, and supplies the data voltage of one horizontal line for every one horizontal period supplied with a pull-up signal to the gate line To the data lines.

The data driver 300 may be a source driver IC connected to the panel 100 in a chip-on-film (COF) mode or a TCP (tape carrier package) mode, as shown in FIG. In this case, at least one data driver 300 may be connected to the panel 100. In addition, at least one data driver 300 formed of the source drive IC may be disposed directly in the non-display area 120 of the panel 100. [

The data driver 300 converts the image data into the data voltage using gamma voltages supplied from a gamma voltage generator (not shown), and outputs the data voltage to the data line. To this end, the data driver 300 includes a shift register unit, a latch unit, a digital-analog converter (DAC), and an output buffer.

The shift register unit outputs a sampling signal using data control signals (SSC, SSP, etc.) received from the timing controller (400).

The latch unit latches the digital image data (Data) sequentially received from the timing controller (400), and simultaneously outputs the digital image data (Data) to the digital-analog converter (DAC).

The digital-to-analog converter converts the image data transmitted from the latch unit into a data voltage of positive or negative polarity and outputs the same. That is, the digital-analog converter uses the gamma voltage supplied from the gamma voltage generator (not shown) to generate the image data according to the polarity control signal POL transmitted from the timing controller 400 Polarity or negative polarity data voltage and outputs the data voltage to the data lines.

The output buffer outputs a positive or negative polarity data voltage transmitted from the digital-analog converter to the data line DL of the panel according to a source output enable signal SOE transmitted from the timing controller 400, .

Next, the timing controller 400 uses the timing signals input from the external system 600, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, The data driver 300 generates a gate control signal GCS for controlling the operation timing of the panel built-in gate driver 200 and a data control signal DCS for controlling the operation timing of the data driver 300, As shown in FIG.

The timing controller 400 includes a receiver for receiving input image data and timing signals from the external system 600, a control signal generator for generating various control signals, And outputting the control signals and the image data. The data sorting unit may include a data sorting unit for sorting the plurality of image data and outputting the rearranged image data, and an output unit for outputting the control signals and the image data.

That is, the timing controller 400 rearranges the input image data input from the external system 600 according to the structure and characteristics of the panel 100, and outputs the rearranged image data to the data driver (300). Such a function can be executed in the data arrangement section.

The timing controller 400 uses the timing signals transmitted from the external system 600, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, The gate driver 200 generates a data control signal DCS for controlling the driver and a gate control signal GCS for controlling the panel built-in gate driver 200 and outputs the control signals to the data driver and the panel- As shown in FIG. This function can be executed in the control signal generation unit.

The gate control signals GCS generated by the control signal generator include a gate output enable signal GOE, a gate start signal VST, and a clock signal CLK.

The data control signals generated by the control signal generator include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

Finally, the panel built-in gate driver 200 sequentially supplies a pull-up signal to each of the gate lines GL1 to GLg using the gate control signals GCS generated by the timing controller 400 .

Here, the pull-up signal refers to a voltage capable of turning on the switching thin film transistor connected to the gate lines. The voltage that can turn off the switching thin film transistor is called a pull-down signal, and the pull-up signal and the pull-down signal are collectively referred to as a scan signal.

When the thin film transistor is of the N type, the pull-up signal is a high level voltage and the pull-down signal is a low level voltage. When the thin film transistor is of the P type, the pull-up signal is a low level voltage and the pull-down signal is a high level voltage.

The panel built-in gate driver 200 receives the gate control signal generated by the timing controller, and sequentially outputs the pull-up signal to the gate lines using the gate control signal.

The specific internal configuration of the panel built-in gate driver 200 will be described below with reference to FIGS. 2 to 4. FIG.

2 is a diagram illustrating the structure of a shift register of a panel-integrated gate driver applied to a flat panel display device according to the present invention.

2, the panel built-in gate driver 200 applied to the flat panel display according to the present invention includes a plurality of stage 230 connected to each gate line, (Not shown).

The stages are embedded in a non-display area of the panel. That is, the stages are formed in the non-display region through the manufacturing process of the elements formed in the display region.

The number of the stages 230 may be variously set according to the structure and size of the panel, the number of the gate lines, and the like. 2, a shift register 210 applied to the panel 100 having 1080 gate lines is shown as an example of the present invention. In this case, each of the 1080 stages 230 constituting the shift register 210 is connected to 1082 gate lines on a one-to-one basis.

The basic operation of the shift register 210 according to the present invention will now be described.

When the gate start signal VST is input from the timing controller 400 to the first stage Stage 1 of the stages 230, the first stage Stage 1 starts driving. The first stage Vstage1 generates a first pull-up signal VGOUT1 using the clock signal CLK and the gate start signal VST transmitted from the timing controller 400 and outputs the first pull- GL1, and transmits the first pull-up signal to the second stage Stgae. The second stage Stage 2 starts driving by the first pull-up signal VGOUT1 and then generates a second pull-up signal VGOUT2 using the clock signal CLK and the gate start signal VST, And outputs it to the second gate line GL2.

The above operation is repeated in the same manner from the third stage (Stage 3) to the 1080th stage (Stage 1080).

That is, the stages sequentially output the scan signal (VGOUT) to each gate line by using the clock signal (CLK) and the gate start signal (VST).

A specific method of driving the stages may be variously formed according to the number of the clock signals input to the stages and the type of the clock signal. That is, in the above description, only one clock signal is input to each of the stages, but the present invention is not limited thereto. Thus, two or more clock signals may be input to the stages to drive the stages.

FIG. 3 is a circuit diagram of a stage applied to a shift register according to the present invention, FIG. 4 is a sectional view of an embodiment of a pull-up transistor applied to the stage shown in FIG. 3, FIG. 6 is an exemplary diagram for explaining the effect of the shift register according to the present invention. Referring to FIG.

Each stage 230 constituting the shift register according to the present invention includes a pull-up transistor Tu for outputting a pull-up signal, a pull-down transistor Td for outputting a pull-down signal, (NCC).

Hereinafter, a shift register including the stage shown in Fig. 3 will be described as an example of the present invention. That is, the shift register according to the present invention is not limited to the configuration shown in FIG.

In addition, although the pull-up transistor Tu, the pull-down transistor Td, and the other transistors constituting the stage 230 shown in FIG. 3 are of N type, the present invention is not limited thereto.

In addition, although the stage 230 shown in FIG. 3 uses two pull-down transistors Td1 and Td2, the present invention is not limited thereto. That is, each stage applied to the shift register according to the present invention may use only one pull-down transistor.

First, the pull-up transistor Tu includes a first electrode connected to a clock signal supply line, a second electrode connected to the output node, and two gate electrodes commonly connected to the first node in a state of being separated from each other . Of the two gate electrodes, the first gate electrode 111 is connected to the first node (Q). A second gate electrode (117) of the two gate electrodes is connected to the first node (Q), is separated from the first gate electrode, and the first electrode and the second And is disposed on the electrode.

The pull-up transistor Tu is turned on in accordance with the voltage of the first node (Q) to supply the clock signal (CLK) of the pull-up signal level to the output node (No).

In particular, when a turn-on voltage capable of turning on the pull-up transistor Tu is supplied to the first node Q, the turn-on voltage is applied to the first gate electrode 111 and the second gate electrode 117 The power of the pull-up signal output to the output node No through the pull-up transistor Tu can be increased.

That is, the pull-up transistor Tu is formed in a double gate structure including a bottom gate electrode (first gate electrode) 111 and a top gate electrode (second gate electrode) 117. The first gate electrode 111 and the second gate electrode 117 are both connected to the first node Q. Therefore, when the first node Q is charged and a high voltage is supplied to the first gate electrode 111 so that the pull-up transistor Tu is turned on, A high voltage is applied to the second gate electrode 117 at the same time.

Therefore, a wider path that allows electrons (or holes) to move can be formed in the active layer (Active) constituting the pull-up transistor Tu and output through the pull-up transistor Tu The power of the pull-up signal can be increased.

When the first node Q is discharged and a low voltage is supplied to the first gate electrode 111, a low voltage is also applied to the second gate electrode 117, Lt; / RTI > As a result, the output of the pull-up signal is interrupted.

The configuration of the pull-up transistor Tu will be described with reference to FIG.

The pull-up transistor Tu includes the first gate electrode 111 formed on the first substrate 110 of the panel 100, the gate insulating layer 112 covering the first gate electrode 111, A semiconductor layer (active layer, ACT) 113 formed on the gate insulating layer 112 to overlap the first gate electrode 111, a channel of the semiconductor layer 113 overlapping the first gate electrode 111 The first electrode 114 and the second electrode 115 formed in parallel with the first electrode 114 and the second electrode 115 and the protective layer 130 covering the semiconductor layer 113 and the first electrode 114 and the second electrode 115, And a second gate electrode 117 formed on the passivation layer 116 to overlap the first gate electrode 111 and the second gate electrode 111. Although not shown in the drawings, the first electrode 114 and the second electrode 115 may be formed on the semiconductor layer 113 with the ohmic contact layer interposed therebetween.

First, the first gate electrode 111 is connected to the first node Q.

Second, the insulating layer 112 insulates the first gate electrode 111 from the first electrode 114, the second electrode 115, and the semiconductor layer 113.

The semiconductor layer 113 may be formed of an oxide such as Zinc Oxide, Tin Oxide, Ga-In-Zn Oxide, In-Zn Oxide, or In-Sn Oxide, Mo, Zr, V, Hf or an oxide of an ion of a Ti material. The semiconductor layer 113 includes a channel region, a source region, and a drain region, and the channel region overlaps the first gate electrode 110. The semiconductor layer 113 forms a path through which electrons or holes are moved.

Fourth, the first electrode 114 and the second electrode 115 function as a source terminal and a drain terminal of the pull-up transistor Tu.

Fifth, the passivation layer 116 protects the first electrode 114, the second electrode 115 and the semiconductor layer 113 while the passivation layer 116 protects the first electrode 114, The second electrode 115, and the semiconductor layer 113 from the second gate electrode 117. In addition,

Sixth, the second gate electrode 117 may be formed on the passivation layer 116 so as to partially or entirely overlap the first gate electrode 111. The second gate electrode 117 is connected to the first node Q in the same manner as the first gate electrode 111.

3, the second gate electrode 117 of the pull-up transistor Tu and the first electrode 114 and the second electrode 115 are formed on different layers. However, The invention is not limited thereto. That is, the second gate electrode 117, the first electrode 114, and the second electrode 115 of the pull-up transistor Tu are formed so as to overlap each other on the semiconductor layer 113 Lt; / RTI > layer. In this case, each of the first electrode 114 and the second electrode 115 of the pull-up transistor Tu may be connected to the semiconductor layer 113 through a contact hole (not shown).

As described above, in the pull-up transistor Tu, since the turn-on voltage is simultaneously supplied to the first gate electrode 111 and the second gate electrode 117, the pull- The power of the pull-up signal output to the node No can be increased.

5, the voltage of the first node Q supplied to the first gate electrode 111 is also supplied to the second gate electrode 117, so that the same timing The same voltage is applied to the first gate electrode 111 and the second gate electrode 117. Accordingly, the path of the semiconductor layer 113 expands, and a large amount of current flows along the semiconductor layer 113. As a result, the power of the pull-up signal Vout output from the pull-up transistor Tu becomes .

The characteristics of the present invention as described above can be confirmed through FIG. 6, at the same gate source voltage Vgs, the voltage supplied to the second gate electrode 117 is increased, and the voltage supplied to the second gate electrode 117 is increased (The direction of the arrow) becomes equal to the voltage applied to the gate electrode 117, the current Id flowing through the pull-up transistor Tu is increased. Therefore, when the voltage of the first node Q is simultaneously supplied to the first gate electrode 111 and the second gate electrode 117, the voltage of the pull-up signal Vout output from the pull- The output is increased.

Next, the pull-down transistor Td includes a gate electrode connected to the second node QB, a first electrode connected to the output node No, and a second electrode connected to a low potential voltage (Vss) supply line do.

The pull-down transistor Td is turned on in response to the voltage on the second node QB connected to the gate electrode to supply the pull-down signal level low potential Vss to the output node No.

FIG. 3 shows a stage in which two pulldown transistors Td are formed. In this case, the two pull-down transistors Td1 and Td2 may be alternately operated every frame or every two frames. That is, the two pull-down transistors are alternately operated every predetermined period.

However, as described above, the present invention is not limited to a stage having two pull-down transistors.

Finally, the node control circuit (NCC) uses the gate start signal (VST), the high potential voltage (Vdd) and the low potential voltage (Vss) to control the first node (Q) ), Respectively.

The node control circuit NCC is driven by the gate start signal VST to supply the high potential voltage Vdd to the first gate electrode 111 and the second gate electrode of the pull- 117). That is, the first node Q is supplied with a turn-on voltage (high-potential voltage Vdd) capable of turning on the pull-up transistor. When the pull-up transistor Tu is turned on by the high potential voltage Vdd, the clock signal CLK is output to the output node No via the pull-up transistor Tu. The clock signal CLK output through the output node No is supplied as the pull-up signal to the gate line connected to the output node No.

The node control circuit NCC supplies a turn-off voltage that can turn off the pull-down transistor to the second node QB while the high-potential voltage Vdd is supplied to the pull-up transistor Tu, that is, , The low potential voltage Vss is supplied to turn off the pull-down transistor Td to prevent the low potential voltage Vss from being output to the output node No at which the pull-up signal is output.

3 is an n-th stage in which the (n-2) -th pull-up signal Vout ((n-2) n-2) is used.

That is, when the first transistor T1 is turned on by the (n-2) th pullup signal Vout (n-2), the high potential voltage Vdd is supplied to the first transistor T1 through the first transistor T1 And is supplied to the node Q.

The high potential voltage Vdd supplied to the first node Q is supplied to the first gate electrode 111 and the second gate electrode 117 of the pull-up transistor Tu. When the pull-up transistor Tu is turned on by the high-potential voltage Vdd, the pull-up signal is output through the pull-up transistor Tu, and the pull-up signal is supplied to the gate line through the output node No do.

In this case, a turn-off voltage for turning off the two pull-down transistors Td1 and Td2 is input to the gate electrodes of the two pull-down transistors Td1 and Td2. Therefore, no signal is output from the two pull-down transistors.

When the output of the (n-2) th pull-up signal is stopped and the (n + 2) th pull-up signal is output, the first transistor T1 is turned off and the second transistor T2 is turned on.

Therefore, the low potential voltage (Vss) is supplied to the first node (Q) instead of the high potential voltage (Vdd). The low potential voltage is an x turn-off transition that turns off the pull-up transistor. As a result, the pull-up transistor Tu is turned off and the pull-up signal is not output from the pull-up transistor.

As an example, in the stage shown in Fig. 3, the first pull-down transistor Td1 is driven in an odd frame and the second pull-down transistor Td2 is driven in an even frame.

In this case, after the odd-numbered frame starts, when the output of the pull-up signal from the n-th stage shown in FIG. 3 is interrupted, by the combination of the odd driving voltage Vdd_o and the even driving voltage Vdd_e, The first pull-down transistor Td1 is turned on. That is, by the combination of the odd-numbered driving voltage and the even-numbered driving voltage, a turn-on voltage capable of turning on the first pull-down transistor is supplied to the gate electrode of the first pull-down transistor.

When the first pull-down transistor Td1 is turned on, the low potential voltage Vss is output to the gate line through the output node No through the first pull-down transistor Td1.

When the output of the pull-up signal is stopped from the n-th stage shown in FIG. 3 after the start of the even-numbered frame, by the combination of the odd-numbered driving voltage Vdd_o and the even-numbered driving voltage Vdd_e, The first pull-down transistor Td2 is turned on.

When the second pull-down transistor Td2 is turned on, the low potential voltage Vss is output to the gate line through the output node No through the second pull-down transistor Td2.

For the above operation, the third to tenth transistors T10 to T10 connected to the first pull-down transistor Td1 and the second pull-down transistor Td2 may be configured in various forms have.

That is, the node control circuit (NCC) is not limited to the configuration shown in FIG. 3, but may be configured in various forms and may be driven by various methods.

The present invention as described above can be summarized as follows.

First, a second gate electrode is formed in the pull-up transistor Tu together with the first gate electrode, so that the pull-up transistor Tu is formed in a double gate structure. The two gate electrodes are connected to a first node (Q) of the node control circuit (NCC).

When the first node Q is charged and a turn-on voltage is simultaneously applied to the first gate electrode and the second gate electrode of the pull-up transistor Tu, the semiconductor layer 113 of the pull- Path is formed, and the power of the pull-up signal output from the pull-up transistor is increased.

Second, the double gate structure may be applied to all the transistors formed in the pull-down transistor Td and the node control circuit NCC in addition to the pull-up transistor Tu. That is, the double gate structure can be applied to all transistors that generate an output.

Third, the present invention can be applied to shift registers of various types (DAC, DC, SLC, etc.) regardless of the type of the node control circuit (NCC).

Fourth, according to the present invention, the size of the pull-up transistor can be reduced, and even if the size of the pull-up transistor is reduced, the power of the pull-up signal output through the pull-up transistor can be increased.

Fifthly, according to the present invention, since the size of the pull-up transistor is reduced, the size of the non-display area where the shift register is formed can be reduced, thereby realizing a narrow bezel.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: panel 200: gate driver
300: Data driver 400: Timing controller
600: external system Tu: pull-up transistor
Td: pull-down transistor NCC: node control circuit

Claims

Comprising a plurality of stages,
Wherein each of the plurality of stages comprises:
A pull-up transistor including a first electrode connected to a clock signal supply line, a second electrode connected to the output node, and two gate electrodes separated from each other and commonly connected to the first node;
A pull-down transistor including a gate electrode connected to a second node, a first electrode connected to the output node, and a second electrode connected to a voltage supply line; And
And a node control circuit for controlling a voltage supplied to the first node and the second node in accordance with the gate start signal.

The method according to claim 1,
A first gate electrode of the two gate electrodes is connected to a first node,
And a second gate electrode of the two gate electrodes is connected to the first node and is separated from the first gate electrode and disposed on the first electrode and the second electrode with an insulating layer therebetween A shift register.

The method according to claim 1,
The pull-
A first gate electrode formed on a substrate;
A gate insulating layer covering the first gate electrode;
A semiconductor layer formed on the gate insulating layer to overlap the first gate electrode;
The first electrode and the second electrode formed in parallel to each other with a channel region of the semiconductor layer overlapping the first gate electrode;
A protective layer covering the semiconductor layer, the first electrode, and the second electrode; And
And a second gate electrode formed on the protection layer to overlap the first gate electrode.

The method according to claim 1,
Wherein the pull-up transistor is turned on by a voltage supplied from the first node and outputs a clock signal supplied through the clock signal supply line to the gate line via the output node,
Wherein the pull-down transistor is turned on by a voltage supplied from the second node, and outputs a voltage supplied through the voltage supply line to the gate line via the output node.

5. The method of claim 4,
Wherein the clock signal is a pull-up signal for turning on the switching transistor formed in the gate line,
Wherein the voltage supplied through the voltage supply line and output to the gate line through the output node is a pull-down signal for turning off the switching transistor.

5. The method of claim 4,
The node control circuit comprising:
Supplying a turn-off voltage capable of turning off the pull-down transistor to the second node while a turn-on voltage capable of turning on the pull-up transistor to the first node is supplied,
And a turn-on voltage capable of turning on the pull-down transistor to the second node while the turn-off voltage capable of turning off the pull-up transistor is supplied to the first node.

The method according to claim 1,
The pull-
A first pull-down transistor and a second pull-down transistor,
The node control circuit comprising:
And the first pull-down transistor and the second pull-down transistor are alternated every predetermined period.

The method according to claim 1,
Wherein the stages are built in a non-display area of the panel.

A panel in which pixels are formed for each intersection of the data lines and the gate lines;
A data driver for supplying a data voltage to the data lines;
A timing controller for driving the data driver; And
A pull-up transistor which is built in a non-display area of the panel and is driven by a clock signal input from the timing controller to sequentially supply a pull-up signal to the gate lines and output the pull- A flat panel display comprising a panel built-in gate driver formed in a double gate structure.

10. The method of claim 9,
The panel built-in gate driver includes a plurality of stages,
Wherein each of the plurality of stages comprises:
A pull-up transistor including a first electrode connected to a clock signal supply line, a second electrode connected to the output node, and two gate electrodes separated from each other and commonly connected to the first node;
A pull-down transistor including a gate electrode connected to a second node, a first electrode connected to the output node, and a second electrode connected to a voltage supply line; And
And a node control circuit for controlling a voltage supplied to the first node and the second node in accordance with the gate start signal.