KR20140019920A - Shift register and display device using the same - Google Patents

Abstract

The present invention relates to a shift register for methodically outputting the signal having the same waveform as a start voltage, and a device using the same. The shift register according to an embodiment of the present invention comprises a plurality of stages outputting methodically. The stages a start terminal in which a start signal or a shear carry signal are inputted; a clock signal; a first clock and a second clock terminal in which a generating clock signal that generates the clock signal is inputted; and an output terminal for outputting the start signal inputted to the start terminal or a signal of same waveform as the shear carry signal.

Description

[0001] SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME [0002]

The present invention relates to a shift register for sequentially outputting a signal having the same waveform as the start voltage and a display device using the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, a variety of flat panel displays (FPDs) have been developed and marketed to reduce weight and volume, which are disadvantages of cathode ray tubes. For example, various flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) . The flat panel display displays an image using a gate driving circuit which sequentially supplies a gate signal to gate lines of the display panel using a shift register and a data driving circuit which supplies a data voltage to the data lines.

Recently, in the organic light emitting diode display, each of the pixels of the display panel includes a plurality of switching thin film transistors (TFTs) for reasons of image quality improvement. In this case, the gate driving circuit needs shift registers as many as the switching control signal for controlling the plurality of switching TFTs. Since the shift register generates an output depending on a clock, the number of clocks input to the shift register and the phase of the clock vary depending on the waveform type of the switching control signal. Therefore, when the waveform types of the plurality of switching control signals are all different, both the number of clocks input to the shift registers and the phase of the clock may be different. As a result, as the number of clock lines increases, the circuit design area of the shift register increases. In particular, in the case of the gate drive IC in panel (GIP) method in which the shift register is directly formed in the bezel area of the display panel, the bezel area of the organic light emitting diode display device becomes large due to the increase in the circuit design area of the shift register. There is.

The present invention provides a shift register that can reduce a bezel area of a display device and a display device using the same.

The shift register according to an embodiment of the present invention includes a plurality of stages that sequentially generate an output, and each of the stages includes a start terminal to which a start signal or a front carry signal is input, a clock signal, and an inverted clock signal. A first clock terminal and a second clock terminal to which the inverted clock signal is input, and an output terminal for outputting a signal having the same waveform as the start signal or the front carry signal input to the start terminal.

According to an exemplary embodiment of the present invention, a display device includes a display panel including data lines and at least one switching signal line group; A data driving circuit for converting input digital video data into analog data voltages and supplying the analog data voltages to the data lines; And a gate driving circuit including one or more shift registers for sequentially outputting a switching control signal to the at least one switching signal line group, wherein the shift register includes a plurality of stages that sequentially generate an output; Each of the start signals includes a start terminal to which a start signal or a front carry signal is input, a first clock terminal and a second clock terminal to which a clock signal and an inverted clock signal inverting the clock signal are input, and the start signal input to the start terminal. Or an output terminal for outputting a signal having the same waveform as the front end carry signal.

The shift register of the present invention sequentially outputs a signal having the same waveform as the start signal using two clock signals. As a result, when the present invention changes only the waveform of the start signal input to each of the plurality of shift registers, the plurality of shift registers may output a plurality of switching control signals having different waveforms. For this reason, the present invention can greatly reduce the circuit design area, and thus reduce the bezel area of the display device.

1 is a block diagram illustrating a shift register according to an exemplary embodiment of the present invention.
2 is a circuit diagram illustrating an example of a circuit configuration of a k-th stage according to the first embodiment of the present invention.
3 is a waveform diagram illustrating an example of input signals and output signals of a first stage;
4A-4J illustrate an example of circuit operation of a first stage during a first to tenth time period.
5 is a waveform diagram illustrating an example of input signals and an output signal of a second stage;
6A-6K illustrate an exemplary circuit operation of a second stage during the first to eleventh periods.
7 is a waveform diagram illustrating an example of input signals and an output signal of a third stage;
8 is a circuit diagram illustrating an example of a circuit configuration of a k-th stage according to the second embodiment of the present invention.
9 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

1 is a block diagram illustrating a shift register according to an exemplary embodiment of the present invention. Referring to FIG. 1, a shift register according to an embodiment of the present invention includes a plurality of stages (ST (1) to ST (n) where n is a number of stages) connected in a cascade manner. In FIG. 1, for convenience of description, only the first to third stages ST (1) to ST (3) are illustrated.

In the following description, the "shear stage" refers to being located on top of the stage to be a reference. For example, with respect to the stage k (1? K? N, where k is a natural number equal to or greater than 2) stage ST (k), the front stage is a stage from the first stage ST (1) -1)). The "back stage" refers to being located at the lower part of the stage used as a reference. For example, on the basis of the k-th stage ST (k), the trailing stage indicates any one of the (k + 1) th stages ST (k + 1) to k (n).

The shift register includes a start signal line STL supplied with the start signal VST, a clock line CL supplied with the clock signal CLK, an inverted clock line CBL supplied with the inverted clock signal CLKB, and a high potential. A high potential voltage line VDDL to which a voltage is applied, and a low potential voltage line VSSL to which a low potential voltage is applied.

Each of the stages ST (1) to ST (n) has a start terminal START, a first clock terminal CLK1, a second clock terminal CLK2, an output terminal OUT, and a high potential voltage input terminal VDDT. ), Low potential voltage input terminal (VSST), Q node voltage output terminal (Q_OUT), QB node voltage output terminal (QB_OUT), rear Q node voltage input terminal (Q_NEXT), and rear QB node voltage input terminal (QB_NEXT) It is provided. The start terminal START of each of the stages ST (1) to ST (n) is connected to the start signal line STL or the output terminal OUT of the preceding stage. The start signal VST or the front carry signal is input to the start terminal START of each of the stages ST (1) to ST (n). Although the start signal VST is input to the start terminal START of the first stage ST (1), the start terminal START of each of the second to nth stages ST (2) to ST (n). The front carry signal is input to the. The front carry signal means a signal input to the start terminal START of the k-th stage ST (k) as an output signal of the output terminal OUT of the front stage. For example, the first output signal GOUT (1) of the output terminal OUT of the first stage ST (1) is a front carry signal at the start terminal START of the second stage ST (2). Is input as.

The first clock terminal CLK1 of each of the stages ST (1) to ST (n) is connected to the clock line CL or the inverted clock line CBL. When the first clock terminal CLK1 of the kth stage ST (k) is connected to the clock line CL, the clock signal CLK is input to the first clock terminal CLK1. When the first clock terminal CLK1 of the kth stage ST (k) is connected to the inverted clock line CBL, the inverted clock signal CLBK is input to the first clock terminal CLK1. The inverted clock signal CLKB is a signal obtained by inverting the clock signal CLK. The second clock terminal CLK2 of each of the stages ST (1) to ST (n) is also connected to the clock line CL or the inverted clock line CBL. When the second clock terminal CLK2 of the kth stage ST (k) is connected to the clock line CL, the clock signal CLK is input to the second clock terminal CLK2. When the second clock terminal CLK2 of the kth stage ST (k) is connected to the inverted clock line CBL, the inverted clock signal CLKB is input to the second clock terminal CLK2. However, a signal input to the first clock terminal CLK1 of the k-th stage ST (k) and a signal input to the second clock terminal CLK2 are different from each other. For example, when the first clock terminal CLK1 of the k-th stage ST (k) is connected to the clock line CL so that the clock signal CLK is input to the first clock terminal CLK1, the second clock terminal CLK1 is connected to the second clock terminal CLK1. The clock terminal CLK2 is connected to the inverted clock line CBL so that the inverted clock signal CLKB is input to the second clock terminal CLK2. The second clock terminal when the first clock terminal CLK1 of the k-th stage ST (k) is connected to the inverted clock line CBL so that the inverted clock signal CLKB is input to the first clock terminal CLK1. CLK2 is connected to the clock line CL, and the clock signal CLK is input to the second clock terminal CLK2. In addition, the first clock terminal CLK1 and the second clock terminal CLK2 of each of the stages ST (1) to ST (n) are alternately connected to the clock line CL and the inverted clock line CBL. do. For example, when the clock signal CLK is input to the first clock terminal CLK1 of the k-th stage ST (k) and the inverted clock signal CLKB is input to the second clock terminal CLK2, The inverted clock signal CLKB is input to the first clock terminal CLK1 of the k + 1 stage ST (k + 1), and the clock signal CLK is input to the second clock terminal CLK2. When the inverted clock signal CLKB is input to the first clock terminal CLK1 of the k-th stage ST (k) and the clock signal CLK is input to the second clock terminal CLK2, the k + 1th stage The clock signal CLK is input to the first clock terminal CLK1 of (ST (k + 1)), and the inverted clock signal CLKB is input to the second clock terminal CLK2.

Since the high potential voltage input terminal VDDT is connected to the high potential voltage supply line VDDL, a high potential voltage is supplied to the high potential voltage input terminal VDDT. Since the low potential voltage input terminal VSST is connected to the low potential voltage supply line VSSL, a low potential voltage is supplied to the low potential voltage input terminal VSST. The high potential voltage may be set to the gate high voltage VGH, and the low potential voltage may be set to the gate low voltage VGL. The gate high voltage VGH may be set to a voltage capable of turning on thin film transistors (TFTs) present in an internal circuit of each of the stages ST (1) to ST (n).

The Q node voltage output terminal Q_OUT of the kth stage ST (k) is connected to the rear Q node voltage input terminal Q_NEXT of the preceding stage. The Q node voltage output terminal Q_OUT of the k-th stage ST (k) outputs the voltage of the Q node of the k-th stage ST (k) to the rear-end Q node voltage input terminal Q_NEXT of the previous stage. The QB node voltage output terminal QB_OUT of the k-th stage ST (k) is connected to the rear-end QB node voltage input terminal QB_NEXT of the preceding stage. The QB node voltage output terminal QB_OUT of the k-th stage ST (k) outputs the voltage of the QB node of the k-th stage ST (k) to the rear QB node voltage input terminal QB_NEXT of the preceding stage. For example, the Q node voltage output terminal Q_OUT of the second stage ST (2) is connected to the Q node voltage input terminal Q_NEXT of the rear stage of the first stage ST (1). The QB node voltage output terminal QB_OUT of the second stage ST (2) is connected to the rear-end QB node voltage input terminal QB_NEXT of the first stage ST (1).

The rear end Q node voltage input terminal Q_NEXT of the kth stage ST (k) is connected to the Q node voltage output terminal Q_OUT of the rear stage. The rear Q node voltage input terminal Q_NEXT of the k-th stage ST (k) receives the Q node voltage of the rear stage. The rear QB node voltage input terminal QB_NEXT of the k-th stage ST (k) is connected to the QB node voltage output terminal QB_OUT of the rear stage. The rear QB node voltage input terminal QB_NEXT of the k-th stage ST (k) receives the QB node voltage of the rear stage. For example, the rear-end Q node voltage input terminal Q_NEXT of the second stage ST (2) is connected to the Q node voltage output terminal Q_OUT of the third stage ST (3). The rear-end QB node voltage input terminal QB_NEXT of the second stage ST (2) is connected to the QB node voltage output terminal QB_OUT of the third stage ST (3).

The output terminal OUT of the k-th stage ST (k) is connected to the k-th output line. The output terminal OUT of the k-th stage ST (k) outputs the k-th output signal GOUT (k) to the k-th output line. The output terminal OUT of the k-th stage ST (k) is connected to the start terminal START of the rear stage. The kth output signal GOUT (k) of the output terminal OUT of the kth stage ST (k) is input as a front carry signal to the start terminal START of the rear stage. For example, the output terminal OUT of the second stage ST (2) outputs the second output signal GOUT (2) to the second output line and at the same time, the third stage ST (3). It is output as a front carry signal to the start terminal START.

2 is a circuit diagram illustrating an example of a circuit configuration of a k-th stage according to the first embodiment of the present invention. Referring to FIG. 2, the Q node charging / discharging unit 10 and the QB node QB controlling the charge / discharge of the Q node Q of the k-th stage ST (k) according to the first embodiment of the present invention. QB node discharge section 20 for controlling discharge, QB node charging section 30 for controlling charging of QB node QB, and Q node boost control section 40 for controlling voltage boost of Q node Q. And an output unit 50 for charging the output node NO connected to the output terminal OUT to a high potential voltage or to a low potential voltage according to the voltages of the Q node Q and the QB node QB. do.

The Q node charging / discharging unit 10 receives a start signal VST or a front end input through the start terminal START in response to a clock signal CLK or an inverted clock signal CLKB input through the first clock terminal CLK1. Charge and discharge with a carry signal. To this end, the Q node charging and discharging unit 10 may include a first TFT connecting the Q node Q to the start terminal START in response to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB. T1). In response to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB, the first TFT T1 may turn the Q node Q into a first logic level voltage of the start signal VST or the front carry signal. Or the Q node Q is discharged to the second logic level voltage of the start signal VST or the front carry signal. The gate electrode of the first TFT T1 is connected to the first clock terminal CLK1, the source electrode is connected to the Q node Q, and the drain electrode is connected to the start terminal START.

Meanwhile, the first logic level voltage and the high potential voltage may be set to the same level voltage, and the second logic level voltage and the low potential voltage may be set to the same level voltage. For example, the first logic level voltage and the high potential voltage may be set to the gate high voltage VGH, and the second logic level voltage and the low potential voltage may be set to the gate low voltage VGL.

The QB node discharge unit 20 may include a clock signal CLK or an inverted clock signal CLKB input through the first clock terminal CLK1 and a start signal VST or a front carry signal input through the start terminal START. In response, the QB node QB is discharged to a low potential voltage. To this end, the QB node discharge unit 20 connects the first node N1 to the start terminal START in response to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB. (T2). In addition, the QB node discharge unit 20 further includes a third TFT T3 for connecting the QB node QB to the low potential voltage input terminal VSST in response to the first logic level voltage of the first node N1. Include. In response to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB, the second TFT T2 moves the first node N1 to the first logic level of the start signal VST or the front carry signal. The battery is charged with a voltage, or the first node N1 is discharged to the second logic level voltage of the start signal VST or the front carry signal. The third TFT T3 discharges the QB node QB to a low potential voltage in response to the first logic level voltage of the first node N1. The gate electrode of the second TFT T2 is connected to the first clock terminal CLK1, the source electrode is connected to the first node N1, and the drain electrode is connected to the start terminal START. The gate electrode of the third TFT T3 is connected to the first node N1, the source electrode is connected to the low potential voltage input terminal VSST, and the drain electrode is connected to the QB node QB.

In addition, the QB node discharge unit 20 discharges the QB node QB to a low potential voltage in response to the first logic level voltage of the Q node Q. To this end, the QB node discharge unit 20 further includes a fourth TFT T4 connecting the QB node QB to the low potential voltage input terminal VSST in response to the first logic level voltage of the Q node Q. Include. The fourth TFT T4 discharges the QB node QB to a low potential voltage in response to the first logic level voltage of the Q node Q. The gate electrode of the fourth TFT T4 is connected to the Q node Q, the source electrode is connected to the low potential voltage input terminal VSST, and the drain electrode is connected to the QB node QB.

The QB node charging unit 30 charges the QB node QB to the high potential voltage VDD in response to the high potential voltage VDD input through the high potential voltage input terminal VDDT. To this end, the QB node charging unit 30 connects the second node N2 to the high potential voltage input terminal VDDT in response to the high potential voltage VDD, and the second node N2. The sixth TFT T6 connects the QB node QB to the low potential voltage input terminal VSST in response to the high potential voltage VDD of N, and the first logic level voltage in response to the first logic level voltage of the Q node Q. And a seventh TFT T7 for connecting the two nodes N2 to the low potential voltage input terminal VSST. The fifth TFT T5 charges the second node N2 to the high potential voltage in response to the high potential voltage VDD. The sixth TFT T6 charges the QB node QB to the high potential voltage in response to the high potential voltage of the second node N2. The seventh TFT T7 discharges the second node N2 to a low potential voltage in response to the first logic level voltage of the Q node Q. The gate electrode and the drain electrode of the fifth TFT T5 are connected to the high potential voltage input terminal VDDT, and the source electrode is connected to the second node N2. The gate electrode of the sixth TFT T6 is connected to the second node N2, the source electrode is connected to the QB node QB, and the drain electrode is connected to the high potential voltage input terminal VDDT. The gate electrode of the seventh TFT T7 is connected to the Q node Q, the source electrode is connected to the low potential voltage input terminal VSST, and the drain electrode is connected to the second node N2.

The Q node boost controller 40 is a Q node of a rear stage stage input through the clock signal CLK or the inverted clock signal CLKB input through the second clock terminal CLK2 and the rear Q node voltage input terminal Q_NEXT. In response to the voltage of Q, the third node N3 is charged to the first logic level voltage, and the amount of voltage change of the third node N3 is reflected in the Q node Q. To this end, the Q node boost controller 40 may respond to the third node in response to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB and the first logic level voltage of the Q node Q of the subsequent stage. An eighth TFT (T8) and a ninth TFT (T9) for connecting (N3) to the second clock terminal (CLK2). The eighth TFT T8 receives the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB in response to the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB. It supplies to the drain electrode of (T9). The ninth TFT T9 transfers the first logic level voltage of the clock signal CLK or the inverted clock signal CLKB to the third node N3 in response to the first logic level voltage of the Q node Q of the later stage. Supply.

In addition, the Q node boost controller 40 discharges the third node N3 to a low potential voltage in response to the voltage of the QB node QB of the rear stage stage input through the rear end QB node voltage input terminal QB_NEXT. To this end, the Q node boost control unit 40 further includes a tenth TFT T10 for connecting the third node N3 to the low potential voltage input terminal VSST in response to the voltage of the QB node QB of the rear stage. Include. The tenth TFT T10 discharges the third node N3 to a low potential voltage in response to the voltage of the QB node QB of the later stage.

In addition, the Q node boost control unit 40 further includes a first capacitor Cp connected between the third node N3 and the Q node Q. One electrode of the first capacitor Cp is connected to the third node N3, and the other electrode is connected to the Q node Q. When a change occurs in the voltage of the third node N3, the first capacitor Cp reflects the amount of voltage change of the third node N3 in the Q node Q.

The output unit 50 charges the output node NO to the high potential voltage in response to the voltage of the Q node Q, and discharges the output node NO to the low potential voltage in response to the voltage of the QB node QB. do. The output unit 50 includes a pull-up TFT TU for connecting the output node NO to the high potential voltage input terminal VDDT in response to the first logic level voltage of the Q node Q, and a QB node QB. And a pull-down TFT TD for connecting the output node NO to the low potential voltage input terminal VSST in response to the first logic level voltage. The gate electrode of the pull-up TFT TU is connected to the Q node Q, the source electrode is connected to the high potential voltage input terminal VDDT, and the drain electrode is connected to the output node NO. The gate electrode of the pull-down TFT TD is connected to the QB node QB, the source electrode is connected to the output node NO, and the drain electrode is connected to the low potential voltage input terminal VSST. Since the output terminal OUT is connected to the output node NO, the output terminal NO outputs the voltage of the output node NO as an output signal.

Meanwhile, in FIG. 2, the first to tenth TFTs (T1 to T10), the pull-up TFT (TU), and the pull-down TFT (TD) are mainly formed of an N type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Explained.

3 is a waveform diagram illustrating an example of input signals and output signals of a first stage. 3 illustrates a start signal VST input to the start terminal START as input signals of the first stage ST (1), a clock signal CLK input to the first clock terminal CLK1, and a second clock. The inverted clock signal CLKB input to the terminal CLK2 is shown. In addition, in FIG. 3, the Q node voltage Q (2) of the second stage ST (2) input to the rear Q node voltage input terminal Q_NEXT and the second QB node voltage input terminal QB_NEXT are input. The QB node voltage QB (2) of the two stages ST (2) is shown. 3, the Q node voltages Q (1) and QB of the first stage ST (1) which are output to the Q node voltage output terminal Q_OUT as output signals of the first stage ST (1) are shown in FIG. The QB node voltage QB (1) of the first stage ST (1) output to the node voltage output terminal QB_OUT and the output terminal OUT of the first stage ST (1) are output. 1 output signal GOUT (1) is shown.

Each of the stages ST (1) to ST (n) has an output signal having the same waveform and phase as the start signal VST or the front carry signal input through the start terminal START through the output terminal OUT. Output The first stage ST (1) outputs the first output signal GOUT (1) having the same waveform as the start signal VST input through the start terminal START through the output terminal OUT. The start signal VST shown in FIG. 3 is generated at the first logic level voltage during the first period t1, the second period t2, and the fifth to eighth periods t5 to t8, and the first period T1 is generated during the remaining period. Generates 2 logic-level voltages. However, the start signal VST shown in FIG. 3 is only one embodiment, and the start signal VST may be predetermined through a preliminary experiment in consideration of the waveform of the first output signal GOUT (1). .

In addition, in FIG. 3, each of the first to tenth periods t1 to t10 is described as being one horizontal period 1H, but it should be noted that the present invention is not limited thereto. The one horizontal period 1H refers to a one line scanning period for supplying a data voltage to all pixels existing in one horizontal line of the display panel.

The clock signal CLK is generated at a predetermined period, and the inverted clock signal CLKB is a signal obtained by inverting the clock signal CLK. Therefore, the clock signal CLK is generated at the same period as the clock signal CLK. Therefore, when the clock signal CLK is generated with the first logic level voltage as shown in FIG. 3, the inverted clock signal CLKB is generated with the second logic level voltage. In addition, when the clock signal CLK is generated with the second logic level voltage, the inverted clock signal CLKB is generated with the first logic level voltage. In FIG. 3, the first logic level voltage is the gate high voltage VGH and the second logic level voltage is the gate low voltage VGL.

The Q node voltage Q (2) of the second stage ST (2) is generated by delaying the phase by a predetermined period than the Q node voltage Q (1) of the first stage ST (1). . The QB node voltage QB (2) of the second stage ST (2) is generated by delaying the phase by a predetermined period than the QB node voltage QB (1) of the first stage ST (1). . In FIG. 3, the predetermined period has been described based on the implementation of one horizontal period.

Q node voltage Q (1) of the first stage ST (1), QB node voltage QB (1) of the first stage ST (1), of the second stage ST (2) Q node voltage Q (2), QB node voltage QB (2) of second stage ST (2), and first output signal GOUT (1) of first stage ST (1). ) Will be described in conjunction with FIGS. 4A to 4I.

4A through 4I are exemplary diagrams illustrating a circuit operation of the first stage during the first to tenth periods. 4A to 4I each show the turn-on and turn-off states of the TFTs present in the first stage ST (1) in each of the first to tenth periods t1 to t10. In each of FIGS. 4A to 4I, the turned-on TFTs are circled. In the following description, the first logic level voltage and the high potential voltage are the gate high voltage VGH, and the second logic level voltage and the low potential voltage are the gate low voltage VGL.

First, an operation of the first stage ST (1) during the first period t1 will be described in detail with reference to FIGS. 3 and 4A. The start signal VST of the first logic level voltage VGH is input to the start terminal START during the first period t1, and the clock signal of the first logic level voltage VGH is input to the first clock terminal CLK1. CLK is input, and the inverted clock signal CLKB of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has the second logic level voltage VGL during the first period t1, the second logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGL is input and the QB node QB of the second stage ST (2) has the first logic level voltage VGH, the first logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGH) is input.

The Q node charging and discharging unit 10 charges the Q node Q to the first logic level voltage VGH during the first period t1. The first TFT T1 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the first period t1. Due to the turn-on of the first TFT T1, the Q node Q is charged to the first logic level voltage VGH of the start signal VST.

The QB node discharge unit 20 discharges the QB node QB to the low potential voltage VGL during the first period t1. The second TFT T2 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the first period t1. Due to the turn-on of the second TFT T2, the first node N1 is charged to the first logic level voltage VGH of the start signal VST. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the first period t1. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the first period t1. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB is discharged to the low potential voltage VGL.

The seventh TFT T7 of the QB node charger 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the first period t1. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the first period t1. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The eighth TFT T8 of the Q node boost control unit 40 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the first period t1, and the ninth TFT T9. Is turned off by the second logic level voltage VGL. The tenth TFT T10 is turned on in response to the first logic level voltage VGH. Due to the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output unit 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the first period t1. The pull-up TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is the low potential voltage VGL of the QB node QB. It is turned off by Due to the turn-on of the pull-up TFT TU, the output node NO is charged with the high potential voltage VGH, so that the output terminal OUT of the first stage ST (1) has a high potential voltage ( The first output signal GOUT (1) of VGH is output.

Secondly, an operation of the first stage ST (1) during the second period t2 will be described in detail with reference to FIGS. 3 and 4B. During the second period t2, the start signal VST of the first logic level voltage VGH is input to the start terminal START, and the clock signal of the second logic level voltage VGL to the first clock terminal CLK1. CLK is input, and the inverted clock signal CLKB of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has the first logic level voltage VGH during the second period t2, the first logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGH is input and the QB node QB of the second stage ST (2) has the second logic level voltage VGL, the second logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGL) is input.

The first TFT T1 of the Q node charging and discharging unit 10 is turned off by the clock signal CLK of the second logic level voltage VGL during the second period t2.

The QB node discharge unit 20 maintains the QB node QB at the low potential voltage VGL for the second period t2. The second TFT T2 is turned off by the clock signal CLK of the second logic level voltage VGL during the second period t2. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the second period t2. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the second period t2. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charger 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the second period t2. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the second period t2. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The Q node boost controller 40 boosts the voltage of the Q node Q during the second period t2. The eighth TFT T8 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged to the first logic level voltage of the inverted clock signal CLKB. That is, during the second period t2, the voltage of the third node N3 rises from the low potential voltage VGL to the first logic level voltage VGH, and the amount of change in voltage of the third node N3 is the first capacitor. Reflected to the Q node Q by (Cp). Therefore, during the second period t2, the Q node Q rises to a voltage VGH 'higher than the first logic level voltage VGH. Pull-up TFT (TU) has the advantage that can be turned on stably due to the voltage rise of the Q node (Q).

The output unit 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the second period t2. The pull-up TFT TU is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is the QB node QB. It is turned off by the second logic level voltage VGL. Due to the turn-on of the pull-up TFT TU, the output node NO maintains the high potential voltage VGH, so that the output terminal OUT of the first stage ST (1) has a high potential voltage The first output signal GOUT (1) of VGH is output.

Third, the operation of the first stage ST (1) during the third period t3 will be described in detail with reference to FIGS. 3 and 4C. During the third period t3, the start signal VST of the second logic level voltage VGL is input to the start terminal START, and the clock signal of the first logic level voltage VGH is input to the first clock terminal CLK1. CLK is input, and the inverted clock signal CLKB of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has a voltage VGH 'higher than the first logic level voltage VGH during the third period t3, the latter Q node voltage input terminal The voltage VGH 'higher than the first logic level voltage VGH is input to Q_NEXT, and the QB node QB of the second stage ST (2) has a second logic level voltage VGL, so The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The Q node charging and discharging unit 10 discharges the Q node Q to the second logic level voltage VGL during the third period t3. The first TFT T1 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the third period t3. Due to the turn-on of the first TFT T1, the Q node Q is discharged to the second logic level voltage VGL of the start signal VST.

The second TFT T2 of the QB node discharge part 20 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the third period t3. Due to the turn-on of the second TFT T2, the first node N1 is discharged to the second logic level voltage VGL of the start signal VST. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the third period t3. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the third period t3. Due to the turn-off of the third TFT T3 and the fourth TFT T4, the QB node QB is not discharged to the low potential voltage VGL.

The QB node charger 30 charges the QB node QB to the high potential voltage VGH during the third period t3. The seventh TFT T7 is turned off by the second logic level voltage VGL of the Q node Q during the third period t3. Due to the turn-off of the seventh TFT T7, the second node N2 is charged to the high potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high potential voltage VGH of the second node N2 during the third period t3. Due to the turn-on of the sixth TFT T6, the QB node QB is charged to the high potential voltage VGH.

The eighth TFT T8 of the Q node boost controller 40 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the third period t3. The ninth TFT T9 is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-off of the eighth TFT T8 and the tenth TFT T10, the third node N3 is floated.

The output unit 50 outputs the first output signal GOUT (1) of the low potential voltage VGL during the third period t3. The pull-up TFT TU is turned off by the second logic level voltage VGL of the Q node Q, and the pull-down TFT TD is the first logic level voltage VGH of the QB node QB. Is turned on in response to Due to the turn-on of the pull-down TFT TD, the output node NO is discharged to the low potential voltage VGL, so that the output terminal OUT of the first stage ST (1) has a low potential voltage ( The first output signal GOUT (1) of the VGL is output.

Fourth, an operation of the first stage ST (1) during the fourth period t4 will be described in detail with reference to FIGS. 3 and 4D. During the fourth period t4, the start signal VST of the second logic level voltage VGL is input to the start terminal START, and the clock signal of the second logic level voltage VGL to the first clock terminal CLK1. CLK is input, and the inverted clock signal CLKB of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has the second logic level voltage VGL during the fourth period t4, the second logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGL is input and the QB node QB of the second stage ST (2) has the first logic level voltage VGH, the first logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGH) is input.

The first TFT T1 of the Q node charging and discharging unit 10 is turned off by the clock signal CLK of the second logic level voltage VGL during the fourth period t4.

The second TFT T2 of the QB node discharge part 20 is turned off by the clock signal CLK of the second logic level voltage VGL during the fourth period t4. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the fourth period t4. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the fourth period t4. Due to the turn-off of the third TFT T3 and the fourth TFT T4, the QB node QB is not discharged to the low potential voltage VGL.

The QB node charger 30 charges the QB node QB to the high potential voltage VGH during the fourth period t4. The seventh TFT T7 is turned off by the second logic level voltage VGL of the Q node Q during the fourth period t4. Due to the turn-off of the seventh TFT T7, the second node N2 is charged to the high potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high potential voltage VGH of the second node N2 during the fourth period t4. Due to the turn-on of the sixth TFT T6, the QB node QB is charged to the high potential voltage VGH.

The eighth TFT T8 of the Q node boost controller 40 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the fourth period t4. The ninth TFT T9 is turned off in response to the second logic level voltage VGL. The tenth TFT T10 is turned on in response to the first logic level voltage VGH. Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output unit 50 outputs the first output signal GOUT (1) of the low potential voltage VGL during the fourth period t4. The pull-up TFT TU is turned off by the second logic level voltage VGL of the Q node Q, and the pull-down TFT TD is the first logic level voltage VGH of the QB node QB. Is turned on in response to Due to the turn-on of the pull-down TFT TD, the output node NO is discharged to the low potential voltage VGL, so that the output terminal OUT of the first stage ST (1) has a low potential voltage ( The first output signal GOUT (1) of the VGL is output.

Fifth, an operation of the first stage ST (1) during the fifth period t5 will be described in detail with reference to FIGS. 3 and 4E. During the fifth period t5, the start signal VST of the first logic level voltage VGH is input to the start terminal START, and the clock signal of the first logic level voltage VGH is input to the first clock terminal CLK1. CLK is input, and the inverted clock signal CLKB of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has the second logic level voltage VGL during the fifth period t5, the second logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGL is input and the QB node QB of the second stage ST (2) has the first logic level voltage VGH, the first logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGH) is input.

The Q node charging and discharging unit 10 charges the Q node Q to the first logic level voltage VGH during the fifth period t5. The first TFT T1 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the fifth period t5. Due to the turn-on of the first TFT T1, the Q node Q is charged to the first logic level voltage VGH of the start signal VST.

The QB node discharge unit 20 discharges the QB node QB to the low potential voltage VGL during the fifth period t5. The second TFT T2 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the fifth period t5. Due to the turn-on of the second TFT T2, the first node N1 is charged to the first logic level voltage VGH of the start signal VST. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the fifth period t5. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the fifth period t5. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB is discharged to the low potential voltage VGL.

The seventh TFT T7 of the QB node charging unit 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the fifth period t5. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the fifth period t5. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The eighth TFT T8 of the Q node boost controller 40 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the fifth period t5. The ninth TFT T9 is turned off by the second logic level voltage VGL. The tenth TFT T10 is turned on in response to the first logic level voltage VGH. Due to the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output unit 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the fifth period t5. The pull-up TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is the low potential voltage VGL of the QB node QB. It is turned off by Due to the turn-on of the pull-up TFT TU, the output node NO is charged with the high potential voltage VGH, so that the output terminal OUT of the first stage ST (1) has a high potential voltage ( The first output signal GOUT (1) of VGH is output.

Sixth, an operation of the first stage ST (1) during the sixth period t6 will be described in detail with reference to FIGS. 3 and 4F. During the sixth period t6, the start signal VST of the first logic level voltage VGH is input to the start terminal START, and the clock signal of the second logic level voltage VGL to the first clock terminal CLK1. CLK is input, and the inverted clock signal CLKB of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has the first logic level voltage VGH during the sixth period t6, the first logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGH is input and the QB node QB of the second stage ST (2) has the second logic level voltage VGL, the second logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGL) is input.

The first TFT T1 of the Q node charging and discharging unit 10 is turned off by the clock signal CLK of the second logic level voltage VGL during the sixth period t6.

The QB node discharge unit 20 maintains the QB node QB at the low potential voltage VGL for the sixth period t6. The second TFT T2 is turned off by the clock signal CLK of the second logic level voltage VGL during the sixth period t6. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the sixth period t6. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the sixth period t6. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charging unit 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the sixth period t6. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the sixth period t6. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The Q node boost controller 40 boosts the voltage of the Q node Q during the sixth period t6. The eighth TFT T8 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged to the first logic level voltage of the inverted clock signal CLKB. That is, during the sixth period t6, the voltage of the third node N3 increases from the low potential voltage VGL to the first logic level voltage VGH, and the amount of change in voltage of the third node N3 is the first capacitor. Reflected to the Q node Q by (Cp). Therefore, during the sixth period t6, the Q node Q rises to a voltage VGH ′ higher than the first logic level voltage VGH. Pull-up TFT (TU) has the advantage that can be turned on stably due to the voltage rise of the Q node (Q).

The output unit 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the sixth period t6. The pull-up TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is turned on in response to the second logic level voltage of the QB node QB. VGL). Due to the turn-on of the pull-up TFT TU, the output node NO maintains the high potential voltage VGH, so that the output terminal OUT of the first stage ST (1) has a high potential voltage The first output signal GOUT (1) of VGH is output.

Seventh, an operation of the first stage ST (1) during the seventh period t7 will be described in detail with reference to FIGS. 3 and 4G. During the seventh period t7, the start signal VST of the first logic level voltage VGH is input to the start terminal START, and the clock signal of the first logic level voltage VGH is input to the first clock terminal CLK1. CLK is input, and the inverted clock signal CLKB of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has a voltage VGH 'higher than the first logic level voltage VGH during the seventh period t7, the rear end Q node voltage input terminal ( The voltage VGH 'higher than the first logic level voltage VGH is input to Q_NEXT, and the QB node QB of the second stage ST (2) has a second logic level voltage VGL, so The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The inverted clock signal CLKB of the first logic level voltage VGH, which is a turn-on voltage, is input to the gate electrode of the first TFT T1 of the Q node charge / discharge unit 10 during the seventh period t7. However, since the voltage of the Q node Q connected to the source electrode of the first TFT T1 is higher than the first logic level voltage VGH, the Q node Q is higher than the first logic level voltage VGH. Maintain the voltage VGH '.

The QB node discharge unit 20 maintains the QB node QB at the low potential voltage VGL for the seventh period t7. The second TFT T2 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the seventh period t7. Due to the turn-on of the second TFT T2, the first node N1 is charged to the first logic level voltage VGH of the start signal VST. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the seventh period t7. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the seventh period t7. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB is discharged to the low potential voltage VGL.

The seventh TFT T7 of the QB node charging unit 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the seventh period t7. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the seventh period t7. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The eighth TFT T8 of the Q node boost controller 40 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the seventh period t7. The ninth TFT T9 is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-off of the eighth TFT T8 and the tenth TFT T10, the third node N3 maintains the first logic level voltage VGH.

The output unit 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the seventh period t7. The pull-up TFT TU is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is the QB node QB. It is turned off by the low potential voltage VGL of. Due to the turn-on of the pull-up TFT TU, the output node NO is charged with the high potential voltage VGH, so that the output terminal OUT of the first stage ST (1) has a high potential voltage ( The first output signal GOUT (1) of VGH is output.

Eighth, an operation of the first stage ST (1) during the eighth period t8 will be described in detail with reference to FIGS. 3 and 4H. During the eighth period t8, the start signal VST of the first logic level voltage VGH is input to the start terminal START, and the clock signal of the second logic level voltage VGL to the first clock terminal CLK1. CLK is input, and the inverted clock signal CLKB of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, during the eighth period t8, the Q node Q of the second stage ST (2) has a voltage VGH ′ that is higher than the first logic level voltage VGH, so that the latter Q node voltage input terminal ( The voltage VGH 'higher than the first logic level voltage VGH is input to Q_NEXT, and the QB node QB of the second stage ST (2) has a second logic level voltage VGL, so The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The first TFT T1 of the Q node charging and discharging unit 10 is turned off by the clock signal CLK of the second logic level voltage VGL during the eighth period t8.

The QB node discharge unit 20 maintains the QB node QB at the low potential voltage VGL for the eighth period t8. The second TFT T2 is turned off by the clock signal CLK of the second logic level voltage VGL during the eighth period t8. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the eighth period t8. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the eighth period t8. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charger 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the eighth period t8. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the eighth period t8. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The eighth TFT T8 of the Q node boost controller 40 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged to the first logic level voltage of the inverted clock signal CLKB.

The output unit 50 outputs the first output signal GOUT (1) of the high potential voltage VGH during the eighth period t8. The pull-up TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is turned on in response to the second logic level voltage of the QB node QB. VGL). Due to the turn-on of the pull-up TFT TU, the output node NO maintains the high potential voltage VGH, so that the output terminal OUT of the first stage ST (1) has a high potential voltage The first output signal GOUT (1) of VGH is output.

Ninth, an operation of the first stage ST (1) during the ninth period t9 will be described in detail with reference to FIGS. 3 and 4I. During the ninth period t9, the start signal VST of the second logic level voltage VGL is input to the start terminal START, and the clock signal of the first logic level voltage VGH is input to the first clock terminal CLK1. CLK is input, and the inverted clock signal CLKB of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has a voltage VGH 'higher than the first logic level voltage VGH during the ninth period t9, the rear Q node voltage input terminal The voltage VGH 'higher than the first logic level voltage VGH is input to Q_NEXT, and the QB node QB of the second stage ST (2) has a second logic level voltage VGL, so The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The Q node charging and discharging unit 10 discharges the Q node Q to the second logic level voltage VGL during the ninth period t9. The first TFT T1 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the ninth period t9. Due to the turn-on of the first TFT T1, the Q node Q is discharged to the second logic level voltage VGL of the start signal VST.

The second TFT T2 of the QB node discharge unit 20 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the ninth period t9. Due to the turn-on of the second TFT T2, the first node N1 is discharged to the second logic level voltage VGL of the start signal VST. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the ninth period t9. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the ninth period t9. Due to the turn-off of the third TFT T3 and the fourth TFT T4, the QB node QB is not discharged to the low potential voltage VGL.

The QB node charger 30 charges the QB node QB to the high potential voltage VGH during the ninth period t9. The seventh TFT T7 is turned off in response to the second logic level voltage VGL of the Q node Q during the ninth period t9. Due to the turn-off of the seventh TFT T7, the second node N2 is charged to the high potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high potential voltage VGH of the second node N2 during the ninth period t9. Due to the turn-on of the sixth TFT T6, the QB node QB is charged to the high potential voltage VGH.

The eighth TFT T8 of the Q node boost controller 40 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the ninth period t9. The ninth TFT T9 is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-off of the eighth TFT T8 and the tenth TFT T10, the third node N3 is floated.

The output unit 50 outputs the first output signal GOUT (1) of the low potential voltage VGL during the ninth period t9. The pull-up TFT TU is turned off by the second logic level voltage VGL of the Q node Q, and the pull-down TFT TD is the first logic level voltage VGH of the QB node QB. Is turned on in response to Due to the turn-on of the pull-down TFT TD, the output node NO is discharged to the low potential voltage VGL, so that the output terminal OUT of the first stage ST (1) has a low potential voltage ( The first output signal GOUT (1) of the VGL is output.

Tenth, an operation of the first stage ST (1) during the tenth period t10 will be described in detail with reference to FIGS. 3 and 4J. During the tenth period t10, the start signal VST of the second logic level voltage VGL is input to the start terminal START, and the clock signal of the second logic level voltage VGL to the first clock terminal CLK1. CLK is input, and the inverted clock signal CLKB of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, since the Q node Q of the second stage ST (2) has the second logic level voltage VGL during the tenth period t10, the second logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGL is input and the QB node QB of the second stage ST (2) has the first logic level voltage VGH, the first logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGH) is input.

The first TFT T1 of the Q node charging and discharging unit 10 is turned off by the clock signal CLK of the second logic level voltage VGL during the tenth period t10.

The second TFT T2 of the QB node discharge part 20 is turned off by the clock signal CLK of the second logic level voltage VGL during the tenth period t10. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the tenth period t10. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the tenth period t10. Due to the turn-off of the third TFT T3 and the fourth TFT T4, the QB node QB is not discharged to the low potential voltage VGL.

The QB node charger 30 charges the QB node QB to the high potential voltage VGH during the tenth period t10. The seventh TFT T7 is turned off in response to the second logic level voltage VGL of the Q node Q during the tenth period t10. Due to the turn-off of the seventh TFT T7, the second node N2 is charged to the high potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high potential voltage VGH of the second node N2 during the tenth period t10. Due to the turn-on of the sixth TFT T6, the QB node QB is charged to the high potential voltage VGH.

The eighth TFT T8 of the Q node boost controller 40 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the tenth period t10. The ninth TFT T9 is turned off in response to the second logic level voltage VGL. The tenth TFT T10 is turned on in response to the first logic level voltage VGH. Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output unit 50 outputs the first output signal GOUT (1) of the low potential voltage VGL during the tenth period t10. The pull-up TFT TU is turned off by the second logic level voltage VGL of the Q node Q, and the pull-down TFT TD is the first logic level voltage VGH of the QB node QB. Is turned on in response to Due to the turn-on of the pull-down TFT TD, the output node NO is discharged to the low potential voltage VGL, so that the output terminal OUT of the first stage ST (1) has a low potential voltage ( The first output signal GOUT (1) of the VGL is output.

The first stage ST (1) may repeatedly perform operations of the ninth period t9 and the tenth period t10 from the tenth period t10 to the first period t1 of the next frame period. will be.

As described above, the first stage ST (1) outputs an output signal GOUT (1) having the same waveform and phase as the start signal VST. However, each of the second to nth stages ST (2) to ST (n) has the same waveform as the front end carry signal input through the start terminal START, and the phase may output an output signal delayed by a predetermined period. Output Hereinafter, input signals, output signals, and an operation method of each of the second to nth stages ST (2) to ST (n) will be described in detail with reference to FIGS. 5 and 6A to 6K. .

5 is a waveform diagram illustrating an example of input signals and output signals of a second stage. 5 shows an output signal GOUT (1) and a first clock of the first stage ST (1), which is a front carry signal input to the start terminal START as input signals of the second stage ST (2). The inverted clock signal CLKB input to the terminal CLK1 and the clock signal CLK input to the second clock terminal CLK2 are shown. That is, while the clock signal CLK is input to the first clock terminal CLK1 of the first stage ST (1) and the inverted clock signal CLKB is input to the second clock terminal CLK2, the second stage is input. Note that the inverted clock signal CLKB is input to the first clock terminal CLK1 of the ST (2) and the clock signal CLK is input to the second clock terminal CLK2.

In addition, in FIG. 5, the Q node voltage Q (3) of the third stage ST (3) input to the rear end Q node voltage input terminal Q_NEXT and the second QB node voltage input terminal QB_NEXT are input. The QB node voltage QB (3) of the three stages ST (3) is shown. 5, Q node voltage Q (2) and QB node output to Q node voltage output terminal Q_OUT as output signals of second stage ST (2). The QB node voltage QB (2) of the second stage ST (2) output to the voltage output terminal QB_OUT and the second output terminal OUT of the second stage ST (2). The output signal GOUT (2) is shown.

Each of the stages ST (1) to ST (n) has the same waveform as the start signal VST or the front carry signal input through the start terminal START, but outputs an output signal whose phase is delayed by a predetermined period. Output through terminal (OUT). The second stage ST (2) has the same waveform as the first output signal GOUT (1), which is a front carry signal input through the start terminal START, but has a phase delayed by one horizontal period 1H. The output signal GOUT (2) is output through the output terminal OUT. In FIG. 5, each of the first to eleventh periods t1 to t11 is described as being one horizontal period 1H, but it should be noted that the present invention is not limited thereto. Meanwhile, as illustrated in FIG. 3, the first output signal GOUT (1) shown in FIG. 5 has the same waveform and phase as the start signal VST input to the start terminal of the first stage ST (1). Have

The clock signal CLK is generated at a predetermined period, and the inverted clock signal CLKB is a signal obtained by inverting the clock signal CLK. Therefore, the clock signal CLK is generated at the same period as the clock signal CLK. Therefore, when the clock signal CLK is generated with the first logic level voltage as shown in FIG. 5, the inverted clock signal CLKB is generated with the second logic level voltage. In addition, when the clock signal CLK is generated with the second logic level voltage, the inverted clock signal CLKB is generated with the first logic level voltage. In FIG. 5, the first logic level voltage is the gate high voltage VGH and the second logic level voltage is the gate low voltage VGL.

The Q node voltage Q (3) of the third stage ST (3) is generated by delaying the phase by a predetermined period than the Q node voltage Q (2) of the second stage ST (2). . The QB node voltage QB (3) of the third stage ST (3) is generated by delaying the phase by a predetermined period than the QB node voltage QB (2) of the second stage ST (2). . In FIG. 5, the predetermined period has been described based on the implementation of one horizontal period.

The Q node voltage Q (2) of the second stage ST (2), the QB node voltage QB (2) of the second stage ST (2), and the third stage ST (3) To the Q node voltage Q (3), the QB node voltage QB (3) of the third stage ST (3), and the output signal GOUT (2) of the second stage ST (2). A detailed description will be given with reference to FIGS. 6A to 6K.

6A through 6K are exemplary diagrams illustrating a circuit operation of a second stage during the first to eleventh periods. 6A to 6K each show the turn-on and turn-off states of the TFTs present in the second stage ST (2) in each of the first to eleventh periods t1 to t11. In each of FIGS. 6A-6K, the turned-on TFTs are circled. In the following description, the first logic level voltage and the high potential voltage are the gate high voltage VGH, and the second logic level voltage and the low potential voltage are the gate low voltage VGL.

First, the operation of the second stage ST (2) during the first period t1 will be described in detail with reference to FIGS. 5 and 6A. During the first period t1, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START, and the second logic level voltage V1 is input to the first clock terminal CLK1. The inverted clock signal CLKB of the VGL is input, and the clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, since the Q node Q of the third stage ST (3) has the second logic level voltage VGL during the first period t1, the second logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGL is input and the QB node QB of the third stage ST (3) has the first logic level voltage VGH, the first logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGH) is input.

The first TFT T1 of the Q node charge / discharge unit 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the first period t1.

The second TFT T2 of the QB node discharge unit 20 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the first period t1. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the first period t1. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the first period t1. Due to the turn-off of the third TFT T3 and the fourth TFT T4, the QB node QB is not discharged to the low potential voltage VGL.

The QB node charger 30 charges the QB node QB to the high potential voltage VGH during the first period t1. The seventh TFT T7 is turned off in response to the second logic level voltage VGL of the Q node Q during the first period t1. Due to the turn-off of the seventh TFT T7, the second node N2 is charged to the high potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high potential voltage VGH of the second node N2 during the first period t1. Due to the turn-on of the sixth TFT T6, the QB node QB is charged to the high potential voltage VGH.

The eighth TFT T8 of the Q node boost controller 40 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the first period t1. The ninth TFT T9 is turned off in response to the second logic level voltage VGL. The tenth TFT T10 is turned on in response to the first logic level voltage VGH. Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output unit 50 outputs the second output signal GOUT (2) of the low potential voltage VGL during the first period t1. The pull-up TFT TU is turned off by the second logic level voltage VGL of the Q node Q, and the pull-down TFT TD is the first logic level voltage VGH of the QB node QB. Is turned on in response to Due to the turn-on of the pull-down TFT TD, the output node NO is discharged to the low potential voltage VGL, so that the output terminal OUT of the second stage ST (2) has a low potential voltage ( The second output signal GOUT (2) of the VGL is output.

Secondly, the operation of the second stage ST (2) during the second period t2 will be described in detail with reference to FIGS. 5 and 6B. During the second period t2, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START, and the first logic level voltage V1 is input to the first clock terminal CLK1. The inverted clock signal CLKB of VGH is input, and the clock signal CLK of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the third stage ST (3) has the second logic level voltage VGL during the second period t2, the second logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGL is input and the QB node QB of the third stage ST (3) has the first logic level voltage VGH, the first logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGH) is input.

The Q node charging and discharging unit 10 charges the Q node Q to the first logic level voltage VGH during the second period t2. The first TFT T1 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the second period t2. Due to the turn-on of the first TFT T1, the Q node Q is charged to the first logic level voltage VGH of the first output signal GOUT (1).

The QB node discharge unit 20 discharges the QB node QB to the low potential voltage VGL during the second period t2. The second TFT T2 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the second period t2. Due to the turn-on of the second TFT T2, the first node N1 is charged to the first logic level voltage VGH of the first output signal GOUT (1). The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the second period t2. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the second period t2. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB is discharged to the low potential voltage VGL.

The seventh TFT T7 of the QB node charger 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the second period t2. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the second period t2. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The eighth TFT T8 of the Q node boost controller 40 is turned off by the clock signal CLK of the second logic level voltage VGL during the second period t2, and the ninth TFT T9 is turned off. It is turned off by the second logic level voltage VGL. The tenth TFT T10 is turned on in response to the first logic level voltage VGH. Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output unit 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the second period t2. The pull-up TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is the low potential voltage VGL of the QB node QB. It is turned off by Due to the turn-on of the pull-up TFT TU, the output node NO is charged with the high potential voltage VGH, so that the output terminal OUT of the second stage ST (2) has a high potential voltage ( The second output signal GOUT (2) of VGH is output.

Third, the operation of the second stage ST (2) during the third period t3 will be described in detail with reference to FIGS. 5 and 6C. During the third period t3, the first output signal GOUT (1) of the second logic level voltage VGH is input to the start terminal START, and the second logic level voltage V1 is input to the first clock terminal CLK1. The inverted clock signal CLKB of the VGL is input, and the clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, since the Q node Q of the third stage ST (3) has the first logic level voltage VGH during the third period t3, the first logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGH is input and the QB node QB of the third stage ST (3) has the second logic level voltage VGL, the second logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGL) is input.

The first TFT T1 of the Q node charge / discharge unit 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the third period t3.

The QB node discharge unit 20 maintains the QB node QB at the low potential voltage VGL for the third period t3. The second TFT T2 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the third period t3. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the third period t3. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the third period t3. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charging unit 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the third period t3. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the third period t3. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The Q node boost control unit 40 boosts the voltage of the Q node Q during the third period t3. The eighth TFT T8 is turned on in response to the clock signal CLK of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged to the first logic level voltage VGH of the clock signal CLK. That is, during the third period t3, the voltage of the third node N3 increases from the low potential voltage VGL to the first logic level voltage VGH, and the amount of change in voltage of the third node N3 is the first capacitor. Reflected to the Q node Q by (Cp). Therefore, during the third period t3, the Q node Q rises to a voltage VGH 'higher than the first logic level voltage VGH. Pull-up TFT (TU) has the advantage that can be turned on stably due to the voltage rise of the Q node (Q).

The output unit 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the third period t3. The pull-up TFT TU is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is the QB node QB. It is turned off by the second logic level voltage VGL. Due to the turn-on of the pull-up TFT TU, the output node NO maintains the high potential voltage VGH, so that the output terminal OUT of the second stage ST (2) has a high potential voltage The second output signal GOUT (2) of VGH is output.

Fourth, an operation of the second stage ST (2) during the fourth period t4 will be described in detail with reference to FIGS. 5 and 6D. During the fourth period t4, the first output signal GOUT (1) of the second logic level voltage VGL is input to the start terminal START, and the first logic level voltage () to the first clock terminal CLK1. The inverted clock signal CLKB of VGH is input, and the clock signal CLK of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the third stage ST (3) has a voltage VGH 'higher than the first logic level voltage VGH during the fourth period t4, the subsequent Q node voltage input terminal The voltage VGH 'higher than the first logic level voltage VGH is input to Q_NEXT, and the QB node QB of the third stage ST (3) has a second logic level voltage VGL, so The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The Q node charging and discharging unit 10 discharges the Q node Q to the second logic level voltage VGL during the fourth period t4. The first TFT T1 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the fourth period t4. Due to the turn-on of the first TFT T1, the Q node Q is discharged to the second logic level voltage VGL of the first output signal GOUT (1).

The second TFT T2 of the QB node discharge unit 20 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the fourth period t4. Due to the turn-on of the second TFT T2, the first node N1 is discharged to the second logic level voltage VGL of the first output signal GOUT (1). The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the fourth period t4. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the fourth period t4. Due to the turn-off of the third TFT T3 and the fourth TFT T4, the QB node QB is not discharged to the low potential voltage VGL.

The QB node charger 30 charges the QB node QB to the high potential voltage VGH during the fourth period t4. The seventh TFT T7 is turned off by the second logic level voltage VGL of the Q node Q during the fourth period t4. Due to the turn-off of the seventh TFT T7, the second node N2 is charged to the high potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high potential voltage VGH of the second node N2 during the fourth period t4. Due to the turn-on of the sixth TFT T6, the QB node QB is charged to the high potential voltage VGH.

The eighth TFT T8 of the Q node boost control unit 40 is turned off by the clock signal CLK of the second logic level voltage VGL during the fourth period t4. The ninth TFT T9 is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-off of the eighth TFT T8 and the tenth TFT T10, the third node N3 is floated.

The output unit 50 outputs the second output signal GOUT (2) of the low potential voltage VGL during the fourth period t4. The pull-up TFT TU is turned off by the second logic level voltage VGL of the Q node Q, and the pull-down TFT TD is the first logic level voltage VGH of the QB node QB. Is turned on in response to Due to the turn-on of the pull-down TFT TD, the output node NO is discharged to the low potential voltage VGL, so that the output terminal OUT of the second stage ST (2) has a low potential voltage ( The second output signal GOUT (2) of the VGL is output.

Fifth, an operation of the second stage ST (2) during the fifth period t5 will be described in detail with reference to FIGS. 5 and 6E. During the fifth period t5, the first output signal GOUT (1) of the second logic level voltage VGL is input to the start terminal START, and the second logic level voltage V1 is input to the first clock terminal CLK1. The inverted clock signal CLKB of the VGL is input, and the clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, since the Q node Q of the third stage ST (3) has the second logic level voltage VGL during the fifth period t5, the second logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGL is input and the QB node QB of the third stage ST (3) has the first logic level voltage VGH, the first logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGH) is input.

The first TFT T1 of the Q node charge / discharge unit 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the fifth period t5.

The second TFT T2 of the QB node discharge part 20 is turned off by the inverted clock signal CLK of the second logic level voltage VGL during the fifth period t5. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the fifth period t5. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the fifth period t5. Due to the turn-off of the third TFT T3 and the fourth TFT T4, the QB node QB is not discharged to the low potential voltage VGL.

The QB node charger 30 charges the QB node QB to the high potential voltage VGH during the fifth period t5. The seventh TFT T7 is turned off by the second logic level voltage VGL of the Q node Q during the fifth period t5. Due to the turn-off of the seventh TFT T7, the second node N2 is charged to the high potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high potential voltage VGH of the second node N2 during the fifth period t5. Due to the turn-on of the sixth TFT T6, the QB node QB is charged to the high potential voltage VGH.

The eighth TFT T8 of the Q node boost controller 40 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the fifth period t5. The ninth TFT T9 is turned off in response to the second logic level voltage VGL. The tenth TFT T10 is turned on in response to the first logic level voltage VGH. Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output unit 50 outputs the second output signal GOUT (2) of the low potential voltage VGL during the fifth period t5. The pull-up TFT TU is turned off by the second logic level voltage VGL of the Q node Q, and the pull-down TFT TD is the first logic level voltage VGH of the QB node QB. Is turned on in response to Due to the turn-on of the pull-down TFT TD, the output node NO is discharged to the low potential voltage VGL, so that the output terminal OUT of the second stage ST (2) has a low potential voltage ( The second output signal GOUT (2) of the VGL is output.

Sixth, an operation of the second stage ST (2) during the sixth period t6 will be described in detail with reference to FIGS. 5 and 6F. During the sixth period t6, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START, and the first logic level voltage V1 is input to the first clock terminal CLK1. The inverted clock signal CLKB of VGH is input, and the clock signal CLK of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the third stage ST (3) has the second logic level voltage VGL during the sixth period t6, the second logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGL is input and the QB node QB of the third stage ST (3) has the first logic level voltage VGH, the first logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGH) is input.

The Q node charging and discharging unit 10 charges the Q node Q to the first logic level voltage VGH during the sixth period t6. The first TFT T1 is turned on in response to the inverted clock signal CLKB of the first logic level voltage VGH during the sixth period t6. Due to the turn-on of the first TFT T1, the Q node Q is charged to the first logic level voltage VGH of the first output signal GOUT (1).

The QB node discharge unit 20 discharges the QB node QB to the low potential voltage VGL during the sixth period t6. The second TFT T2 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the sixth period t6. Due to the turn-on of the second TFT T2, the first node N1 is charged to the first logic level voltage VGH of the first output signal GOUT (1). The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the sixth period t6. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the sixth period t6. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB is discharged to the low potential voltage VGL.

The seventh TFT T7 of the QB node charging unit 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the sixth period t6. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the sixth period t6. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The eighth TFT T8 of the Q node boost controller 40 is turned off by the clock signal CLK of the second logic level voltage VGL during the sixth period t6. The ninth TFT T9 is turned off by the second logic level voltage VGL. The tenth TFT T10 is turned on in response to the first logic level voltage VGH. Due to the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output unit 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the sixth period t6. The pull-up TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is the low potential voltage VGL of the QB node QB. It is turned off by Due to the turn-on of the pull-up TFT TU, the output node NO is charged with the high potential voltage VGH, so that the output terminal OUT of the second stage ST (2) has a high potential voltage ( The second output signal GOUT (2) of VGH is output.

Seventh, an operation of the second stage ST (2) during the seventh period t7 will be described in detail with reference to FIGS. 5 and 6G. During the seventh period t7, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START, and the second logic level voltage () to the first clock terminal CLK1. The inverted clock signal CLKB of the VGL is input, and the clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, since the Q node Q of the third stage ST (3) has the first logic level voltage VGH during the seventh period t7, the first logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGH is input and the QB node QB of the third stage ST (3) has the second logic level voltage VGL, the second logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGL) is input.

The first TFT T1 of the Q node charge / discharge unit 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the seventh period t7.

The QB node discharge unit 20 maintains the QB node QB at the low potential voltage VGL for the seventh period t7. The second TFT T2 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the seventh period t7. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the seventh period t7. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the seventh period t7. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charging unit 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the seventh period t7. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the seventh period t7. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The Q node boost controller 40 boosts the voltage of the Q node Q during the seventh period t7. The eighth TFT T8 is turned on in response to the clock signal CLK of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged to the first logic level voltage VGH of the clock signal CLKB. That is, during the seventh period t7, the voltage of the third node N3 rises from the low potential voltage VGL to the first logic level voltage VGH, and the amount of voltage change of the third node N3 is the first capacitor. Reflected to the Q node Q by (Cp). Therefore, during the seventh period t7, the Q node Q rises to a voltage VGH ′ that is higher than the first logic level voltage VGH.

The output unit 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the seventh period t7. The pull-up TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is turned on in response to the second logic level voltage of the QB node QB. VGL). Due to the turn-on of the pull-up TFT TU, the output node NO maintains the high potential voltage VGH, so that the output terminal OUT of the second stage ST (2) has a high potential voltage The second output signal GOUT (2) of VGH is output.

Eighth, the operation of the second stage ST (2) during the eighth period t8 will be described in detail with reference to FIGS. 5 and 6H. During the eighth period t8, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START, and the first logic level voltage V1 is input to the first clock terminal CLK1. The inverted clock signal CLKB of VGH is input, and the clock signal CLK of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, during the eighth period t8, the Q node Q of the third stage ST (3) has a voltage VGH ′ that is higher than the first logic level voltage VGH, so that the latter Q node voltage input terminal The voltage VGH 'higher than the first logic level voltage VGH is input to Q_NEXT, and the QB node QB of the third stage ST (3) has a second logic level voltage VGL, so The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The inverted clock signal CLKB of the first logic level voltage VGH, which is a turn-on voltage, is input to the gate electrode of the first TFT T1 of the Q node charge / discharge unit 10 during the eighth period t8. However, since the voltage of the Q node Q connected to the source electrode of the first TFT T1 is higher than the first logic level voltage VGH, the Q node Q is higher than the first logic level voltage VGH. Maintain the voltage VGH '.

The QB node discharge unit 20 maintains the QB node QB at the low potential voltage VGL for the eighth period t8. The second TFT T2 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the eighth period t8. Due to the turn-on of the second TFT T2, the first node N1 is charged to the first logic level voltage VGH of the start signal VST. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the eighth period t8. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the eighth period t8. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB is discharged to the low potential voltage VGL.

The seventh TFT T7 of the QB node charger 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the eighth period t8. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the eighth period t8. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The eighth TFT T8 of the Q node boost controller 40 is turned off by the clock signal CLK of the second logic level voltage VGL during the eighth period t8. The ninth TFT T9 is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-off of the eighth TFT T8 and the tenth TFT T10, the third node N3 maintains the first logic level voltage VGH.

The output unit 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the eighth period t8. The pull-up TFT TU is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is the QB node QB. It is turned off by the low potential voltage VGL of. Due to the turn-on of the pull-up TFT TU, the output node NO is charged with the high potential voltage VGH, so that the output terminal OUT of the second stage ST (2) has a high potential voltage ( The second output signal GOUT (2) of VGH is output.

Ninth, an operation of the second stage ST (2) during the ninth period t9 will be described in detail with reference to FIGS. 5 and 6I. During the ninth period t9, the first output signal GOUT (1) of the first logic level voltage VGH is input to the start terminal START, and the second logic level voltage is input to the first clock terminal CLK1. The inverted clock signal CLKB of the VGL is input, and the clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, since the Q node Q of the third stage ST (3) has a voltage VGH 'higher than the first logic level voltage VGH during the ninth period t9, the latter Q node voltage input terminal ( The voltage VGH 'higher than the first logic level voltage VGH is input to Q_NEXT, and the QB node QB of the third stage ST (3) has a second logic level voltage VGL, so The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The first TFT T1 of the Q node charge / discharge unit 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the ninth period t9.

The QB node discharge unit 20 maintains the QB node QB at the low potential voltage VGL for the ninth period t9. The second TFT T2 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the ninth period t9. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned on in response to the first logic level voltage VGH of the first node N1 during the ninth period t9. The fourth TFT T4 is turned on in response to the first logic level voltage VGH of the Q node Q during the ninth period t9. Due to the turn-on of the third TFT T3 and the fourth TFT T4, the QB node QB maintains the low potential voltage VGL.

The seventh TFT T7 of the QB node charging unit 30 is turned on in response to the first logic level voltage VGH of the Q node Q during the ninth period t9. Due to the turn-on of the seventh TFT T7, the second node N2 is discharged to the low potential voltage VGL. Therefore, the sixth TFT T6 is turned off by the low potential voltage VGL of the second node N2 during the ninth period t9. Due to the turn-off of the sixth TFT T6, the high potential voltage VGH is not supplied to the QB node QB.

The eighth TFT T8 of the Q node boost controller 40 is turned on in response to the clock signal CLK of the first logic level voltage VGH. The ninth TFT T9 is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-on of the eighth TFT T8 and the ninth TFT T9, the third node N3 is charged to the first logic level voltage of the clock signal CLK.

The output unit 50 outputs the second output signal GOUT (2) of the high potential voltage VGH during the ninth period t9. The pull-up TFT TU is turned on in response to the first logic level voltage VGH of the Q node Q, and the pull-down TFT TD is turned on in response to the second logic level voltage of the QB node QB. VGL). Due to the turn-on of the pull-up TFT TU, the output node NO maintains the high potential voltage VGH, so that the output terminal OUT of the second stage ST (2) has a high potential voltage The second output signal GOUT (2) of VGH is output.

Tenth, the operation of the second stage ST (2) during the tenth period t10 will be described in detail with reference to FIGS. 5 and 6J. During the tenth period t10, the first output signal GOUT (1) of the second logic level voltage VGL is input to the start terminal START, and the first logic level voltage V1 is input to the first clock terminal CLK1. The inverted clock signal CLKB of VGH is input, and the clock signal CLK of the second logic level voltage VGL is input to the second clock terminal CLK2. In addition, since the Q node Q of the third stage ST (3) has a voltage VGH 'higher than the first logic level voltage VGH during the tenth period t10, the latter Q node voltage input terminal The voltage VGH 'higher than the first logic level voltage VGH is input to Q_NEXT, and the QB node QB of the third stage ST (3) has a second logic level voltage VGL, so The second logic level voltage VGL is input to the QB node voltage input terminal QB_NEXT.

The Q node charging and discharging unit 10 discharges the Q node Q to the second logic level voltage VGL during the tenth period t10. The first TFT T1 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the tenth period t10. Due to the turn-on of the first TFT T1, the Q node Q is discharged to the second logic level voltage VGL of the first output signal GOUT (1).

The second TFT T2 of the QB node discharge unit 20 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the tenth period t10. Due to the turn-on of the second TFT T2, the first node N1 is discharged to the second logic level voltage VGL of the first output signal GOUT (1). The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the tenth period t10. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the tenth period t10. Due to the turn-off of the third TFT T3 and the fourth TFT T4, the QB node QB is not discharged to the low potential voltage VGL.

The QB node charger 30 charges the QB node QB to the high potential voltage VGH during the tenth period t10. The seventh TFT T7 is turned off in response to the second logic level voltage VGL of the Q node Q during the tenth period t10. Due to the turn-off of the seventh TFT T7, the second node N2 is charged to the high potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high potential voltage VGH of the second node N2 during the tenth period t10. Due to the turn-on of the sixth TFT T6, the QB node QB is charged to the high potential voltage VGH.

The eighth TFT T8 of the Q node boost controller 40 is turned off by the clock signal CLK of the second logic level voltage VGL during the tenth period t10. The ninth TFT T9 is turned on in response to the voltage VGH 'higher than the first logic level voltage VGH. The tenth TFT T10 is turned off by the second logic level voltage VGL. Due to the turn-off of the eighth TFT T8 and the tenth TFT T10, the third node N3 is floated.

The output unit 50 outputs the second output signal GOUT (2) of the low potential voltage VGL during the tenth period t10. The pull-up TFT TU is turned off by the second logic level voltage VGL of the Q node Q, and the pull-down TFT TD is the first logic level voltage VGH of the QB node QB. Is turned on in response to Due to the turn-on of the pull-down TFT TD, the output node NO is discharged to the low potential voltage VGL, so that the output terminal OUT of the second stage ST (2) has a low potential voltage ( The second output signal GOUT (2) of the VGL is output.

Eleventh, the operation of the second stage ST (2) during the eleventh period t11 will be described in detail with reference to FIGS. 5 and 6K. During the eleventh period t11, the first output signal GOUT (1) of the second logic level voltage VGL is input to the start terminal START, and the second logic level voltage V1 is input to the first clock terminal CLK1. The inverted clock signal CLKB of the VGL is input, and the clock signal CLK of the first logic level voltage VGH is input to the second clock terminal CLK2. In addition, since the Q node Q of the third stage ST (3) has the second logic level voltage VGL during the eleventh period t11, the second logic level is included in the subsequent Q node voltage input terminal Q_NEXT. Since the voltage VGL is input and the QB node QB of the third stage ST (3) has the first logic level voltage VGH, the first logic level voltage is applied to the subsequent QB node voltage input terminal QB_NEXT. (VGH) is input.

The first TFT T1 of the Q node charge / discharge unit 10 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the eleventh period t11.

The second TFT T2 of the QB node discharge part 20 is turned off by the inverted clock signal CLKB of the second logic level voltage VGL during the eleventh period t11. Due to the turn-off of the second TFT T2, the first node N1 is floated. The third TFT T3 is turned off by the second logic level voltage VGL of the first node N1 during the eleventh period t11. The fourth TFT T4 is turned off by the second logic level voltage VGL of the Q node Q during the eleventh period t11. Due to the turn-off of the third TFT T3 and the fourth TFT T4, the QB node QB is not discharged to the low potential voltage VGL.

The QB node charger 30 charges the QB node QB to the high potential voltage VGH during the eleventh period t11. The seventh TFT T7 is turned off in response to the second logic level voltage VGL of the Q node Q during the eleventh period t11. Due to the turn-off of the seventh TFT T7, the second node N2 is charged to the high potential voltage VGH. Therefore, the sixth TFT T6 is turned on in response to the high potential voltage VGH of the second node N2 during the eleventh period t11. Due to the turn-on of the sixth TFT T6, the QB node QB is charged to the high potential voltage VGH.

The eighth TFT T8 of the Q node boost controller 40 is turned on in response to the clock signal CLK of the first logic level voltage VGH during the eleventh period t11. The ninth TFT T9 is turned off in response to the second logic level voltage VGL. The tenth TFT T10 is turned on in response to the first logic level voltage VGH. Due to the turn-off of the ninth TFT T9 and the turn-on of the tenth TFT T10, the third node N3 is discharged to the low potential voltage VGL.

The output unit 50 outputs the second output signal GOUT (2) of the low potential voltage VGL during the eleventh period t11. The pull-up TFT TU is turned off by the second logic level voltage VGL of the Q node Q, and the pull-down TFT TD is the first logic level voltage VGH of the QB node QB. Is turned on in response to Due to the turn-on of the pull-down TFT TD, the output node NO is discharged to the low potential voltage VGL, so that the output terminal OUT of the second stage ST (2) has a low potential voltage ( The second output signal GOUT (2) of the VGL is output.

The second stage ST (2) may repeatedly perform operations of the tenth period t11 and the eleventh period t11 after the eleventh period t11 and before the first period t1 of the next frame period. will be.

As described above, the second stage ST (2) outputs the second output signal GOUT (2) having the same waveform as the previous carry signal and having a phase delayed by a predetermined period. On the other hand, it should be noted that the operation method of the second stage ST (2) described with reference to FIGS. 6A to 6K is one embodiment. That is, the inverted clock signal CLKB is input to the first clock terminal CLK1, the clock signal CLK is input to the second clock terminal CLK2, and the front carry signal is input to the start terminal START. The operation method of the k stage ST (k) is the same as the operation method of the second stage ST (2) described with reference to FIGS. 6A to 6K. Therefore, the inverted clock signal CLKB is input to the first clock terminal CLK1, the clock signal CLK is input to the second clock terminal CLK2, and the front carry signal is input to the start terminal START. The k stage ST (k) has the same waveform as the previous carry signal and outputs the kth output signal GOUT (k) whose phase is delayed by a predetermined period.

7 is a waveform diagram illustrating an example of input signals and output signals of a third stage. 7 shows an output signal GOUT (2) and a first clock of the second stage ST (2), which is a front carry signal input to the start terminal START as input signals of the third stage ST (3). The clock signal CLK input to the terminal CLK1 and the inverted clock signal CLKB input to the second clock terminal CLK2 are shown. That is, the clock signal CLK is input to the first clock terminal CLK1 of the first stage ST (1) and the third stage ST (3), and the inverted clock signal (CLK2) is input to the second clock terminal CLK2. While the CLKB is input, the inverted clock signal CLKB is input to the first clock terminal CLK1 of the second stage ST (2) and the clock signal CLK is input to the second clock terminal CLK2. Note that

In addition, in FIG. 7, the Q node voltage Q (4) of the fourth stage ST (4), which is input to the rear Q node voltage input terminal Q_NEXT, and the second QB node voltage input terminal QB_NEXT, are input. The QB node voltage QB (4) of the four stages ST (4) is shown. In addition, in FIG. 7, the Q stage voltage Q (3) and the QB node of the third stage ST (3) output to the Q node voltage output terminal Q_OUT as output signals of the third stage ST (3). QB node voltage QB (3) of third stage ST (3) output to voltage output terminal QB_OUT, and third output to output terminal OUT of third stage ST (3). The output signal GOUT (3) is shown.

Each of the stages ST (1) to ST (n) has the same waveform as the start signal VST or the front carry signal input through the start terminal START, but outputs an output signal whose phase is delayed by a predetermined period. Output through terminal (OUT). The third stage ST (3) has the same waveform as the second output signal GOUT (2), which is the front carry signal input through the start terminal START, but has a phase delayed by one horizontal period 1H. The output signal GOUT (3) is output through the output terminal OUT. In FIG. 7, each of the second to twelfth periods t2 to t12 is one horizontal period 1H, but it should be noted that the present invention is not limited thereto.

The clock signal CLK is generated at a predetermined period, and the inverted clock signal CLKB is a signal obtained by inverting the clock signal CLK. Therefore, the clock signal CLK is generated at the same period as the clock signal CLK. Therefore, when the clock signal CLK is generated with the first logic level voltage as shown in FIG. 7, the inverted clock signal CLKB is generated with the second logic level voltage. In addition, when the clock signal CLK is generated with the second logic level voltage, the inverted clock signal CLKB is generated with the first logic level voltage. In FIG. 7, the first logic level voltage is the gate high voltage VGH and the second logic level voltage is the gate low voltage VGL.

The Q node voltage Q (4) of the fourth stage ST (4) is generated by delaying the phase by a predetermined period than the Q node voltage Q (3) of the third stage ST (3). . The QB node voltage QB (4) of the fourth stage ST (4) is generated by delaying the phase by a predetermined period than the QB node voltage QB (3) of the third stage ST (3). . In FIG. 7, the predetermined period has been described based on the implementation of one horizontal period.

Meanwhile, the operation method of the third stage ST (3) during the second to twelfth periods t2 to t12 is the second method during the first to eleventh periods t1 to t11 described with reference to FIGS. 6A to 6K. The operation method of the stage ST (2) is the same. Therefore, the Q node voltage Q (3) of the third stage ST (3), the QB node voltage QB (3) of the third stage ST (3), and the fourth stage ST (4). Q node voltage Q (4) of Q3, QB node voltage QB (4) of fourth stage ST (4), and third output signal GOUT (3) of third stage ST (3). 3)) is also described with reference to FIGS. 6A to 6K. However, the first output signal GOUT (1) is input to the start terminal START of the second stage ST (2), and the inverted clock signal CLKB is input to the first clock terminal CLK1. The clock signal CLK is input to the second clock terminal CLK2, and the Q node voltage Q (3) of the third stage ST (3) is input to the subsequent Q node voltage input terminal Q_NEXT. The QB node voltage Q (3) of the third stage ST (3) is input to the subsequent QB node voltage input terminal QB_NEXT. However, the second output signal GOUT2 is input to the start terminal START of the third stage ST (3), the clock signal CLK is input to the first clock terminal CLK1, and the second clock terminal is provided. The inverted clock signal CLKB is input to the CLK2, the Q node voltage Q (4) of the fourth stage ST (4) is input to the rear Q node voltage input terminal Q_NEXT, and the rear QB node. Note that the QB node voltage Q (4) of the fourth stage ST (4) is input to the voltage input terminal QB_NEXT.

As a result, the third stage ST (3) outputs the third output signal GOUT (3) having the same waveform as the previous carry signal and having a phase delayed by a predetermined period. Kth stage in which the clock signal CLK is input to the first clock terminal CLK1, the inverted clock signal CLKB is input to the second clock terminal CLK2, and the front carry signal is input to the start terminal START. The operation method of ST (k) is the same as the operation method of the third stage ST (3) described with reference to FIG. Therefore, the clock signal CLK is input to the first clock terminal CLK1, the inverted clock signal CLKB is input to the second clock terminal CLK2, and the front carry signal is input to the start terminal START. The k stage ST (k) has the same waveform as the previous carry signal and outputs the kth output signal GOUT (k) whose phase is delayed by a predetermined period.

As described above, the shift register according to an embodiment of the present invention includes first to nth stages ST (1) to ST (n), and the clock signal CLK is applied to the first clock terminal CLK1. ) And the inverted clock signal CLKB are input to the second clock terminal CLK2 and the start signal VST is input to the start terminal START. It operates as described in conjunction with FIG. 4J. The k-th stage ST in which the inverted clock signal CLKB is input to the first clock terminal CLK1, the clock signal CLK is input to the second clock terminal CLK2, and the front carry signal is input to the start terminal START. (k) operates as described in conjunction with FIGS. 5 and 6A to 6K. Finally, the k th clock signal CLK is input to the first clock terminal CLK1, the inverted clock signal CLKB is input to the second clock terminal CLK2, and the front carry signal is input to the start terminal START. The stage ST (k) operates as described with reference to FIG.

8 is a circuit diagram illustrating an example of a circuit configuration of a k-th stage according to the second embodiment of the present invention. Referring to FIG. 8, the Q node charging / discharging unit 10 and the QB node QB controlling the charge / discharge of the Q node Q of the k-th stage ST (k) according to the second embodiment of the present invention. QB node discharge section 20 for controlling discharge, QB node charging section 30 for controlling charging of QB node QB, and Q node boost control section 40 for controlling voltage boost of Q node Q. And an output unit 50 for charging the output node NO connected to the output terminal OUT to a high potential voltage or to a low potential voltage according to the voltages of the Q node Q and the QB node QB. do.

The Q node charging and discharging unit 10, the QB node discharging unit 20, the Q node boost control unit 40, and the output unit 50 of the k-th stage ST (k) according to the second embodiment of the present invention are Since it may be implemented substantially the same as the first embodiment of the present invention described with reference to FIG. 2, description thereof will be omitted. However, the QB node charger 30 of the k-th stage ST (k) according to the second embodiment of the present invention is implemented differently from the first embodiment of the present invention, and will be described in detail below.

Referring to FIG. 8, the QB node charger 30 charges the QB node QB to the high potential voltage VDD in response to the high potential voltage VDD input through the high potential voltage input terminal VDDT. To this end, the QB node charging unit 30 includes a fifth TFT T5 connecting the QB node QB to the high potential voltage input terminal VDDT in response to the high potential voltage VDD. The fifth TFT T5 charges the QB node QB to a high potential voltage in response to the high potential voltage VDD. The gate electrode and the drain electrode of the fifth TFT T5 are connected to the high potential voltage input terminal VDDT, and the source electrode is connected to the QB node QB.

Meanwhile, the k-th stage ST (k) according to the second embodiment of the present invention operates substantially the same as the k-th stage ST (k) according to the first embodiment of the present invention. The description will be omitted.

9 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention. Referring to FIG. 9, a display device according to an exemplary embodiment of the present invention includes a display panel 10, a data driving circuit, a gate driving circuit, a timing controller 11, and the like.

A display device according to an embodiment of the present invention may include any display device that sequentially supplies gate pulses (or scan pulses) to gate lines (or scan lines) to write digital video data to pixels by line sequential scanning have. For example, a display device according to an embodiment of the present invention may include a liquid crystal display (LCD), an organic light emitting diode (OLED), a field emission display (FED) , And an electrophoresis display (EPD). Although the present invention has been described in the following embodiments mainly on the display device being implemented as an organic light emitting diode display device, it should be noted that the display device of the present invention is not limited to the organic light emitting diode display device.

The display panel 10 includes data lines and at least one switching signal line group. One switching signal line group includes first to nth switching signal lines. In the display panel 10, a pixel array in which pixels are arranged in a matrix form is formed. Each of the pixels of the display panel 10 includes at least one switching thin film transistor (TFT), a driving TFT, an organic light emitting diode device, and at least one capacitor. Each of the pixels controls an electric current flowing in the organic light emitting diode element using a switching TFT and a driving TFT to display an image. The display panel 10 may display an image in the form of bottom emission and top emission depending on the pixel structure.

The data drive circuit includes a plurality of source drive ICs 12. [ The source drive ICs 12 receive the digital video data DATA from the timing controller 11. Each of the source drive ICs 12 converts the digital video data DATA into a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, and synchronizes the data voltage with a gate pulse. The data lines of the display panel 10 are supplied to each other. The source drive ICs 12 may be connected to data lines of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driving circuit includes a level shifter 13 and at least one shift register 14. The level shifter 13 level shifts the TTL logic level voltages of the clock signals CLK and CLKB input from the timing controller 11 to the first logic level voltage and the second logic level voltage. . The level shifted clocks CLK and CLKB are input to at least one shift register 14. The shift register 14 is connected to one switching signal line group of the display panel 10 to sequentially output a switching control signal. That is, the shift register 14 sequentially outputs the switching control signal to the first to nth signal lines. Also, for example, when each of the pixels of the organic light emitting diode display includes first to third switching TFTs, the gate driving circuit may include a first switching control signal to control the first switching TFT. A first shift register for supplying the line group, a second shift register for supplying a second switching control signal to the second switching signal line group for controlling the second switching TFT, and a third switching for controlling the third switching TFT. It may include a third shift register for supplying a control signal to the third switching signal line group.

Since the shift register 14 sequentially outputs a switching control signal having the same waveform as the start signal using two clock signals, only the waveform of the start signal input to each of the plurality of shift registers is different. In this case, the plurality of shift registers may output a plurality of switching control signals having different waveforms. As a result, the present invention can significantly reduce the circuit design area of the shift register, thereby reducing the bezel area of the display device.

The shift register 14 is directly formed on the lower substrate of the display panel 10 by a gate drive-IC in panel (GIP) method. In the GIP method, the level shifter 13 is mounted on a printed circuit board 15. The shift register 14 has been described in detail above with reference to FIGS. 1 to 7.

The timing controller 11 receives digital video data DATA from an external host system through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 11 transmits digital video data DATA input from the host system to the source drive ICs 12. In addition, the timing controller 11 receives a timing signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a main clock, and the like from the host system through an LVDS or TMDS interface receiving circuit. The timing controller 11 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the timing signal from the host system. The timing control signals include a gate timing control signal for controlling the operation timing of the gate driving circuit, and a data timing control signal for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The gate timing control signal includes a start voltage VST and clock signals CLK and CLKB. The start voltage VST is input to the shift register 14 to control the shift start timing of the shift register 14. The clock signals CLK and CLKB are input to the level shifter 13 and then level shifted to the shift register 14 to control each of the stages of the shift register 14.

The data timing control signal DCS includes a source start pulse, a source sampling clock, a polarity control signal, and a source output enable signal. The source start pulse controls the shift start timing of the source drive ICs 12. The source sampling clock is a clock signal that controls the sampling timing of data within the source drive ICs 12 based on the rising or falling edge. The polarity control signals control the polarity of the data voltages output from the source drive ICs 12. [ If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

As described above, the shift register of the present invention sequentially outputs a signal having the same waveform as the start signal using two clock signals. As a result, when the present invention changes only the waveform of the start signal input to each of the plurality of shift registers, the plurality of shift registers may output a plurality of switching control signals having different waveforms. For this reason, the present invention can greatly reduce the circuit design area, and thus reduce the bezel area of the display device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source drive IC 13: Level shifter
14: shift register 15: printed circuit board
10: Q node voltage charge and discharge unit 20: QB node voltage discharge unit
30: QB node voltage charging section 40: Q node boost control section
50: output unit

Claims (20)

It has a plurality of stages to sequentially generate the output,
Each of the stages includes:
A start terminal to which a start signal or a front carry signal is input, a first clock terminal and a second clock terminal to which a clock signal and an inverted clock signal inverting the clock signal are input, and the start signal or the front end input to the start terminal; And an output terminal for outputting a signal having the same waveform as the carry signal. The method of claim 1,
Each of the stages includes:
A Q node charging and discharging unit configured to charge and discharge a Q node with the start signal or the front carry signal input through the start terminal in response to the clock signal or the inverted clock signal input through the first clock terminal;
A QB node discharge unit configured to discharge the QB node to a low potential voltage in response to the clock signal or the inverted clock signal input through the first clock terminal and the start signal or the front carry signal input through the start terminal; ;
A QB node charger configured to charge the QB node to a high potential voltage; And
And a output unit configured to output the high potential voltage to the output terminal in response to the voltage of the Q node, and output the low potential voltage to the output terminal in response to the voltage of the QB node. . 3. The method of claim 2,
The Q node charging and discharging unit,
And a first TFT connecting the Q node to the start terminal in response to a first logic level voltage of the clock signal or the inverted clock signal. The method of claim 3, wherein
The QB node discharge unit,
A second TFT connecting a first node to the start terminal in response to the first logic level voltage of the clock signal or the inverted clock signal; And
And a third TFT configured to discharge the QB node to the low potential voltage in response to a first logic level voltage of the first node. 5. The method of claim 4,
The QB node discharge unit,
And a fourth TFT configured to discharge the QB node to the low potential voltage in response to the first logic level voltage of the Q node. The method of claim 5, wherein
The QB node charging unit,
And a fifth TFT supplying the high potential voltage to the QB node in response to the high potential voltage. The method of claim 5, wherein
The QB node charging unit,
A fifth TFT supplying the high potential voltage to the second node in response to the high potential voltage;
A sixth TFT charging the QB node to the high potential voltage in response to the high potential voltage of the second node; And
And a seventh TFT configured to discharge the second node to the low potential voltage in response to the first logic level voltage of the Q node. The method of claim 7, wherein
The output unit includes:
A pull-up TFT charging an output node connected to the output terminal with the high potential voltage in response to a first logic level voltage of the Q node; And
And a pull-down TFT which discharges the output node to the low potential voltage in response to the high potential voltage of the QB node. The method of claim 8,
The output unit includes:
And a first capacitor connected between the Q node and the output node. 3. The method of claim 2,
Each of the stages includes:
The third node is charged to the first logic level voltage in response to the voltage of the Q node of the later stage inputted through the clock signal or the inverted clock signal input through the second clock terminal and the latter Q node voltage input terminal. And a Q node boost control unit configured to discharge the third node to the low potential voltage in response to a voltage of the QB node of the rear stage stage input through a rear end QB node voltage input terminal. 11. The method of claim 10,
The Q node boost control unit,
An eighth TFT and a ninth TFT connecting the third node to the second clock terminal in response to a first logic level voltage of the clock signal or the inverted clock signal and a first logic level voltage of a Q node of the rear stage; ;
A tenth TFT discharging the third node to the low potential voltage in response to the high potential voltage of the QB node of the rear stage; And
And a second capacitor connected between the Q node and the third node. 11. The method of claim 10,
When the clock signal is input to the first clock terminal, the inverted clock signal is input to the second clock terminal,
And the clock signal is input to the second clock terminal when the inverted clock signal is input to the first clock terminal. 11. The method of claim 10,
K (1≤k≤n, k is a natural number of 2 or more, n is the number of stages) When the clock signal is input to the first clock terminal of the stage and the inverted clock signal is input to the second clock terminal, And the inverted clock signal is input to the first clock terminal of the k + 1th stage and the clock signal is input to the second clock terminal. The method of claim 1,
K (1≤k≤n, k is a natural number of 2 or more, n is the number of stages) When the start signal is input to the start terminal of the stage, the output terminal outputs a signal having the same phase as the start signal,
And the output terminal outputs a signal having a phase delayed from that of the front end carry signal when the front end carry signal is input to the start terminal of the kth stage. A display panel including data lines and at least one switching signal line group;
A data driving circuit for converting input digital video data into analog data voltages and supplying the analog data voltages to the data lines; And
A gate driving circuit including one or more shift registers to sequentially output a switching control signal to the at least one switching signal line group,
The shift register has a plurality of stages that sequentially generate an output,
Each of the stages may include a start terminal to which a start signal or a front carry signal is input, a first clock terminal and a second clock terminal to which a clock signal and an inverted clock signal inverting the clock signal are input, and the input terminal input to the start terminal. And an output terminal for outputting a signal having the same waveform as the start signal or the front carry signal. The method of claim 15,
Each of the stages includes:
A Q node charging and discharging unit configured to charge and discharge a Q node with the start signal or the front carry signal input through the start terminal in response to the clock signal or the inverted clock signal input through the first clock terminal;
A QB node discharge unit configured to discharge the QB node to a low potential voltage in response to the clock signal or the inverted clock signal input through the first clock terminal and the start signal or the front carry signal input through the start terminal; ;
A QB node charger configured to charge the QB node to a high potential voltage; And
And an output unit configured to output the high potential voltage to the output terminal in response to the voltage of the Q node, and output the low potential voltage to the output terminal in response to the voltage of the QB node. . 17. The method of claim 16,
Each of the stages includes:
The third node is charged to the first logic level voltage in response to the voltage of the Q node of the later stage inputted through the clock signal or the inverted clock signal input through the second clock terminal and the latter Q node voltage input terminal. And a Q node boost control unit configured to discharge the third node to the low potential voltage in response to a voltage of the QB node of the rear stage stage input through a rear end QB node voltage input terminal. The method of claim 17,
When the clock signal is input to the first clock terminal, the inverted clock signal is input to the second clock terminal,
And the clock signal is input to the second clock terminal when the inverted clock signal is input to the first clock terminal. The method of claim 17,
K (1≤k≤n, k is a natural number of 2 or more, n is the number of stages) When the clock signal is input to the first clock terminal of the stage and the inverted clock signal is input to the second clock terminal, And the inverted clock signal is input to the first clock terminal of the k + 1th stage and the clock signal is input to the second clock terminal. The method of claim 15,
K (1≤k≤n, k is a natural number of 2 or more, n is the number of stages) When the start signal is input to the start terminal of the stage, the output terminal outputs a signal having the same phase as the start signal,
And the output terminal outputs a signal having a phase delayed from that of the front end carry signal when the front end carry signal is input to the start terminal of the kth stage.

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