KR102637600B1 - Gate driving circuit and display device comprising the same - Google Patents

Abstract

The present invention relates to a gate driving circuit mounted in the form of a gate in panel (GIP) and a display device including the same. The gate driving circuit according to an embodiment of the present invention includes a plurality of stages that are dependently connected. Each of the plurality of stages includes an output unit that outputs a gate voltage by the voltage of the Q node and the voltage of the QB node, in response to the gate voltage or gate start signal of the previous stage to control the voltage of the Q node, Q It includes a Q node control unit including a first transistor for charging the node, a QB node control unit for controlling the voltage at the QB node, and a tenth transistor that outputs a high potential voltage to the first transistor according to the voltage of the Q node. Thus, not only can the life expectancy of the gate driving circuit be increased, but also the problem of poor gate voltage output can be solved.

Description

Gate driving circuit and display device including the same {GATE DRIVING CIRCUIT AND DISPLAY DEVICE COMPRISING THE SAME}

The present invention relates to a display device, and more specifically, to a gate driving circuit mounted in the form of a gate in panel (GIP) and a display device including the same.

As we enter the information age, the field of displays that visually express electrical information signals has developed rapidly, and in response to this, a variety of display devices with excellent performance such as thinness, weight reduction, and low power consumption have been developed. It is being developed. Examples of such display devices include Liquid Crystal Display devices (LCD) and Organic Light Emitting Display Devices (OLED).

This display device includes a display panel on which pixel arrays for displaying images are arranged, a data driving circuit that supplies data voltage to data lines arranged in the display panel, and a gate pulse that is sequentially supplied to gate lines arranged in the display area. It includes a driving circuit such as a gate driving circuit and a data driving circuit and a timing control circuit that controls the gate driving circuit.

Among such driving circuits, the gate driving circuit has recently been applied to display devices in the form of a Gate In Panel (hereinafter referred to as 'GIP') built into the display panel along with the pixel arrays.

The GIP includes a shift register for sequentially outputting the gate voltage, and the shift register includes a plurality of dependently connected stages.

Each stage includes a pull-up transistor that outputs a gate voltage according to the voltage of the Q node and a plurality of transistors that control the voltage of the Q node.

In order for GIP to output the gate voltage, the voltage of the Q node must be bootstrapped. In this case, the source-drain voltage of a plurality of transistors that control the voltage of the Q node rapidly increases.

Accordingly, the plurality of transistors that control the voltage of the Q node are subjected to high junction stress, and the plurality of transistors that control the voltage of the Q node not only deteriorate but also generate unintended leakage current.

As a result, the expected lifespan of the GIP decreases due to deterioration. In addition, the GIP has a problem in that the output of the gate voltage is delayed due to leakage current or that an undesired gate voltage is output.

The problem to be solved by the present invention is to provide a gate driving circuit capable of reducing junction stress by including a separate transistor that fixes the potential of some electrodes of the transistor, and a display device including the same.

Another problem to be solved by the present invention is to provide a gate driving circuit that can minimize leakage current by applying a dual transistor structure and a display device including the same.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

The gate driving circuit according to an embodiment of the present invention includes a plurality of stages that are dependently connected, and each of the plurality of stages includes an output unit that outputs a gate voltage according to the voltage of the Q node and the voltage of the QB node, and the voltage of the Q node. In order to control, in response to the gate voltage or gate start signal of the previous stage, a Q node control unit including a first transistor for charging the Q node, a QB node control unit for controlling the voltage at the QB node, and By including a tenth transistor that outputs a high potential voltage to the first transistor depending on the voltage, the problem of gate voltage output failure can be solved.

A display device according to an embodiment of the present invention is composed of a display panel including a plurality of pixels, a plurality of stages, a gate driving circuit that sequentially outputs a gate voltage to the plurality of pixels, and a gate driving circuit that controls the driving of the gate driving circuit. It includes a timing controller, and each of the plurality of stages includes a seventh transistor that outputs a gate voltage by the voltage of the Q node, a first transistor that controls the voltage of the Q node and includes a first sub-transistor and a second sub-transistor connected in series. and a tenth transistor having a gate electrode connected to the Q node and a second electrode connected to the QA node disposed between the first sub-transistor and the second sub-transistor, so that the life expectancy of the display device may be increased.

Specific details of other embodiments are included in the detailed description and drawings.

In the present invention, by reducing the degree of deterioration of the transistor, the life expectancy of the gate driving circuit can be increased.

Also, in the present invention, the gate driving circuit can solve the problem of gate voltage output failure by minimizing leakage current.

The effects according to the present invention are not limited to the details exemplified above, and further various effects are included within the present invention.

1 is a block diagram of a display device according to an embodiment of the present invention.
Figure 2 is a block diagram of a gate driving circuit according to an embodiment of the present invention.
Figure 3 is a circuit diagram showing each stage of the gate driving circuit according to an embodiment of the present invention.
Figure 4 is a timing diagram for explaining the driving of each stage of the gate driving circuit according to an embodiment of the present invention.
Figure 5a is a circuit diagram showing a portion of each stage of the gate driving circuit according to an embodiment of the present invention. Figure 5b is a circuit diagram showing the dual transistor structure of the first transistor.
Figure 6 is a graph showing the internal voltage of each stage of the gate driving circuit according to an embodiment of the present invention.
Figure 7 is a circuit diagram showing a portion of each stage of the gate driving circuit according to another embodiment of the present invention.
Figure 8 is a graph showing the internal voltage of each stage of the gate driving circuit according to another embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to complete the disclosure of the present invention, and are not limited to the embodiments disclosed below, and are known to those skilled in the art in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'comprises', 'has', 'consists of', etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

When an element or layer is referred to as “on” another element or layer, it includes instances where the other layer or other element is directly on top of or interposed between the other elements.

Additionally, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the components shown.

Each feature of the various embodiments of the present invention can be combined or combined with each other, partially or entirely, and various technological interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

Embodiments of the present invention have been described based on a liquid crystal display device, but the present invention is not limited to a liquid crystal display device and can be applied to any display device equipped with a gate driving circuit, such as an organic light emitting display device.

Hereinafter, the present invention will be examined in detail with reference to the drawings.

1 is a block diagram of a display device according to an embodiment of the present invention.

Referring to FIG. 1, a display device according to an embodiment of the present invention includes a display panel 100, a timing control circuit 200, a data driving circuit 300, and a gate driving circuit 400.

The display panel 100 is located outside the display area (A/A) and a display area (A/A) for displaying images, and a non-display area (N/A) where various signal lines and the gate driving circuit 400 are arranged. ) includes.

A plurality of pixels P are arranged in the display area A/A to display an image. Additionally, n gate lines (GL1 to GLn) arranged in the first direction and m data lines (DL1 to DLm) arranged in a direction different from the first direction are arranged in the display area (A/A). The plurality of pixels (P) are electrically connected to n gate lines (GL1 to GLn) and m data lines (DL1 to DLm). Accordingly, the gate voltage and data voltage are applied to each pixel P through the gate lines GL1 to GLn and the data lines DL1 to DLm. And, each pixel (P) implements grayscale by the gate voltage and data voltage. Finally, an image is displayed in the display area A/A according to the gradation displayed by each pixel P.

In the non-display area (N/A), various signal lines (GL1 to GLn and DL1 to DLm) and a gate driving circuit (400) transmit signals that control the operation of the pixels (P) arranged in the display area (A/A). ) is placed.

The timing control circuit 200 transmits the input image signal (RGB) received from the host system to the data driving circuit 300.

The timing control circuit 200 uses timing signals such as a clock signal (DCLK), horizontal synchronization signal (Hsync), vertical synchronization signal (Vsync), and data enable signal (DE) received along with video data (RGB). Control signals (GCS, DCS) for controlling the operation timing of the gate driving circuit 200 and the data driving circuit 300 are generated. Here, the horizontal synchronization signal (Hsync) is a signal representing the time it takes to display one horizontal line on the screen, the vertical synchronization signal (Vsync) is a signal representing the time it takes to display one frame of the screen, and the data enable signal (DE) ) is a signal indicating the period for supplying the data voltage to the pixel P defined in the display panel 100.

In other words, the timing control circuit 200 receives a timing signal, outputs a gate control signal (GCS) to the gate driving circuit 200, and outputs a data control signal (DCS) to the data driving circuit 300. .

The data driving circuit 300 receives the data control signal DCS and outputs a data voltage to the data lines DL1 to DLm.

Specifically, the data driving circuit 300 generates a sampling signal according to the data control signal (DCS), latches the image data (RGB) according to the sampling signal, changes it to a data voltage, and then activates the source output (Source Output). Data voltage is supplied to the data lines (DL1 to DLm) in response to the Enable (SOE) signal.

The data driving circuit 300 may be connected to a bonding pad of the display panel 100 using a chip on glass (COG) method, or may be placed directly on the display panel 100. In some cases, the data driving circuit 300 may be connected to the bonding pad of the display panel 100 using a chip on glass (COG) method. ) may be integrated and deployed. Additionally, the data driving circuit 300 may be arranged in a chip on film (COF) method.

The gate driving circuit 400 sequentially supplies gate voltage to the gate lines GL1 to GLn according to the gate control signal GCS. The gate driving circuit 400 may include a shift register and a level shifter.

A typical gate driving circuit is formed independently from the display panel and can be electrically connected to the display panel in various ways. However, the gate driving circuit 400 of the display device according to an embodiment of the present invention is formed in the form of a thin film pattern when manufacturing the substrate of the display panel 100, and is formed in a gate in panel (gate in panel) on the non-display area (N/A). It can be embedded in the Gate In Panel (GIP) method. In FIG. 1, only one gate driving circuit 400 is shown to be disposed in the non-display area (N/A) of the display panel 100, but this is not limited, and two gate driving circuits 400 may be disposed. You can.

The gate driving circuit 400 includes a plurality of stages that output gate voltage. Below, we will look at the detailed configuration and driving method of the gate driving circuit according to an embodiment of the present invention.

Figure 2 is a block diagram of a gate driving circuit according to an embodiment of the present invention.

Referring to FIG. 2, the gate driving circuit 400 according to an embodiment of the present invention includes a plurality of stages (S1 to S(n)) cascaded.

That is, the gate voltage (Vout1 to Vout(n-1)) output from the previous stage (S1 to S(n-1)) is input to each of the plurality of cascaded stages (S1 to S(n)). . The gate voltages (Vout1 to Vout(n-1)) output from the previous stage (S1 to S(n-1)) and input to the next stage (S2 to S(n)) are separated into a separate carry signal (Carry signal). signal), but in the gate driving circuit 400 according to an embodiment of the present invention, it is output from the previous stage (S1 to S(n-1)) and is output from the next stage (S2 to S(n-1). )), the gate voltage (Vout1 to Vout(n-1)) and the carry signal have the same waveform, so they are integrated and explained.

For example, the gate voltage Vout1 output from the first stage S1 may be input to the second stage S2, and the gate voltage Vout2 output from the second stage S2 may be input to the third stage (S2). S3), and the gate voltage (Vout(n-1)) output from the n-1th stage (S(n-1)) may be input to the nth stage (S(n)).

Specifically, the first to nth stages (S1 to S(n)) each receive a gate low voltage (VGL), a high potential voltage (VDD), and a low potential voltage (VSS), and a gate start signal (VST) or Gate voltages (Vout1 to Vout(n)) synchronized to the timing of the clock signal (CLK) by the gate voltages (Vout1 to Vout(n-1)) output from the previous stage (S1 to S(n-1)). can be output.

For example, the first stage (S1) receives the gate start signal (VST) at the start timing of the frame and outputs the first gate voltage (Vout1) using the clock signal (CLK). Thereafter, the second stage (S2) to the n-th stage (S(n)) performs a plurality of signals according to the gate voltages (Vout1 to Vout(n-1)) output from the previous stages (S1 to S(n-1)). The second to nth gate voltages (Vout2 to Vout(n)) are sequentially output using the clock signal (CLK).

As described above, each stage (S1 to S(n)) sequentially outputs gate voltages (Vout1 to Vout(n)) to implement one frame.

Below, the configuration and driving method of each stage (S1 to S(n)) will be described in detail.

The switch elements constituting each stage (S1 to S(n)) may be implemented as transistors with an n-type or p-type MOSFET structure. Although an n-type transistor is illustrated in the following examples, the present invention is not limited thereto.

Additionally, a transistor is a three-electrode device including a gate electrode, a source electrode, and a drain electrode. The source electrode is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source electrode. The drain electrode is the electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source electrode to the drain electrode. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the voltage of the source electrode is lower than the voltage of the drain electrode so that electrons can flow from the source electrode to the drain electrode. In an n-type MOSFET, since electrons flow from the source electrode to the drain electrode, the direction of current flows from the drain electrode to the source electrode. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the voltage of the source electrode is higher than the voltage of the drain electrode so that holes can flow from the source electrode to the drain electrode. In a p-type MOSFET, since holes flow from the source electrode to the drain electrode, current flows from the source electrode to the drain electrode. It should be noted that the source and drain electrodes of the MOSFET are not fixed. For example, the source electrode and drain electrode of the MOSFET may change depending on the applied voltage. In the following embodiments, the invention should not be limited by the source electrode and drain electrode of the transistor.

Hereinafter, the source electrode of the transistor is expressed as a first electrode, and the drain electrode of the transistor is expressed as a second electrode. However, depending on the type of transistor, the source electrode can be interpreted as a second electrode, and the drain electrode can be interpreted as a first electrode.

In addition, each stage (S1 to S(n)) of the gate driving circuit 400 of the present invention uses low temperature poly-silicon (hereinafter referred to as LTPS), a transistor using a polycrystalline semiconductor material as an active layer. An LTPS transistor may be used. Polysilicon materials have high mobility (more than 100㎠/Vs), low energy consumption and excellent reliability, so they can be applied to transistors for driving devices.

Figure 3 is a circuit diagram showing each stage of the gate driving circuit according to an embodiment of the present invention.

Referring to FIG. 3, the nth stage (S(n)) of the gate driving circuit according to an embodiment of the present invention includes a Q node control unit (T1, T2, T3), a QB node control unit (T4, T5, T6), It includes an output unit (T7, T8, T9), a tenth transistor (T10), and a capacitor (C).

The Q node control unit (T1, T2, T3) controls the voltage of the Q node (Q-node). In other words, the Q node control unit (T1, T2, T3) determines the Q-node charging and discharging timing.

The Q node control unit (T1, T2, T3) includes a first transistor (T1), a second transistor (T2), and a third transistor (T3).

The first transistor T1 charges the Q node (Q-node) in response to the gate voltage (Vout(n-4)) or gate start signal (VST) of the previous stage. Specifically, each of the gate electrode and the first electrode of the first transistor T1 is connected to the output terminal of the gate voltage Vout(n-4) of the previous stage or the output terminal of the gate start signal VST, and the first The second electrode of the transistor T1 is connected to the Q node (Q-node). Accordingly, while the gate voltage (Vout(n-4)) or gate start signal (VST) of the previous stage is at a high level, the first transistor (T1) is turned on, and the Q node (Q-node) ) is charged with the gate voltage (Vout(n-4)) or gate start signal (VST) of the previous stage at a high level.

The second transistor T2 discharges the Q node (Q-node) in response to the voltage of the QB node (QB-node). Specifically, the gate electrode of the second transistor T2 is connected to the QB node (QB-node), the first electrode of the second transistor T2 is connected to the supply line of the low potential voltage (VSS), and the second The second electrode of the transistor T2 is connected to the Q node (Q-node). Accordingly, while the QB node (QB-node) is being charged, the second transistor (T2) is turned on and discharges the Q node (Q-node) to the low potential voltage (VSS).

The third transistor T3 discharges the Q node (Q-node) in response to the gate voltage (Vout(n+4)) of the next stage. Specifically, the gate electrode of the third transistor (T3) is connected to the output terminal of the gate voltage (Vout(n+4)) of the next stage, and the first electrode of the third transistor (T3) is connected to the low potential voltage (VSS). It is connected to the supply line, and the second electrode of the third transistor T3 is connected to the Q node (Q-node). Accordingly, while the gate voltage (Vout(n+4)) of the next stage is at a high level, the third transistor (T3) is turned on, and the Q node (Q-node) is set to a low potential voltage (VSS). ) until discharged.

The QB node control unit (T4, T5, T6) controls the voltage of the QB node (QB-node). In other words, the QB node control unit (T4, T5, T6) determines the charging and discharging timing of the QB node (QB-node).

The QB node control unit (T4, T5, T6) includes a fourth transistor (T4), a fifth transistor (T5), and a sixth transistor (T6).

The fourth transistor T4 charges the QB node (QB-node) with the high potential voltage (VDD). Specifically, each of the gate electrode and the first electrode of the fourth transistor (T4) is connected to the supply line of the high potential voltage (VDD), and the second electrode of the fourth transistor (T4) is connected to the QB node (QB-node). connected. Accordingly, the fourth transistor T4 is turned on by the high potential voltage VDD, thereby charging the QB node (QB-node) with the high potential voltage VDD.

The fifth transistor T5 discharges the QB node (QB-node) in response to the gate voltage (Vout(n-4)) or gate start signal (VST) of the previous stage. Specifically, the gate electrode of the fifth transistor T5 is connected to the output terminal of the gate voltage Vout(n-4) of the previous stage or the output terminal of the gate start signal VST, and the gate electrode of the fifth transistor T5 is connected to the output terminal of the gate voltage Vout(n-4) of the previous stage. The first electrode is connected to the supply line of the low potential voltage (VSS), and the second electrode of the fifth transistor (T5) is connected to the QB node (QB-node). Accordingly, while the gate voltage (Vout(n-4)) or gate start signal (VST) of the previous stage is at a high level, the fifth transistor (T5) is turned on, and the QB node (QB-node) ) is discharged to low potential voltage (VSS).

The sixth transistor T6 discharges the QB node in response to the voltage of the Q node (Q-node). Specifically, the gate electrode of the sixth transistor T6 is connected to the Q node (Q-node), the first electrode of the sixth transistor T6 is connected to the supply line of the low potential voltage (VSS), and the sixth transistor T6 is connected to the Q-node. The second electrode of the transistor T6 is connected to the QB node (QB-node). Accordingly, while the Q node (Q-node) is being charged, the fifth transistor (T5) is turned on and discharges the QB node (QB-node) to the low potential voltage (VSS).

The output units (T7, T8, T9) output the gate voltage (Vout(n)) by the voltage of the Q node (Q-node) and the QB node (QB-node).

Specifically, the output units (T7, T8, T9) pull down the gate voltage (Vout (n)) and the seventh transistor (T7), which is a transistor that pulls up the gate voltage (Vout (n)). It includes an eighth transistor (T8) and a ninth transistor (T9) that are -down transistors.

The gate electrode of the seventh transistor T7 is connected to the Q node (Q-node), the first electrode of the seventh transistor T7 is connected to the output terminal of the clock signal CLK(n), and the seventh transistor T7 The second electrode of (T7) is connected to the output terminal of the gate voltage (Vout(n)). Accordingly, when the Q-node is in a charged state, the seventh transistor T7 is turned on and transmits the high-level clock signal CLK(n) to the gate voltage Vout(n). Output as

The gate electrode of the eighth transistor T8 is connected to the QB node (QB-node), the first electrode of the eighth transistor T8 is connected to the supply line of the gate low voltage VGL, and the eighth The second electrode of the transistor T8 is connected to the output terminal of the gate voltage Vout(n). Accordingly, when the QB node (QB-node) is in a charged state, the eighth transistor T8 is turned on and outputs the gate low voltage VGL as the gate voltage Vout(n).

The gate electrode of the ninth transistor (T9) is connected to the output terminal of the gate voltage (Vout(n+4)) of the next stage, and the first electrode of the ninth transistor (T9) is connected to the supply line of the gate low voltage (VGL). and the second electrode of the ninth transistor T9 is connected to the output terminal of the gate voltage Vout(n). Accordingly, when the gate voltage (Vout(n+4)) of the next stage is high level, the ninth transistor (T9) is turned on, and the gate low voltage (VGL) is changed to the gate voltage (Vout(n) ))).

The tenth transistor T10 serves to reduce junction stress of the first transistor T1. Specifically, the gate electrode of the tenth transistor (T10) is connected to the Q node (Q-node), the first electrode of the tenth transistor (T10) is connected to the supply line of the high potential voltage (VDD), and the tenth The second electrode of the transistor T10 is connected to the first transistor T1. Accordingly, when the Q-node is in a charged state, the tenth transistor T10 is turned on and outputs the high potential voltage VDD to the first transistor T1. Accordingly, the junction stress of the first transistor T1 can be reduced. A detailed description of this will be described later with reference to FIGS. 5A, 5B, and 6.

And, the capacitor (C) bootstraps the Q node (Q-node). Specifically, one end of the capacitor C is connected to the gate electrode of the seventh transistor T7, and the other end of the capacitor C is connected to the second terminal of the seventh transistor T7, which is the gate voltage (Vout(n)) output terminal. connected to the electrode. Accordingly, while the Q node (Q-node) is charging, when the clock signal (CLK(n)) output from the second electrode of the seventh transistor (T7) rises to a high level, the Q by the capacitor (C) Nodes (Q-nodes) can be bootstrapped.

Hereinafter, the driving of each stage of the gate driving circuit according to an embodiment of the present invention will be described with reference to FIG. 4.

Figure 4 is a timing diagram for explaining the driving of each stage of the gate driving circuit according to an embodiment of the present invention.

As an example, the operation of the third stage (S3) will be described.

At the first time point t1, the first transistor T1 is turned on by the gate start signal VST3 raised to a high level, and the Q node (Q-node) is charged. Then, the fifth transistor T5 is turned on by the high-level gate start signal VST3 and the QB node (QB-node) is discharged.

At the second time point t2, the Q node (Q-node) is bootstrapped by the clock signal CLK3 raised to a high level. Accordingly, as the seventh transistor T7 is turned on, a high level gate voltage Vout(3) may be output. Additionally, the sixth transistor T6 is turned on by the voltage charged in the Q node (Q-node), and the QB node (QB-node) is discharged.

More specifically, referring to FIG. 3, since the gate electrode and the second electrode of the seventh transistor T7 are coupled by the capacitor C, the seventh transistor T7 is turned on. ), when the clock signal CLK(3) rises to a high level at the second time point t2, the voltage of the Q-node, which is the gate electrode of the seventh transistor T7, also rises. That is, the phenomenon in which the voltage of the Q node (Q-node) increases at the second time point (t2) is called bootstrapping.

As described above, the Q-node is bootstrapped and the seventh transistor T7 is completely turned on, and a high level gate voltage Vout(3) is output. It can be.

At the third time point (t3), the third transistor (T3) is turned on by the gate voltage (Vout(7)) of the next stage raised to a high level, so that the Q-node is low. It is discharged at potential voltage (VSS). Then, the fourth transistor T4 is turned on by the high potential voltage VDD, and the QB node (QB-node) is charged with the high potential voltage VDD. Accordingly, the second transistor T2 is turned on by the high potential voltage VDD charged in the QB node (QB-node), and the Q node (Q-node) is discharged.

Then, the eighth transistor T8 is turned on by the high potential voltage VDD charged in the QB node (QB-node), so that the gate low voltage VGL becomes the gate voltage Vout(3). ) can be output. At the same time, the ninth transistor (T9) is turned on by the gate voltage (Vout(7)) of the next stage raised to a high level, so that the gate low voltage (VGL) is increased to the gate voltage (Vout(3)). ) can be output.

Figure 5a is a circuit diagram showing a portion of each stage of the gate driving circuit according to an embodiment of the present invention. Figure 5b is a circuit diagram showing the dual transistor structure of the first transistor.

In Figure 5a, only the first transistor (T1), fourth transistor (T4), seventh transistor (T7), tenth transistor (T10), and capacitor (C) are shown.

As will be described later with reference to FIG. 6, in the time interval between the second time point (t2) and the third time point (t3) when the Q node (Q-node) is bootstrapped, the Q node (Q-node) The voltage of increases to 38V, while the gate voltage of the previous stage (Vout(n-4)) decreases to -16.0V.

Accordingly, the voltage of the first electrode of the first transistor (T1) is -16.0V, and the voltage of the second electrode of the first transistor (T1) is 38V, so the source-drain voltage of the first transistor (T) is 54V. . Therefore, due to the high voltage applied between the source electrode (the first electrode) and the drain electrode (the second electrode) of the first transistor (T1), the first transistor (T1) experiences high junction stress.

As a result, deterioration and leakage current may occur in the first transistor T1. To prevent this, the first transistor T1 may be configured as a dual length transistor, as shown in FIG. 5B. .

The first transistor T1, which is a dual transistor, shares a gate electrode and includes a first sub-transistor ST1 and a second sub-transistor ST2 connected in series.

More specifically, the gate electrode of the first sub-transistor (ST1) and the gate electrode of the second sub-transistor (ST2) are both the output terminal of the gate voltage (Vout(n-4)) of the previous stage or the gate start signal (VST). ) is connected to the output terminal.

And, the first electrode of the first sub-transistor (ST1) is connected to the output terminal of the gate voltage (Vout(n-4)) of the previous stage or the output terminal of the gate start signal (VST), and the first sub-transistor (ST1) ) is connected to the first electrode of the second sub-transistor ST2, and the second electrode of the second sub-transistor ST2 is connected to the Q node (Q-node).

As described above, the second electrode of the first sub-transistor (ST1) is connected to the first electrode of the second sub-transistor (ST2), so the first sub-transistor (ST1) and the second sub-transistor (ST2) are connected in series. do.

For convenience of explanation, the second electrode of the first sub-transistor ST1 and the first electrode of the second sub-transistor ST2 are defined as a QA node (QA-node). That is, the QA node (QA-node) refers to a node (Q-node) disposed between the first sub-transistor (ST1) and the second sub-transistor (ST2).

Since the first transistor (T1) is configured as a double transistor, the source-drain voltage applied to the first transistor (T1) is the source-drain voltage of the first sub-transistor (ST1) and the source-drain voltage of the second sub-transistor (ST2). It can be divided into drain voltage.

Accordingly, the high junction stress of the first transistor T1 is distributed to the first sub-transistor ST1 and the second sub-transistor ST2, and leakage current of the first transistor T1 can be prevented.

In addition, as shown in FIGS. 3 and 5A, not only the first transistor (T1) is composed of a double transistor, but also the second transistor (T2), the third transistor (T3), the fourth transistor (T4), and the second transistor (T2). The 5th transistor (T5), the 6th transistor (T6), and the 10th transistor (T10) are also composed of dual transistors, and can prevent deterioration of the transistors and leakage current by dispersing junction stress.

Referring to FIG. 7, in the gate driving circuit according to another embodiment of the present invention, the gate electrode of the tenth transistor (T10) is connected to the Q node (Q-node), and the first electrode of the tenth transistor (T10) is connected to the output terminal of the clock signal CLK(n), and the second electrode of the tenth transistor T10 is connected to the QA node (QA-node).

And, as shown in FIG. 4, during the time interval between the second time point (t2) and the third time point (t3) when the Q node (Q-node) is bootstrapped, the clock signal (CLK(n) ) can be raised to high potential voltage (VDD).

Accordingly, when the Q-node is in a charged state, the tenth transistor T10 is turned on, and the clock signal CLK(n), which is the high potential voltage VDD, is transmitted to the QA node ( output to QA-node).

Figure 6 is a graph showing the internal voltage of each stage of the gate driving circuit according to an embodiment of the present invention.

Figure 6 shows the voltage of the Q node (Vq), the voltage of the QA node (Vqa), and the gate voltage (Vout(n-4)) or gate start signal (VST) of the previous stage.

Specifically, in the time interval between the second time point (t2) and the third time point (t3) when the Q-node is bootstrapped, the voltage (Vq) of the Q node increases to 38.0V, while , the gate voltage (Vout(n-4)) of the previous stage drops to -16.0V. And, since the tenth transistor T10 outputs a high potential voltage (VDD) to the QA node (QA-node), the voltage of the QA node (QA-node) is measured to be 15.8V.

That is, the source-drain voltage of the first sub-transistor ST1 is 31.8V, and the source-drain voltage of the second sub-transistor ST2 is 22.2V. Accordingly, the source-drain voltage of the first transistor (T1) of 54V will be divided into the source-drain voltage of the first sub-transistor (ST1) of 31.8V and the source-drain voltage of the second sub-transistor (ST2) of 22.2V. You can.

That is, the junction stress of the first transistor T1 may be distributed to the first sub-transistor ST1 and the second sub-transistor ST2, respectively.

Accordingly, deterioration of the first transistor T1 including the first sub-transistor ST1 and the second sub-transistor ST2 and the resulting leakage current can be prevented.

As a result, the degree of deterioration of the first transistor T1 is reduced, so that the life expectancy of the gate driving circuit according to an embodiment of the present invention can be increased.

Additionally, the gate driving circuit according to an embodiment of the present invention can solve the problem of gate voltage output failure by minimizing leakage current.

Below, a gate driving circuit according to another embodiment of the present invention will be described. Since one embodiment of the present invention and another embodiment of the present invention differ only in the connection relationship of the first electrode of the tenth transistor, the connection relationship of the tenth transistor will be described in detail.

Figure 7 is a circuit diagram showing a portion of each stage of a gate driving circuit according to another embodiment of the present invention.

Referring to FIG. 7, the gate electrode of the tenth transistor (T10) is connected to the Q node (Q-node), and the first electrode of the tenth transistor (T10) is connected to the supply line of the high potential voltage (VDD). , the second electrode of the tenth transistor T10 is connected to the QA node (QA-node). Accordingly, when the Q node (Q-node) is in a charged state, the tenth transistor (T10) is turned on and outputs the high potential voltage (VDD) to the QA node (QA-node).

Figure 8 is a graph showing the internal voltage of each stage of the gate driving circuit according to another embodiment of the present invention.

Figure 8 shows the voltage of the Q node (Vq), the voltage of the QA node (Vqa), and the gate voltage (Vout(n-4)) or gate start signal (VST) of the previous stage.

Specifically, in the time interval between the second time point (t2) and the third time point (t3) when the Q-node is bootstrapped, the voltage (Vq) of the Q node increases to 27.7V, while , the gate voltage (Vout(n-4)) of the previous stage drops to -16.0V. And, since the tenth transistor T10 outputs a high potential voltage (VDD) to the QA node (QA-node), the voltage of the QA node (QA-node) is measured to be 14.1V.

That is, the source-drain voltage of the first sub-transistor ST1 is 30.1V, and the source-drain voltage of the second sub-transistor ST2 is 13.6V. Accordingly, the source-drain voltage of the first transistor (T1) of 43.7V is divided into the source-drain voltage of the first sub-transistor (ST1) of 30.1V and the source-drain voltage of the second sub-transistor (ST2) of 13.6V. It can be.

That is, the junction stress of the first transistor T1 may be distributed to the first sub-transistor ST1 and the second sub-transistor ST2, respectively.

Accordingly, deterioration of the first transistor T1 including the first sub-transistor ST1 and the second sub-transistor ST2 and the resulting leakage current can be prevented.

As a result, the degree of deterioration of the first transistor T1 is reduced, so that the life expectancy of the gate driving circuit according to another embodiment of the present invention can be increased.

In addition, the gate driving circuit according to another embodiment of the present invention can also solve the problem of gate voltage output failure by minimizing leakage current.

A gate driving circuit and a display device including the same according to various embodiments of the present invention may be described as follows.

In order to solve the above-described problem, the gate driving circuit according to an embodiment of the present invention includes a plurality of stages that are dependently connected, and each of the plurality of stages adjusts the gate voltage by the voltage of the Q node and the voltage of the QB node. An output unit for outputting, a Q node control unit including a first transistor for charging the Q node in response to the gate voltage or gate start signal of the previous stage to control the voltage of the Q node, and a QB for controlling the voltage at the QB node. Including a node control unit and including a tenth transistor that outputs a high potential voltage to the first transistor according to the voltage of the Q node, not only can the life expectancy of the gate driving circuit be increased, but also the problem of poor output of the gate voltage. can be solved.

According to another feature of the present invention, the first transistor may include a first sub-transistor and a second sub-transistor connected in series.

According to another feature of the present invention, the tenth transistor may be connected to a QA node disposed between the first sub-transistor and the second sub-transistor.

According to another feature of the present invention, the tenth transistor may be connected to a supply line of high potential voltage.

According to another feature of the present invention, the tenth transistor is connected to the output terminal of the clock signal, and the clock signal can be raised to a high potential voltage while the Q node is bootstrapped.

According to another feature of the present invention, the Q node control unit further includes a second transistor for discharging the Q node in response to the voltage of the QB node and a third transistor for discharging the Q node in response to the gate voltage of the next stage. can do.

According to another feature of the present invention, the QB node control unit includes a fourth transistor for charging the QB node with a high potential voltage, a fifth transistor for discharging the QB node in response to the gate voltage or gate start signal of the previous stage, and It may include a sixth transistor that discharges the QB node in response to the voltage of the Q node.

A display device according to an embodiment of the present invention is composed of a display panel including a plurality of pixels, a plurality of stages, a gate driving circuit that sequentially outputs a gate voltage to the plurality of pixels, and a gate driving circuit that controls the driving of the gate driving circuit. It includes a timing controller, and each of the plurality of stages includes a seventh transistor that outputs a gate voltage by the voltage of the Q node, a first transistor that controls the voltage of the Q node and includes a first sub-transistor and a second sub-transistor connected in series. and a tenth transistor whose gate electrode is connected to the Q node and whose second electrode is connected to the QA node disposed between the first sub-transistor and the second sub-transistor, so that the life expectancy of the display device can be increased. In addition, it can solve the problem of poor gate voltage output.

According to another feature of the present invention, the first electrode of the tenth transistor may be connected to a high potential voltage supply line.

According to another feature of the present invention, the first electrode of the tenth transistor is connected to the output terminal of the clock signal, and the clock signal can be raised to a high potential voltage while the Q node is bootstrapped.

According to another feature of the present invention, each of the gate electrode of the first sub-transistor and the gate electrode of the second sub-transistor may be connected to the output terminal of the gate voltage of the previous stage or the output terminal of the gate start signal.

According to another feature of the present invention, the gate electrode of the seventh transistor is connected to the Q node, the first electrode of the seventh transistor is connected to the output terminal of the clock signal, and the second electrode of the seventh transistor is connected to the gate voltage. It can be connected to the output terminal.

According to another feature of the present invention, each of the plurality of stages may further include a gate electrode and a fourth transistor in which the first electrode is connected to a high potential voltage supply line and the second electrode is connected to the QB node.

According to another feature of the present invention, each of the plurality of stages further includes a capacitor connected between the gate electrode of the seventh transistor and the second electrode of the seventh transistor.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

100: display panel
200: Timing control circuit
300: data driving circuit
400: Gate driving circuit
GL1 to GLn: Gate lines
DL1 to DLm: data lines
N/A: Non-display area
A/A: Display area
S1 to S(n): Stage
Vout1 to Vout(n): Gate voltage
VDD: high potential voltage
VSS: Low potential voltage
VGL: Gate low voltage
CLK: clock signal
VST: Gate Start Signal
T1: first transistor
T2: second transistor
T3: third transistor
T4: fourth transistor
T5: fifth transistor
T6: sixth transistor
T7: seventh transistor
T8: 8th transistor
T9: ninth transistor
T10: 10th transistor
Q-node: Q node
QB-node: QB node
QA-node: QA node
ST1: first sub-transistor
ST2: second sub-transistor

Claims (14)

Includes a plurality of stages that are dependently connected,
Each of the plurality of stages is,
An output unit that outputs a gate voltage based on the voltage of the Q node and the voltage of the QB node;
A Q node control unit including a first transistor that charges the Q node in response to a gate voltage or gate start signal of a previous stage to control the voltage of the Q node; and
It includes a QB node control unit that controls the voltage of the QB node,
It includes a tenth transistor that outputs a high potential voltage to the first transistor according to the voltage of the Q node,
The QB node control unit,
A gate driving circuit comprising a gate electrode and a fourth transistor whose first electrode is directly connected to the supply line of the high potential voltage and whose second electrode is directly connected to the QB node.
According to paragraph 1,
The first transistor is,
A gate driving circuit including a first sub-transistor and a second sub-transistor connected in series. According to paragraph 2,
A gate driving circuit wherein the tenth transistor is connected to a QA node disposed between the first sub-transistor and the second sub-transistor.
According to paragraph 1,
A gate driving circuit wherein the tenth transistor is connected to a supply line of the high potential voltage.
According to paragraph 1,
The tenth transistor is connected to the output terminal of the clock signal,
A gate driving circuit wherein the clock signal is raised to the high potential voltage while the Q node is bootstrapped.
According to paragraph 1,
The Q node control unit,
A second transistor that discharges the Q node in response to the voltage of the QB node, and
A gate driving circuit further comprising a third transistor that discharges the Q node in response to the gate voltage of the next stage.
According to paragraph 1,
The QB node control unit,
A fifth transistor that discharges the QB node in response to the gate voltage of the previous stage or the gate start signal, and
A gate driving circuit further comprising a sixth transistor that discharges the QB node in response to the voltage of the Q node.
A display panel including a plurality of pixels;
A gate driving circuit composed of a plurality of stages and sequentially outputting gate voltages to the plurality of pixels, and
It includes a timing controller that controls driving of the gate driving circuit,
Each of the plurality of stages is,
A seventh transistor outputting the gate voltage according to the voltage of the Q node;
a first transistor that controls the voltage of the Q node and includes a first sub-transistor and a second sub-transistor connected in series;
a tenth transistor whose gate electrode is connected to the Q node and whose second electrode is connected to the QA node disposed between the first sub-transistor and the second sub-transistor; and
A display device comprising a fourth transistor in which a gate electrode and a first electrode are directly connected to a supply line of a high potential voltage, and a second electrode is directly connected to a QB node.
According to clause 8,
A first electrode of the tenth transistor is connected to a supply line of the high potential voltage.
According to clause 8,
The first electrode of the tenth transistor is connected to the output terminal of the clock signal,
The display device wherein the clock signal is raised to a high potential voltage while the Q node is bootstrapped.
According to clause 8,
Each of the gate electrodes of the first sub-transistor and the gate electrode of the second sub-transistor is connected to the output terminal of the gate voltage of the previous stage or the output terminal of the gate start signal.
According to clause 8,
The gate electrode of the seventh transistor is connected to the Q node,
The first electrode of the seventh transistor is connected to the output terminal of the clock signal,
A second electrode of the seventh transistor is connected to an output terminal of the gate voltage.
delete According to clause 8,
Each of the plurality of stages is,
The display device further includes a capacitor connected between the gate electrode of the seventh transistor and the second electrode of the seventh transistor.

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