KR102174833B1 - Gate Driving Circuit and Display Device having the Same - Google Patents

Abstract

The gate driving circuit of the present invention includes a plurality of stages that are dependently connected to each other in order to supply a gate signal to each of the gate lines connected to the pixels, and among the stages, the n-th stage includes a pull-up unit, a pull-down unit, and a first And a compensation transistor and a first capacitor. The pull-up section is precharged by the Q node voltage, and is synchronized with the timing of the gate clock. The pull-down unit is controlled by the voltage of the P node maintaining the turn-off voltage in the period when the Q node is the turn-on voltage, and discharges the voltage of the Q node to the turn-off voltage when the P node is the turn-on voltage. In the first compensation transistor, the gate electrode and the drain electrode are electrically connected to the P node during the threshold voltage extraction period. The first capacitor is connected between the P node and a gate clock input terminal providing a gate clock.

Description

Gate Driving Circuit and Display Device having the Same

The present invention relates to a gate driving circuit and a display device including the same.

Flat panel displays (FPDs) are widely used not only for monitors of desktop computers, but also for portable computers and mobile phone terminals, such as notebook computers and tablets, due to their advantages in miniaturization and weight reduction. Such a flat panel display includes a liquid crystal display; LCD), Plasma Display Panel (PDP), Field Emission Display; FED) and Organic Light Emitting Diode Display (OLED).

The display device includes a data line to which a data voltage is applied and a gate line to which a gate signal synchronized with the data voltage is applied. The gate driving circuit that generates the gate signal sequentially outputs the gate signal. The gate driving circuit can be implemented in various forms, and a method for optimizing a circuit configuration to increase the reliability of driving is being sought.

An object of the present invention is to provide a gate driving circuit capable of increasing driving reliability regardless of the type of transistors constituting the gate driving circuit, and a display device including the same.

An object of the present invention is to provide a gate driving circuit and a display device including the same, which can improve the reduction in driving reliability due to deterioration of the pull-down transistor of the present invention. In particular, the present invention is to provide a gate driving circuit capable of improving a deterioration phenomenon regardless of whether a threshold voltage of a pull-down transistor is negatively shifted or positively shifted, and a display device including the same.

The gate driving circuit of the present invention includes a plurality of stages that are dependently connected to each other in order to supply a gate signal to each of the gate lines connected to the pixels, and among the stages, the n-th stage includes a pull-up unit, a pull-down unit, and a first And a compensation transistor and a first capacitor. The pull-up section is precharged by the Q node voltage, and is synchronized with the timing of the gate clock. The pull-down unit is controlled by the voltage of the P node maintaining the turn-off voltage in the period when the Q node is the turn-on voltage, and discharges the voltage of the Q node to the turn-off voltage when the P node is the turn-on voltage. In the first compensation transistor, the gate electrode and the drain electrode are electrically connected to the P node during the threshold voltage extraction period. The first capacitor is connected between the P node and a gate clock input terminal providing a gate clock.

The present invention extracts the threshold voltage of the pull-down transistor and controls the pull-down transistor by using the voltage reflecting it, so that driving can be stably maintained regardless of the amount of change in the threshold voltage of the pull-down transistor. In particular, since the present invention directly compensates for the magnitude of the threshold voltage of the pull-down transistor, operation reliability of the gate driving circuit can be improved regardless of the direction in which the threshold voltage of the pull-down transistor is shifted.

1 is a diagram showing a configuration of a display device according to the present invention.
2 is a diagram showing a shift register of a gate driving circuit according to the present invention.
3 is a diagram showing a circuit diagram of an nth stage of a gate driving circuit according to the present invention.
4 is a diagram illustrating driving timing of the nth stage shown in FIG. 3.
5A to 8B are diagrams illustrating an operation of an n-th stage for each section according to the present invention.
9 is a diagram for explaining the timing of a threshold voltage extraction period according to the present invention.
10 to 12 are diagrams showing driving simulation results of a gate driving circuit according to the present invention.

Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

Switch elements in the gate driving circuit of the present invention may be implemented as transistors having an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. Although the n-type transistor is illustrated in the following embodiments, it should be noted that the present invention is not limited thereto. The transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type MOSFET, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET can be changed according to the applied voltage. In the following embodiments, the invention should not be limited due to the source and drain of the transistor.

1 is a diagram showing a display device according to the present invention.

Referring to FIG. 1, a display device according to the present invention includes a display panel 100, a timing controller 200, a data driving circuit 300, and a gate driving circuit 400.

The active area AA of the display panel 100 includes a plurality of data lines DL disposed in a column direction and a plurality of gate lines GL disposed in a row direction. Pixels P for image display are disposed in the intersection area of the data lines DL and the gate lines GL.

The timing controller 200 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE, and generates a data control signal and a gate control signal based thereon. The data control signal controls the operation timing of the data driving circuit 300, and the gate control signal controls the operation timing of the gate driving circuit 400.

The data driving circuit 300 generates a data voltage based on the data control signal and image data DATA provided from the timing controller 200 and supplies the data voltage to the data line DL.

The gate driving circuit 400 may include a level shifter and a shift register. The level shifter generates a gate clock CLK based on the gate control signal provided from the timing controller 200. The gate clock CLK may include first and second gate clocks CLK1 and CLK2 as shown in FIG. 4. The shift register generates gate signals based on the gate clock CLK output from the level shifter 400 and outputs the gate signals to the gate lines GL. To this end, the shift registers include shift registers that are dependently connected to each other. The shift register may be directly formed on the non-display area NAA of the display panel 100 according to a gate-driver in panel (GIP) method.

2 is a diagram showing a gate driving circuit according to the present invention. In particular, FIG. 2 shows a connection relationship between signals used as a start signal in stages of a gate driving circuit.

Referring to FIG. 2, the gate driving circuit according to the present invention includes a shift register including stages STG1 to STG[n+1] that are dependently connected to each other. The first stage STG1 generates a first gate signal VOUT1 and applies it to the first gate line. The n-th stage STG[n] generates an n-th gate signal VOUT[n] and applies it to the n-th gate line.

The Q node is set in the first stage STG1 in response to the start signal VST, and the Q node is set in the second stage STG2 in response to the first carry signal CR1. Similarly, in the nth stage STG[n], the Q node is set in response to the [n-1]th carry signal CR[n-1]. Setting the Q node means that the Q node is precharged to the turn-on voltage.

3 is a diagram illustrating an nth stage among the stages shown in FIG. 2. 4 is a diagram illustrating driving timing of the nth stage shown in FIG. 3.

3 shows an embodiment in which the clock signal applied to the nth stage is the first gate clock CLK1. The first low-potential driving voltage VGL1 and the second low-potential driving voltage VGL2 may be set to the same voltage level. However, as can be seen in the driving description to be described later, in order to prevent the voltage drop and leakage current of the Q node during the bootstrapping process, the first low potential driving so that the voltage level of "VGL2-VGL1" becomes a negative (-) voltage. The magnitudes of the voltage VGL1 and the second low potential driving voltage VGL2 may be set. For example, the first low-potential driving voltage VGL1 and the second low-potential driving voltage VGL2 are both negative (-) voltages, and the second low-potential driving voltage VGL2 is the first low-potential driving voltage ( It is preferably set to have a voltage level lower than VGL1).

3 and 4, the stage according to the present invention includes a start control unit T1, second to sixth transistors T2 to T6, a compensation control transistor T7, a first compensation transistor T13, and It includes two compensation transistors T12, pull-up units T10 and T8, and pull-down units T11 and T9. The pull-up units T10 and T8 include a first pull-up transistor T10 and a second pull-up transistor T8, and the pull-down units T11 and T9 include a first pull-down transistor T11 and a second pull-down transistor T9. Includes.

The start control unit T1 is applied to the gate electrode to which the n-1th carry signal CR[n-1] is applied, the drain electrode to which the n-1th gate signal VOUT[n-1] is applied, and the Q node It includes a connected source electrode. When the n-1th carry signal CR[n-1] is a turn-on voltage, the start control unit T1 charges the high voltage of the n-1th gate signal VOUT[n-1] to the Q node. do.

The second transistor T2 includes a gate electrode to which an n+2th carry signal CR[n+2] is applied, a drain electrode connected to the Q node, and a source electrode connected to the QC node. The second transistor T2 electrically connects the Q node and the QC node when the n+2th carry signal CR[n+2] is a turn-on voltage.

The third transistor T3 includes a gate electrode connected to the P node, a drain electrode connected to the Q node, and a source electrode connected to the QC node. The third transistor T3 electrically connects the Q node and the QC node when the P node is a turn-on voltage.

The fourth transistor T4 is a gate electrode to which an n-1th carry signal CR[n-1] is applied, a drain electrode to which an n-1th gate signal VOUT[n-1] is applied, and a QC node It includes a source electrode connected to. When the n-1 th carry signal CR[n-1] is a turn-on voltage, the fourth transistor T4 applies the high voltage of the n-1 th gate signal VOUT[n-1] to the QC node. Charge.

The fifth transistor T5 includes a gate electrode connected to the P node, a drain electrode connected to the QC node, and a source electrode connected to the second output terminal Nout2. The fifth transistor T5 electrically connects the QC node and the second output terminal Nout2 when the P node is a turn-on voltage.

The sixth transistor T6 includes a gate electrode to which an n+2th carry signal CR[n+2] is applied, a drain electrode connected to the QC node, and a source electrode connected to the second output terminal Nout2. The sixth transistor T6 electrically connects the QC node and the second output terminal Nout2 when the n+2th carry signal CR[n+2] is a turn-on voltage.

The second capacitor C2 is connected between the QC node and the second output terminal Nout2.

The compensation control transistor T7 includes a gate electrode connected to the QC node, a drain electrode connected to the P node, and a source electrode connected to the output terminal of the n+1th gate signal VOUT[n+1]. The compensation control transistor T7 electrically connects the P node to the output terminal of the n+1th gate signal VOUT[n+1] when the QC node is a turn-on voltage. The output terminal of the n+1th gate signal VOUT[n+1] refers to the first output terminal Nout1 of the n+1th stage STG[n+1].

The first pull-up transistor T10 includes a gate electrode connected to the Q node, a drain electrode connected to the input terminal of the first gate clock CLK1, and a source electrode connected to the first output terminal Nout1. The first pull-up transistor T10 charges the high voltage of the first gate clock CLK1, which is applied while the Q node is precharged, to the first output terminal Nout1. As a result, the first output terminal Nout1 outputs the n-th gate signal VOUT[n] having a high voltage level of the first gate clock CLK1.

The first pull-down transistor T11 includes a gate electrode connected to the P node, a drain electrode connected to the first output terminal Nout1, and a source electrode connected to an input terminal of the first low potential driving voltage VGL1. The first pull-down transistor T11 discharges the first output terminal Nout1 to the first low potential driving voltage VGL1 when the P node is the turn-on voltage.

The second pull-up transistor T8 includes a gate electrode connected to the Q node, a drain electrode connected to the input terminal of the first gate clock CLK1, and a source electrode connected to the second output terminal Nout2. The second pull-up transistor T8 charges the high voltage of the first gate clock CLK1 applied while the Q node is precharged to the second output terminal Nout2. As a result, the second output terminal Nout2 outputs an n-th carry signal CR[n] having a high voltage level of the first gate clock CLK1.

The second pull-down transistor T9 includes a gate electrode connected to the P node, a drain electrode connected to the second output terminal Nout2, and a source electrode connected to the input terminal of the second low potential driving voltage VGL2. When the P node is the turn-on voltage, the second pull-down transistor T9 discharges the second output terminal Nout2 to the second low-potential driving voltage VGL2.

The first compensation transistor T13 includes a gate electrode connected to the P node, a drain electrode connected to the PA node, and a source electrode connected to the input terminal of the first low potential driving voltage VGL1. The second compensation transistor T12 includes a gate electrode to which an n+1th carry signal CR[n+1] is applied, a drain electrode connected to the P node, and a source electrode connected to the PA node. The first capacitor C1 includes a first capacitor C1 connected between the input terminal of the first gate clock CLK1 and the P node. The first compensation transistor T13 is in a diode-connected state in which the gate electrode and the drain electrode are connected to the P node in a period in which the second compensation transistor T12 is turned on.

5A to 8B are diagrams illustrating an operation of an n-th stage for each section according to the present invention. Referring to FIGS. 5A to 8B, the driving of the n-th stage will be described as follows.

5A and 5B, a first timing t1 corresponds to a setting period for charging the Q node and the QC node to a high voltage.

At the first timing t1, the n-1th carry signal CR[n-1] and the n-1th gate signal VOUT[n-1] are applied as high voltages. The start control unit T1 is turned on in response to the n-1th carry signal CR[n-1], and applies a high voltage of the n-1th gate signal VOUT[n-1] to the Q node. do. The fourth transistor T4 is turned on in response to the n-1th carry signal CR[n-1], and applies a high voltage of the n-1th gate signal VOUT[n-1] to the QC node. Approved. That is, at the first timing t1, the Q node and the QC node are precharged to the high voltage.

The compensation control transistor T7 is turned on by the high voltage of the QC node, and applies the voltage of the n+1th gate signal VOUT[n+1] to the P node. At the first timing t1, since the n+1th gate signal VOUT[n+1] is the first low-potential driving voltage VGL1, the P node is discharged to the first low-potential driving voltage VGL1. As a result, the first and second pull-down transistors T10 and T8 maintain a turn-off state.

6A and 6B, the second timing t2 corresponds to a bootstrapping period for outputting a gate signal and a carry signal.

At the second timing t2, the first gate clock CLK1 is applied as a high voltage, and the first pull-up transistor T10 applies the high voltage of the first gate clock CLK1 to the first output terminal Nout1. While the Q node is bootstrapped, the first pull-up transistor T10 outputs the n-th gate signal VOUT[n] through the first output terminal Nout1.

The second pull-up transistor T8 applies the high voltage of the first gate clock CLK1 to the second output terminal Nout2, and the second output terminal Nout2 outputs the n-th carry signal CR[n]. As the voltage of the second output terminal Nout2 increases, the QC node is also bootstrapped through the second capacitor C2. As a result, at the second timing t2, the compensation control transistor T7 maintains the turn-on state, and the P node is the n+1th gate signal VOUT[n+1] which is the first low potential driving voltage VGL1. ]) to maintain the discharged state.

In order to output the n-th gate signal VOUT[n] and the n-th carry signal CR[n] at a high level at the second timing t2, the Q node must stably maintain a high voltage. Accordingly, the start control unit T1 and the second transistor T2 and the third transistor T3 for discharging the Q node to the turn-off voltage must maintain the turn-off state. According to the present invention, it is possible to prevent a Q node voltage drop from occurring through the start control unit T1, the second transistor T2, and the third transistor T3 in the bootstrapping period by the following operation.

At the second timing t2, the gate electrode of the start control unit T1 is the first low-potential driving voltage VGL1, and when the Q node is a high voltage, the n-1th gate signal VOUT[ The voltage of n-1]) becomes the second low-potential driving voltage VGL2. That is, at the second timing t2, Vgs of the start control unit T1 corresponds to “VGL2-VGL1”, and since this is a negative (-) voltage, a voltage drop of the Q node does not occur through the start control unit T1. .

Since the QC node connected to the source electrode of the second transistor T2 and the third transistor T3 is bootstrapped at the second timing t2, the Vgs of the second transistor T2 and the third transistor T3 are The voltage level is much lower than 0V. As a result, the second transistor T2 and the third transistor T3 can stably maintain a turn-off state, and the stage has an n-th gate signal VOUT[n] and an n-th carry signal CR[n]. ) Can be output stably.

7A and 7B, the third timing t3 corresponds to a threshold voltage extraction period for extracting the threshold voltage of the pull-down transistor.

At the third timing t3, the first gate clock CLK1 is inverted from the high voltage to the first low potential driving voltage VGL1.

At the third timing t3, the Q node is held at a high level voltage, and the voltage of the first output terminal Nout1 is connected to the input terminal of the first low-potential driving voltage VGL1 through the first pull-up transistor T10 and discharged. do. Similarly, the voltage of the second output terminal is discharged by being connected to the input terminal of the first low-potential driving voltage VGL1 through the second pull-up transistor T8. That is, the present invention uses the pull-up units T8 and T10 instead of the pull-down units T9 and T11 after the bootstrapping period of the Q node is ended to provide the n-th gate signal VOUT[n] and the n-th carry. The voltage level of the signal CR[n] is discharged.

At the third timing t3, the n-th carry signal CR[n] is inverted to the first low-potential driving voltage VGL1, and during the holding period t3_h, the QC node voltage is held as a turn-on voltage. The control transistor T7 is in a turned-on state. At the third timing t3, the n+1th gate signal VOUT[n+1] becomes a high voltage, and the compensation control transistor T7 is high at the n+1th gate signal VOUT[n+1]. Charge the voltage to the P node. As the P node is charged to the high voltage, the fifth transistor T5 is turned on. The fifth transistor T5 connects the QC node to the second output terminal Nout2, and as a result, the QC node is discharged to the first low-potential driving voltage VGL1. That is, after the holding period t3_h, the QC node is discharged to the first low potential driving voltage VGL1.

As the P node is charged to the high voltage, the first compensation transistor T13 is turned on. At the third timing t3, the n+1th carry signal CR[n+1] becomes a high voltage, and accordingly, the second compensation transistor T12 is turned on. As a result, the P node is connected to the input terminal of the first low potential driving voltage VGL1 via the second compensation transistor T12 and the first compensation transistor T13. That is, the voltage of the P node temporarily charged to the high voltage during the holding period t3_h is discharged to the first low potential driving voltage VGL1 after the holding period t3_h. At this time, the gate electrode and the drain electrode of the first compensation transistor T13 are connected to the P node to become a diode connection. As a result, the P node is discharged from the first low-potential driving voltage VGL1 to a voltage reflecting the threshold voltage Vth of the first compensation transistor T13. That is, at the third timing t3, the voltage of the P node is discharged to "VGL1+Vth".

As described above, in the present invention, the threshold voltage of the first compensation transistor T13 is stored in the first capacitor C1 during the third timing t3 corresponding to the 1H period in which the bootstrapping in which the gate signal is output is finished. Since the gate electrodes of the second pull-down transistor T9 and the first pull-down transistor T11 are connected to the P node, electrical stress applied to the gate electrodes of the second pull-down transistor T9 and the first pull-down transistor T11? z may be regarded as the same as the electrical stress applied to the gate electrode of the first compensation transistor. Accordingly, the threshold voltage Vth stored in the first capacitor C1 at the third timing t3 may be regarded as the threshold voltage Vth of the second pull-down transistor T9 and the first pull-down transistor T11.

8A and 8B, the fourth timing t4 corresponds to the threshold voltage compensation and the Q node discharge period.

At the fourth timing t4, the first gate clock CLK1 becomes a high voltage. At the fourth timing t4, the first capacitor C1 is charged with the high voltage of the first gate clock CLK1, and the voltage of the P node also rises due to a coupling phenomenon. At this time, since the first capacitor C1 is in a state in which the threshold voltages of the second pull-down transistor T9 and the first pull-down transistor T11 are stored, the voltage of the P node is at the high voltage of the first gate clock CLK1. The threshold voltages of the second pull-down transistor T9 and the first pull-down transistor T11 are charged to the summed level.

At the fourth timing t4, since the n+2th carry signal CR[n+2] and the voltage of the P node are turn-on voltages, the second transistor T2, the fifth transistor T5, and the sixth The transistor T6 and the first and second pull-down transistors T11 and T9 are turned on. As a result, the Q node is electrically connected to the second output terminal Nout2 through the QC node. At the fourth timing t4, since the second output terminal Nout2 is the second low-potential driving voltage VGL2, the Q node is discharged to the second low-potential driving voltage VGL2.

In addition, the first pull-down transistor T11 discharges the first output terminal Nout1 to a first low-potential driving voltage VGL1, and the second pull-down transistor T9 drives the second output terminal Nout2 to a second low potential. Discharge with voltage VGL2.

As described above, according to the present invention, the P node may be charged with the threshold voltage of the pull-down transistors T11 and T9 reflected. Accordingly, even if the magnitude of the threshold voltage of the pull-down transistors T11 and T9 changes, the magnitude of Vgs of the pull-down transistors T11 and T9 can be maintained at a constant level, thereby improving driving reliability, and rising/ It is possible to keep the falling/peak voltage characteristics constant.

9 is a diagram illustrating timing for compensating for a threshold voltage.

9, the operation of extracting the threshold voltage of the pull-down transistor of the shift register according to the present invention is performed after the output period of the gate signal. For example, the first stage extracts the threshold voltages of the pull-down transistors T9 and T11 within 1H period after the first gate signal VOUT1 is output. In the next frame, threshold voltage compensation is performed in a period in which the gate clock CLK applied to the stage is a high voltage within a period before the first gate signal VOUT1 is output.

10 to 12 are diagrams showing a driving simulation of the shift register of the present invention. 10 to 12 show simulation results in which the first low-potential driving voltage VGL1 is -5V.

10 shows a simulation result in which a change in the threshold voltage of the pull-down transistors T9 and T11 is relatively small. In FIG. 10, the voltage of the P node before the gate signal is output to the high level indicates that the voltage of the P node is extracted as -5V equal to the first low-potential driving voltage VGL1, and after the gate signal is output to the high level, The voltage was extracted as -3.9V reflecting the threshold voltage of "+1.1V".

FIG. 11 shows a simulation result in which the threshold voltage change amount of the pull-down transistors T9 and T11 is "+8V" when the gate driving circuit is implemented with oxide transistors in the multiplication mode. Further, FIG. 12 shows a simulation result in which the threshold voltage change amount of the pull-down transistors T9 and T11 is "-7V" when the gate driving circuit is implemented with depletion mode oxide transistors.

As shown in FIGS. 11 and 12, the gate driving circuit according to the present invention can stabilize the output of the gate signal by compensating for a change in the threshold voltage of the pull-down transistors T9 and T11 regardless of the type of transistors. In addition, the present invention can compensate for the amount of change in the threshold voltage of the pull-down transistors T9 and T11 regardless of whether the electrical stress applied to the pull-down transistors T9 and T11 is negative or positive.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100: display panel 200: timing controller
300: data driving circuit 400: gate driving circuit
STG: Stage

Claims (14)

In order to supply a gate signal to each of the gate lines connected to the pixels, in the gate driving circuit including a plurality of stages connected to each other dependently,
Among the stages, the n-th stage
A pull-up unit precharged by a Q node voltage and outputting an n-th gate signal and an n-th carry signal synchronized with a timing of a gate clock;
Controlled by the voltage of the P node maintaining the turn-off voltage in the period where the Q node is a turn-on voltage, and discharging the voltage of the Q node to a turn-off voltage when the P node is a turn-on voltage. Pull down;
A first compensation transistor having a diode connection structure by electrically connecting a gate electrode and a drain electrode to the P node during a threshold voltage extraction period; And
A gate driving circuit comprising a first capacitor connected between the P node and a gate clock input terminal providing the gate clock. The method of claim 1,
The first compensation transistor is
During the threshold voltage extraction period, a gate driving circuit for discharging the P node to a low potential driving voltage. The method of claim 2,
The first compensation transistor is
A gate electrode connected to the P node, a drain electrode connected to the PA node, and a source electrode connected to an input terminal of a first low potential driving voltage,
The nth stage
A gate driving circuit further comprising a second compensation transistor connecting the PA node to the P node during the threshold voltage extraction period. The method of claim 3,
The second compensation transistor is
A gate driving circuit electrically connecting the P node and the PA node in response to an n+1th carry signal output from the n+1th stage. The method of claim 2,
The first capacitor is
A gate driving circuit for storing a threshold voltage of the first compensation transistor during the threshold voltage extraction period. The method of claim 1,
In the initial period of the threshold voltage extraction period, the gate driving circuit further comprising a compensation control transistor for charging the P node with a turn-on voltage. The method of claim 6,
The compensation control transistor is
A gate driving circuit for discharging the P node to a low potential voltage during the threshold voltage extraction period. A display panel including pixels disposed in a region where a gate line and a data line cross each other, and a shift register for outputting a gate signal provided to the gate line; And
Including a data driving circuit for providing a data voltage to the data line,
The shift register includes a plurality of stages dependently connected to each other,
Among the stages, the n-th stage
A pull-up unit precharged by a Q node voltage and outputting an n-th gate signal and an n-th carry signal synchronized with a timing of a gate clock;
A P node maintaining a turn-off voltage in a period in which the Q node is a turn-on voltage;
A pull-down unit discharging the voltage of the Q node to a turn-off voltage when the P node is a turn-on voltage;
A first compensation transistor having a diode connection structure by electrically connecting a gate electrode and a drain electrode to the P node during a threshold voltage extraction period; And
And a first capacitor connected between the P node and a gate clock input terminal providing the gate clock. The method of claim 8,
The first compensation transistor is
During the threshold voltage extraction period, the display device discharges the P node to a low potential driving voltage. The method of claim 9,
The first compensation transistor is
A gate electrode connected to the P node, a drain electrode connected to the PA node, and a source electrode connected to an input terminal of a first low potential driving voltage,
The nth stage
The display device further comprising: a second compensation transistor connecting the PA node to the P node during the threshold voltage extraction period. The method of claim 10,
The second compensation transistor is
The display device electrically connects the P node and the PA node in response to an n+1th carry signal output from the n+1th stage. The method of claim 9,
The first capacitor is
A display device that stores a threshold voltage of the first compensation transistor during the threshold voltage extraction period. The method of claim 8,
And a compensation control transistor for charging the P node with a turn-on voltage in an initial period of the threshold voltage extraction period. The method of claim 13,
The compensation control transistor is
The display device discharging the P node to a low potential voltage during the threshold voltage extraction period.

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