KR102627933B1 - Scan driver circuit for improving degradation of TFT - Google Patents

Abstract

According to the first feature of the present invention, a scan driver circuit including a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage is bootstrapping. A first node to which the technique is applied; An output unit including two output nodes that output a scan signal and a carry signal, respectively, and connected to the first node; and an inverter structure including a second node discharging the first node, wherein the scan driver circuit applies a first reference voltage that is a DC voltage and a second reference voltage that is a lower DC voltage than the first reference voltage. It is used as a control signal for the device, and the first node and the second node are connected through a boosted down structure including a capacitor. Accordingly, based on two types of reference voltages and a boosted down structure, multi-output and device degradation are prevented, and depletion mode operation is possible.

Description

Scan driver circuit for improving degradation of TFT}

The present invention relates to a scan driver circuit for improving the TFT deterioration phenomenon, and more specifically, to a scan driver circuit for improving the TFT deterioration phenomenon that controls circuit malfunction based on two types of reference voltages and a boosted down structure. It's about the driver circuit.

The display device includes a data driver circuit that supplies data signals to the data lines of the pixel array, a scan driver circuit that sequentially supplies scan pulses synchronized with the data signals to the scan lines of the pixel array, It includes a timing controller that controls the data driver circuit and the scan driver circuit. Each of the pixels may include a thin film transistor (TFT) that supplies the voltage of the data line to the pixel electrode in response to the scan pulse. The scan pulse swings between gate high voltage (VGH) and gate low voltage (VGL). The gate high voltage (VGH) is set to a voltage higher than the threshold voltage (VTH) of the pixel TFT, and the gate low voltage (VGH) is set to a voltage lower than the threshold voltage (VTH) of the pixel TFT.

Meanwhile, it has high mobility and low production costs, can be applied to large-area display panels due to high uniformity between elements compared to LTPS TFTs, and has low off-current characteristics, enabling low power consumption. Recently, research on oxide TFTs is actively underway.

The existing scan driver circuit used to drive the display applies a bootstrapping technique to the pull-up transistor to stably supply voltage to each pixel, raising the gate voltage of the TFT to create a structure that can deliver a stable voltage to the output terminal. It has a basic structure. Here, the node to which the bootstrapping technique is applied is called the Q node.

FIG. 1A is a diagram showing a prior art scan driver circuit, and FIG. 1B is a diagram showing a timing diagram for the circuit.

Generally, the Q node in a scan driver circuit does not operate except during the precharge and bootstrapping sections for stable pixel driving. When the Q node operates in sections other than the output section, the clock voltage can be applied to the VOUT node through the pull-up transistor, so in the conventional scan driver circuit, a QB node (pull-down unit) is designed to discharge the Q node.

The QB node is always on to discharge the Q node except during pixel operation time, so it can be considered to be driven in a DC type. Due to this DC type drive, continuous bias stress is applied to the pull-down unit, causing deterioration in the TFT. Deterioration of the TFT and changes in electrical characteristics (shift in threshold voltage, decrease in on-current, etc.) directly affect the stability of the circuit.

Meanwhile, oxide TFT has high mobility, low production cost, and higher uniformity between elements compared to LTPS (Low-Temperature Polycrystalline Silicon) TFT, so it can be applied to large-area display panels and has low off-current characteristics. It is possible to implement low power consumption.

This oxide TFT configures the channel layer by adjusting the ratio of In-Ga-Zn-O (IGZO), and the ratio of indium (In) is increased to increase electron mobility. However, as the ratio of indium increases, oxygen vacancy increases and the threshold voltage of the oxide TFT has a negative value, so that the transistor channel is formed in a normally on state even without applying a bias to the gate voltage, which is called depletion mode operation. do.

Referring again to FIG. 1A, in the past, stable output was achieved by applying a bootstrapping technique using a clock signal to the Q node, and then multiple outputs were prevented by discharging the output node to 100% duty through a pull-down unit.

However, the pull-down unit is driven in a DC type to discharge the Q node and VOUT node and is always turned on, thereby continuously applying bias stress to the pull-down unit and causing deterioration of the TFT.

In addition, in the conventional scan driver circuit as shown in Figure 1a, the depletion mode operation of the oxide TFT is not considered, so the TFT with a negative threshold voltage has the disadvantage of generating leakage current and increasing power consumption, and the parasitic capacitance of the pull-up transistor and the clock A high ripple voltage is momentarily generated at the Q node by the signal, causing multiple outputs to be generated at the VOUT output node.

Additionally, during the bootstrapping period, a fairly high drain-source voltage is applied to T1, T2, and T3 connected to the Q node, resulting in device deterioration.

Accordingly, a scan driver circuit capable of responding to depletion mode operation is needed to solve the problem of increased power consumption due to leakage current due to the normally on operation of the TFT.

The present invention is intended to solve the problems of the prior art as described above. The present invention considers depletion mode operation and scans to improve the TFT deterioration phenomenon by controlling circuit malfunction based on two types of reference voltages and boosted down structure. It provides a driver circuit.

According to the first feature of the present invention, a scan driver circuit including a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage is bootstrapping. A first node to which the technique is applied; An output unit including two output nodes that output a scan signal and a carry signal, respectively, and connected to the first node; and an inverter structure including a second node discharging the first node, wherein the scan driver circuit applies a first reference voltage that is a DC voltage and a second reference voltage that is a lower DC voltage than the first reference voltage. It is used as a control signal for the device, and the first node and the second node are connected through a boosted down structure including a capacitor.

According to the second feature of the present invention, a control method of a scan driver circuit including a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage, includes the scan driver circuit, The driver circuit includes a first node to which a bootstrapping technique is applied; An output unit including two output nodes that output a scan signal and a carry signal, respectively, and connected to the first node; and an inverter structure including a second node discharging the first node, wherein the scan driver circuit supplies a first reference voltage that is a DC voltage and a second reference voltage that is a lower DC voltage than the first reference voltage. It is used as a control signal, and the first node and the second node are connected through a boosted down structure including a capacitor, and the control method includes precharging the first node. step; The first node is in a floating state, bootstrapping occurs through a capacitor and a clock signal connecting the first node and the scan signal output node, and a gate high voltage is output from the two output nodes of the output unit. step; discharging the scan signal output node to the first reference voltage and discharging the carry signal output node to the second reference voltage; and discharging the second node to the second reference voltage.

A display device based on a thin film transistor according to a third aspect of the present invention includes a display panel including a plurality of pixels; a data driver circuit that supplies data signals to data lines among the array of pixels; a scan driver circuit that sequentially supplies scan pulses synchronized with the data signal to scan lines in the array of pixels; and a timing controller that controls the data driver circuit and the scan driver circuit, wherein the scan driver circuit sequentially generates an output signal by transferring the output signal of the previous stage to the next stage according to the first feature. It is characterized as a scan driver circuit including a plurality of stages.

A scan driver circuit for improving TFT deterioration phenomenon according to an embodiment of the present invention provides the following effects.

In a structure that used one VSS (reference voltage), VSS2, a DC voltage of a lower level than VSS, is added and used as a control signal for the depletion mode operation TFT, preventing the normally on state and realizing low power consumption. .

When the VSS2 voltage is applied to the A node through the boosted down structure, the Q node voltage is induced to VSS2 through the coupling effect of the capacitor in the structure, causing Q node ripple due to the high parasitic capacitor of the pull-up transistor and clock signals. Voltage is prevented and multi-output does not occur.

The Q node and output nodes are each discharged for a clock duty ratio of 50%, preventing deterioration of the pull-down unit, and the use of a single pull-down TFT simplifies the scan driver circuit, making it possible to implement a bezel-less display. .

Therefore, the yield of the product can be improved by preventing multi-output, preventing device deterioration, and responding to depletion mode operation based on two types of reference voltages and a boosted down structure.

1A is a diagram showing a scan driver circuit of the prior art.
FIG. 1B is a diagram illustrating a timing diagram of a prior art scan driver circuit.
FIG. 2A is a diagram illustrating a scan driver circuit according to one disclosed embodiment.
FIG. 2B is a diagram illustrating a timing diagram of a scan driver circuit according to one disclosed embodiment.
3A to 3D are circuit diagrams and timing diagrams showing the operation of a scan driver circuit according to an embodiment of the disclosure.
4A to 4C are graphs showing scan driver circuit simulation waveforms when the threshold voltages of all TFTs used in the scan driver circuit are +2.0V, +10.5V, and -3.5V, respectively, according to an embodiment of the disclosure.
FIG. 5A is a diagram illustrating a scan driver circuit according to another disclosed embodiment.
FIG. 5B is a diagram illustrating a timing diagram of a scan driver circuit according to another disclosed embodiment.
6A to 6D are circuit diagrams and timing diagrams showing the operation of a scan driver circuit according to another disclosed embodiment.
FIGS. 7A and 7B are graphs showing scan driver circuit simulation waveforms when the threshold voltages of all TFTs used in the scan driver circuit are +2.0V and -2.0V, respectively, according to another disclosed embodiment.
FIG. 7C is a graph showing a B-node voltage simulation waveform for checking drain-source voltage stress depending on the presence or absence of an anti-deterioration TFT in a scan driver circuit according to another disclosed embodiment.

Hereinafter, the present invention will be described in detail with reference to examples and drawings. However, the following description is not intended to limit the present invention to specific embodiments, and in describing the present invention, if it is determined that a detailed description of related known technology may obscure the gist of the present invention, the detailed description will be omitted. .

FIG. 2A is a diagram illustrating a scan driver circuit according to an embodiment of the disclosure, and FIG. 2B is a diagram illustrating a timing diagram of the scan driver circuit.

Referring to FIG. 2A, the scan driver circuit of one embodiment may be composed of 9 TFTs and 2 capacitors. A scan signal input to each pixel is output from the VOUT node, and a carry signal used as an input signal to each scan driver stage is output from the Vc node. A total of 4 phases (CLK, CLKb, CLKL, CLKLb) can be used as a clock signal.

The scan driver circuit of the disclosed embodiment uses not only the reference voltage VSS1 but also VSS2, a DC voltage of a lower level than VSS1, as a control signal for the depletion type operation TFT. Through this, the normally on state of the TFT can be prevented.

A bootstrapping technique is applied to the Q node, and the output unit 10 includes two output nodes that output a scan signal (VOUT) and a carry signal (Vc), respectively, and is connected to the Q node.

A single TFT element (T6, T7) is connected to each of the output nodes of the output unit 10 and functions as a pull-down unit that discharges the voltage of the output nodes.

The inverter structure 20 includes an A node, and discharge of the Q node occurs through the A node. More specifically, the Q node and the A node are connected through a boosted down 30 structure including a capacitor C2, and when the VSS2 voltage is applied to the A node, the coupling effect of the C2 capacitor The Q node voltage goes down to VSS2. Accordingly, the high parasitic capacitor of the pull-up transistors (T2, T3) of the output unit 10 and the Q node ripple voltage caused by the clock signals (CLK, CLKL) are prevented, thereby solving the multi-output phenomenon.

The output nodes (i.e., scan and carry output nodes) of the Q node and output unit 10 are discharged for a clock duty ratio of 50% to prevent deterioration of the pull-down units T6 and T7. In this case, the discharge of the Q node occurs through the A node. Therefore, it is possible to secure the reliability of the Q node and output nodes by preventing deterioration of each pull-down unit.

Referring to FIG. 2A, in the scan driver circuit of one embodiment, the VSS2 reference voltage to the A node may be applied through a series two transistor (STT) structure. In addition, the drain-source voltage of T5a and T5b is stabilized through the STT structure of T5a and T5b.

With reference to FIG. 2A, the functions of each TFT element, main node, and input/output signal of the scan driver circuit according to the disclosed embodiment are summarized in Tables 1 and 2 below.

T1: Q node precharging element
T2: VOUT[n] output device
T3: Vc[n] output device
T4: A node VGH applying element
T5a, T5b: A node VGL2 enabling and V _DS stabilizing elements
T6: VOUT[n] pull-down element
T7: Vc[n] pull-down element
T8: Q node pulldown element

Q[n]: Node for VOUT[n] / Vc[n] output
A[n]: (i) Discharge VOUT[n], Vc[n] through T6, T7 for 50% clock duty ratio
(ii) Q node boosting down
VOUT[n]: Scan signal output
Vc[n]: Carry signal output
VOUT[n-1]: Q node precharging
Vc[n+1]: Q node reset

In the timing diagram of FIG. 2B, the gate low voltages VGL1 and VGL2 correspond to the reference voltages VSS1 and VSS2, respectively, where VGL2 is a DC voltage at a lower level than VGL1. This is the same in all timing diagrams below.

3A to 3D are circuit diagrams and timing diagrams showing the operation of a scan driver circuit according to an embodiment of the disclosure.

The operation of the scan driver circuit of one embodiment will be described in detail below with reference to FIGS. 3A to 3D.

A-(1) Precharging section

Referring to Figure 3a, VOUT[n-1] becomes VGH (gate high voltage), and the Q node voltage is charged to VGH-V _{TH_T1} through the T1 transistor. Reference voltages VSS1 and VSS2 are applied to the VOUT[n] and Vc[n] output nodes through T2 and T3 transistors and CLK and CLKL clock signals, respectively.

A-(2) Bootstrapping and VOUT[n] output section

Referring to FIG. 3b, the T1 transistor is turned off, the Q node is in a floating state, and bootstrapping occurs through the CLK clock signal and the C1 capacitor. The Q node voltage increases to [VGH-V _{TH_T1} ]+[VGH-VSS1], and VGH voltage is output to the VOUT[n] and Vc[n] output nodes through T2 and T3 pull-up transistors. At this time, since Vc[n+1] has the VSS2 voltage, V _GS of the T8 transistor has a sufficiently large negative voltage to prevent changes in the Q node voltage.

A-(3) Reset and VOUT[n] discharge section

Referring to Figure 3c, Vc[n+1] becomes VGH and the T8 transistor is turned on. The CLKLb clock signal becomes VGH and the A node is charged to [VGH-V _{TH_T4} ]. VOUT[n] and Vc[n] are discharged to reference voltages VSS1 and VSS2 through transistors T6 and T7, respectively.

A-(4) Discharge holding section

Referring to Figure 3d, as the CLKL clock signal becomes VGH, transistors T5a and T5b of the STT structure are turned on and the A node is discharged to the VSS2 voltage. Boosting down occurs at the Q node, which is in a floating state, and is discharged to a voltage lower than VSS1. At this time, the Q node ripple voltage caused by the CLK clock signal and the parasitic capacitor of the T2 transistor is reduced, preventing multi-output of the VOUT[n] output node.

FIGS. 4A to 4C are graphs showing scan driver circuit simulation waveforms when the threshold voltages of all TFTs used in the scan driver circuit are +2.0V, +10.5V, and -3.5V, respectively, according to an embodiment of the disclosure.

Simulation results of the scan driver circuit of one embodiment will be described below with reference to FIGS. 4A to 4C.

SmartSpice simulation was conducted based on oxide TFT, and the threshold voltage (VTH) of the TFT model used was 2V and the channel length was 5μm. CLK(L) to CLKb(L) were used as clock signals, Vc[n-1] and VOUT[n-1] input signals swing from -5V to 28V, and VGH, VSS1, and VSS2 were 28V and -, respectively. It has a voltage of 5V, -13V.

Referring to Figure 4a, it can be seen that the precharge and bootstrapping voltages at the Q node are 26V and 51V, respectively, and the VOUT output is maintained at +28V without voltage loss.

Referring to FIG. 4b, it can be seen that the VOUT output is maintained at a voltage of +28V without voltage loss, despite a threshold voltage shift of +10.5V.

Referring to Figure 4c, it can be seen that despite the threshold voltage shift by -3.5V, the VOUT output outputs a voltage of +28V without voltage loss.

FIG. 5A is a diagram illustrating a scan driver circuit according to another disclosed embodiment, and FIG. 5B is a diagram illustrating a timing diagram of the scan driver circuit.

Referring to FIG. 5A, a scan driver circuit in another embodiment may be composed of 10 TFTs and 2 capacitors. A scan signal input to each pixel is output from the VOUT node, and a carry signal used as an input signal to each scan driver stage is output from the Vc node. A total of 4 phases (CLK, CLKb, CLKL, CLKLb) can be used as a clock signal.

The scan driver circuit of the disclosed embodiment uses not only the reference voltage VSS1 but also VSS2, a DC voltage of a lower level than VSS1, as a control signal for the depletion type operation TFT. Through this, the normally on state of the TFT can be prevented.

A bootstrapping technique is applied to the Q node, and the output unit 10 includes two output nodes that output a scan signal (VOUT) and a carry signal (Vc), respectively, and is connected to the Q node.

A single TFT element (T6, T7) is connected to each of the output nodes of the output unit 10 and functions as a pull-down unit that discharges the voltage of the output nodes.

The inverter structure 20 includes an A node, and discharge of the Q node occurs through the A node. More specifically, the Q node and the A node are connected through a boosted down 30 structure including a capacitor C2, and when the VSS2 voltage is applied to the A node, the coupling effect of the C2 capacitor The Q node voltage goes down to VSS2. Accordingly, the high parasitic capacitor of the pull-up transistors (T2, T3) of the output unit 10 and the Q node ripple voltage caused by the clock signals (CLK, CLKL) are prevented, thereby solving the multi-output phenomenon.

The output nodes (i.e., scan and carry output nodes) of the Q node and output unit 10 are discharged for a clock duty ratio of 50% to prevent deterioration of the pull-down units T6 and T7. In this case, the discharge of the Q node occurs through the A node. Therefore, it is possible to secure the reliability of the Q node and output nodes by preventing deterioration of each pull-down unit.

Referring to FIG. 5A, in the scan driver circuit of another embodiment, the Q node and the A node are connected through the B node, the Q node and the B node are connected through the anti-deterioration TFT (T10) 50, and the B node And the A node may be connected in a boosted down (30) structure including a capacitor (C2). Through this, deterioration of the TFT is prevented by preventing a high V _DS voltage from being applied to the T1 and T5 transistors during the bootstrapping section.

With reference to FIG. 5A, the functions of each TFT element, main node, and input/output signal of the scan driver circuit according to another disclosed embodiment are summarized in Table 3 and Table 4 below.

T1: Q node precharging element
T2: VOUT[n] output device
T3: Vc[n] output device
T4: A node VGH applying element
T5: B-node pull-down element
T6: VOUT[n] pull-down element
T7: Vc[n] pull-down element
T8: A node reset element
T9: A-node pull-down element
T10: V _DS lowering element of T1, T5

Q[n]: Node for VOUT[n] / Vc[n] output
A[n]: (i) Discharge VOUT[n], Vc[n] through T6, T7 for 50% clock duty ratio
(ii) Q node boosting down
VOUT[n]: Scan signal output
Vc[n]: Carry signal output
VOUT[n-1]: Q node precharging
Vc[n+1]: A node reset

6A to 6D are circuit diagrams and timing diagrams showing the operation of a scan driver circuit according to another disclosed embodiment.

The operation of the scan driver circuit of another embodiment will be described in detail below with reference to FIGS. 6A to 6D.

B-(1) Precharging section

Referring to Figure 6a, as the CLKLb clock signal becomes VGH (gate high voltage), the T1 transistor operates, and VOUT[n-1] pre-charges the Q node voltage to VGH-V _{TH_T1} . Reference voltages VSS1 and VSS2 are applied to the VOUT[n] and Vc[n] output nodes through T2 and T3 transistors and CLK and CLKL clock signals, respectively.

B-(2) Bootstrapping and VOUT[n] output section

Referring to FIG. 6b, the T1 transistor is turned off, the Q node is in a floating state, and bootstrapping occurs through the CLK clock signal and the C1 capacitor. The Q node voltage increases to [VGH-V _{TH_T1} ]+[VGH-VSS1], and VGH voltage is output to the VOUT[n] and Vc[n] output nodes through T2 and T3 pull-up transistors. At this time, since Vc[n+1] has the VSS2 voltage, V _GS of the T8 transistor has a sufficiently large negative voltage to prevent changes in the Q node voltage. In addition, the T10 transistor is turned off, and voltage is not transmitted to the drain nodes of the T1 and T5 transistors, thereby reducing V _DS applied to the T1 and T5 transistors, thereby ensuring the stability of the TFT.

B-(3) Reset and VOUT[n] discharge section

Referring to Figure 6c, the CLKLb clock signal becomes the VGH voltage and the T5 transistor is turned on, so the voltage is charged to the A node through the T4 transistor. Accordingly, the T10 transistor is turned on and the Q node voltage is discharged to VSS1 through the T10 and T5 transistors. The VOUT[n] and Vc[n] output node voltages discharge through T6 and T7 to VSS1 and VSS2, respectively. At this time, the A node has the VGH voltage and stores the VGH-VSS1 voltage in the C2 capacitor.

B-(4) Discharge holding section

Referring to Figure 6d, as the CLKL and CLKLb clock signals become VGH and VSS2 voltage states, respectively, the T9 transistor is turned on, and the A node is discharged to the VSS2 voltage through the T9 transistor. Boosting down occurs at the Q node, which is in a floating state, and is discharged to a voltage lower than VSS1. Negative V _GS turns off the T2 transistor and prevents output ripple voltage caused by the CLK clock signal and parasitic capacitance. Additionally, during this period, the T6 transistor is turned off, but the VOUT output node voltage becomes VSS2 through the T1 and T5 transistors of the next stage. The T1 and T5 transistors of the next stage are turned on by the CLKL clock signal, and the VOUT output node can be discharged by the T1 and T5 transistors of the next stage. As a result, the invented circuit exhibits a stable off-stage output using one pull-down TFT with a duty ratio of 50%.

FIGS. 7A and 7B are graphs showing scan driver circuit simulation waveforms when the threshold voltages of all TFTs used in the scan driver circuit are +2.0V and -2.0V, respectively, according to another disclosed embodiment, and FIG. 7C is a scan This is a graph showing the B-node voltage simulation waveform to check the drain-source voltage stress depending on the presence or absence of anti-deterioration TFT in the driver circuit.

Simulation results of a scan driver circuit of another embodiment will be described below with reference to FIGS. 7A to 7C.

SmartSpice simulation was conducted based on oxide TFT, and the threshold voltage (VTH) of the TFT model used was 2V and the channel length was 5μm. CLK(L) to CLKb(L) were used as clock signals, Vc[n-1] and VOUT[n-1] input signals swing from -5V to 28V, and VGH, VSS1, and VSS2 were 28V and -, respectively. It has a voltage of 5V, -13V.

Referring to Figure 7a, it can be seen that the precharge and bootstrapping voltages at the Q node are 26V and 51V, respectively, and the VOUT output is maintained at +28V without voltage loss.

Referring to Figure 7b, it can be seen that despite the threshold voltage shift by -2.0V, the VOUT output outputs a voltage of +28V without voltage loss.

Referring to FIG. 7C, in the case where the anti-deterioration TFT (T10) 50 is not present, a large voltage of 44.3 V is applied to the drains of the T1 and T5 transistors in the bootstrapping section, compared to the anti-deterioration TFT (T10) (50). In the case where 50) is present, it can be confirmed that a relatively low voltage of 27.3V is applied. Therefore, it can be seen that there is an effect of relieving V _DS stress applied to the T1 and T5 transistors.

As such, the scan driver circuit according to the disclosed embodiment can prevent multi-output, prevent device deterioration, and respond to depletion mode operation based on two types of reference voltages and a boosted down structure. In addition, the use of a single pull-down TFT when discharging major nodes such as the Q node and output nodes provides simplification of the scan driver circuit.

Meanwhile, a display device that controls pixels based on a TFT includes a display panel including a plurality of pixels, a data driver circuit that supplies data signals to data lines of a pixel array, and a data driver circuit that supplies data signals to the data lines. It may be configured to include a scan driver circuit that sequentially supplies scan pulses to the scan lines of the pixel array, and a timing controller that controls the data driver circuit and the scan driver circuit, and the scan driver circuit used here is as described above. It may be a scan driver circuit of the same disclosed embodiments.

Since various modifications may be made to the configurations and methods described and illustrated herein without departing from the scope of the present invention, all matters contained in the foregoing detailed description or shown in the accompanying drawings are exemplary and are not intended to limit the present invention. It's not. Accordingly, the scope of the present invention should not be limited by the above-described exemplary embodiments, but should be determined only by the following claims and their equivalents.

10: output unit 20: inverter structural unit
30: Boosted down structure 40: STT structure
50: anti-deterioration element

Claims (15)

In a scan driver circuit including a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage,
A first node to which a bootstrapping technique is applied;
An output unit including two output nodes that output a scan signal and a carry signal, respectively, and connected to the first node; and
an inverter structure including a second node discharging the first node;
Including,
The scan driver circuit uses a first reference voltage that is a DC voltage and a second reference voltage that is a lower DC voltage than the first reference voltage as a control signal for the device,
The first node and the second node are connected through a boosted down structure including a capacitor,
The first node and the second node are connected through a third node. The first node and the third node are connected through a thin film transistor, and the third node and the second node include a capacitor. A scan driver circuit connected in a boosted down structure. According to paragraph 1,
A scan driver circuit, wherein when the second reference voltage is applied to the second node, the voltage of the first node goes down to the second reference voltage due to the boosted down structure. According to paragraph 1,
The output unit further includes two single thin film transistors,
A scan driver circuit, wherein the two single thin film transistors are connected to each of the output nodes to discharge the output nodes, respectively. According to paragraph 3,
A scan driver circuit, wherein the first node and the two output nodes are each discharged for a duty ratio of 50%. According to paragraph 4,
A scan driver circuit, wherein discharge of the first node occurs through the second node. According to paragraph 1,
A scan driver circuit, wherein the application of the second reference voltage to the second node is performed through a series two transistor (STT) structure. delete In the control method of a scan driver circuit including a plurality of stages that sequentially generate output signals by passing the output signal of the previous stage to the next stage,
The scan driver circuit is,
A first node to which a bootstrapping technique is applied; An output unit including two output nodes that output a scan signal and a carry signal, respectively, and connected to the first node; and an inverter structure including a second node discharging the first node,
The scan driver circuit uses a first reference voltage that is a DC voltage and a second reference voltage that is a lower DC voltage than the first reference voltage as a control signal for the device, and the first node and the second node include a capacitor. connected through a boosted down structure,
The first node and the second node are connected through a third node, and the first node and the third node are connected through a thin film transistor, and the third node and the second node include a capacitor. It is connected with a boosted down structure that
The control method is,
precharging the first node;
The first node is in a floating state, bootstrapping occurs through a capacitor and a clock signal connecting the first node and the scan signal output node, and a gate high voltage is output from the two output nodes of the output unit. step;
discharging the scan signal output node to the first reference voltage and discharging the carry signal output node to the second reference voltage; and
discharging the second node to the second reference voltage;
A control method of a scan driver circuit including. According to clause 8,
The step of discharging the second node to the second reference voltage further includes the step of inducing the voltage of the first node to the second reference voltage due to the boosted down structure. control method. According to clause 8,
The output unit further includes two single thin film transistors,
The control method of a scan driver circuit, wherein the two single thin film transistors are connected to each of the output nodes to discharge the output nodes, respectively. According to clause 10,
The first node and the two output nodes are each discharged for a duty ratio of 50%. According to clause 11,
A method of controlling a scan driver circuit, characterized in that discharge of the first node is performed through the second node. According to clause 8,
A method of controlling a scan driver circuit, wherein the application of the second reference voltage to the second node is performed through a series two transistor (STT) structure. delete In a thin film transistor-based display device,
A display panel including a plurality of pixels;
a data driver circuit that supplies data signals to data lines among the array of pixels;
a scan driver circuit that sequentially supplies scan pulses synchronized with the data signal to scan lines in the array of pixels; and
A timing controller that controls the data driver circuit and the scan driver circuit,
A display device, wherein the scan driver circuit is the scan driver circuit of any one of claims 1 to 6.