KR102471098B1 - Gip driving circuit and display device using the same - Google Patents

Abstract

A gate-in-panel (GIP) driving circuit and a display device using the same are provided.
A gate-in-panel (GIP) driving circuit includes a plurality of stages including an inverter unit connected between a Q node and a QB node through feedback. The inverter unit is connected to a first inverter composed of a first PMOS transistor and a first NMOS transistor, a second inverter composed of a second PMOS transistor and a second NMOS transistor, and a source terminal of the first PMOS transistor, respectively. It includes a reset signal transmission line for resetting the stage. A buffer circuit controlled by the voltages of the Q node and QB node, receiving the first clock CLK1 and outputting a gate voltage is further included. It is characterized in that the voltage of the Q node and the voltage of the QB node have an inverted relationship with each other by a latch logic circuit. The reset signal transmission line transmits a reset voltage to the Q node of the first inverter so that the GIP driving circuit is reset when an abnormal voltage occurs at the QB node of the first inverter. In addition, the reset of the Q node is controlled by the gate low voltage VGL when the first PMOS transistor is turned on by external noise or an abnormal voltage output from the previous stage.
In addition, in the GIP (Gate-In-Panel) driving circuit according to an embodiment of the present invention, immediately after power-on of the display device, each stage of the gate driving circuit is in a random state in which the initial value is not determined. It is possible to control the initial driving anomaly caused by placing In addition, since the Q node of a stage is charged with a high voltage by an output signal of a previous stage including a noise signal, it is possible to control output of a gate signal at an undesirable timing.

Description

GIP (Gate-In-Panel) driving circuit and display device using the same {GIP DRIVING CIRCUIT AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a GIP (Gate-In-Panel) driving circuit and a display device using the same, and more particularly, to a GIP (Gate-In-Panel) driving circuit including a CMOS transistor (Complementary Metal-Oxide-Semiconductor) transistor element. and a display device using the same.

Flat panel displays (FPDs) have been employed in various electronic devices such as mobile phones, tablets, notebook computers, televisions and monitors. Recently, FPDs include a liquid crystal display device (hereinafter referred to as 'LCD') and an organic light emitting diode display (hereinafter referred to as 'OLED'). Such a display device includes a plurality of pixels, displays an image, includes a pixel array composed of a plurality of pixels, and a driving circuit that controls light to be transmitted or emitted from each of the plurality of pixels.

The driving circuit of the display device includes a data driving circuit supplying data signals to data lines of the pixel array and sequentially supplying a gate signal (or scan signal) synchronized with the data signal to the gate lines (or scan lines) of the pixel array. and a timing controller controlling the gate driving circuit (or scan driving circuit) and the data driving circuit and the gate driving circuit.

Each of the plurality of pixels may include a thin film transistor that supplies a voltage of a data line to a pixel electrode in response to a gate signal supplied through a gate line. The gate signal swings between a gate high voltage (VGH) and a gate low voltage (VGL). That is, the gate signal appears in the form of a pulse.

The gate high voltage VGH is set to a voltage higher than the threshold voltage of the thin film transistor formed in the display panel, and the gate low voltage VGL is set to a voltage lower than the threshold voltage of the thin film transistor. The thin film transistors of the pixels are turned on in response to the gate high voltage.

As display devices have recently become thinner, a technology for embedding a gate driving circuit together with a pixel array into a display panel is being developed. The gate driving circuit built into the display panel is known as a "GIP (Gate In Panel) driving circuit". Here, the gate driving circuit includes a shift register for generating a gate signal. The shift register is It includes a plurality of stages connected in cascade. The plurality of stages generate an output in response to a start signal and shift the output according to a shift clock. Accordingly, the gate driving circuit has a plurality of stages in the shift register. The gate signal can be generated by sequentially driving the stages.

In addition, right after the power on of the display device, during the non-display period, the gate driving circuit is in a random state because initial values of the Q node and the QB node of each stage are not determined. Thus, a situation in which a gate signal is output in an abnormal state may occur. To solve this problem, stability of gate driving is ensured by resetting a plurality of stages.

For stable operation of the gate driving circuit, a reset signal for initializing the Q node = Low Voltage and QB = High Voltage needs to be commonly supplied to each stage of the gate driving circuit.

In addition, each stage outputs a gate signal by being driven dependently on the output signal of the previous stage and the output signal of the next stage. Accordingly, when there is a noise signal in the output signal of the previous stage, the Q node is charged with a high voltage by the noise signal of the previous stage, and the gate signal is output at an undesirable timing. may occur.

Therefore, in recent years, various researches and developments have been conducted to implement a reset signal and prevent an abnormal signal from being output in order to stably initialize the gate driving circuit.

As described above, the inventors of the present invention control the initial driving abnormality caused by placing each stage of the gate driving circuit in a random state in which the initial value is not determined immediately after the power on of the display device. A new structure of a GIP driving circuit including a circuit and a display device including the same was invented.

In addition, the inventors of the present invention have a GIP including a circuit for controlling the output of a gate signal at an undesired timing when the Q node of a stage is charged with a high voltage by an output signal of a previous stage including a noise signal. A new structure of a driving circuit and a display device including the driving circuit was invented.

Therefore, the problem to be solved by the present invention is that in each stage of the GIP driving circuit immediately after the power on of the display device, the Q node is a low voltage and the QB node is a GIP that can be reset to a high voltage It is to provide a driving circuit and a display device including the same.

In addition, another problem to be solved by the present invention is that the Q node of a stage is charged with a high voltage by an output signal of a previous stage including a noise signal, so that a gate signal can be controlled at an undesired timing. It is to provide a GIP gate driving circuit and a display device including the same.

In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention will be described below, or will be clearly understood by those skilled in the art from such description and description.

In order to solve the above problems, a gate-in-panel (GIP) driving circuit and a display device using the same are provided according to an embodiment of the present invention. A gate-in-panel (GIP) driving circuit includes a plurality of stages including an inverter unit connected between a Q node and a QB node through feedback, and the inverter unit includes a first PMOS transistor and a first NMOS transistor. An inverter, a second inverter composed of a second PMOS transistor and a second NMOS transistor, and a reset signal transmission line connected to a source terminal of the first PMOS transistor to reset each of the plurality of stages.

According to another feature of the present invention, the gate-in-panel (GIP) driving circuit may further include a buffer circuit controlled by the voltage of the Q node and the voltage of the QB node, receiving the first clock and outputting a gate voltage. can

According to another feature of the present invention, the buffer circuit of the GIP (Gate-In-Panel) driving circuit is a pull-up transistor that responds to the voltages of the Q node and the QB node and increases the gate voltage by supplying the first clock to the output terminal. , and a pull-down transistor that drops the gate voltage by supplying a voltage input from a gate low voltage (VGL) line to an output terminal in response to the voltage of the QB node, and the pull-up transistor includes a transmission gate (TG) can do.

According to another feature of the present invention, a transmission gate (TG) of a gate-in-panel (GIP) driving circuit includes a gate connected to the QB node, a drain connected to an output terminal, and a source to which the first clock is input. A sixth NMOS transistor having a gate connected to the Q node, a source connected to an output terminal, and a drain to which the first clock is input, and the pull-down transistor includes a gate connected to the QB node and an output terminal. It may include an eighth NMOS transistor having a drain connected to and a source connected to a gate low voltage (VGL) line.

According to another feature of the present invention, the inverter unit of the GIP (Gate-In-Panel) driving circuit is a latch logic circuit that controls the gate voltage output of the buffer circuit by the voltage of the Q node and the voltage of the QB node. can

According to another feature of the present invention, the voltage of the Q node and the voltage of the QB node of the inverter unit of the GIP (Gate-In-Panel) driving circuit may be in an inverted relationship with each other by a latch logic circuit.

According to another feature of the present invention, the reset signal transmission line of the GIP (Gate-In-Panel) driving circuit is directly connected to the input terminal of the first inverter without passing through an additional transistor, thereby reducing power consumption of the stage.

According to another feature of the present invention, the reset signal of the Q node of the GIP (Gate-In-Panel) driving circuit turns on the first PMOS transistor by external noise or an abnormal voltage output from the previous stage. Then, the Q node may be applied to be controlled by the gate low voltage VGL.

According to another feature of the present invention, the GIP (Gate-In-Panel) driving circuit further includes a gate low voltage (VGL) line for transmitting the gate low voltage (VGL) to the source terminal of the first NMOS transistor, the gate low As for the voltage (VGL) line, the initial values of the Q node (Q) and QB node (QB) are not determined immediately after the GIP driving circuit is powered on, so the Q node (Q) and QB node (QB) are random ) state, the gate low voltage VGL may be transmitted to the Q node of the first inverter so that the GIP driving circuit is reset.

According to another feature of the present invention, the GIP (Gate-In-Panel) driving circuit may further include a fifth PMOS transistor connected to a source of the second PMOS transistor and a fifth NMOS transistor connected to a drain of the second NMOS transistor. have.

According to another feature of the present invention, in the GIP (Gate-In-Panel) driving circuit, the fifth PMOS transistor is turned on by the carry signal input from the previous stage to control the QB node with the gate high voltage (VGH). can

According to another feature of the present invention, the fifth NMOS transistor of the GIP (Gate-In-Panel) driving circuit is turned off by a reverse signal input from the next stage, and the gate low voltage (VGL) is supplied to the QB node you can control things

According to another feature of the present invention, a GIP (Gate-In-Panel) driving circuit is electrically connected to the QB node, a third inverter having a third PMOS transistor and a third NMOS transistor, and a third PMOS transistor source. An abnormal output control circuit including a fourth PMOS transistor connected and a fourth NMOS transistor connected to a drain of the third NMOS transistor may be further included.

According to another feature of the present invention, the abnormal output control circuit of the GIP (Gate-In-Panel) driving circuit is a carry input to the third inverter based on the second clock (CLK_B) and the carry signal received from the previous stage. When the signal and the second clock CLK_B input to the fourth NMOS transistor are synchronized with each other, the QB node QB may be at the gate low voltage VGL.

According to another feature of the present invention, the second clock (CLK_B) input to the fourth NMOS transistor of the GIP (Gate-In-Panel) driving circuit is QB when the carry signal is input to the third inverter at abnormal timing. It may be controlled so that the gate low voltage VGL is not applied to the node QB.

According to another feature of the present invention, the fourth PMOS transistor of the GIP (Gate-In-Panel) driving circuit is turned on by a reverse signal input from the next stage to control the QB node with the gate high voltage (VGH). can

According to another feature of the present invention, the gate high voltage (VGH) of the QB node of the GIP (Gate-In-Panel) driving circuit can turn off the transmission gate and control the gate voltage output.

In order to solve the problems described above, a CMOS gate driving circuit according to an embodiment of the present invention includes a plurality of stages receiving sequentially phase-delayed first clocks and second clocks and generating output signals. The nth (n is a positive integer) stage is a latch circuit having an inverter connected between the Q node and the QB node through feedback, and is connected to the Q node and the QB node and is synchronized with the first clock to generate an output signal. A buffer circuit electrically connected to the QB node to control the output signal according to the synchronization of the second clock (CLK_B) and the carry signal input from the previous stage, and an abnormal output control circuit electrically connected to the inverter to reset to the Q node and a reset signal transmission line for transmitting a signal.

According to another feature of the present invention, the inverter of the CMOS gate driving circuit may be a CMOS transistor composed of a PMOS transistor and an NMOS transistor.

According to another feature of the present invention, the CMOS gate driving circuit may further include a plurality of control switches connected to the source of the PMOS transistor and the drain of the NMOS transistor, respectively, to increase the operating speed of the inverter.

According to another feature of the present invention, the operating speed of the inverter of the CMOS gate driving circuit may increase as voltages are applied to the Q node and the QB node without overlapping with each other in time.

According to another feature of the present invention, the CMOS gate driving circuit further includes a dummy stage that controls the gate signal output of the nth stage by maintaining the voltage applied to the QB node of the nth stage as a gate high voltage (VGH). can include

Other embodiment specifics are included in the detailed description and drawings.

The GIP driving circuit of the present invention includes a plurality of stages each having an inverter unit connected between a Q node and a QB node through feedback. The inverter unit of each stage includes a first inverter composed of a first PMOS transistor and a first NMOS transistor, and a second inverter composed of a second PMOS transistor and a second NMOS transistor. In addition, a reset signal transmission line is connected to the source terminal of the second NMOS transistor to supply a reset signal for initializing each stage. As a result, when an abnormal voltage occurs at the QB node of the first inverter, each stage may be initialized by directly transmitting a reset signal to the Q node of the first inverter.

The reset signal may directly receive power from the input terminal of the first inverter without adding a transistor. Accordingly, power consumption of the gate driving circuit can be reduced, and a narrow bezel of the display device can be implemented without increasing the area of the gate driving circuit.

In addition, the GIP driving circuit of the present invention includes a third inverter electrically connected to the QB node and having a third PMOS transistor and a third NMOS transistor, a fourth PMOS transistor connected to a source of the third PMOS transistor, and a third NMOS transistor. and a gate voltage output control circuit having a fourth NMOS transistor connected to a drain. As a result, based on the second clock CLK_B and the carry signal received from the previous stage, the gate gate only when the carry signal input to the third inverter and the second clock CLK_B input to the fourth NMOS transistor are synchronized with each other. Controls the output voltage.

1 is a block diagram illustrating a driving circuit of a display device according to an exemplary embodiment and a relationship between driving circuits.
2 is a block diagram showing the relationship between a plurality of stages of a GIP driving circuit and a control signal of the GIP driving circuit according to an embodiment of the present invention.
3A is a circuit diagram showing in detail the configuration of one stage among a plurality of stages shown in FIG. 2 according to an embodiment of the present invention.
FIG. 3B is a circuit diagram briefly illustrating the detailed circuit diagram of FIG. 3A according to an embodiment of the present invention.
4 is a waveform diagram illustrating input/output signals in the stage shown in FIG. 3A according to an embodiment of the present invention.
5A to 5D are circuit diagrams illustrating the flow of a signal within each stage of the waveform diagram of FIG. 4 according to an embodiment of the present invention.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown.

In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range. In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

When an element or layer is referred to as (on) another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or another element is interposed therebetween.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the size and thickness of the illustrated components.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, and as those skilled in the art can fully understand, various interlocking and driving operations are possible, and each embodiment can be implemented independently of each other. It may be possible to implement together in an association relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to FIGS. 1 to 6 .

1 is a block diagram illustrating a driving circuit of a display device according to an exemplary embodiment and a relationship between driving circuits. Referring to FIG. 1 , the display device 100 includes a display panel PNL and a driving circuit for inputting data of an input image to a pixel array 110 of the display panel PNL.

The display panel PNL may be implemented as a display panel of a flat panel display device such as an LCD or OLED display device requiring a gate driving circuit.

The display panel PNL is defined by a plurality of data lines 139, a plurality of gate lines 149 orthogonal to the plurality of data lines 139, and a plurality of data lines 150 and a plurality of gate lines 149. and a pixel array 110 in which pixels are arranged in a matrix form.

The driving circuit of the display panel PNL includes a data driving circuit 130 supplying data voltages to the plurality of data lines 139 and a gate sequentially supplying gate signals synchronized with the data voltages to the plurality of gate lines 149. It includes a driving circuit and a timing controller (Timing Controller, TCON) 120.

Here, the gate driving circuit according to an embodiment of the present invention is located around the pixel array 110 of the display panel PNL and supplies gate signals via a plurality of gate lines 149 (Gate In Panel GIP). ) drive circuit 140.

The timing controller 120 transmits data of an input image received from an external host system to the data driving circuit 130 and the GIP driving circuit 140 . The timing controller 120 receives timing signals such as a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock synchronized with an input image from an external host system.

The timing controller 120 generates various control signals for controlling operation timings of the data driving circuit 130 and the GIP driving circuit 140 based on the input timing signal. That is, the timing controller 120 generates a data driver control signal (DDC) to control the data driving circuit 130 and a gate driver control signal (Gate) to control the GIP driving circuit 140. Generates Driver Control signal (GDC).

The timing controller 120 may be disposed outside the display panel PNL. Specifically, the timing controller 120 is disposed on a pad portion such as a printed circuit board. Accordingly, the timing controller 120 transmits the data driver control signal DDC to the data driving circuit 130 from the outside of the display panel PNL and transmits the gate driver control signal GDC to the GIP driving circuit 140. send.

The data driving circuit 130 receives data of an input image and a data driver control signal DDC from the timing controller 120 . The data driving circuit 130 generates a data voltage by converting data of an input image into a gamma compensation voltage by a data driver control signal DDC transmitted from the timing controller 120, and converts the data voltage into a plurality of data lines 150. ) is output as

The data driving circuit 130 includes a plurality of source electrode driver integrated circuits (ICs). The source electrode drive IC is connected to the plurality of data lines 139 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate driving circuit further includes a level shifter in addition to the GIP driving circuit 140 . Here, the level shifter may be physically separated from the GIP driving circuit 140). The level shifter may be disposed outside the display panel PNL and may be disposed on an external circuit unit (eg, a printed circuit board) connected to the display panel PNL.

The voltage level of the gate driver control signal GDC transmitted from the timing controller 120 is converted by the level shifter and then input to the GIP driving circuit 140 .

Since the signal input to the level shifter is a digital signal, the thin film transistors of the display panel PNL cannot be driven. Accordingly, the level shifter shifts the voltage of each gate driver control signal (GDC) transmitted from the timing controller 120 to obtain a voltage that swings between the gate low voltage (VGL) and the gate high voltage (VGH). converted to a signal with

The gate high voltage VGH is set to a voltage higher than the threshold voltage of the thin film transistor formed on the display panel PNL, and the gate low voltage VGL is set to a voltage lower than the threshold voltage of the thin film transistor.

The GIP driving circuit 140 may be disposed on one edge or both edges of the display panel PNL according to the driving method. The gate driving circuit shown in FIG. 1 is an interlace type GIP driving circuit 140 and is disposed on the left and right edges of the display panel PNL. That is, the GIP driving circuit 140 includes a first GIP driving circuit 140L disposed on the left side of the display panel PNL and a second GIP driving circuit 140R disposed on the right side of the display panel PNL. The location where the GIP driving circuit 140 is disposed on the display panel PNL is not limited to that shown in FIG. 1 and may be implemented in various ways according to embodiments.

Hereinafter, the configuration and operation of the gate driving circuit will be described based on the interlaced GIP driving circuit 140.

The GIP driving circuit 140 may be formed on the substrate of the display panel PNL at the same time as the pixel array 110 . That is, in the gate driving circuit, the GIP driving circuit 140 may be formed simultaneously with the pixel array 110 in the bezel area on both sides of the display panel PNL.

The display device 100 according to an exemplary embodiment includes a timing controller 120 for driving a pixel array 110 , a data driving circuit 130 , and a GIP driving circuit 140 . Here, the GIP driving circuit 140 sequentially supplies gate signals to the gate lines 149 by the gate driver control signal GDC transmitted from the timing controller 120 .

In particular, the GIP driving circuit 140 may receive a gate driver control signal GDC composed of a plurality of control signals involved in supplying gate signals to the gate line 149 from the timing controller 120 .

A specific configuration of the GIP driving circuit 140 in the gate driving circuit will be described later with reference to FIG. 2 .

2 is a block diagram showing the relationship between a plurality of stages of a GIP driving circuit and a control signal of the GIP driving circuit according to an embodiment of the present invention.

The GIP driving circuit 140 includes a plurality of stages (ST1 to STn, where n is a natural number greater than or equal to 2) that are cascaded. Each of the stages ST1 to STn outputs first to n th gate pulses Gout1 to Goutn, respectively. The gate pulses Gout(1) to Gout(n) are applied to the gate lines of the display device and serve as a first carry signal Gout_pre transmitted to the previous stage and the next stage. In the following description, "front stage" refers to a stage positioned above a standard stage.

For example, based on the kth (k is a natural number of 1<k<n) stage STk, the previous stage is any one of the first stage ST1 to the k−1th stage ST(k−1). instruct

In addition, the term "latest stage" refers to a stage positioned below a standard stage. For example, based on the k(1<k<n) stage (STk), the latter stage is the k+1th stage (ST(k+ 1)) to indicate any one of the n-th stages.

In the GIP driving circuit 140L, signals and clocks written together with (L) are symbols indicating signals and clocks applied to the first GIP driving circuit 140L disposed on the left side, and those written together with (R) are symbols on the right side. It is a symbol meaning a signal and a clock applied to the second GIP driving circuit 140R disposed in .

Referring to FIG. 2 , GIP driving circuits 140 are disposed on both sides of the pixel array 110 .

The GIP driving circuit 140 is a shift resistor (SR) that receives the gate driver control signal (GDC) and sequentially outputs the gate signal to the gate line 149 . That is, the shift register SR sequentially supplies the gate signal generated by the level shifter to the gate line 149 by the gate driver control signal GDC.

Here, the gate driver control signal GDC is a gate start pulse (GSP) (VST(L), VST(R)) and clocks involved in gate signal shift (CLK_A(L), CLK_A(R), CLK_B(L), CLK_B(R)) and the like.

Specifically, the first GIP driving circuit 140L includes a first shift register SR_A that sequentially supplies gate signals to odd-numbered gate lines G1, G3, ..., Gn−1. The second GIP driving circuit 140R is disposed on the right side of the display panel PNL and sequentially supplies gate signals to the even-th gate lines G2, G4, ..., Gn. The second shift register SR_B ).

Referring to FIG. 2, after power is turned on to the GIP driving circuit 140, the shift register SR generates reset signals (RST(L), RST(R)) for resetting. is supplied

Referring to FIG. 2 , each of the shift registers SR includes dummy stages D_GL and D_GR that supply a reverse signal (R_Post) to other stages without generating an output.

The dummy stages are reverse generators (Reverse_Generator: RG) that generate a reverse signal R_Post whose phase is opposite to that of the output signal of the previous stage. That is, the first shift register SR_A includes the first dummy stage D_GL as a stage following the last stage SLn/2, and the second shift register SR_B is a stage following the last stage SRn/2. A second dummy stage D_GR is included.

That is, the dummy stages D_GL and D_GR are connected to the last stages SLn/2 and SRn/2 that output the last gate signal, and the dummy stages D_GL and D_GR do not output gate signals and the last stage SLn/ 2, SRn/2) is supplied with a reverse signal (R_Post).

Each shift register (SR) includes a plurality of stages. Specifically, the first shift register SR_A disposed on the left side of the pixel array 110 includes a plurality of stages SL1 to SLn/2 cascadedly connected. The first stage SL1 of the first shift register SR_A starts outputting a gate signal in response to the gate start pulse VST(L) and shifts the gate signal in response to the first clock CLK_A(L). The gate signal output from each of the stages SL1 to SLn/2 is supplied to odd-numbered gate lines G1, G3, ... Gn-1, and is input to the next stage as a carry signal Gout_Pre.

Similarly, the second shift register SR_B disposed on the right side of the pixel array 110 includes a plurality of stages SR1 to SRn2/n cascadedly connected. The first stage SR1 of the second shift register SR_B starts outputting a gate signal in response to the gate start pulse VST(R) and outputs the gate signal in response to the first clock CLK_A(R). Shift and output. The gate signal output from each of the stages SR1 to SRn/2 is supplied to the even-th gate lines G2, G4, ... Gn and is input to the next stage as the first carry signal Gout_Pre.

In addition, the second clock CLK_B(L) is input from the first stage SL1 of the first shift register SR_A. The second clock CLK_B(L) is synchronized with the carry signal Gout_Pre to control timing input to the first shift register SR_A. Similarly, the second clock CLK_B(R) is input to the stage SR1 of the second shift register. The second clock CLK_B(R) is synchronized with the carry signal Gout_Pre to control timing input to the second shift register SR_B.

Therefore, the first clocks CLK_A(L) and CLK_A(R), the second clocks CLK_B(L) and CLK_B(R), the carry signal Gout_Pre received from the previous stage, or Reset ( Reset signals RST(L) and RST(R), gate high voltage VGH and gate low voltage VGL are input.

The carry signal Gout_Pre input to the nth stage excluding the first stage SL1 and SR1 is the output Gout of the n−2th stage, and the reverse signal R_Post input to the nth stage is the n+2th stage. It is a signal whose phase is opposite to that of the stage output (Gout). The carry signal Gout_Pre is not input to the first stages SL1 and SR1, but the start pulses VST(L) and VST(R) are input. The carry signal Gout_Pre is input to the last stages SLn/2 and SRn/2, and the reverse signal R_Post is input to the dummy stages D_GL and D_GR.

The dummy stages D_GL and D_GR are stages for maintaining the QB node voltage of the last stage SLn/2 and SRn/2 at a gate high voltage. Therefore, the dummy stages (D_GL, D_GR) do not output gate signals, and set the Q node (Q) and QB node (QB) of the last stage (SLn/2, SRn/2) to a constant voltage so that an abnormal voltage is output. A reverse signal (R_Post) is output so that it does not occur.

In addition, through the prior art, the initial values of the Q node (Q) and the QB node (QB) are not determined immediately after the GIP driving circuit 140 is powered on, so the Q node (Q) and the QB node (QB) The state is a random state. In this random state, the GIP driving circuit 140 may malfunction and generate an abnormal output.

In addition, an initial driving abnormality may occur due to a noise signal and an abnormality of the previous stage STn_2, and in this case, a gate signal is output to the gate line in the non-display period.

Therefore, the GIP driving circuit 140 according to an embodiment of the present invention provides a reset signal for initializing the Q node (Q) = Low and the QB node (QB) = High of the GIP driving circuit 140 for stable operation. It is commonly supplied to the stages. In addition, for this purpose, a reset signal (RST) transmission line for supplying a reset signal (Reset, RST) to the GIP driving circuit 140 is connected. A detailed circuit configuration of the stage will be described later with reference to FIGS. 3A and 3B.

FIG. 3A is a circuit diagram showing in detail the configuration of one stage among a plurality of stages shown in FIG. 2 according to an embodiment of the present invention. FIG. 3B is a circuit diagram briefly illustrating the detailed circuit diagram of FIG. 3A according to an embodiment of the present invention.

The circuit shown in FIGS. 3A and 3B is an nth (n is a positive integer) stage circuit STn. 3A and 3B, PT1, PT2, PT3, PT4, PT5, PT6, and PT7 are implemented as p-type MOS FETs (hereinafter referred to as 'PMOS transistors'), and NT1, NT2, NT3, NT4, NT5, NT6, NT7 and NT8 are implemented with n-type MOS FETs (hereinafter referred to as 'NMOS transistors'). Hereinafter, the n-th stage STn of the shift register will be described with reference to FIGS. 3A and 3B.

3A and 3B, the nth stage circuit 300 includes an inverter unit 310, a reverse signal generating circuit 340, an abnormal output control circuit 330, a buffer circuit 320, and a reset signal RST. transmission line 350.

The reset signal RST, the first clock and the second clocks CLK_A and CLK_B, the carry signal Gout_Pre or the start pulse VST received from the previous stage STn-2, and the next stage of the n-th stage circuit 300 The reverse signal R_Post, the gate high voltage VGH, and the gate low voltage VGL received from the stage STn+2 are input. The carry signal Gout_Pre input to the nth stage excluding the first stage is the output Gout of the n−2th stage. In the first stage ST1, the carry signal Gout_Pre is not input and the start pulse VST is input.

The inverter unit 310 includes two inverters INV1 and INV2 connected by a closed loop feedback circuit between the Q node Q and the QB node QB, and the Q node ( The voltage of the QB node (QB) is adjusted in an inverted state of the Q) voltage and the Q node (Q) voltage.

That is, if the voltage of the Q node (QB) is the gate low voltage (VGL), the voltage of the QB node (QB) is the gate high voltage (VGH), and if the voltage of the Q node (QB) is the gate high voltage (VGH), the QB node The relationship that the voltage of (QB) is the gate low voltage (VGL) will be explained.

The inverter unit 310 is a latch circuit in which two inverters composed of CMOS transistors are formed as feedback. A latch circuit is a kind of memory circuit that has two stable states. A stable state means a state of a circuit in which an original value can be maintained unless an input is applied from the outside of the circuit. Commonly, the two stable states mean that a value of 1 or 0 may be stored as a previous value, and while the first and second clocks CLK_A and CLK_B are 1 (high), the inverter unit 310 Changes in the input are reflected in the output as they are.

The first inverter INV1 includes a first NMOS transistor NT1 and a first PMOS transistor PT1. The first inverter INV1 supplies the inverted signal of the QB node QB to the Q node QB. The first PMOS transistor PT1 has a gate connected to the QB node QB, a drain connected to the source and Q node QB of the first NMOS transistor NT1, and a reset signal RST to the n-th stage circuit 300. A source connected to the input reset signal (RST) transmission line 350 is included. The reset signal RST input to the nth stage circuit 300 is the gate low voltage VGL. The first NMOS transistor NT1 includes a gate connected to the QB node QB, a drain connected to the drain and Q node Q of the first PMOS transistor PT1, and a source connected to the gate low voltage VGL line. .

When the power of the GIP driving circuit 140 is turned on, the Q node (QB) and the QB node (QB) of the nth stage circuit 300 are in a random state with undetermined initial values . Therefore, the Q node QB of the first inverter INV1 is controlled to the gate low voltage VGL by the voltage supplied from the gate low voltage VGL line so that the nth stage circuit 300 is reset. .

In addition, when the power of the GIP driving circuit 140 is turned on, noise may be generated at the QB node QB. As a result, the first NMOS transistor NT1 and the first PMOS transistor PT1 of the first inverter INV1 may turn on. Also, noise generated at the QB node QB may be transmitted to the Q node QB.

Therefore, the GIP driving circuit 140 according to the embodiment of the present invention connects the reset signal (RST) transmission line 350 to the source of the first PMOS transistor PT1 so that the first PMOS transistor PT1 turns-on. Even when turned on, the Q node (QB) is controlled by the gate low voltage (VGL). Therefore, the nth stage circuit 300 may be reset without generating an abnormal output. The voltage transmitted to the reset signal (RST) transmission line 350 changes from the gate high voltage (VGH) to the gate low voltage (VGL) according to the driving timing of the GIP driving circuit 140, and then again to the gate high voltage (VGH). ) will change to

In addition, when an abnormal output voltage of the previous stage STn-2 is generated at the QB node QB, the first PMOS transistor PT1 is turned on so that the QB node QB The abnormal voltage generated in may be delivered to the Q node (QB).

In the GIP driving circuit 140 according to the embodiment of the present invention, the reset signal (RST) transmission line 350 is connected to the source of the first PMOS transistor PT1 so that the first PMOS transistor PT1 turns on. -On), the Q node (QB) is reset to the gate low voltage (VGL).

The second inverter INV2 includes a second NMOS transistor NT2 and a second PMOS transistor PT2. The second inverter INV2 supplies the inverted signal of the Q node QB to the QB node QB.

The second PMOS transistor PT2 includes a gate connected to the Q node Q, a drain connected to the drain and QB node QB of the fifth NMOS transistor NT5, and a source connected to the drain of the fifth PMOS transistor PT5. do.

The second NMOS transistor NT2 includes a gate connected to the Q node QB, a drain connected to the source of the fifth NMOS transistor NT5, and a source connected to the gate low voltage VGL line.

The source of the fifth PMOS transistor PT5 connected to the source of the second PMOS transistor PT2 is connected to the gate high voltage VGH line. In addition, the gate of the fifth PMOS transistor PT5 receives the carry signal Gout_Pre of the gate low voltage VGL from the previous stage STn-2. As a result, the QB node QB of the second inverter INV2 is maintained at the gate high voltage VGH. That is, it is possible to prevent an abnormal output from occurring in the n-th stage (STn) circuit 300 of the GIP driving circuit 140.

Also, the fifth NMOS transistor NT5 is connected to the drain of the second NMOS transistor NT2. The gate of the fifth NMOS transistor NT5 receives the reverse signal R_Post of the gate low voltage VGL from the next stage STn+2. The fifth NMOS transistor NT5 is turned off by the reverse signal R_Post to block the gate low voltage VGL from being applied to the QB node QB.

As a result, the QB node QB connected to the second inverter INV2 is controlled to the gate high voltage VGH by the fifth NMOS transistor NT5, so that the n-th stage circuit 300 can become a stabilized circuit. have.

The latch circuit composed of the inverter unit 310 controls the output voltage by inverting the voltage of the Q node (QB) and the voltage of the QB node (QB). In the latch circuit, the voltage of the Q node QB and the voltage of the QB node QB are activated as input voltages to the buffer circuit 320 to control the timing at which the output voltage of the buffer circuit 320 is supplied to the gate line.

Referring to FIGS. 3A and 3B , the buffer circuit 320 includes a transmission gate (TG) and a pull-down transistor.

The transmission gate (TG) is a switch element in which an NMOS transistor and a PMOS transistor are connected in parallel to lower an on-resistance (RON) and can be driven with a full range voltage. For example, when VGH = 10V, VGL = 0V, Vth = 1V, Vgs = 10V, the driving range is 1~10V, the output voltage range of NMOS transistor is 1~10V, and the output voltage range of PMOS transistor is 0~ It is 9V. Here, Vth is the threshold voltage, and Vgs is the gate-to-source voltage. TG connects an NMOS transistor and a PMOS transistor in parallel, and its output voltage range is 0 to 10V, that is, it can be driven in a full range.

3A and 3B, the transmission gate (TG) supplies the first clock (CLK_A) to the output terminal in response to the voltage of the Q node (Q) and pulls up the output voltage (Gout) to rise. It is a pull-up transistor.

Also, the transmission gate TG includes a sixth PMOS transistor PT6 and a sixth NMOS transistor NT6. The source electrode of the sixth PMOS transistor PT6 and the sixth NMOS transistor NT6 are connected to each other, and the drain electrode of the sixth PMOS transistor PT6 and the sixth NMOS transistor NT6 are connected to each other.

The sixth PMOS transistor PT6 of the transmission gate TG includes a gate connected to the QB node QB, a drain connected to an output terminal, and a source to which the first clock CLK_A is input. In addition, the sixth NMOS transistor NT6 of the transmission gate TG includes a gate connected to the Q node Q, a source connected to an output terminal, and a drain to which the first clock CLK_A is input.

That is, the transmission gate TG is a switch element in which the sixth PMOS transistor PT6 and the sixth NMOS transistor NT6 are connected in parallel to reduce the on-resistance RON and drive a full range voltage.

Referring to FIGS. 3A and 3B , a pull-down transistor includes one NMOS transistor NT8.

The pull-down transistor causes the output voltage Gout to fall by discharging the output terminal in response to the voltage of the QB node QB. The eighth NMOS transistor NT8 of the pull-down transistor includes a gate connected to the QB node QB, a drain connected to an output terminal, and a source connected to the VGL line (VGL_SL).

3A and 3B, the buffer circuit 320 increases the gate pulse of the first clock CLK_A to the output voltage Gout when the gate high voltage VGH is applied to the Q node QB. In addition, the buffer circuit 320 outputs the gate low voltage VGL transmitted from the gate low voltage VGL line through the eighth NMOS transistor NT8 when the gate high voltage VGH is applied to the QB node QB. Drop to the voltage (Gout).

The buffer circuit 320 increases the output voltage in synchronization with the first clock CLK_A when the voltage of the Q node QB is the gate high voltage VGH, and the voltage of the QB node QB is the gate high voltage VGH. ), drop the output voltage. Accordingly, when the voltage of the Q node QB is the gate high voltage VGH, the output signal is supplied to the gate line through the output node Gout of the buffer circuit 320 in synchronization with the first clock CLK_A. . Similarly, when the voltage of the QB node QB is the gate high voltage VGH, the output node Gout of the buffer circuit 320 is connected to the gate low voltage VGL line, so that the output voltage drops. That is, the buffer circuit 320 is connected to the Q node Q and the QB node QB, and controls the output voltage in synchronization with the first clock CLK_A.

3A and 3B, the abnormal output control circuit 330 includes a third inverter INV3, a fourth PMOS transistor PT4 and a fourth NMOS transistor NT4 connected to the third inverter INV3. .

The third inverter INV3 includes a third PMOS transistor PT3 and a third NMOS transistor NT3. The third inverter INV3 is connected to the QB node QB, and the source of the third PMOS transistor PT3 of the third inverter INV3 is gated by the reverse signal R_Post received from the next stage STn+2. is connected to the turned-on fourth PMOS transistor PT4. The reverse signal R_Post controls the voltage transmitted from the gate high voltage VGH line connected to the source of the fourth PMOS transistor PT4 to be supplied to the third inverter INV3.

The drain of the third NMOS transistor NT3 of the third inverter INV3 is connected to the fourth NMOS transistor NT4 whose gate is turned on by the second clock CLK_B. The second clock CLK_B controls the voltage transmitted from the gate low voltage VGL line connected to the source of the fourth NMOS transistor NT4 to be supplied to the third inverter INV3.

Also, the second clock CLK_B is connected to the fourth NMOS transistor NT4 and is not connected to the additional transistor. The abnormal output control circuit 330 uses only the second clock CLK_B connected to the fourth NMOS transistor NT4 and does not use an additional clock. As a result, driving power consumption of the GIP driving circuit 130 can be minimized.

3A and 3B, the abnormal output control circuit 330 receives the second clock (CLK_B), the reverse signal (R_Post) received from the next stage (STn+2) and the input from the previous stage (STn-2). The voltage applied to the QB node (QB) is controlled by the carry signal (Gout_Pre). The buffer circuit 320 can control the output gate voltage Gout by the voltage applied to the QB node QB.

More specifically, the abnormal output control circuit 330 controls the timing of the second clock CLK_B input to the fourth NMOS transistor when the carry signal Gout_Pre is input to the inverter INV3 at an abnormal timing. When synchronized with , the gate low voltage VGL is supplied to the QB node QB from the gate low voltage VGL line. Then, the gate low voltage VGL of the QB node QB and the gate high voltage VGH of the Q node Q are input to the buffer circuit 320 and the gate voltage Gout is output.

That is, even if the timing of the carry signal Gout_Pre input to the third inverter INV3 with the gate voltage Gout of the previous stage STn-2 is in an abnormal state, the fourth NMOS transformer The abnormally output gate voltage Gout can be controlled according to whether or not it is synchronized with the second clock CLK_B connected to the gate.

Further, in the abnormal output control circuit 330, the carry signal Gout_Pre turns on the third inverter INV3 with the gate low voltage VGL, and the reverse signal R_Post turns on the fourth PMOS transistor PT4. - By turning on, the QB node (QB) is controlled to change to the gate high voltage (VGH). As a result, after the gate voltage Gout is output from the transmission gate TG by the first clock CLK_A, the transmission gate TG is turned off to control the output of the abnormal voltage.

Referring to FIGS. 3A and 3B , the reverse signal generation circuit 340 includes a fourth inverter INV4 composed of a seventh PMOS transistor PT7 and a seventh NMOS transistor NT7. A gate high voltage (VGH) line is connected to the source of the seventh PMOS transistor PT7, and a gate low voltage (VGL) line is connected to the source of the seventh NMOS transistor NT7.

The reverse signal generating circuit 340 generates the reverse signal R_Post by the gate voltage Gout output from the transmission gate TG. That is, when the gate voltage Gout is input to the fourth inverter INV4 as the gate low voltage VGH, the gate of the seventh MOS transistor PT7 is turned on, and the gate high voltage is generated from the gate high voltage VGH line. (VGH) is supplied to generate a reverse signal (R_Post). This reverse signal R_Post is a signal involved in the operation of the previous stage STn_2.

Therefore, the GIP driving circuit 140 according to an embodiment of the present invention binds the first inverter (INV1) and the second inverter (INV2) with feedback between the Q node (Q) and the QB node (QB) to latch (Latch) ) is formed, and the reset signal transmission line 350 is connected to the source of the first PMOS transistor PT1 of the first inverter INV1. As a result, after the driving of the GIP driving circuit 140 starts, even if an abnormal voltage such as noise occurs at the QB node QB, the Q node Q generates the first clock signal CLK_A through the buffer circuit 320. The phenomenon of being output with this gate voltage Gout can be prevented.

In addition, the GIP driving circuit 140 according to an embodiment of the present invention connects the fifth PMOS transistor PT5 and the fifth NMOS transistor NT5 to the second inverter INV. As a result, the Q node Q is maintained at the gate low voltage VGL and the QB node QB is maintained at the gate high voltage VGH by the carry signal Gout_pre and the reverse signal R_Post, thereby forming a GIP driving circuit. It is possible to prevent abnormal output from occurring in the furnace 140.

In the GIP driving circuit 140 according to an embodiment of the present invention, the third inverter INV3 is connected to the QB node QB, and the fourth PMOS transistor PT4 and the fourth NMOS transistor NT4 are connected to the third inverter INV3. ) is connected. As a result, the QB node QB maintains the gate high voltage VGH by the carry signal Gout_pre and the reverse signal R_Post, and the buffer circuit 320 is switched to the gate voltage Gout by the first clock CLK_A. ) is output, turn it off so that abnormal voltage output does not occur. In addition, the gate low voltage VGL is applied to the QB node QB only when the carry signal Gout_pre and the second clock CLK_B are synchronized, so that the carry signal Gout_pre is abnormally input to the third inverter INV3. However, it is possible to prevent an abnormal voltage from being output from the buffer circuit 320.

Accordingly, the GIP driving circuit 140 according to an embodiment of the present invention can improve the stability of the output gate signal by controlling the Q node (Q) and the QB node (QB). A detailed relationship between various signals input to the n-th stage circuit 300 and the output voltage will be described later with reference to FIGS. 4 to 5D.

4 is a waveform diagram illustrating input/output signals in the stage shown in FIG. 3A according to an embodiment of the present invention. 5A to 5D are circuit diagrams illustrating the flow of a signal within each stage of the waveform diagram of FIG. 4 according to an embodiment of the present invention.

The n-th stage circuit 500 of FIGS. 5A to 5D shows an activated state by signals input to the n-th stage circuit 300 of FIG. 3, and is substantially similar to the n-th stage circuit 300 of FIG. Since it is the same, redundant description is omitted. The dotted lines shown in FIGS. 5A to 5D represent internal signal flows by signals input to the nth stage circuit 300 . In addition, dotted lines of some transistors shown in the n-th stage circuit 300 indicate portions that are not activated by a signal input to the n-th stage circuit 300 .

Referring to FIG. 4 , period ① is a non-display period before an image is displayed by supplying a gate signal to the pixel array 110 of the display panel PNL. In addition, a section ② to a section ④ is a display section for displaying an image on the display panel PNL.

Referring to FIGS. 4 and 5A, section ① is a power-on period of the n-th stage circuit 300 of the GIP driving circuit 140. During period ①, the QB node QB becomes the gate high voltage VGH. That is, the first NMOS transistor NT1 is turned on, the gate low voltage VGL is applied to the Q node Q, and the Q node Q is reset to the gate low voltage VGL. .

Also, during the period ①, an abnormal state in which noise is generated at the QB node QB and the first PMOS transistor PT1 is turned on may occur.

Then, the gate low voltage VGL is applied to the Q node Q from the reset signal transmission line 350 connected to the source of the first PMOS transistor PT1, and the Q node Q is the gate low voltage VGL ) is reset. During period ①, the gate low voltage VGL is supplied to the reset signal transmission line 350.

Therefore, after power-on of the GIP driving circuit 140 according to an embodiment of the present invention, the gate high voltage (VGH) or noise is generated at the QB node (QB) during section ①. Even if this occurs, a reset in which the Q node Q is maintained at the gate low voltage VGL can be performed.

Next, referring to FIGS. 4 and 5B , period ② is a period prior to the output of the gate voltage (Gout) from the nth stage circuit 300 of the GIP driving circuit 140 .

During period ②, the second clock CLK_B and the carry signal Gout_pre are synchronized, so that the third NMOS transistor NT3 and the fourth NMOS transistor NT4 are simultaneously turned on. As a result, the QB node QB is controlled by the gate low voltage VGL. Subsequently, the voltage of the Q node Q is controlled to the gate high voltage VGH by the first inverter INV1.

That is, the gate low voltage VGL of the QB node QB is input to the gate of the first PMOS transistor PT1 of the first inverter INV1, and the first PMOS transistor PT1 is turned on. As a result, the gate high voltage VGH is input from the reset signal transmission line 350 connected to the source of the first PMOS transistor PT1, and the voltage at the Q node Q is controlled to the gate high voltage VGH. .

The transmission gate TG of the buffer circuit 320 is turned on due to the voltage applied to the Q node Q and the QB node QB. That is, the gate low voltage VGL of the first clock CLK_A is output as the gate voltage Gout. In addition, the gate low voltage VGL output from the transmission gate TG turns on the seventh PMOS transistor PT7 of the reverse signal generating circuit 340 . The reverse signal Rn of the gate high voltage VGH is output by the gate high voltage VGH line connected to the source of the seventh PMOS transistor PT7.

Therefore, in the GIP driving circuit 140 according to an embodiment of the present invention, since the QB node QB is controlled to the gate low voltage VGL only when the second clock CLK_B and the carry signal Gout_pre are synchronized, the carry Even if the signal Gout_pre is input to the third NMOS transistor NT3 with the voltage abnormally output in the previous stage STn-2, the abnormal voltage output can be controlled.

Next, referring to FIGS. 4 and 5C , period ③ is a gate voltage (Gout) output period in the nth stage circuit 300 of the GIP driving circuit 140 .

During section ③, the transmission gate TG of the buffer circuit 320 is turned on due to the gate high voltage VGH of the Q node Q and the gate low voltage VGL of the QB node QB. At this time, the first clock CLK_A is input to the transmission gate TG as the gate high voltage VGH. As a result, the gate high voltage VGH of the first clock CLK_A is output as the gate voltage Gout.

Also, the output gate high voltage VGH turns on the seventh NMOS transistor NT7 of the reverse signal generating circuit 340 . The reverse signal Rn of the gate low voltage VGL is output by the gate low voltage VGL line connected to the source of the seventh NMOS transistor NT7.

Referring to FIGS. 4 and 5D , period ④ is a period in which the nth stage circuit 300 of the GIP driving circuit 140 is turned off.

During period ④, the carry signal Gout_Pre of the previous stage STn-2 is input to the third PMOS transistor PT3 of the third inverter INV3 as the gate low voltage VGL. The reverse signal R_Post of the next stage STn+2 is input to the fourth PMOS transistor PT4 as the gate low voltage VGL. The third PMOS transistor PT3 and the fourth PMOS transistor PT4 are turned on by the carry signal Gout_Pre and the reverse signal R_Post, and the gate high voltage VGH supplied from the gate high voltage VGH line It is caught on this QB node (QB).

Subsequently, the gate high voltage VGH of the QB node QB turns on the first NMOS transistor NT1 of the first inverter INV1, and as a result, the gate low voltage supplied from the gate low voltage VGL line is turned on. A voltage (VGL) is applied to the Q node (Q).

In addition, the gate low voltage VGL of the Q node Q turns on the second PMOS transistor PT2 of the second inverter INV2, and the carry signal Gout_Pre turns on the fifth PMOS transistor PT5. - Turn it on. As a result, the QB node QB of the second inverter INV2 is maintained at the gate high voltage VGH. The transmission gate TG of the buffer circuit 320 is turned off due to the voltage applied to the Q node Q and the QB node QB. In addition, the eighth NMOS transistor NT8 is turned on by the gate high voltage VGH of the QB node QB. As a result, the output gate voltage Gout is output as the gate low voltage VGL regardless of the voltage of the first clock CLK_A.

Therefore, during the turn-off period ④ of the GIP driving circuit 140 according to an embodiment of the present invention, the nth stage circuit 300 can be stably turned off.

The GIP driving circuit 140 according to an embodiment of the present invention includes a plurality of stages each having an inverter unit connected between a Q node (Q) and a QB node (QB) by feedback. The inverter unit of each stage includes a first inverter composed of a first PMOS transistor and a first NMOS transistor, and a second inverter composed of a second PMOS transistor and a second NMOS transistor. In addition, a reset signal transmission line is connected to the source terminal of the second NMOS transistor to supply a reset signal for initializing each stage. As a result, when an abnormal voltage occurs at the QB node QB of the first inverter, each stage may be initialized by directly transmitting a reset signal to the Q node Q of the first inverter.

The reset signal may directly receive power from the input terminal of the first inverter without adding a transistor. Accordingly, power consumption of the gate driving circuit can be reduced, and a narrow bezel of the display device can be implemented without increasing the area of the gate driving circuit.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and may be variously modified and implemented without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display panel 110: pixel array
120: timing controller 130: data driving circuit
139: multiple data lines 40L, 140R: first and second GIP driving circuits
140: GIP driving circuit 149: multiple gate lines
310: inverter unit 320: buffer circuit
330: abnormal output control circuit 300, 500: nth stage
340: reverse signal generating circuit 350: reset signal transmission line

Claims (23)

An inverter circuit connected by feedback to each other between the Q node and the QB node, a buffer circuit outputting a gate voltage according to the voltages of the Q node and the QB node, and an abnormal output control circuit controlling the output of an abnormal voltage of the gate voltage. Equipped with a plurality of stages including,
The inverter circuit is
a first inverter composed of a first PMOS transistor and a first NMOS transistor; and
A second inverter composed of a second PMOS transistor and a second NMOS transistor;
The abnormal output control circuit
A third inverter electrically connected to the QB node and having a third PMOS transistor and a third NMOS transistor;
A fourth PMOS transistor and a fourth NMOS transistor connected to the third inverter;
The abnormal output control circuit generates a QB node when the carry signal input to the third inverter and the second clock input to the fourth NMOS transistor are synchronized with each other based on the second clock and the carry signal received from the previous stage. GIP (Gate In Panel) driving circuit that supplies gate low voltage to According to claim 1,
The reset of the Q node is controlled by the gate low voltage (VGL) when the first PMOS transistor is turned on by external noise or the abnormal voltage output from the previous stage. Characterized by GIP (Gate In Panel) driving circuit. According to claim 1,
a gate low voltage (VGL) line for transmitting a gate low voltage (VGL) to a source terminal of the first NMOS transistor;
The gate low voltage (VGL) line immediately after the GIP driving circuit is powered on, the initial values of the Q node (Q) and the QB node (QB) are not determined, so the Q node (Q) and the QB node (QB) A GIP (Gate In Panel) driving circuit, characterized in that when it is in a random state, the gate low voltage (VGL) is transmitted to the Q node of the first inverter so that the GIP driving circuit is reset. According to claim 1,
A Gate In Panel (GIP) driving circuit further comprising a fifth PMOS transistor connected to a source of the second PMOS transistor and a fifth NMOS transistor connected to a drain of the second NMOS transistor. According to claim 4,
The fifth PMOS transistor is turned on by a carry signal input from a previous stage to control the QB node to a gate high voltage (VGH). According to claim 4,
The fifth NMOS transistor is turned off by a reverse signal input from a later stage to control supply of a gate low voltage (VGL) to the QB node. According to claim 1,
The fourth PMOS transistor is connected to the source of the third PMOS transistor;
The fourth NMOS transistor is connected to the drain of the third NMOS transistor, GIP (Gate In Panel) driving circuit. According to claim 1,
Directly connected to the input terminal of the first inverter, the Q of the first inverter so that the GIP driving circuit is reset only when an abnormal voltage occurs at the QB node of the first inverter before the gate voltage is output. A GIP (Gate In Panel) driving circuit further comprising a reset signal transmission line for transmitting a reset voltage to the node. According to claim 1,
The second clock input to the fourth NMOS transistor controls the gate low voltage (VGL) not to be applied to the QB node when the carry signal is input to the third inverter at an abnormal timing, GIP ( Gate In Panel) drive circuit. According to claim 1,
The fourth PMOS transistor is turned on by a reverse signal input from a later stage to control the QB node with a gate high voltage (VGH). According to claim 1,
The buffer circuit,
a sixth PMOS transistor including a gate connected to the QB node, a drain connected to an output terminal of the gate voltage, and a source to which a first clock is input; and a transmission gate (TG) including a sixth NMOS transistor including a gate connected to the Q node, a source connected to the output terminal, and a drain to which the first clock is input.
and an eighth NMOS transistor having a gate connected to the QB node, a drain connected to the output terminal, and a source connected to the gate low voltage line. According to claim 11,
A gate high voltage (VGH) of the QB node turns off the transmission gate and controls a gate voltage output. According to claim 1,
Gate In Panel (GIP) driving circuit, characterized in that the voltage of the Q node and the voltage of the QB node are inverted to each other by the inverter circuit composed of a latch logic circuit. A plurality of stages receiving a first clock and a second clock having sequentially delayed phases and generating output signals;
The nth (n is a positive integer) stage is
A latch circuit having inverters connected between a Q node and a QB node by feedback to each other;
a buffer circuit connected to the Q node and the QB node and generating the output signal in synchronization with the first clock; and
An abnormal output control circuit electrically connected to the QB node to control the output signal according to synchronization of the second clock and a carry signal input from a previous stage;
The abnormal output control circuit
A third inverter electrically connected to the QB node and having a third PMOS transistor and a third NMOS transistor;
Including a fourth PMOS transistor and a fourth NMOS transistor connected to the third inverter,
and supplying a gate low voltage to a QB node when a carry signal input to the third inverter and the second clock input to the fourth NMOS transistor are synchronized with each other. According to claim 14,
The inverter is a CMOS gate driving circuit, characterized in that a CMOS transistor composed of a PMOS transistor and an NMOS transistor. According to claim 14,
and a reset signal transmission wire directly connected to the inverter and transmitting a reset signal to the Q node only when noise is generated in the inverter before the carry signal is input. delete 15. The method of claim 14,
and a dummy stage controlling a gate signal output of the n-th stage by maintaining a voltage applied to the QB node of the n-th stage at a gate high voltage (VGH). delete delete delete delete delete

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