GB2360650A

GB2360650A - A shift register stage for driving an LCD pixel row, with rapid row discharge

Info

Publication number: GB2360650A
Application number: GB0115351A
Authority: GB
Inventors: Ju Cheon Yeo; Sang Young Yoon
Original assignee: LG Philips LCD Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 1998-10-21
Filing date: 1999-09-24
Publication date: 2001-09-26
Anticipated expiration: 2019-09-24
Also published as: GB0115352D0; GB2360651A; GB0115351D0; GB2360651B; GB2360650B

Abstract

A scan pulse generator for an LCD comprises a cascade of clocked shift register stages. In each stage, the input signal g from the previous stage charges the gate of the output pull-up transistor T5 so that when a clock signal at its drain is asserted the output node ROWi goes high. The output node is discharged by T6 when a further clock signal coupled to the gate of T3 is asserted. The discharge of the output node is accelerated by T7 in response to the output of the next stage.

Description

2360650 SHIFT REGISTER This invention relates to a circuit for driving a

display device of active matrix type, and more particularly to a shift register for driving pixel rows in a liquid crystal display.

Generally, a conventional liquid crystal display device used in a television or a computer includes a liquid crystal matrix having liquid crystal cells arranged at intersections of data lines and select or gate lines. The select lines are horizontal lines (i.e., row lines) of the liquid crystal matrix, which are sequentially driven with a shift register. As shown in Fig. 1, the conventional shift register includes n stages 21 to 2,' connected in cascade and simultaneously connected, via output lines to 41. to 4,, to n row lines ROW1 to ROWn or gate lines, respectively. A scanning pulse SP is inputted to the first stage 21, and out ut signals g, to g,-[ of the previous stages are inputted to the 2nd to 0 p nth stages 22 to 2,, respectively. Also, n stages 21 to 2, receive two clock signals out of three clock signals C I to C3. Each of the n stages 21 to 2, drives an associated row line ROWi connected to a pixel train with the two clock signals and the output signals of previous stages or with the two clock signals and the scanning pulse SP.

As.shown in Fig. 2, each of the stages 21 to 2,, includes a fifth NMOS transistor T5 for applying a high logic voltage signal to an output line 4j, and a sixth NMOS transistor T6 for applying a low logi-C voltage signal to the output line 4j. If a high logic level of (i-1)th row line input signal gi-1 is applied from the previous stage 2j-1, then first and fourth NMOS transistors T 1 and T4 are turned on. As seen from Fig. 3), a high logic level of third clock signal C3 is synchronized with the (i-1)th row line input signal gi-1 and applied to a third NMOS transistor T3, thereby turning on the third NMOS transistor T1 The third and fourth NMOS transistors T3 and T4 are a so-called 'ratioed logic' which are set to an appropriate ratio of resistance values in such a manner that a voltage 2 at a second node P2 becomes a low level when the third and fourth NMOS transistors T3 and T4 are simultaneously turned on. Accordingly, when (i-1)th row line input signal gi,l is applied, a low logic level voltage emerges at the second node P2. At th-is time, the second and sixth NMOS transistor T2 and T6 are turned off by a low logic level voltage from the second node P2. A first node P 1 is charged into a high logic level voltage by a supply voltage VDD when the first NMOS transistor T1 is t=ed on and the second NMOS transistor T2 is turned off. Alen the high logic level voltage at the first node P 1 arrives at a threshold voltage thereof, the fifth NMOS transistor T5 is turned off. At this time, since the first clock signal Cl remains at a low logic level, a low logic level voltage emerges at the output line 4j.

If the first clock signal Cl has a high logic level voltage during a time interval when a voltage at the first node P l remains at a high logic level, then the output line 41 becomes a high logic level by a high logic level first clock signal Cl applied via the fifth NMOS transistor TS. Accordingly, a high logic level output signal Vout emerges at the output line 4i. At this time, since the output line 4i and the first node P I are coupled as shown in Fig. 4 with a parasitic capacitance Cgs existing between the gate and the source of the fifth NMOS transistor T5, a voltage at the first node P 1 is bootstrapped into a high logic voltage level. Accordingly, the high logic level voltage of the fi- rst clock signal Cl is applied to the output line 4i almost without a loss. Such a bootstrap system is used to compensate a voltage loss caused by a threshold voltage generated at a circuit including NMOS transistors.

Also, if the first clock signal Cl is changed from a high logic level voltage into a low logic level voltage, a voltage Voitit at the output line 4i drops into a low logic level voltage because the fifth NMOS transistor T5 is in a turned-off state. Furthermore, since the first and fourth NMOS transistors Tl'and T4 are turned off by the (i- 1)th row line input signal g-,-, having a 10-w logic level voltage in such a manner to be supplied mdth no voltage, a voltage level at the first node P 1 also drops slowly. In such a state, if the third clock sienal C3 has a Egh log-ic: level voltage, then the third]-\TMOS transistor T3 is turned off to thereby begin charging the second node P2 into a hiRh loeic level voltaRe with the aid of the supply, voltage VDD applied via the third NMOS transistor T-3. The six-th NMOS transistor T6 is mmed on by a voltage signal higher than its threshold C 3 voitasze applied from the second node P2 to discharge a voltage charged on the ouil)ut line 4i toward a ground volta!z---VSS. As a result, a voltage at the ro,,;, line ROlyV' connected to the output line 4i maintains a low logic level.

In order to operate such a shift register normally, a resistance ratio of the third and fourth NMOS transistors T3 and T4 serving as a ratioed logic must be set accurately. In other words, in order to generate a low logic level voltage at the second node P2 when the third clock signal C3) having a high level voltage and the (1-1)th row line input signal gi-1 are applied siumultaneously to the aates of the third and fourth NMOS transistors T3 and T4, a channel width of the fourth NMOS transistor T4 must be about ten tirnes larger than 10 that of the third NMOS transistor T3. If characteristics of the NMOS transistors T3 and T4 become non-uiiiforrn, a current ratio of the third NMOS transistor T3 to the fourth NMO S transistor T4 varies. In this case, the shift register fails to operate properly.

Further, since a direct current flows continuously at the third and fourth NMOS transistors T3 and T4 when the third and fourth 1,TMOS transistors T3 and T4 are simultaneously turned on by the third clock signal C3 and the (i-1)th row line input signal gi.,, the characteristics of the third and fourth NMOS transistors T3 and T4 are susceptible to deterioration by dvercuirent. Also, if the first clock signal Cl is changed from a low logic level voltage into a high logic level voltage during an interva.1 when a W Cl -1- voitac,e at the first node P 1 is in a state of high logic level, then a risne Width in a bootstrapped voltage at the first node P l becomes. different in accordance -%,dth a parasitic capacitance value of the fifth NIMOS transistor T5 and a change in the parasitic capacitance at the first node P 1. The voltage rising %Addth at the first node P 1 is as described in the following formula (l):

CAP + COX CLI + CAP + Cox wherem' AVp 1 and 11 Vout represent a voltage change amount at the first node P 1 and a voltage chance amount at the output line 4j, respectively, and Cl_ and Co- represenis a parasitic capacitance at the first node P I and a parasitic capacitance of the fir-th lOS 4 transistor T5, respectively. The parasitic capacitance Cox of the fifth NMOs transistor T5 is equal to a sum of parasitic. capacitance Cgs between the gate and the source thereof and parasitic capacitance Cds between the drain and the gate thereof.

As seen from the formula (1), since a rising width in voltage at the first node P 1 is changed by the capacitance CL at the first node P 1 and the parasitic capacitance C,,, of the fifth NMOS transistor T5, it is difficult to set a characteristic of shift register accurately. Moreover, in the shift register of Fig. 2, the output voltage Vout at the output line 4j, is distorted because a voltage at the second node P2 also is raised by a parasitic capacitance between the gate and the drain of the sixth NMOS transistor T6 as a voltage at the output line 4i changes into a high logic level.

Accordingly, it is an object of the present invention to provide a shift register that is adaptive for preventing a change in a circuit characteristic caused by a change in a parasitic capacitance.

A further object of the present invention is to provide a shift register that is adaptive for preventing a deterioration in a circuit characteristic caused by overcurrent.

A still further object of the present invention is to provide a shift register that is adaptive for minimising a voltage loss caused by the threshold voltage.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realised and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

In order to achieve these and other objects of the invention, a shift register according to one aspect of the present invention includes a plurality of stages which are commonly connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, connected to row lines, and connected, in cascade, with respect to a scanning signal, for charging and discharging the row lines.

Each of the plurality of stages included in the shift register according to one aspect of the present invention compri ses output circuit means including a pull-up zansistor and a pull-down transistor, said pull-up transistor having a first input electrode for receiving a first clock signal havinga delayed phase. in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode; said pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a second control electrode; input circuit means being responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; and means for raising a voltage of thefirst control signal.

Each of the plurality of stages included in the shift register according to another aspect of the present invention comprises output circuit means including a pull-up transistor and a pull-down transistor, said pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode; said pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a secqnd control electrode; input circuit means being responsive to the scanning signal for generating a first control signal to be applied to the flirst control electrode, and responsive to a second clock signal having a.delayed phase in comparison to the first clock signal for generating asecond control signal to be applied to the second control electrode; means for raising a voltac,e of the first control signal; and means for discharging the second control signal during a time interval when the first control signal is enabled.

Each of the plurality of stages included in the shift register according to still another aspect of the present invention comprises output circuit means including a pull up transistor and a pull-dolArn transistor, said pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signa a first output electrode connected to the row line. and a first control electrode; said pull-down transistor having a second input electrode connected to the low level voltage source. a second output electrode connected to therow line, and a second control -electrode; input circuit means being responsive to the scanning signal for 6 generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; means for raising a voltage of the first control signal; and means for accelerating a discharging speed at the row line.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

For a better understanding of the present invention, specific embodiments will now be described, by way of example, with reference to the accompanying drawings, in which:

Fig. 1 is a schematic block diagram showing the configuration of a conventional shift register; Fig. 2 is a detailed circuit diagram of each stage in Fig. 1; Fig. 3 is input/output waveform diagrams of the stage in Fig. 2; Fig. 4 is a detailed circuit diagram of the output part of the stage in Fig. 2; Fig. 5 is a schematic block diagram showing the configuration of a shift register according to an embodiment of the present invention; Fig. 6 a detailed circuit diagram of an embodiment of the shift register stage in Fig. 5; Fig. 7 is input/output waveform diagrams of the stage in Fig. 6; Fig. 8 is voltage waveform diagrams showing a variation in voltages at first and second nodes resulting from the presence of capacitance CL2 in Fig. 6; Fig. 9 is a detailed circuit diagram of another embodiment of the stage in Fig. 5; Fig. 10 is a detailed circuit diagram of still another embodiment of the stage in Fig. 5; and Fit. 11 voltage waveform diagrams showing that a falling time of the output voltage becomes long.

7 Referring to Fig. 5, there is shown a shifl. register according to a first embodiment of the present invention. The shift register includes n stages 121 to 12,, connected, in cascade, to a scanning pulse input line SPI, to drive m x n pixel array. Output lines 141 to 14, of the n stages 1.21 to 12,, are connected to n row lines ROW1 to ROWn included in the pixel array,'respectively. A scanning pulse SP is inputted to the first stage 121, and output signals g, to g,-t of the Ist to (n-1)th stages 121 to 12,[ are applied as a scanning pulse to the subsequent stages 122 to 12, respectively.

The shift register receives first to fourth clock signals C I to C4, which are phase- delayed in comparison to the scanning pulse, a supply voltage VDD and a ground voltage VSS from the exterior driving system in addition to the scanning pulse. As shown in Fig. 6, each of the stages 121 to 12, includes a first NMOS transistor T 1 connected among a scanning pulse input line 14j- 1, a first node P 1 and a third node P3; a second NMOS transistor T2 connected among the first node P 1, a second node P2 and a ground voltage line VSSL; a third NMOS transistor T3 connected between a third clock signal line CLK3 and the second node P2; a fourth NMOS transistor T4 connected among the second node P2, the third node P3 and the ground voltage line VSSL; a capacitor CA-P I connected between the first node P 1 and an output line 14j; a fifth NMOS transistor T5 connected between the first clock signal line CKL 1 and the output line 14j; and a sixth M NMOS transistor T6 connected among the second node P2, the output line 14i and the ground voltage line VSSL.

If a high logic level of (i-1)th row line input signal g-,-t is applied from the previous stage 12j-1 to the scanning pulse input line 14j-1, then first and fourth NMOS transistors T 1 and T4 are turned on. Accordingly, a voltage at the first node P 1 is changed into a high logic level by the supply voltage VDD applied as the first NMOS transistor Tl is turned on, and a voltage at the seco-rid node P2 is discharged toward a ground voltage source VSS as the fourth NMOS trwisistor T4 is turned on. As a result, a low logic level voltage emerges at the second node P2.

As seen from Fig. 7, the third clock signal C3 remains at a low level voltage 0 - durina, a time interval when the (i- 1)th row line input signal gi-1 has a Wgh logic level voltage. In other words, a hiLyh logic level voltage region of the third clock signal C3 is 8 not overlapped with a high level voltage region of the (I- 1)th row line input signal gi-j.

Accordingly, the third and fourth NMOS transistors T3 and T4 are not turned on simultaneously, so that a voltage at the second node P21 is determined independently of a channel width ratio (i.e., resistance ratio) of the third NMOS transistor T3 to the fourth NMOS transistor T4. Accordingly, even when device characteristics of the third and fourth NMO S transistors T') and T4 are not uniform, a circuit characten- stic, of the shift register is not changed to such a large extent to make its normal operation impossible.

Also, the third and fourth NMOS transistors T3 and T4 are not simultaneously turned on, so that overcurrent does not flow at the third and fourth NMOS transistors T3 and T4. As a result device characteristics of the third and fourth transistors T3 and T4 are not deteriorated and, finthermore, the power consumption is reduced.

It a high logic level voltage appears at the first node P 1, then the fifth NMOS transistor T5 is turned on. In this state, when the first clock signal C I has a high logic level voltage, the output line 14i begins to reach a high logic level of first clock signal C 1 via the drain and the source of the fifth NMOS transistor T5. Accordingly, a high logic level of output signal Vout emerges at the output line 14j. The capacitor CAP 1 raises a voltage at the first node P 1 by the voltage level of the first clock signal Cl when a high level of first clock signal C I is applied to the output line 14j. Since a gate voltage is increased by means of the capacitor CAP I, the fifth NMOS transistor T5 rapidly transfers the high logic level of the first clock signal Cl to the output line 14i without any attenuation and with shorter delay. Accordingly, a voltage loss caused by a threshold voltage of theflifth NMOS transistor T5 is minimized. In this embodiment, the capacitor CAP I can be replaced by a parasitic capacitance existing in the fifth NMOS transistor TS.

If the first clock signal Cl chan es from a high logic level voltage into a low logic 9 level voltage, then the output signal Vout at the output line 14i also changes frorn a heh level voltage into a low level voltage. This results from the fifth NMOS transistor T5 being in a turned-on state With the aid of a voltage at the first node P I.

Next, if the third clock signal C3 changes from a low logic level voltage into a j high logic level voltage, then the third NMOS transistor T3 is turned on in such a manner that a voltace at the second node P2 has a high level. The second NMOS transistor 722 is 9 also turned on with the aid of a high logic level voltage at the second node P2 applied to its gate to thereby discharge a voltage at the first node P 1 toward the ground voltage source VSS connected to. the ground voltage line VSSL. In a similar manner, the sixth NMOS transistor T6 also discharges a voltage at the output line 14j, via the ground voltage line VSSL, into the ground voltage source VSS Wlith the aid of a high level voltage at the second node P2 applied to its gate. As a result, both a voltage at the first node P 1 and an output signal Vout at the output line 14i have a low logic level voltage.

On the other hand, when the first clock signal Cl inputted to the drain of the fifth NMO S transistor T5 is such a state that a voltage at the first node P 1 remains at a hi gh logic level changes from a high logic level voltage into a low logic level voltage, a voltage at the first node P 1 rises. At this time, a voltage rising width AVp at the first node P 1 can be established accurately by the capacitor CAP 1 connected between the first node P 1 and the output line 1 4j. and a capacitor CLI provided between the frst node P 1 and the ground voltage line VSSL. The voltage rising Yddth AVp at the first node P I is as described in the following formula (2):

AvP1 CAP + COX AVout - - - - - - (2) CLI CAP + COX wherein Cox represents a parasitic capacitance of the Fifth NMOS transistor TS.

Preferably, capacitances. of the capacitors CA.P 1 and CL, are preferably set to about 0. 1 to 10 pF. However, other suitable values may be used.

The shift register further includes a capacitor CL, connected between the second node P2 and the ground voltage line VSSL. 71e capacitor CL2 restrains a voltage variation at the second node P2 when the output signal Vout at the output line 14i changes and a voltage variation at the second node P2 due to leakage current. Such a restraint of the voltage variation can be seen from voltage waveforms P I and P2 at the first and second nodes when the capacitor CL2 is provided and voltage waveforms P 1' and P2' at the first and second nodes when the capacitor CL, is not provided, as sho-s;m in Fia. 8.

CP Refeming now to Fig. 9, there is shown each stage of a shift register according to another embodiment of the present invention. The shift register will be descnibed with reference to the waveform diagrams in Fig. 7. 'In Fig. 9, the ith stages 12i includes a first NMOS transistor Tl connected between a scanning pulse input line 14j-1 and a first node P I; a second NMOS transistor T2 connected among the first node P 1, a second node P2 and a ground voltage line VSSL; a third NMOS transistor T3 connected among a supply voltage line VIDDL, a third clock signal line CLK3 and the second node P2; a fourth NMOS transistor T4 connected among the first node P 1, the second node P2 and the ground voltage line VSSL; a capacitor CAP 1 connected between the first node P 1 and an output line 14j; a fifth NMOS transistor T5 connected between the first clock signal line CKL 1 and the output line 14j; and a sixth NMOS transistor T6 connected among the second node P2, the output line 14j, and the ground voltage line VSSL.

If a high logic level of (i-1)th row line input signal gi-1 is applied from the previous stage 12j-[ to the scanning pulse input line 14j-1, then first NMOS transistors T1 15';; is t=ed on to charge a voltage at the first node P 1 into a high logic level. When the voltage at the first node P l is charged into a level higher than the threshold voltage, the fourth and fifth NMOS transistors T4 and T5 are turned on. As the fourth NMOS transistor T4 is turned on, a voltage at the second node P2 is discharged, via the fourth NMOS transistor T4 and the ground voltage line VSSL, toward the ground voltage source VSS. Accordingly, a voltage at the second node P2 is not varied during a time interval when a voltage at the first node P 1 remains at a high logic level (i.e., when the (l- 1)th row line input signal gi- 1 remains at a high logic level). Further, since a voltage at the second node P2 becomes a low logic level, the second and sixth NMOS transistors T2 and T6 are turned off. As seen from Fig. 7, the third clock signal C3 remains at a low logic level voltage during a tuine interval when the (i-1)th row line input signal gi- 1 has a high logic level voltage, so that a voltage level at the second node P2 is determined independently of a channel width ratio (i.e., resistance ratio) of the third NMOS transistor T') to the fourth NMOS transistor T4. Subsequently, if the first clock signal Cl changes from a low logic level voltage into a high logic level voltage, then the output line 14i is charged into a high 3) 0 logic level voltage with the aid of a high logic level of first clock signal Cl applied via the drain and the source of the fifth NMOS transistor T5. At this time, the capacitor CAP 1 bootstraps a voltage at the first node P 1 by a voltage of the first clock signal C 1 when the high logic level of first clock signal C I is applied to the output line 14j.

Further, if the first clock signal Cl transits from a high logic level voltage into a low logic level voltage, the output signal Vout at the output line 14i drops into a low log' P 1 ic level. This results from the fifth NMOS transistor T5 being in a t=ed-on state.

Next, if the third clock signal C3 changes ftom a low logic level voltage into a high logic level voltage, then the third NMOS transistor T3 is tumed on to char e the 0 9 second node P2 into a high logic level voltage v.,ith the aid of a high level of third clock signal C3). The second NMOS transistor T2 also is turned on with the aid of a high logic level voltage at the second node P2 applied to its gate to thereby discharge a voltage at the first node P l toward the ground voltage source VSS connected to the ground voltage line VSSL. In a similar manner, the sixth NMOS t=istor T6 also discharges an output signal Vout at the output line 141, via the ground voltage line VSSL, into the ground voltage source VSS with the aid of a high logic level voltage at the second node P2 applied to its gate. As a result, both a voltage at the first node P 1 and an output signal Vout at the output line 14i have a low logic level.

Referring to Fig. 10, there is shown each stage of a shift register according to still another embodiment of the present iny ention. The shift register of Fig. 10 will be described with reference to the waveform diagrams in Fig. 7. In Fig. 10, the i th stages 1 2i 0 includes a first NMOS t=istor T1 connected between a scanning pulse input line 14j-1 and a first node P 1; a second NMO S transistor T2 connected among the first node P 1, a second node P2 and a ground voltage line VSSL; a third NMOS transistor T3 connected among a supply voltage line VDDL, a d-iird clock signal line CLK3 and the second node P2; a fourth NMOS transistor T4 connected among the first NMO S transistor T 1, the second node P2 and the ground voltage line VSSL; a capacitor CAP l connected between the first node P1 and a_n output line 141; a fifth NMOS transistor TS connected between the first clock signal line CKL l and the output line 14j; a sixth NMOS transistor T6 connected among the second node P2, the output line 14i and the ground voltage line VSSL; and a seventh NMOS transistor T7 connected between the output line 14i and the ground voltage line VSSL.

12 If a high level of (I- 1)th row line input signal gi- 1 is applied from the previous.3tag-- 12j-1 to the scanning pulse input line 14j-1, then first NMOS transistors T1 is turned on to charge a voltage at the first node'P I into a high logic level. The fourth NMOS transistor T4 also is turned on with the aid of a high level of row line input signal gi-i, a voltage at the second node P2 is discharged, via the ground voltage line VSSL, toward the ground voltage source VSS. Accordingly, a voltage at the second node P2 is not varied by the fourth NMOS transistor T4 during a time interval when a voltage at the first node P I remains at a high level. Such a voltage level at the second node P2 is determined independently of a channel width ratio (i.e., resistance ratio) of the third NMO S transistor T3 to the fourth NMOS transistor T4 because the third clock signal C3 has a low logic level voltage in a high logic level voltage region of the (i-1)th row line input signal gi-j. Also, since a voltage at the second node P2 remains at a low logic level during a time interval from when the fourth NMOS transistor T4 is turned on until a time interval before the third transistor T3 is turned on, the second and sixth NMOS transistors T-2 and T6 are turned off.

If the first clock signal Cl changes from a low logic level voltage into a high logic level voltage, then the output line 14i is charged into a high logic level voltage with the aid of a high logic level of first clock signal C I applied via the drain and the source of the flifth NMOS transistor T5. The capacitor CAP 1 raises a voltage at the first node P 1 by a voltage level of the first clock signal Cl when a high logic level of first clock signal Cl is applied to the output line 14j.

Further, if the first clock signal C I transits from a high logic level voltage into a low logic level voltage, the output signal Vout at the output line 14i changes into a low logic level. This results from the fifth NMOS transistor T5 being in a turned-on state. In addition, theseventh NMOS. transistor T7 is turned on with the aid of a high logic level voltage of feedback signal W from the next stage 12j+1, thereby discharging the output signal Vout at the output line 14j, via the ground voltage line VSSL, into the ground voltage source VSS rapidly. Accordingly, a long falling time of the output signal Vout is shortenedas shown in Fig. 11. The increased falling time of the output signal Vout is 3 0 caused by a fact that the channel width of the fifth NMOS transistor T5 becomes narrow slowly as a voltage at the first node P 1 decreases slowly. in other words, since a discharge path provided by the fifth NMOS transistor T5 becomes narrow slowly, a falling time of the output signal Vout is lengthened. A new discharge path from the seventh NMOS transistor T7 is provided in addition to the discharge path from the fifth NMOS transistor TS, so that the output voltage Vout at the output line 14pis rapidly 5 discharged. As a result, a falling time of the output signal Vout is shortened, As described above, the shift register according to the embodiments drives stages sequentially by utilizing four clock signals, and allows each stage to be configured irrespective of the size of transistors. Accordingly, in the shift register according to the embodiments a change in a circuit characteristic caused by a variation in a device drift and a threshold voltage, etc. can be minimized. As a result, current flows only during a transition interval of signal, so that the power consumption is reduced, and also a deterioration in a device characteristic caused by overcurrent is restrained. Furthermore, in the shift register according to the 1 embodiments.,a separate capacitor is provided between the outputriode and the bootstrap node and a capacitor is provided between the direct current source and the bootstrap node, so that a voltage variation at the bootstrap node can be restrained. As a result, the shift register according to the embodiments operates more stably.

Although the present invention has been explained by the embodiments shown in the drawinas described above. it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be detern-dned only by the appended claims and their equivalents.

14

Claims

Claims:

1 A shift register having a plurality of stages which are connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, wherein the stages are connected to coiTesponding row lines Z:> In and are connected in cascade with respect to a scanning signal for charging and discharging the row lines, each one of the stages comprising:

output circuit device including a pull-up transistor and a pull-down transistor, said pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode, said pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a second control electrode, input circuit device being responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; means for raising a voltage of the first control signal; and means, responsive to a scanning signal at a next row line, for accelerating a discharging speed at the row line.

2. The shift register of claim 1, wherein the input circuit device comprises:

a first transistor having a third input electrode responsive to the scanning signal, a third output electrode connected to the first control electrode, and a third control electrode connected to the third input electrode; and a second transistor having a fourth input electrode connected to the low level voltage source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode.

3. The shift register of claim 2, wherein the input circuit device further comprises:

a third transistor having a fifth input electrode connected to the high level voltage source, a fifth output electrode connected to the second control electrode, and a fifth control electrode responsive to the second clock signal; and a fourth transistor having a sixth input electrode connected to the low level voltage source, a sixth output electrode connected to the second control electrode, and a sixth control electrode responsive to the scanning signal.

4. The shift register of any of claims 1 to 3, wherein the voltage raising means includes a capacitor connected to the row line and the first control electrode.

5. The shift register of any of claims 1 to 4, wherein the accelerating means includes a fifth transistor having a seventh input electrode connected to the low level voltage source, an output electrode connected to the row line, and a seventh control electrode for responding to a signal from the output line of the next stage.

6. A shift register for driving gate lines of liquid crystal display and responsive to a scanning signal, a first voltage source and a second voltage source, the shift register comprising:

a plurality of stages, each stage including:

output circuit device including a pull-up transistor and a pull down transistor, the pull-up transistor having a first control electrode, a first input electrode coupled to a first clock signal having a delayed phase in comparison to the scanning signal and a first output electrode connected to a gate line; said pull-down transistor having a second control electrode, a second input electrode coupled to the second voltage source and a second output electrode connected to the gate line; input circuit device responsive to the scanning, signal for generating a first control signal to be applied to the first control electrode, and 16 responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; a voltage controller coupled between the first control electrode and the gate line to raise a voltage of the first control signal; a first discharging device responsive to the scanning signal to discharge the second control signal; and a second discharging device, responsive to a scanning signal at a next gate line, for discharging the scanning signal at the gate line.

7. The shift register of claim 6, wherein the input circuit device comprises:

a first transistor having a third input electrode responsive to the scanning signal, a third output electrode connected to the first control electrode, and a third control electrode connected to the third input electrode; and is a second transistor having a fourth input electrode connected to the second voltage source, a fourth output electrode connected to the first control electrode, and a fourth control electrode connected to the second control electrode.

8. The shift register of claim 7, wherein the input circuit device further comprises:

a third transistor having a fifth input electrode connected to the first voltage source, a fifth output electrode connected to the second control electrode, and a fifth control electrode for receiving the second clock signal; and a fourth transistor having a sixth input electrode connected to the second voltage source, a sixth output electrode connected to the second control electrode, and a sixth control electrode for responding to the scanning signal.

9. The shift register of any of claims 6 to 8, wherein the voltage controller includes a capacitor.

10. The shift register of any of claims 6 to 9, wherein the second discharging device includes a fifth transistor havino, a seventh input electrode connected to t> 17 the second voltage source, an output electrode connected to the gate line, and a seventh control electrode responsive to a signal from an output line of the next stage of the shift register.