TWI514361B - Gate driving circuit - Google Patents
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本發明係相關於一種閘極驅動電路，尤指一種可改善驅動能力之閘極驅動電路。The present invention relates to a gate driving circuit, and more particularly to a gate driving circuit capable of improving driving capability.
一般而言，液晶顯示面板包含有複數個畫素、閘極驅動電路以及源極驅動電路。源極驅動電路係用以寫入資料訊號於被開啟之畫素。閘極驅動電路包含複數級移位暫存器，用來提供複數個閘極訊號以控制畫素之開啟與關閉。在移位暫存器的運作中，移位暫存器之儲能單元儲存之驅動電壓和移位暫存器之驅動能力相關，當驅動電壓較高且較穩定，移位暫存器輸出之閘極訊號具有較佳之驅動能力。然而，習知移位暫存器之儲能單元儲存之驅動電壓除了被用來產生閘極訊號以外，驅動電壓亦會被用來產生其他控制訊號，因此，習知移位暫存器之儲能單元儲存之驅動電壓較不穩定，進而影響習知移位暫存器之驅動能力。Generally, a liquid crystal display panel includes a plurality of pixels, a gate driving circuit, and a source driving circuit. The source driver circuit is used to write a data signal to the pixel that is turned on. The gate drive circuit includes a plurality of shift register registers for providing a plurality of gate signals to control the turning on and off of the pixels. In the operation of the shift register, the driving voltage stored in the energy storage unit of the shift register is related to the driving capability of the shift register. When the driving voltage is high and stable, the shift register outputs The gate signal has better driving capability. However, in addition to the driving voltage stored in the energy storage unit of the conventional shift register, in addition to being used to generate the gate signal, the driving voltage is also used to generate other control signals. Therefore, the conventional shift register is stored. The driving voltage of the energy storage unit is relatively unstable, thereby affecting the driving ability of the conventional shift register.
本發明之目的在於提供一種可改善驅動能力之閘極驅動電路，以解決先前技術的問題。SUMMARY OF THE INVENTION An object of the present invention is to provide a gate driving circuit capable of improving driving ability to solve the problems of the prior art.
本發明閘極驅動電路包含複數級移位暫存器，該些級移位暫存器之第N級移位暫存器包含一上拉單元，電連接於一輸出線及一閘極線，用以根據一驅動電壓及一高頻時脈訊號將該輸出線之一第一傳遞訊號及該閘極線之一第一閘極訊號上拉至一高準位電壓；一儲能單元，電連接於該上拉單元， 用來提供該驅動電壓至該上拉單元；一第一驅動單元，電連接於該上拉單元，用來根據該第一傳遞訊號及該第一閘極訊號對一後級移位暫存器之儲能單元執行充電程序；一第二驅動單元，電連接於該輸出線，用來根據該第一傳遞訊號提供一下拉控制訊號至該後級移位暫存器；一第一下拉單元，電連接於該儲能單元，該輸出線及該閘極線，用以根據一第一控制訊號下拉該驅動電壓、該第一閘極訊號及該第一傳遞訊號；以及一第一控制單元，電連接於該第一下拉單元，用以根據一第一低頻時脈訊號及一前級移位暫存器提供之下拉控制訊號產生該第一控制訊號。The gate driving circuit of the present invention comprises a plurality of stages of shift registers, and the stage N shift register of the stage shift registers comprises a pull-up unit electrically connected to an output line and a gate line. The first transmission signal of the output line and the first gate signal of the gate line are pulled up to a high level voltage according to a driving voltage and a high frequency clock signal; an energy storage unit, electricity Connected to the pull up unit, The first driving unit is electrically connected to the pull-up unit, and is configured to perform a post-stage shift register according to the first transfer signal and the first gate signal. The energy storage unit performs a charging process; a second driving unit is electrically connected to the output line for providing a pull control signal to the subsequent shift register according to the first transfer signal; a first pull down unit Electrically connected to the energy storage unit, the output line and the gate line are configured to pull down the driving voltage, the first gate signal and the first transmission signal according to a first control signal; and a first control unit And electrically connected to the first pull-down unit, configured to generate the first control signal according to a first low frequency clock signal and a pre-stage shift register providing a pull-down control signal.
相較於先前技術，本發明閘極驅動電路之移位暫存器具有較穩定且電壓較高之驅動電壓，以及可提供具較短下降時間之閘極訊號，因此，本發明閘極驅動電路輸出之傳遞訊號及閘極訊號具有較佳之驅動能力。Compared with the prior art, the shift register of the gate driving circuit of the present invention has a relatively stable and high voltage driving voltage, and can provide a gate signal with a shorter falling time. Therefore, the gate driving circuit of the present invention The output signal and gate signal have better driving capability.
100‧‧‧閘極驅動電路100‧‧‧ gate drive circuit
110N‧‧‧移位暫存器110N‧‧‧Shift register
112‧‧‧上拉單元112‧‧‧Upper pull unit
114‧‧‧儲能單元114‧‧‧ Energy storage unit
116‧‧‧第一驅動單元116‧‧‧First drive unit
118‧‧‧第二驅動單元118‧‧‧Second drive unit
120‧‧‧第一下拉單元120‧‧‧First pulldown unit
122‧‧‧第二下拉單元122‧‧‧Secondary pull-down unit
124‧‧‧第一控制單元124‧‧‧First Control Unit
126‧‧‧第二控制單元126‧‧‧second control unit
128‧‧‧升壓單元128‧‧‧Boost unit
GL(n-1),GL(n),GL(n+1)‧‧‧閘極線GL(n-1), GL(n), GL(n+1)‧‧‧ gate line
OL(n-1),OL(n),OL(n+1)‧‧‧輸出線OL(n-1), OL(n), OL(n+1)‧‧‧ output lines
T‧‧‧電晶體T‧‧‧O crystal
C1,C2‧‧‧電容C1, C2‧‧‧ capacitor
HC1‧‧‧高頻時脈訊號HC1‧‧‧ high frequency clock signal
LC1,LC2‧‧‧低頻時脈訊號LC1, LC2‧‧‧ low frequency clock signal
Q(n),Q(n+2)‧‧‧驅動電壓Q(n), Q(n+2)‧‧‧ drive voltage
Qp(n),Qp(n+2)‧‧‧下拉控制訊號Qp(n), Qp(n+2)‧‧‧ pulldown control signal
P(n)‧‧‧第一控制訊號P(n)‧‧‧ first control signal
K(n)‧‧‧第二控制訊號K(n)‧‧‧second control signal
G(n-1),G(n),G(n+1)‧‧‧閘極訊號G(n-1), G(n), G(n+1)‧‧‧ gate signal
ST(n-1),ST(n),ST(n+1)‧‧‧傳遞訊號ST(n-1), ST(n), ST(n+1)‧‧‧ transmission signals
VGH‧‧‧高準位電壓源VGH‧‧‧ high level voltage source
VSS1‧‧‧第一準位電壓VSS1‧‧‧first level voltage
VSS2‧‧‧第二準位電壓VSS2‧‧‧second level voltage
t1,t2,t3‧‧‧時間點T1, t2, t3‧‧‧ time point
第1圖為本發明閘極驅動電路的示意圖。Figure 1 is a schematic view of a gate drive circuit of the present invention.
第2圖為第1圖閘極驅動電路之第N級移位暫存器的示意圖。Fig. 2 is a schematic diagram of the Nth stage shift register of the gate driving circuit of Fig. 1.
第3圖為第2圖之第N級移位暫存器的相關訊號波形示意圖。Figure 3 is a schematic diagram of the relevant signal waveforms of the Nth stage shift register of Fig. 2.
請同時參考第1圖及第2圖，第1圖為本發明閘極驅動電路的示意圖，第2圖為第1圖閘極驅動電路之第N級移位暫存器的示意圖。如圖所示，閘極驅動電路100包含複數級移位暫存器，為方便說明，閘極驅動電路100只顯示第(N-1)級移位暫存器110(N-1)、第N級移位暫存器110N及第(N+1)級移位暫存器110(N+1)，其中只有第N級移位暫存器110N於第2圖中顯示內部架構，其餘級移位暫存器係類同於第N級移位暫存器110N，所以不另贅述。N為大於1的正整數。第(N-1)級移位暫存器110(N-1)用以提供傳遞訊號 ST(n-1)及閘極訊號G(n-1)，第N級移位暫存器110N用以提供傳遞訊號ST(n)及閘極訊號G(n)，第(N+1)級移位暫存器110(N+1)用以提供傳遞訊號ST(n+1)及閘極訊號G(n+1)。閘極訊號G(n-1)、G(n)、G(n+1)係依序經由閘極線GL(n-1)、GL(n)、GL(N+1)傳送至畫素陣列以開啟對應之畫素單元。另外，傳遞訊號ST(n-1)、ST(n)、ST(n+1)被用來產生移位暫存器所需之控制訊號。Please refer to FIG. 1 and FIG. 2 simultaneously. FIG. 1 is a schematic diagram of a gate driving circuit of the present invention, and FIG. 2 is a schematic diagram of an Nth stage shift register of the gate driving circuit of FIG. As shown, the gate driving circuit 100 includes a plurality of stages of shift registers. For convenience of explanation, the gate driving circuit 100 only displays the (N-1)th stage shift register 110 (N-1), The N-stage shift register 110N and the (N+1)-stage shift register 110 (N+1), wherein only the N-th shift register 110N displays the internal architecture in FIG. 2, and the remaining stages The shift register is similar to the Nth shift register 110N, so it will not be described again. N is a positive integer greater than one. The (N-1)th stage shift register 110 (N-1) is used to provide a transmission signal ST(n-1) and gate signal G(n-1), the Nth stage shift register 110N is used to provide the transmission signal ST(n) and the gate signal G(n), (N+1) The stage shift register 110 (N+1) is used to provide the transfer signal ST(n+1) and the gate signal G(n+1). The gate signals G(n-1), G(n), and G(n+1) are sequentially transmitted to the pixels via the gate lines GL(n-1), GL(n), and GL(N+1). The array opens the corresponding pixel unit. In addition, the transfer signals ST(n-1), ST(n), ST(n+1) are used to generate the control signals required for shifting the register.
第N級移位暫存器110N包含上拉單元112、儲能單元114、第一驅動單元116、第二驅動單元118、第一下拉單元120、第二下拉單元122、第一控制單元124，第二控制單元126，以及升壓單元128。上拉單元112係電連接於輸出線OL(n)及閘極線GL(n)，用以根據驅動電壓Q(n)及高頻時脈訊號HC1將輸出線OL(n)之傳遞訊號ST(n)及閘極線GL(n)之閘極訊號G(n)上拉至高準位電壓。儲能單元114之第一端係電連接於上拉單元112。儲能單元114係用來根據第(N-2)級移位暫存器之第一驅動單元所輸出之訊號執行充電程序，進而於儲能單元114之第一端產生驅動電壓Q(n)，並提供驅動電壓Q(n)至上拉單元112。第一驅動單元116係電連接於上拉單元112，用來根據傳遞訊號ST(n)及閘極訊號G(n)對第(N+2)級移位暫存器之儲能單元執行充電程序。第二驅動單元118係電連接於輸出線OL(n)，用來根據傳遞訊號ST(n)提供下拉控制訊號Qp(n+2)至第(N+2)級移位暫存器。升壓單元128係電連接於儲能單元114，用以根據第(N+1)級移位暫存器110(N+1)之傳遞訊號ST(n+1)對驅動電壓Q(n)進行升壓。The Nth stage shift register 110N includes a pull-up unit 112, an energy storage unit 114, a first driving unit 116, a second driving unit 118, a first pull-down unit 120, a second pull-down unit 122, and a first control unit 124. The second control unit 126, and the boosting unit 128. The pull-up unit 112 is electrically connected to the output line OL(n) and the gate line GL(n) for transmitting the signal ST of the output line OL(n) according to the driving voltage Q(n) and the high-frequency clock signal HC1. (n) and the gate signal G(n) of the gate line GL(n) is pulled up to a high level voltage. The first end of the energy storage unit 114 is electrically connected to the pull up unit 112. The energy storage unit 114 is configured to perform a charging process according to the signal output by the first driving unit of the (N-2)th stage shift register, and further generate a driving voltage Q(n) at the first end of the energy storage unit 114. And providing a driving voltage Q(n) to the pull-up unit 112. The first driving unit 116 is electrically connected to the pull-up unit 112 for charging the energy storage unit of the (N+2)th stage shift register according to the transmission signal ST(n) and the gate signal G(n). program. The second driving unit 118 is electrically connected to the output line OL(n) for providing the pull-down control signals Qp(n+2) to the (N+2)th stage shift register according to the transmission signal ST(n). The boosting unit 128 is electrically connected to the energy storage unit 114 for shifting the signal ST(n+1) to the driving voltage Q(n) according to the (N+1)th stage shift register 110(N+1). Boost.
第一下拉單元120係電連接於儲能單元114、輸出線OL(n)及閘極線GL(n)用以根據第一控制訊號P(n)下拉驅動電壓Q(n)、傳遞訊號ST(n)及閘極訊號G(n)。驅動電壓Q(n)係被下拉至和傳遞訊號ST(n)相同之電壓準位，傳遞訊號ST(n)係被下拉至第二準位電壓VSS2，而閘極訊號G(n)係被下拉至第一準位電壓VSS1。第一控制單元124係電連接於第一下拉單元120，用以 根據第一低頻時脈訊號LC1及第(N-2)級移位暫存器提供之下拉控制訊號Qp(n)產生第一控制訊號P(n)。The first pull-down unit 120 is electrically connected to the energy storage unit 114, the output line OL(n) and the gate line GL(n) for pulling down the driving voltage Q(n) according to the first control signal P(n), and transmitting the signal. ST(n) and gate signal G(n). The driving voltage Q(n) is pulled down to the same voltage level as the transmission signal ST(n), the transmission signal ST(n) is pulled down to the second level voltage VSS2, and the gate signal G(n) is Pull down to the first level voltage VSS1. The first control unit 124 is electrically connected to the first pull-down unit 120 for The first control signal P(n) is generated according to the first low frequency clock signal LC1 and the (N-2)th stage shift register providing the pull-down control signal Qp(n).
相似地，第二下拉單元122係電連接於儲能單元114、輸出線OL(n)及閘極線GL(n)用以根據第二控制訊號K(n)下拉驅動電壓Q(n)、傳遞訊號ST(n)及閘極訊號G(n)。驅動電壓Q(n)係被下拉至和傳遞訊號ST(n)相同之電壓準位，傳遞訊號ST(n)係被下拉至第二準位電壓VSS2，而閘極訊號G(n)係被下拉至第一準位電壓VSS1。第二控制單元124係電連接於第二下拉單元120，用以根據第二低頻時脈訊號LC2及第(N-2)級移位暫存器提供之下拉控制訊號Qp(n)產生第二控制訊號K(n)。第一準位電壓VSS1及第二準位電壓VSS2可相同或相異。Similarly, the second pull-down unit 122 is electrically connected to the energy storage unit 114, the output line OL(n), and the gate line GL(n) for pulling down the driving voltage Q(n) according to the second control signal K(n), The signal ST(n) and the gate signal G(n) are transmitted. The driving voltage Q(n) is pulled down to the same voltage level as the transmission signal ST(n), the transmission signal ST(n) is pulled down to the second level voltage VSS2, and the gate signal G(n) is Pull down to the first level voltage VSS1. The second control unit 124 is electrically connected to the second pull-down unit 120 for generating a second pullback control signal Qp(n) according to the second low frequency clock signal LC2 and the (N-2)th stage shift register. Control signal K(n). The first level voltage VSS1 and the second level voltage VSS2 may be the same or different.
其中第二低頻時脈訊號LC2之相位係相反於第一低頻時脈訊號LC1之相位，因此第一下拉單元120及第二下拉單元122可交替地下拉驅動電壓Q(n)、傳遞訊號ST(n)及閘極訊號G(n)。The phase of the second low-frequency clock signal LC2 is opposite to the phase of the first low-frequency clock signal LC1. Therefore, the first pull-down unit 120 and the second pull-down unit 122 can alternately pull down the driving voltage Q(n) and transmit the signal ST. (n) and gate signal G(n).
在本實施例中，上拉單元112包含電晶體T21及電晶體T22。電晶體T21之第一端係用以接收高頻時脈訊號HC1，電晶體T21之控制端係電連接於儲能單元114之第一端以接收驅動電壓Q(n)，而電晶體T21之第二端係電連接於閘極線GL(n)。電晶體T22之第一端係用以接收高頻時脈訊號HC1，電晶體T22之控制端係電連接於儲能單元114之第一端以接收驅動電壓Q(n)，而電晶體T22之第二端係電連接於輸出線OL(n)。儲能單元114包含電容C1。第一驅動單元116包含電晶體T11。電晶體T11之第一端係電連接於閘極線GL(n)，電晶體T11之控制端係電連接於輸出線OL(n)，而電晶體T11之第二端係電連接於第(N+2)級移位暫存器之儲能單元。第二驅動單元包含一電晶體T15，電晶體T15之第一端及控制端係電連接於輸出線OL(n)， 電晶體T15之第二端係電連接於第(N+2)級移位暫存器之第一控制單元及第二控制單元。In the present embodiment, the pull-up unit 112 includes a transistor T21 and a transistor T22. The first end of the transistor T21 is for receiving the high frequency clock signal HC1, and the control end of the transistor T21 is electrically connected to the first end of the energy storage unit 114 to receive the driving voltage Q(n), and the transistor T21 The second end is electrically connected to the gate line GL(n). The first end of the transistor T22 is configured to receive the high frequency clock signal HC1, and the control end of the transistor T22 is electrically connected to the first end of the energy storage unit 114 to receive the driving voltage Q(n), and the transistor T22 The second end is electrically connected to the output line OL(n). The energy storage unit 114 includes a capacitor C1. The first driving unit 116 includes a transistor T11. The first end of the transistor T11 is electrically connected to the gate line GL(n), the control end of the transistor T11 is electrically connected to the output line OL(n), and the second end of the transistor T11 is electrically connected to the first ( The energy storage unit of the N+2) stage shift register. The second driving unit includes a transistor T15, and the first end and the control end of the transistor T15 are electrically connected to the output line OL(n). The second end of the transistor T15 is electrically connected to the first control unit and the second control unit of the (N+2)th stage shift register.
升壓單元包含電晶體T23及電晶體T24。電晶體T23之第一端及控制端係電連接於第(N+1)級移位暫存器110(N+1)之輸出線OL(n+1)，電晶體T23之第二端係電連接於儲能單元114之第一端。電晶體T24之第一端係電連接於第(N+1)級移位暫存器110(N+1)之輸出線OL(n+1)，電晶體T24之控制端係電連接於一高準位電壓源VGH，電晶體T24之第二端係電連接於儲能單元114之第一端。高準位電壓源VGH係高於第一準位電壓VSS1及第二準位電壓VSS2。The boosting unit includes a transistor T23 and a transistor T24. The first end and the control end of the transistor T23 are electrically connected to the output line OL(n+1) of the (N+1)th stage shift register 110(N+1), and the second end of the transistor T23 Electrically connected to the first end of the energy storage unit 114. The first end of the transistor T24 is electrically connected to the output line OL(n+1) of the (N+1)th stage shift register 110(N+1), and the control end of the transistor T24 is electrically connected to the The high-level voltage source VGH, the second end of the transistor T24 is electrically connected to the first end of the energy storage unit 114. The high level voltage source VGH is higher than the first level voltage VSS1 and the second level voltage VSS2.
第一下拉單元120包含電晶體T32，電晶體T34及電晶體T42。電晶體T32之第一端係電連接於閘極線GL(n)，T32之控制端係電連接於第一控制單元124以接收第一控制訊號P(n)，T32之第二端係電連接於第一準位電壓VSS1。電晶體T34之第一端係電連接於輸出線OL(n)，電晶體T34之控制端係電連接於第一控制單元124以接收第一控制訊號P(n)，電晶體T34之第二端係電連接於第二準位電壓VSS2。電晶體T42之第一端係電連接於儲能單元114之第一端，電晶體T42之控制端係電連接於第一控制單元124以接收第一控制訊號P(n)，電晶體T42之第二端係電連接於閘極線GL(n)。The first pull-down unit 120 includes a transistor T32, a transistor T34, and a transistor T42. The first end of the transistor T32 is electrically connected to the gate line GL(n), and the control end of the T32 is electrically connected to the first control unit 124 to receive the first control signal P(n), and the second end of the T32 is electrically connected. Connected to the first level voltage VSS1. The first end of the transistor T34 is electrically connected to the output line OL(n), and the control end of the transistor T34 is electrically connected to the first control unit 124 to receive the first control signal P(n), and the second of the transistor T34. The terminal is electrically connected to the second level voltage VSS2. The first end of the transistor T42 is electrically connected to the first end of the energy storage unit 114, and the control end of the transistor T42 is electrically connected to the first control unit 124 to receive the first control signal P(n), and the transistor T42 The second end is electrically connected to the gate line GL(n).
第一控制單元124包含電晶體T51、電晶體T52、電晶體T53及電晶體T54。電晶體T51之第一端係用以接收第一低頻時脈訊號LC1，電晶體T51之控制端係電連接於電晶體T51之第一端。電晶體T52之第一端係電連接於電晶體T51之第二端，電晶體T52之控制端係用以接收驅動電壓Qp(n)，而電晶體T52之第二端係電連接於第一準位電壓VSS。電晶體T53之第一端係電連接於電晶體T51之第一端，電晶體T53之控制端係電連接於 電晶體T51之第二端，而電晶體T53之第二端係電連接於第一下拉單元120。電晶體T54之第一端係電連接於電晶體T53之第二端，電晶體T54之控制端係電連接於電晶體T52之控制端，而電晶體T54之第二端係電連接於第一準位電壓VSS1。The first control unit 124 includes a transistor T51, a transistor T52, a transistor T53, and a transistor T54. The first end of the transistor T51 is for receiving the first low frequency clock signal LC1, and the control end of the transistor T51 is electrically connected to the first end of the transistor T51. The first end of the transistor T52 is electrically connected to the second end of the transistor T51, the control end of the transistor T52 is for receiving the driving voltage Qp(n), and the second end of the transistor T52 is electrically connected to the first end. The level voltage VSS. The first end of the transistor T53 is electrically connected to the first end of the transistor T51, and the control end of the transistor T53 is electrically connected to The second end of the transistor T51 is electrically connected to the first pull-down unit 120. The first end of the transistor T54 is electrically connected to the second end of the transistor T53, the control end of the transistor T54 is electrically connected to the control end of the transistor T52, and the second end of the transistor T54 is electrically connected to the first end. The level voltage VSS1.
另一方面，在本實施例中，第二下拉單元122及第二控制單元126之配置係分別相似於第一下拉單元120及第一控制單元124之配置，因此不再進一步說明。On the other hand, in the present embodiment, the configurations of the second pull-down unit 122 and the second control unit 126 are similar to the configurations of the first pull-down unit 120 and the first control unit 124, respectively, and therefore will not be further described.
請參考第3圖，並一併參考第1圖及第2圖。第3圖為第2圖之第N級移位暫存器的相關訊號波形示意圖。如第3圖所示，每一級移位暫存器110(N-1)、110N、110(N+1)之閘極訊號係部分重疊。於時間點t1，驅動電壓Q(n)被第(N-2)級移位暫存器之閘極訊號G(n-2)上拉。於時間點t2，第N級移位暫存器110N之閘極訊號G(n)被高頻時脈訊號HC1由低準位上拉至高準位，驅動電壓Q(n)也因電容耦合效應再度被提昇。於時間點t3，第(N+1)級移位暫存器110(N+1)之傳遞訊號ST(n+1)由低準位上昇至高準位，進而驅動升壓單元128將驅動電壓Q(n)再度提昇。Please refer to Figure 3 and refer to Figure 1 and Figure 2 together. Figure 3 is a schematic diagram of the relevant signal waveforms of the Nth stage shift register of Fig. 2. As shown in FIG. 3, the gate signals of each stage of the shift register 110 (N-1), 110N, 110 (N+1) are partially overlapped. At time t1, the driving voltage Q(n) is pulled up by the gate signal G(n-2) of the (N-2)th stage shift register. At time t2, the gate signal G(n) of the Nth stage shift register 110N is pulled up from the low level to the high level by the high frequency clock signal HC1, and the driving voltage Q(n) is also due to the capacitive coupling effect. Once again being promoted. At time t3, the transmission signal ST(n+1) of the (N+1)th stage shift register 110(N+1) rises from the low level to the high level, thereby driving the boosting unit 128 to drive the voltage. Q(n) is improved again.
依據上述配置，由於驅動電壓Q(n)可以被提升兩次，因此上拉單元112可以輸出較大之電流，亦即增加上拉單元112輸出之傳遞訊號及閘極訊號之驅動能力。另外，第一控制單元124及第二控制單元126之下拉控制訊號Qp(n)係由前級移位暫存器提供，而不是利用驅動電壓Q(n)來產生第一控制訊號P(n)及第二控制訊號K(n)，因此，Q(n)節點負載較低，使驅動電壓Q(n)可以較高且穩定。再者，由於驅動電壓Q(n)較高，因此當閘極訊號G(n)被高頻時脈訊號HC1由高準位下拉至低準位時，閘極訊號G(n)下降之時間會減少，相對地增加顯示面板之資料訊號寫入的時間。According to the above configuration, since the driving voltage Q(n) can be boosted twice, the pull-up unit 112 can output a larger current, that is, increase the driving ability of the transmission signal and the gate signal outputted by the pull-up unit 112. In addition, the first control unit 124 and the second control unit 126 pull-down control signal Qp(n) are provided by the pre-stage shift register instead of using the driving voltage Q(n) to generate the first control signal P(n). And the second control signal K(n), therefore, the Q(n) node load is low, so that the driving voltage Q(n) can be high and stable. Furthermore, since the driving voltage Q(n) is high, when the gate signal G(n) is pulled down from the high level to the low level by the high frequency clock signal HC1, the gate signal G(n) falls. It will be reduced, and the time for writing the data signal of the display panel is relatively increased.
相較於先前技術，本發明閘極驅動電路之移位暫存器具有較穩定且電壓較高之驅動電壓，以及可提供具較短下降時間之閘極訊號，因此，本發明閘極驅動電路輸出之傳遞訊號及閘極訊號具有較佳之驅動能力。Compared with the prior art, the shift register of the gate driving circuit of the present invention has a relatively stable and high voltage driving voltage, and can provide a gate signal with a shorter falling time. Therefore, the gate driving circuit of the present invention The output signal and gate signal have better driving capability.
110N‧‧‧移位暫存器110N‧‧‧Shift register
112‧‧‧上拉單元112‧‧‧Upper pull unit
114‧‧‧儲能單元114‧‧‧ Energy storage unit
116‧‧‧第一驅動單元116‧‧‧First drive unit
118‧‧‧第二驅動單元118‧‧‧Second drive unit
120‧‧‧第一下拉單元120‧‧‧First pulldown unit
122‧‧‧第二下拉單元122‧‧‧Secondary pull-down unit
124‧‧‧第一控制單元124‧‧‧First Control Unit
126‧‧‧第二控制單元126‧‧‧second control unit
128‧‧‧升壓單元128‧‧‧Boost unit
GL(n)‧‧‧閘極線GL(n)‧‧‧ gate line
OL(n)‧‧‧輸出線OL(n)‧‧‧output line
T‧‧‧電晶體T‧‧‧O crystal
C1,C2‧‧‧電容C1, C2‧‧‧ capacitor
HC1‧‧‧高頻時脈訊號HC1‧‧‧ high frequency clock signal
LC1,LC2‧‧‧低頻時脈訊號LC1, LC2‧‧‧ low frequency clock signal
Q(n),Q(n+2)‧‧‧驅動電壓Q(n), Q(n+2)‧‧‧ drive voltage
Qp(n),Qp(n+2)‧‧‧下拉控制訊號Qp(n), Qp(n+2)‧‧‧ pulldown control signal
P(n)‧‧‧第一控制訊號P(n)‧‧‧ first control signal
K(n)‧‧‧第二控制訊號K(n)‧‧‧second control signal
G(n)‧‧‧閘極訊號G(n)‧‧‧ gate signal
ST(n),ST(n+1)‧‧‧傳遞訊號ST(n), ST(n+1)‧‧‧ transmission signal
VGH‧‧‧高準位電壓源VGH‧‧‧ high level voltage source
VSS1‧‧‧第一準位電壓VSS1‧‧‧first level voltage
VSS2‧‧‧第二準位電壓VSS2‧‧‧second level voltage
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| CN104064160B (en) * | 2014-07-17 | 2016-06-15 | 深圳市华星光电技术有限公司 | There is the gate driver circuit of self-compensating function |
| CN104078021B (en) * | 2014-07-17 | 2016-05-04 | 深圳市华星光电技术有限公司 | There is the gate driver circuit of self-compensating function |
| CN104392700B (en) * | 2014-11-07 | 2016-09-14 | 深圳市华星光电技术有限公司 | Scan drive circuit for oxide semiconductor thin-film transistor |
| CN104505050B (en) * | 2014-12-31 | 2017-02-01 | 深圳市华星光电技术有限公司 | Scanning driving circuit for oxide semiconductor thin film transistor |
| CN105161134B (en) * | 2015-10-09 | 2018-10-23 | 京东方科技集团股份有限公司 | Shift register cell and its operating method, shift register |
| TWI623926B (en) * | 2017-08-15 | 2018-05-11 | 友達光電股份有限公司 | Gate driving circuit |
| TWI625711B (en) * | 2017-08-29 | 2018-06-01 | 友達光電股份有限公司 | Gate driving circuit |
| CN108172181A (en) * | 2017-12-21 | 2018-06-15 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display panel |
| CN108877713B (en) * | 2018-07-17 | 2020-06-12 | 惠科股份有限公司 | Display device and shift register circuit |
| TWI701657B (en) * | 2019-07-30 | 2020-08-11 | 友達光電股份有限公司 | Shift register and display device having the same |
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